aboutsummaryrefslogtreecommitdiff
path: root/gas
AgeCommit message (Collapse)AuthorFilesLines
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu4-298/+6
There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is 0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable, but may also cause risk of compatibility. Binutils already support the -mpriv-spec options and ELF priv attributes, which can used to choose what privileged spec you want, and then give a correponding CSR name and address to use. But Gdb and other tools don't have the simialr mechanism for now. However, there are two things can be confirmed, 1. If we don't have a way to control the priv specs, then the changes, like MISA, will cause risk and hard to maintain. 2. We get the guarantee that the CSR address won't be reused in the future specs, even if it is dropped. I'm not sure if Gdb needs to care about the priv spec versions, it is still discussing. But drop the priv spec v1.9, and make sure that we won't reuse the CSR address is a useful solution for now. Also, we might drop the v1.9.1 in a year or two. After that, specs above v1.10 should be compatible anyway. gas/ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. include/ * opcode/riscv-opc.h: Update the defined versions of CSR from PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9. * opcode/riscv.h (enum riscv_priv_spec_class): Remove PRIV_SPEC_CLASS_1P9. opcodes/ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-09[PATCH] gas/doc: improve AVR modifiers wording.Seth Girvan2-14/+27
* doc/c-avr.texi: Improve wording.
2020-06-09x86: add missing 64-bit tests for "don't ignore mandatory pseudo prefixes"Jan Beulich3-0/+12
Commit da4977e00b73 added the 32-bit test files, but failed to add the 64-bit ones.
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich3-1/+15
All of data size, rep, lock, and rex prefixes are invalid with VEX- and alike encoded insns. Make sure they get printed explicitly in all cases, to signal the anomaly. With this, do away with "rex_ignored" - if there is a rex prefix, we want to print it anyway for VEX etc (and there's nothing "ignored" about it in the first place - such an instruction will raise #UD).
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich3-0/+80
Various AVX insns utilizing the X macro fail to reject F3/F2 embedded prefix encodings. As the PREFIX_OPCODE attribute wasn't used by any non-legacy-encoded insns so far, re-use it to achieve the intended effect.
2020-06-09x86-64: adjust far indirect branch handlingJan Beulich8-1/+160
An unwanted side effect of 5990e377e5a3 ("x86-64: Intel64 adjustments for insns dealing with far pointers") was that with -mintel64 LCALL and LJMP would now default to 64-bit operand size. Since 64-bit far branches aren't portable, the default operand size should still be 32-bit. However, since the 64-bit variant is permitted, an ambiguous operand warning should be issued. As to the actual code change, please note that the conditional surrounding the switch() that gets adjusted covers several cases which are of no interest to or benign in 64-bit mode, hence the new conditional added can be quite a bit less involved.
2020-06-09x86: don't ignore mandatory pseudo prefixesJan Beulich6-26/+89
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not be randomly ignored. Fix this for insns without operands as well as for insns referencing the high 16 [XYZ]MM registers. To achieve the former, re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and moving its only operand check to check_VecOperands(). This involves fixing a testcase relying on {vex2} to get ignored.
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan4-0/+42
gas/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * config/tc-arm.c (insns): Add dfb. * testsuite/gas/arm/dfb.d: New test. * testsuite/gas/arm/dfb.s: Input for test. opcodes/ChangeLog: 2020-06-08 Alex Coplan <alex.coplan@arm.com> * arm-dis.c (arm_opcodes): Add dfb. (thumb32_opcodes): Add dfb.
2020-06-08Fix a gas testsuite failure for PE based targets which cannot assemble the ↵Nick Clifton2-0/+7
cfi-i386-2 test. * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
2020-06-08x86: also handle %k<N> and %bnd<N> in debugging helpersJan Beulich2-1/+7
Adjustment of this function was missed when support for the respective registers was added.
2020-06-08x86: simplify check_byte_reg()Jan Beulich2-15/+9
With the introduction of what right now is the very first conditional in the function's loop (commit dc821c5f9ae5 ["x86: replace Reg8, Reg16, Reg32, and Reg64"]), the last if() in the same loop has become pointless - retain just its body.
2020-06-08x86: restrict %tr<N> visibilityJan Beulich5-2/+24
First of all, these registers have never been available on any 64-bit CPU, and hence should not be recognized in 64-bit mode. But even before that they had already disappeared - also don't recognize them when 586 or 686 architectures were explicitly set.
2020-06-08ix86: enable 2nd CFI testJan Beulich3-7/+13
While putting together the previous patch I noticed that this test, forever since its introduction, was dead. Update it so it will pass, and enable it.
2020-06-08x86: also allow %st(N) in CFI directivesJan Beulich3-1/+9
In 0e0eea782025 ("x86: x87-related adjustments") I screwed up CFI directives with FPU support disabled, by moving the conditional there across a check of "allow_pseudo_reg". Add the missing check.
2020-06-08x86: restrict use of register aliasesJan Beulich7-65/+149
Register aliases (created e.g. via .set) check their target register at the time of creation of the alias. While this makes sense, it's not enough: The underlying register must also be "visible" at the time of use. Wrong use of such aliases would lead to internal errors in e.g. add_prefix() or build_modrm_byte(). Split the checking part of parse_real_register() into a new helper function and use it also from the latter part of parse_register() (at the same time replacing a minor open coded part of it). Since parse_register() returning NULL already has a meaning, a fake new "bad register" indicator gets added, which all callers need to check for.
2020-06-06Power10 tidiesAlan Modra3-0/+10
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10. gas/ * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-06Rename PowerPC64 pcrel GOT TLS relocationsAlan Modra2-16/+20
These relocations should have had REL in their names, to reflect the fact that they are pc-relative. Fix that now by adding _PCREL. I've added some back-compatibility code to support anyone using .reloc with the old relocations. include/ * elf/ppc64.h (elf_ppc64_reloc_type): Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. bfd/ * reloc.c: Rename BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34, BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34, BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34, BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34. * elf64-ppc.c: Update throughout for reloc renaming. (ppc64_elf_reloc_name_lookup): Handle old reloc names. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-ppc.c: Update throughout for reloc renaming. elfcpp/ * powerpc.h: Rename R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34, R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34, R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34. gold/ * powerpc.cc: Update throughout for reloc renaming.
2020-06-05gas: avoid GCC 10 warning stringop-overflow in tc-bpf.cJose E. Marchesi2-2/+7
The GAS struct frag ends with a field `fr_literal' whose purpose is to mark the begining of the frag's data: struct frag { ... /* Data begins here. */ char fr_literal[1]; }; The code in gas/config/tc-bpf.c recently committed: where = fixP->fx_frag->fr_literal + fixP->fx_where; where[1] = target_big_endian ? 0x01 : 0x10; triggers the stringop-overflow warning in GCC 10+, since the compiler assumes the size of the modified buffer is 1 byte. This patch slightly modifies the code to make tc-bpf.c buildable with GCC 10+. 2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning stringop-overflow.
2020-06-05RISC-V: Don't generate the ELF privilege attributes when no CSR are used.Nelson Chu16-30/+60
gas/ * config/tc-riscv.c (explicit_csr): New static boolean. Used to indicate CSR are explictly used. (riscv_ip): Set explicit_csr to TRUE if any CSR is used. (riscv_write_out_attrs): If we already have set elf priv attributes, then generate them. Otherwise, don't generate them when no CSR are used. * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-11.s: New testcase. * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is used, so we should output the ELF priv attributes. * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is used, so output the priv attributes according to the -mpriv-spec. * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't used, so ignore the -mpriv-spec setting. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-06-04gas: Fix ip2k-elf and xstormy16-elf buildH.J. Lu3-3/+13
Fix ip2k-elf and xstormy16-elf build due to commit e9bffec9afc45cf7c49308f0b4b8cc6bf68f58f2 Author: Jose E. Marchesi <jose.marchesi@oracle.com> Date: Thu Jun 4 16:15:53 2020 +0200 opcodes: discriminate endianness and insn-endianness in CGEN ports * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to cgen_get_insn_value. * config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass endianness to cgen_get_insn_value and cgen_put_insn_value.
2020-06-04gas: simplify code in tc-bpf.c:md_apply_fixJose E. Marchesi2-3/+6
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_apply_fix): Simplify and avoid using cgen_put_insn_value.
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi2-4/+8
cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise.
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi4-5/+20
The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04tcl global directive outside proc body does nothing (gas)Alan Modra7-7/+10
* testsuite/config/default.exp: Remove global directive outside proc body. * testsuite/gas/mep/complex-relocs.exp: Likewise. * testsuite/gas/microblaze/relax_size.exp: Likewise. * testsuite/gas/microblaze/reloc_sym.exp: Likewise. * testsuite/gas/mt/relocs.exp: Likewise. * testsuite/gas/rx/rx.exp: Likewise.
2020-06-03* gas/doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.Stephen Casner2-1/+5
2020-06-02RISC-V: Fix minor bugs in .insn docs.Jim Wilson2-7/+15
This fixes some minor bugs in the docs for the .insn directive pointed out by Frédéric Pétrot, and I added a few more cleanups since I was changing the docs. gas/ PR 26051 * doc/c-riscv.texi (RISC-V-Formats): Add missing I format using simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B formats using simm12(rs1). Correct SB and B to use rs1 and rs2. Move B before SB. Move J before UJ.
2020-06-02gas: Fix checking for backwards .org with negative offsetAlex Coplan8-2/+27
This patch fixes internal errors in (at least) arm and aarch64 GAS when assembling code that attempts a negative .org. The bug appears to be a regression introduced in binutils-2.29 by commit 9875b36538d. * write.c (relax_segment): Fix handling of negative offset when relaxing an rs_org frag. * testsuite/gas/aarch64/org-neg.d: New test. * testsuite/gas/aarch64/org-neg.l: Error output for test. * testsuite/gas/aarch64/org-neg.s: Input for test. * testsuite/gas/arm/org-neg.d: New test. * testsuite/gas/arm/org-neg.l: Error output for test. * testsuite/gas/arm/org-neg.s: Input for test.
2020-05-28Fix all unexpected failures in gas testsuite for pdp11-aout.Stephen Casner6-3/+133
These failures were caused by the PDP11's mix of little-endian octets in shorts but shorts in big endian order for long or quad so regexps did not match. Also tests used addresses as values in .long which required BRD_RELOC_32 that was not implemented. * gas/config/tc-pdp11.c (md_number_to_chars): Implement .quad * gas/testsuite/gas/all/gas.exp: Select alternate test scripts for pdp11, skip octa test completely. * gas/testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s * gas/testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order. * gas/testsuite/gas/all/cond-pdp11.l: Match different octet order. * bfd/pdp11.c: Implement BRD_RELOC_32 to relocate the low 16 bits of addreses in .long (used in testsuites) and .stab values.
2020-05-28[PATCH] gas: Fix comment on definition of frag_grow()Nick Clifton2-3/+7
* frags.c (frag_grow): Fix comment.
2020-05-27Fix PR gas/26001 (pdp11-*-*)Stephen Casner5-1/+41
PR gas/26001 * gas/config/tc-pdp11.c (parse_reg): Distinguish register names from symbols that begin with a register name. * gas/testsuite/gas/pdp11/pdp11.exp: Add test of such symbols. * gas/testsuite/gas/pdp11/pr26001.s: Likewise. * gas/testsuite/gas/pdp11/pr26001.d: Likewise.
2020-05-27RISC-V: Fix missing initialization of riscv_csr_extra structsSimon Cook2-0/+6
The next pointer of struct riscv_csr_extra was not always initilized to NULL or a valid pointer, causing the assembler to attempt to read through an uninitialized pointer on startup. gas/ChangeLog: * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next pointer when creating struct riscv_csr_extra.
2020-05-26gas: Adjust x86 tests for PECOFFH.J. Lu4-1/+11
* testsuite/gas/i386/align-branch-9.d: Updated for PECOFF. * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF. * testsuite/gas/i386/inval-avx512f.l: Updated.
2020-05-26ChangeLog entries for f687f5f563Stefan Schulze Frielinghaus1-0/+7
2020-05-26tc-xgate.c: Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_XH.J. Lu2-4/+12
Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X to silence GCC 10 warning: gas/config/tc-xgate.c:1339:5: error: implicit conversion from ‘enum elf_xgate_reloc_type’ to ‘bfd_reloc_code_real_type’ {aka ‘enum bfd_reloc_code_real’} [-Werror=enum-conversion] 1339 | R_XGATE_PCREL_9); | ^~~~~~~~~~~~~~~ PR gas/26044 * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X instead of R_XGATE_PCREL_X. (xgate_parse_operand): Replace R_XGATE_PCREL_X with BFD_RELOC_XGATE_PCREL_X.
2020-05-26S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus2-8/+16
Accept vector alignment hints on z13 although they are ignored there. The advantage is that any binary compiled for architecture level z13 may run on z14 or later and benefit from vector alignment hints. gas/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector load/store instruction variants with alignment hints. * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store instruction variants with alignment hints. opcodes/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * s390-opc.txt: Relocate vector load/store instructions with additional alignment parameter and change architecture level constraint from z14 to z13.
2020-05-26gas: Silence GCC 10 warning on tc-visium.cH.J. Lu2-1/+7
PR gas/26044 * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26gas: Silence GCC 10 warning tc-vax.cH.J. Lu2-2/+9
PR gas/26044 * config/tc-vax.c (md_estimate_size_before_relax): Replace fragP->fr_literal with &fragP->fr_literal[0]. (md_convert_frag): Likewise.
2020-05-26gas: Silence GCC 10 warning on tc-v850.cH.J. Lu2-2/+8
PR gas/26044 * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26gas: Silence GCC 10 warning on tc-crx.cH.J. Lu2-3/+10
opcode/crx.h has typedef enum { ... MAX_REG } reg; typedef enum { c0 = MAX_REG, } copreg; tc-crx.c has static int getreg_image (reg r) { ... /* Check whether the register is in registers table. */ if (r < MAX_REG) rreg = &crx_regtab[r]; /* Check whether the register is in coprocessor registers table. */ else if (r < (int) MAX_COPREG) rreg = &crx_copregtab[r-MAX_REG]; } Change getreg_image's argument type to int and replace fragP->fr_literal with &fragP->fr_literal[0] to silence GCC 10 warning. PR gas/26044 * config/tc-crx.c (getreg_image): Change argument type to int. (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-26tc-score.c: Replace overlapping sprintf with memmoveH.J. Lu2-8/+18
Fix GCC 10 warning: gas/config/tc-score.c:4575:6: error: ‘sprintf’ argument 3 may overlap destination object ‘keep_data’ [-Werror=restrict] 4575 | sprintf (append_str, "bne %s", keep_data); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ PR gas/26044 * onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping sprintf with memmove.
2020-05-25gas: Silence GCC 10 warning on tc-mcore.cH.J. Lu2-1/+6
* config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-25tc-cr16.c: Use memmove to concatenate 2 overlapping stringsH.J. Lu2-1/+10
PR gas/26041 * config/tc-cr16.c (md_assemble): Use memmove to concatenate 2 overlapping strings.
2020-05-25gas: Silence GCC 10 warning on tc-cr16.cH.J. Lu2-1/+6
* config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal with &fragP->fr_literal[0].
2020-05-25gas: Update fr_literal access in frag for GCC 10H.J. Lu4-3/+10
When access fr_literal in struct frag { ... /* Data begins here. */ char fr_literal[1]; }; with char *buf = fragp->fr_fix + fragp->fr_literal; GCC 10 gave gas/config/tc-csky.c: In function ‘md_convert_frag’: gas/config/tc-csky.c:4507:9: error: writing 1 byte into a region of size 0 [-Werror=stringop-overflow=] 4507 | buf[1] = BYTE_1 (CSKYV1_INST_SUBI | (7 << 4)); | ^ Change char *buf = fragp->fr_fix + fragp->fr_literal; to char *buf = fragp->fr_fix + &fragp->fr_literal[0]; to silence GCC 10 warning. * config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal with &fragp->fr_literal[0]. * config/tc-microblaze.c (md_apply_fix): Likewise. * config/tc-sh.c (md_convert_frag): Likewise.
2020-05-24RISC-V: Gas inserts cfa relocs in wrong section.Jim Wilson2-1/+19
The frag code makes a distinction between inserting frags before the frag chains are chained together and afterward. After chaining, we need to set now_seg before creating the frag. tc-xtensa.c has a function called fix_new_exp_in_seg that handles this right, but switches segments twice each time it is called. In this case, we can inline it and pull the save and restore out of the loop to get better code. gas/ PR 26025 * config/tc-riscv.c (riscv_pre_output_hook): Change s type from const asection to segT. New locals seg and subseg. Call subseg_set before fix_new_exp. Call subseg_set after loop to restore original values.
2020-05-21Replace "if (x) free (x)" with "free (x)", gasAlan Modra13-52/+41
* atof-generic.c: Replace "if (x) free (x)" with "free (x)" throughout. * config/obj-elf.c: Likewise. * config/tc-aarch64.c: Likewise. * config/tc-arm.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-nios2.c: Likewise. * config/tc-tic30.c: Likewise. * ecoff.c: Likewise. * read.c: Likewise. * stabs.c: Likewise. * symbols.c: Likewise. * testsuite/gas/all/test-gen.c: Likewise.
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard ↵Nelson Chu42-2434/+4423
extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter *use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. * elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner5-0/+91
opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov6-10/+21
PR 25992 gas * config/tc-arm.c : Add arm_ext_v8r feature. (it_fsm_post_encode): Check arm_ext_v8r feature. (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature. include * opcode/arm.h (ARM_EXT2_V8R): Define. Modified ARM_AEXT2_V8R.
2020-05-19Use bfd_get_filename throughout gasAlan Modra2-6/+16
* write.c (write_contents): Use bfd_get_filename rather than accessing bfd->filename directly. Use bfd_section_name rather than accessing section->name directly.
generated by cgit v1.1 at 2025-01-28 17:18:17 +0000