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| author | Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> | 2020-05-18 17:22:57 +0200 |
|---|---|---|
| committer | Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> | 2020-05-26 18:15:41 +0200 |
| commit | f687f5f563a6407f74a6f3aacb00f07b1889470b (patch) | |
| tree | c6ce862d321a4cc8e4a82d7f6eba77f568065cfa /gas | |
| parent | 8bbc5da5ee827bd9c962d238777e20db2c100598 (diff) | |
| download | gdb-f687f5f563a6407f74a6f3aacb00f07b1889470b.zip gdb-f687f5f563a6407f74a6f3aacb00f07b1889470b.tar.gz gdb-f687f5f563a6407f74a6f3aacb00f07b1889470b.tar.bz2 | |
S/390: z13: Accept vector alignment hints
Accept vector alignment hints on z13 although they are ignored there.
The advantage is that any binary compiled for architecture level z13 may
run on z14 or later and benefit from vector alignment hints.
gas/ChangeLog:
2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
load/store instruction variants with alignment hints.
* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
instruction variants with alignment hints.
opcodes/ChangeLog:
2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* s390-opc.txt: Relocate vector load/store instructions with
additional alignment parameter and change architecture level
constraint from z14 to z13.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/s390/zarch-z13.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/s390/zarch-z13.s | 12 |
2 files changed, 16 insertions, 8 deletions
diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d index e61352b..bfb6fe1 100644 --- a/gas/testsuite/gas/s390/zarch-z13.d +++ b/gas/testsuite/gas/s390/zarch-z13.d @@ -17,7 +17,6 @@ Disassembly of section .text: .*: e7 f0 fd fc 10 46 [ ]*vgmh %v15,253,252 .*: e7 f0 fd fc 20 46 [ ]*vgmf %v15,253,252 .*: e7 f0 fd fc 30 46 [ ]*vgmg %v15,253,252 -.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\) .*: e7 f1 00 00 04 56 [ ]*vlr %v15,%v17 .*: e7 f6 9f a0 d0 05 [ ]*vlrep %v15,4000\(%r6,%r9\),13 .*: e7 f6 9f a0 00 05 [ ]*vlrepb %v15,4000\(%r6,%r9\) @@ -42,7 +41,6 @@ Disassembly of section .text: .*: e7 f6 9f a0 10 04 [ ]*vllezh %v15,4000\(%r6,%r9\) .*: e7 f6 9f a0 20 04 [ ]*vllezf %v15,4000\(%r6,%r9\) .*: e7 f6 9f a0 30 04 [ ]*vllezg %v15,4000\(%r6,%r9\) -.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\) .*: e7 f6 9f a0 d0 07 [ ]*vlbb %v15,4000\(%r6,%r9\),13 .*: e7 f6 9f a0 d0 22 [ ]*vlvg %v15,%r6,4000\(%r9\),13 .*: e7 f6 9f a0 00 22 [ ]*vlvgb %v15,%r6,4000\(%r9\) @@ -98,12 +96,10 @@ Disassembly of section .text: .*: e7 f1 00 00 04 5f [ ]*vsegb %v15,%v17 .*: e7 f1 00 00 14 5f [ ]*vsegh %v15,%v17 .*: e7 f1 00 00 24 5f [ ]*vsegf %v15,%v17 -.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\) .*: e7 f6 9f a0 d0 08 [ ]*vsteb %v15,4000\(%r6,%r9\),13 .*: e7 f6 9f a0 d0 09 [ ]*vsteh %v15,4000\(%r6,%r9\),13 .*: e7 f6 9f a0 d0 0b [ ]*vstef %v15,4000\(%r6,%r9\),13 .*: e7 f6 9f a0 d0 0a [ ]*vsteg %v15,4000\(%r6,%r9\),13 -.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\) .*: e7 f6 9f a0 00 3f [ ]*vstl %v15,%r6,4000\(%r9\) .*: e7 f1 00 00 d4 d7 [ ]*vuph %v15,%v17,13 .*: e7 f1 00 00 04 d7 [ ]*vuphb %v15,%v17 @@ -680,3 +676,11 @@ Disassembly of section .text: .*: e3 69 b8 f0 fd 3b [ ]*lzrf %r6,-10000\(%r9,%r11\) .*: e3 69 b8 f0 fd 2a [ ]*lzrg %r6,-10000\(%r9,%r11\) .*: b9 3c 00 69 [ ]*prno %r6,%r9 +.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\) +.*: e7 f6 9f a0 d0 06 [ ]*vl %v15,4000\(%r6,%r9\),13 +.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\) +.*: e7 f1 6f a0 d4 36 [ ]*vlm %v15,%v17,4000\(%r6\),13 +.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\) +.*: e7 f6 9f a0 d0 0e [ ]*vst %v15,4000\(%r6,%r9\),13 +.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\) +.*: e7 f1 6f a0 d4 3e [ ]*vstm %v15,%v17,4000\(%r6\),13 diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s index c2964d8..646dd30 100644 --- a/gas/testsuite/gas/s390/zarch-z13.s +++ b/gas/testsuite/gas/s390/zarch-z13.s @@ -11,7 +11,6 @@ foo: vgmh %v15,253,252 vgmf %v15,253,252 vgmg %v15,253,252 - vl %v15,4000(%r6,%r9) vlr %v15,%v17 vlrep %v15,4000(%r6,%r9),13 vlrepb %v15,4000(%r6,%r9) @@ -36,7 +35,6 @@ foo: vllezh %v15,4000(%r6,%r9) vllezf %v15,4000(%r6,%r9) vllezg %v15,4000(%r6,%r9) - vlm %v15,%v17,4000(%r6) vlbb %v15,4000(%r6,%r9),13 vlvg %v15,%r6,4000(%r9),13 vlvgb %v15,%r6,4000(%r9) @@ -92,12 +90,10 @@ foo: vsegb %v15,%v17 vsegh %v15,%v17 vsegf %v15,%v17 - vst %v15,4000(%r6,%r9) vsteb %v15,4000(%r6,%r9),13 vsteh %v15,4000(%r6,%r9),13 vstef %v15,4000(%r6,%r9),13 vsteg %v15,4000(%r6,%r9),13 - vstm %v15,%v17,4000(%r6) vstl %v15,%r6,4000(%r9) vuph %v15,%v17,13 vuphb %v15,%v17 @@ -674,3 +670,11 @@ foo: lzrf %r6,-10000(%r9,%r11) lzrg %r6,-10000(%r9,%r11) ppno %r6,%r9 + vl %v15,4000(%r6,%r9) + vl %v15,4000(%r6,%r9),13 + vlm %v15,%v17,4000(%r6) + vlm %v15,%v17,4000(%r6),13 + vst %v15,4000(%r6,%r9) + vst %v15,4000(%r6,%r9),13 + vstm %v15,%v17,4000(%r6) + vstm %v15,%v17,4000(%r6),13 |