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2018-05-16NDS32/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-2/+7
Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../gas/config/tc-nds32.c: In function 'md_assemble': .../gas/config/tc-nds32.c:5212: error: declaration of 'expr' shadows a global declaration .../gas/expr.h:180: error: shadowed declaration is here make[4]: *** [tc-nds32.o] Error 1 which for versions of GCC before 4.8 prevent support for NDS32 targets from being built. See also GCC PR c/53066. gas/ * tc-nds32.c (md_assemble): Rename `expr' local variable to `insn_expr'.
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina7-5/+35
This patch adds constraints for read and write only system registers with the msr and mrs instructions. The code will treat having both flags set and none set as the same. These flags add constraints that must be matched up. e.g. a system register with a READ only flag set, can only be used with mrs. If The constraint fails a warning is emitted. Examples of the warnings generated: test.s: Assembler messages: test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3' test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0' test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' and disassembly notes: 0000000000000000 <main>: 0: d5130503 msr dbgdtrtx_el0, x3 4: d5130503 msr dbgdtrtx_el0, x3 8: d5330503 mrs x3, dbgdtrrx_el0 c: d5330503 mrs x3, dbgdtrrx_el0 10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register. Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during disassembly the constraints are use to disambiguate between the two. An exact constraint match is always prefered over partial ones if available. As always the warnings can be suppressed with -w and also be made errors using warnings as errors. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. gas/ PR binutils/21446 * testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test. * testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise. * testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise. * testsuite/gas/aarch64/sysreg-diagnostic.s: New. * testsuite/gas/aarch64/sysreg-diagnostic.l: New. * testsuite/gas/aarch64/sysreg-diagnostic.d: New. include/ PR binutils/21446 * opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New. opcodes/ PR binutils/21446 * aarch64-asm.c (opintl.h): Include. (aarch64_ins_sysreg): Enforce read/write constraints. * aarch64-dis.c (aarch64_ext_sysreg): Likewise. * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. (F_REG_READ, F_REG_WRITE): New. * aarch64-opc.c (aarch64_print_operand): Generate notes for AARCH64_OPND_SYSREG. (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. * aarch64-tbl.h (aarch64_opcode_table): Add constraints to msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on ↵Tamar Christina2-51/+89
AArch64 This patch adds a new platform option "notes" that can be used to indicate if disassembly notes should be placed in the disassembly as comments. These notes can contain information about a failing constraint such as reading from a write-only register. The disassembly will not be blocked because of this but -M notes will emit a comment saying that the operation is not allowed. For assembly this patch adds a new non-fatal status for errors. This is essentially a warning. The reason for not creating an actual warning type is that this causes the interaction between the ordering of warnings and errors to be problematic. Currently the error buffer is almost always filled because of the way operands are matched during assembly. An earlier template may have put an error there that would only be displayed if no other template matches or generates a higher priority error. But by definition a warning is lower priority than a warning, so the error (which is incorrect if another template matched) will supersede the warning. By treating warnings as errors and only later relaxing the severity this relationship keeps working and the existing reporting infrastructure can be re-used. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. * NEWS: Document notes and warnings. gas/ PR binutils/21446 * config/tc-aarch64.c (print_operands): Indicate no notes. (output_operand_error_record): Support non-fatal errors. (output_operand_error_report, warn_unpredictable_ldst, md_assemble): Likewise. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal. (aarch64_print_operand): Support notes. opcodes/ PR binutils/21446 * aarch64-dis.c (no_notes: New. (parse_aarch64_dis_option): Support notes. (aarch64_decode_insn, print_operands): Likewise. (print_aarch64_disassembler_options): Document notes. * aarch64-opc.c (aarch64_print_operand): Support notes.
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and ↵Tamar Christina2-10/+25
report why. This patch if the first patch in a series to add the ability to add constraints to system registers that an instruction must adhere to in order for the register to be usable with that instruction. These constraints can also be used to disambiguate between registers with the same encoding during disassembly. This patch adds a new flags entry in the sysreg structures and ensures it is filled in and read out during assembly/disassembly. It also adds the ability for the assemble and disassemble functions to be able to gracefully fail and re-use the existing error reporting infrastructure. The return type of these functions are changed to a boolean to denote success or failure and the error structure is passed around to them. This requires aarch64-gen changes so a lot of the changes here are just mechanical. gas/ PR binutils/21446 * config/tc-aarch64.c (parse_sys_reg): Return register flags. (parse_operands): Fill in register flags. gdb/ PR binutils/21446 * aarch64-tdep.c (aarch64_analyze_prologue, aarch64_software_single_step, aarch64_displaced_step_copy_insn): Indicate not interested in errors. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. (aarch64_decode_insn): Accept error struct. opcodes/ PR binutils/21446 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean and take error struct. * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, aarch64_ins_reglist, aarch64_ins_ldst_reglist, aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, aarch64_ext_reglist, aarch64_ext_ldst_reglist, aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. (determine_disassembling_preference, aarch64_decode_insn, print_insn_aarch64_word, print_insn_data): Take errors struct. (print_insn_aarch64): Use errors. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-gen.c (print_operand_inserter): Use errors and change type to boolean in aarch64_insert_operan. (print_operand_extractor): Likewise. * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-14Stop generating GNU build notes for linkonce sections.Nick Clifton2-48/+49
gas * write.c (maybe_generate_build_notes): Generate notes on a per-code-section basis. Skip linkonce sections. ld * testsuite/ld-elf/notes.exp: New file: Run new test. * testsuite/ld-elf/note1_1.s: New file: Source file for test. * testsuite/ld-elf/note1_2.s: New file: Source file for test. * testsuite/ld-elf/note1.r: New file: Expected readelf output.
2018-05-14Fix a problem in the assembler when checking for overlapping input and ↵Nick Clifton2-1/+7
output files on non-POSIX compliant systems. PR 23153 * as.c (main): When checking for an output file that is also an input file, also check that the inode is not zero.
2018-05-12score gcc-8 warning fixesAlan Modra2-70/+72
Rather than just silencing the gcc-8 warnings, I decided to rewrite the buffer handling in the two functions where gcc was warning. The rest of the file could do with the same treatment. * config/tc-score.c (s3_do_macro_bcmp): Don't use fixed size buffers. (s3_do_macro_bcmpz): Likewise.
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina8-43/+37
This patch makes it possible to use an integer immediate with the fmov instructions allowing you to simply write fmov d0, #2 instead of needing fmov d0, #2.0. The parse double function already know to deal with this so we just need to list the restriction put in place in parser. The is considered a QoL improvement for hand assembly writers and allows more code portability between assembler. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Remove restrictions. * testsuite/gas/aarch64/diagnostic.s: Move fmov int test to.. * testsuite/gas/aarch64/fpmov.s: Here. * testsuite/gas/aarch64/fpmov.d: Update results with fmov. * testsuite/gas/aarch64/diagnostic.l: Remove fmov values. * testsuite/gas/aarch64/sve-invalid.s: Update test files. * testsuite/gas/aarch64/sve-invalid.l: Likewise
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina4-0/+34
This patch fixes the case where you want to use an integer value the floating point immediate to a VFP vmov instruction such as vmovmi.f32 s27, #11. If the immediate is not a float we convert it and copy it's representation into the imm field and then carry on validating as if we originally entered a floating point immediate. The is considered a QoL improvement for hand assembly writers and allows more code portability between assembler. gas/ * gas/config/tc-arm.c (do_neon_mov): Allow integer literal for float immediate. * testsuite/gas/arm/vfp-mov-enc.s: New. * testsuite/gas/arm/vfp-mov-enc.d: New.
2018-05-09gas: xtensa: fix literal movementMax Filippov9-21/+116
Not all literals need to be moved in the presence of --text-section-literals or --auto-litpools, but only those created by .literal pseudo op or generated as a result of relaxation. Attempts to move other literals may result in abnormal termination of the assembler due to the following assertion failure: Internal error in xg_find_litpool at gas/config/tc-xtensa.c:11209. The same assertion may also be triggered by attempting to assign literal pools to literals in .init and .fini sections; don't try to do that. gas/ 2018-05-09 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_is_init_fini): New function. (xtensa_move_literals): Only attempt to assign literal pool to literals with tc_frag_data.is_literal mark and not in .init or .fini sections. Join nested 'if' conditions to simplify function structure. (xtensa_switch_to_non_abs_literal_fragment): Use xtensa_is_init_fini to test for .init/.fini sections. * testsuite/gas/xtensa/all.exp (auto-litpools-3) (auto-litpools-4, text-section-literals-1): New tests. * testsuite/gas/xtensa/auto-litpools-3.d: New test results. * testsuite/gas/xtensa/auto-litpools-3.s: New test source. * testsuite/gas/xtensa/auto-litpools-4.d: New test results. * testsuite/gas/xtensa/auto-litpools-4.s: New test source. * testsuite/gas/xtensa/text-section-literals-1.d: New test results. * testsuite/gas/xtensa/text-section-literals-1.s: New test source.
2018-05-09Fix binary compatibility between GCC and the TI compiler for the PRU target.Dimitar Dimitrov6-9/+37
My original implementation for LDI32 pseudo does not conform to the TI ABI. I wrongly documented my TI PRU ELF object files inspection, which got propagated into my binutils implementation. Issue was exposed when running the GCC ABI testsuite against TI toolchain. According to TI ABI, LDI32 must use first LDI instruction to load the MSB 16bits, and second LDI instruction for the LSB 16bits. This patch will break binary compatibility with previously released binutils versions for PRU. Still, I think it is better to fix binutils to conform to the chip vendor ABI. bfd * elf32-pru.c (pru_elf32_do_ldi32_relocate): Make LDI32 relocation conformant to TI ABI. (pru_elf32_relax_section): Likewise. (pru_elf_relax_delete_bytes): Fix offsets for new LDI32 code. * elf32-pru.c (pru_elf32_do_ldi32_relocate): Ignore addend. (pru_elf32_pmem_relocate): Trap - should not get here. (pru_elf32_relocate_section): Add support for REL relocations. (elf_info_to_howto_rel): Enable REL. (elf_backend_may_use_rel_p): Likewise. (elf_backend_may_use_rela_p): Likewise. (elf_backend_default_use_rela_p): Likewise. gas * config/tc-pru.c (md_apply_fix): Make LDI32 relocation conformant to TI ABI. (pru_assemble_arg_i): Likewise. (output_insn_ldi32): Likewise. * testsuite/gas/pru/ldi.d: Update test for the now fixed LDI32. * gas/config/tc-pru.c (pru_assemble_arg_b): Check imm8 operand range. * gas/testsuite/gas/pru/illegal2.l: New test. * gas/testsuite/gas/pru/illegal2.s: New test. * gas/testsuite/gas/pru/pru.exp: Register new illegal2 test. ld * scripttempl/pru.sc: Add LD sections to allow linking TI toolchain object files. * scripttempl/pru.sc: Switch to init_array. * testsuite/ld-pru/ldi32.d: Update LDI32 test to conform to TI ABI. * testsuite/ld-pru/norelax_ldi32-data.d: Likewise. * testsuite/ld-pru/norelax_ldi32-dis.d: Likewise. * testsuite/ld-pru/relax_ldi32-data.d: Likewise. * testsuite/ld-pru/relax_ldi32-dis.d: Likewise.
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson5-2/+26
gas/ * testsuite/gas/riscv/c-zero-imm.d: Add more tests. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled future test for RV128 support. * testsuite/gas/riscv/c-zero-reg.s: Likewise. include/ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. (MATCH_C_SRAI64, MASK_C_SRAI64): New. (MATCH_C_SLLI64, MASK_C_SLLI64): New. opcodes/ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. (match_c_slli64, match_srxi_as_c_srxi): New. (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. <c.slli, c.srli, c.srai>: Use match_s_slli. <c.slli64, c.srli64, c.srai64>: New.
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu14-0/+199
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New file. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (Gva): New. (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). (OP_G): Handle va_mode. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2-3/+12
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that the size of register operand is controlled by the address size prefix. This will be used by Intel MOVDIRI and MOVDIR64B instructions later. gas/ * config/tc-i386.c (process_suffix): Check addrprefixopreg instead of addrprefixop0. opcodes/ * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with AddrPrefixOpReg. * i386-opc.h (AddrPrefixOp0): Renamed to ... (AddrPrefixOpReg): This. (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner2-38/+34
include/ * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. opcodes/ * ppc-opc.c (powerpc_num_opcodes): Likewise. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite initialization loop. (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize only once. gas/ * config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code to dump the entire opcode table. (ppc_setup_opcodes) <spe2_opcodes>: Likewise. (ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of opcode index.
2018-05-06gas/i386/xmmhi32.d: Also allow dir32 relocationH.J. Lu2-42/+46
Also allow dir32 relocation to support mingw targets. * testsuite/gas/i386/xmmhi32.d: Also allow dir32 relocation.
2018-05-06i386: Append ".p2align 4,0" to gas testsH.J. Lu9-0/+23
Append ".p2align 4,0" to i386 assembler tests to support mingw targets. * testsuite/gas/i386/avx512f-plain.s: Append ".p2align 4,0". * testsuite/gas/i386/avx512vl-plain.s: Likewise. * testsuite/gas/i386/bnd.s: Likewise. * testsuite/gas/i386/stN.s: Likewise. * testsuite/gas/i386/avx512f-plain.l: Updated. * testsuite/gas/i386/avx512vl-plain.l: Likewise. * testsuite/gas/i386/bnd.l: Likewise. * testsuite/gas/i386/stN.l: Likewise.
2018-05-04-Wstringop-truncation warningsAlan Modra3-9/+18
This patch is aimed at silencing gcc8 -Wstringop-truncation warnings. Unfortunately adding __attribute__ ((__nonstring)) doesn't work in a number of the places patched here, (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643) so if you have recent glibc headers installed you'll need to configure binutils with --disable-werror to compile using gcc8 or gcc9. include/ * ansidecl.h: Import from gcc. * coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING to s_name. (struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name. bfd/ * elf-linux-core.h (struct elf_external_linux_prpsinfo32_ugid32), (struct elf_external_linux_prpsinfo32_ugid16), (struct elf_external_linux_prpsinfo64_ugid32), (struct elf_external_linux_prpsinfo64_ugid16): Add ATTRIBUTE_NONSTRING to pr_fname and pr_psargs fields. Remove GCC diagnostic pragmas. Move comment to.. * elf.c (elfcore_write_prpsinfo): ..here. Indent nested preprocessor directives. * elf32-arm.c (elf32_arm_nabi_write_core_note): Add ATTRIBUTE_NONSTRING to data. * elf32-ppc.c (ppc_elf_write_core_note): Likewise. * elf32-s390.c (elf_s390_write_core_note): Likewise. * elf64-s390.c (elf_s390_write_core_note): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise. * elf64-x86-64.c (elf_x86_64_write_core_note): Add GCC diagnostic pragmas. * peXXigen.c (_bfd_XXi_swap_scnhdr_out): Use strnlen to avoid false positive gcc-8 warning. gas/ * config/obj-evax.c (shorten_identifier): Use memcpy in place of strncpy. * config/obj-macho.c (obj_mach_o_make_or_get_sect): Ensure segname and sectname fields are NUL terminated.
2018-05-01Updated Spanish translation for the gas sub-directory.Nick Clifton2-1394/+909
2018-04-27testsuite: Support filtering targets by TCL procedure in `run_dump_test'Maciej W. Rozycki2-16/+26
Implement a more complex way of selecting targets to include or exclude with `run_dump_test' cases, by extending the syntax for the `target', `not-target', `skip' and `not-skip' options (with the binutils and GAS test suites) and the `target', `alltargets' and `notarget' options (with the LD test suite) to also accept a name of a TCL procedure instead of a target triplet glob matching expression. The result, 1 or 0, of the procedure determines whether the test is to be run or not. This mimics and expands `dg-require-effective-target' from the GCC test suite. Names of TCL procedures are supplied in square brackets `[]' as with TCL procedure calls, observing that target triplet glob matching expressions do not normally start and end with matching square brackets both at a time. Arguments for procedures are allowed if required. Having a way to specify a complex condition for a `run_dump_test' case to run has the advantage of keeping it local within the test case itself where tool options related to the check might be also present, removing the need to wrap `run_dump_test' calls into an `if' block whose only reason is to do a feature check, and ultimately lets one have the test reported as UNSUPPORTED automagically if required (not currently supported by the `run_dump_test' options used for LD). binutils/ * testsuite/lib/binutils-common.exp (match_target): New procedure. * testsuite/lib/utils-lib.exp (run_dump_test): Use it in place of `istarget' for matching with `target', `not-target', `skip' and `not-skip' options. gas/ * testsuite/lib/gas-defs.exp (run_dump_test): Use `match_target' in place of `istarget' for matching with `target', `not-target', `skip' and `not-skip' options. ld/ * testsuite/lib/ld-lib.exp (run_dump_test): Use `match_target' in place of `istarget' for matching with `target', `alltargets' and `notarget' options.
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist14-197/+0
This reverts commit a914a7c95895161c99533d5919b8504b37ea54a0.
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist14-0/+197
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New test. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9. (prefix_table): New instructions (see prefix above). Add Gva macro and handling in OP_G. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Likewise. (opcode_modifiers): Add AddrPrefixOpReg. (i386_opcode_modifier): Likewise. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-26Extend the assembler so that it can automatically generate GNU Build ↵Nick Clifton10-20/+314
attribute notes if none are present in the input files. gas * as.c (flag_generate_build_notes): New variable. (show_usage): Add entry for --generate-missing-build-notes. (parse_args): Parse --generate-missing-build-notes. * as.h: Export flag_generate_build_notes. * symbols.c (save_symbol_name): Ensure that the name parameter is not NULL. * write.c (create_obj_attrs_section): Reformat. (create_note_reloc): New function - creates a relocation for a field in a GNU Build attribute note. (maybe_generate_build_notes): New function - created GNU Build attribute notes if none are present in the output file. (write_object_file): Call maybe_generate_build_notes. * configure.ac (--enable-generate-build-notes): New option. * NEWS: Announce the new feature. * doc/as.textinfo: Document the new option. * config.in: Regenerate. * configure: Regenerate. binutils* readelf.c (is_32bit_abs_reloc): Support R_PARISC_DIR32 as a 32-bit absolute reloc for the HPPA target. * testsuite/binutils-all/note-5.d: New test. * testsuite/binutils-all/note-5.s: Source file for new test. * testsuite/binutils-all/objcopy.exp: Run new test.
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich2-17/+61
There's little point carrying up to three templates per insn flavor when the sole difference is operand size and the dependency on AVX512VL being enabled. Instead the need for AVX512VL can be derived from an operand allowing for ZMMword as well as one or both or XMMword and YMMword (irrespective of whether this is a register or memory operand). Without further abstraction to deal with the different Disp8MemShift values between the templates, only a limited set (mostly ones only allowing for non-memory operands) can be folded, which is being done here. Also drop IgnoreSize wherever possible from anything that's being touched anyway.
2018-04-26x86: also optimize zeroing-masking variants of insnsJan Beulich8-73/+84
When zeroing an element of a register it doesn't matter whether the zero results from the actual operation (xor, sub, or nand) or from the zeroing-masking taking effect due to a clear mask register bit.
2018-04-26x86: properly force / avoid forcing EVEX encodingJan Beulich7-7/+76
Pseudo prefixes are supposed to be a hint only - when the specific encoding can't be used to encode an insn, silently override it. But this overriding must only happen after the respective check, to avoid forcing EVEX encoding because of something that isn't a valid register name in the given context.
2018-04-26x86: CpuXSAVE is a prereq for various other featuresJan Beulich4-0/+56
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as XRSTOR should be enabled when enabling these ISA extensions. Leverage these implications to shorten some of the cpu_flag_init[] entries.
2018-04-26x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMaskJan Beulich7-11/+110
It's not clear to me why they had been introduced - the respective comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers are very well supported (and necessary) with just AVX512F.
2018-04-26x86: don't recognize bnd<N> as registers without CpuMPXJan Beulich5-0/+29
This is just like for all other extended/optional register sets.
2018-04-26x86: x87-related adjustmentsJan Beulich7-6/+55
Neither 287 wrt 8087 nor 387 wrt 287 are proper supersets - in each case some insns get removed from the ISA (they become NOPs, but code intended for newer co-processors should not use them). Furthermore with .no87, ST should not be recognized as a register name.
2018-04-26x86: fix indentation in build_modrm_byte()Jan Beulich2-39/+43
The VEX3SOURCES code was (originally) written with just space indentation, which is not in line with general coding style as well as the style later in the function.
2018-04-26x86: move and fold common code in build_modrm_byte()Jan Beulich2-29/+18
The source and reg_slot calculations in the VEX3SOURCES only depend on the number of immediate operands.
2018-04-26x86: drop VexImmExtJan Beulich2-7/+8
It's only used in assertions, and hence not really needed for correct code generation.
2018-04-26x86: tighten assertion in build_modrm_byte()Jan Beulich2-4/+8
All VEX3SOURCES cases should have VexW set, and all should have a SIMD register destination.
2018-04-26x86: drop dead code from build_modrm_byte()Jan Beulich2-19/+10
There are no templates with VexImmExt and ImmExt set at the same time. There are also no VEX3SOURCES templates with CpuFMA. I assume both are left-overs from the implementation of an early specification which was later revised.
2018-04-25[ARM] Add TLS relocations for FDPIC.Christophe Lyon2-1/+34
Define and handle TLS relocations for FDPIC in BFD and gas. In gas, the new relocations are rejected if the --fdpic option was not specified. We also define the __tdata_start symbol to mark the start of the .tdata section. This allows FDPIC static binaries to find the start of .tdata section, since phdr->p_vaddr of TLS segment is not a valid value for FDPIC. 2018-04-25 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> bfd/: * bfd-in2.h (BFD_RELOC_ARM_TLS_GD32_FDPIC) (BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC): New relocations. * elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC relocations. (elf32_arm_reloc_map): Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC. (struct elf32_arm_link_hash_table): Update comment. (elf32_arm_final_link_relocate): Handle TLS FDPIC relocations. (IS_ARM_TLS_RELOC): Likewise. (elf32_arm_check_relocs): Likewise. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_size_dynamic_sections): Update comment. * reloc.c: Add BFD_RELOC_ARM_TLS_GD32_FDPIC, BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC. gas/ * config/tc-arm.c (reloc_names): Add TLSGD_FDPIC, TLSLDM_FDPIC, GOTTPOFF_FDIC relocations. (md_apply_fix): Handle the new TLS FDPIC relocations. (tc_gen_reloc): Likewise. (arm_fix_adjustable): Likewise. include/ * elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC. ld/ * scripttempl/elf.sc: Define __tdata_start for .tdata section.
2018-04-25[ARM] Add FDPIC relocations definitionsChristophe Lyon4-1/+65
Add FDPIC relocation definitions in BFD and gas. Gas rejects them if the --fdpic option was not specified. 2018-04-25 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> bfd/ * bfd-in2.c (BFD_RELOC_ARM_GOTFUNCDESC) (BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC) (BFD_RELOC_ARM_FUNCDESC_VALUE): New. * elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC, R_ARM_FUNCDESC, R_ARM_FUNCDESC_VALUE. (elf32_arm_howto_from_type): Take new members of elf32_arm_howto_table_2 into account. (elf32_arm_reloc_map): Add BFD_RELOC_ARM_GOTFUNCDESC, BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC, BFD_RELOC_ARM_FUNCDESC_VALUE. * reloc.c: Add BFD_RELOC_ARM_GOTFUNCDESC, BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC, BFD_RELOC_ARM_FUNCDESC_VALUE. gas/ * config/tc-arm.c (reloc_names): Add gotfuncdesc, gotofffuncdesc, funcdesc. (md_apply_fix): Support the new relocations. (tc_gen_reloc): Likewise. * testsuite/gas/arm/reloc-fdpic.d: New. * testsuite/gas/arm/reloc-fdpic.s: New. include/ * elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC) (R_ARM_FUNCDESC) (R_ARM_FUNCDESC_VALUE): Define new relocations.
2018-04-25[ARM] Add FDPIC OSABI flag support.Christophe Lyon2-3/+41
ELF files targetting ARM FDPIC use the ELFOSABI_ARM_FDPIC flag. Set it appropriately in file generators (eg. gas), and handle it in readers (eg. readelf). 2018-04-25 Christophe Lyon <christophe.lyon@st.com> Mickaël Guêné <mickael.guene@st.com> bfd/ * elf32-arm.c (elf32_arm_print_private_bfd_data): Support EF_ARM_PIC and ELFOSABI_ARM_FDPIC. (elf32_arm_post_process_headers): Support ELFOSABI_ARM_FDPIC. (ELF_OSABI): Define to ELFOSABI_ARM_FDPIC. binutils/ * readelf.c (decode_ARM_machine_flags): Support EF_ARM_PIC. (get_osabi_name): Support ELFOSABI_ARM_FDPIC. gas/ * config/tc-arm.c (arm_fdpic): New. (elf32_arm_target_format): Support FDPIC. (OPTION_FDPIC): New. (md_longopts): Support FDPIC. (md_parse_option): Likewise. (md_show_usage): Likewise. include/ * elf/arm.h (EF_ARM_FDPIC): New.
2018-04-25Fix the mask for the sqrdml(a|s)h instructions.Tamar Christina4-125/+10064
Rn is supposed to have a 5 bit range but instead was given 4 bits causing these instructions to disassemble as unknown instructions. opcodes/ * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. gas/ * testsuite/gas/aarch64/rdma.s: Test for larger register numbers. * testsuite/gas/aarch64/rdma.d: Update results. * testsuite/gas/aarch64/rdma-directive.d: Likewise.
2018-04-25Updated Spanish translation for the gas directory.Nick Clifton2-559/+432
2018-04-25Remove arm-aout and arm-coff supportAlan Modra159-233/+311
This also removes arm-netbsd (not arm-netbsdelf!), arm-openbsd, and arm-riscix. Those targets weren't on the obsolete list but they are all aout, and it doesn't make all that much sense to remove arm-aout without removing them too. bfd/ * Makefile.am: Remove arm-aout and arm-coff support. * config.bfd: Likewise. * configure.ac: Likewise. * targets.c: Likewise. * aout-arm.c: Delete. * armnetbsd.c: Delete. * riscix.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/arm/objdump.exp: Remove arm-aout and arm-coff support. * testsuite/binutils-all/objcopy.exp: Likewise. * testsuite/lib/binutils-common.exp: Likewise. gas/ * Makefile.am: Remove arm-aout and arm-coff support. * config/tc-arm.c: Likewise. * config/tc-arm.h: Likewise. * configure.tgt: Likewise. * testsuite/gas/aarch64/codealign.d: Likewise. * testsuite/gas/aarch64/mapping.d: Likewise. * testsuite/gas/aarch64/mapping2.d: Likewise. * testsuite/gas/arm/adds-thumb1-reloc-local-armv7-m.d: Likewise. * testsuite/gas/arm/adds-thumb1-reloc-local.d: Likewise. * testsuite/gas/arm/addsw-bad.d: Likewise. * testsuite/gas/arm/align.d: Likewise. * testsuite/gas/arm/align64.d: Likewise. * testsuite/gas/arm/arch7.d: Likewise. * testsuite/gas/arm/arch7a-mp.d: Likewise. * testsuite/gas/arm/arch7em.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/arm-it-auto-2.d: Likewise. * testsuite/gas/arm/arm-it-auto-3.d: Likewise. * testsuite/gas/arm/arm-it-auto.d: Likewise. * testsuite/gas/arm/arm-it-bad-2.d: Likewise. * testsuite/gas/arm/arm-it.d: Likewise. * testsuite/gas/arm/armv7e-m+fpv5-d16.d: Likewise. * testsuite/gas/arm/armv7e-m+fpv5-sp-d16.d: Likewise. * testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: Likewise. * testsuite/gas/arm/armv8-2-fp16-scalar.d: Likewise. * testsuite/gas/arm/armv8-2-fp16-simd-thumb.d: Likewise. * testsuite/gas/arm/armv8-2-fp16-simd.d: Likewise. * testsuite/gas/arm/armv8-a+crypto.d: Likewise. * testsuite/gas/arm/armv8-a+fp.d: Likewise. * testsuite/gas/arm/armv8-a+ras.d: Likewise. * testsuite/gas/arm/armv8-a+rdma-warning.d: Likewise. * testsuite/gas/arm/armv8-a+rdma.d: Likewise. * testsuite/gas/arm/armv8-a+simd.d: Likewise. * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8-r+fp.d: Likewise. * testsuite/gas/arm/armv8-r+simd.d: Likewise. * testsuite/gas/arm/armv8-r-barrier-thumb.d: Likewise. * testsuite/gas/arm/armv8_1-a+simd.d: Likewise. * testsuite/gas/arm/armv8_2+rdma.d: Likewise. * testsuite/gas/arm/armv8_2-a.d: Likewise. * testsuite/gas/arm/armv8_3-a-fp.d: Likewise. * testsuite/gas/arm/armv8_3-a-simd.d: Likewise. * testsuite/gas/arm/armv8a-automatic-hlt.d: Likewise. * testsuite/gas/arm/armv8a-automatic-lda.d: Likewise. * testsuite/gas/arm/attr-syntax.d: Likewise. * testsuite/gas/arm/automatic-bw.d: Likewise. * testsuite/gas/arm/automatic-cbz.d: Likewise. * testsuite/gas/arm/automatic-clrex.d: Likewise. * testsuite/gas/arm/automatic-lda.d: Likewise. * testsuite/gas/arm/automatic-ldaex.d: Likewise. * testsuite/gas/arm/automatic-ldaexb.d: Likewise. * testsuite/gas/arm/automatic-ldrex.d: Likewise. * testsuite/gas/arm/automatic-ldrexd.d: Likewise. * testsuite/gas/arm/automatic-movw.d: Likewise. * testsuite/gas/arm/automatic-sdiv.d: Likewise. * testsuite/gas/arm/automatic-strexb.d: Likewise. * testsuite/gas/arm/barrier-bad-thumb.d: Likewise. * testsuite/gas/arm/barrier-bad.d: Likewise. * testsuite/gas/arm/barrier-thumb.d: Likewise. * testsuite/gas/arm/barrier.d: Likewise. * testsuite/gas/arm/bignum1.d: Likewise. * testsuite/gas/arm/blx-bad.d: Likewise. * testsuite/gas/arm/blx-bl-convert.d: Likewise. * testsuite/gas/arm/blx-local.s: Likewise. * testsuite/gas/arm/crc32-armv8-a-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/dis-data.d: Likewise. * testsuite/gas/arm/dis-data2.d: Likewise. * testsuite/gas/arm/dis-data3.d: Likewise. * testsuite/gas/arm/eabi_attr_1.d: Likewise. * testsuite/gas/arm/fp-save.d: Likewise. * testsuite/gas/arm/group-reloc-alu-encoding-bad.d: Likewise. * testsuite/gas/arm/group-reloc-alu-parsing-bad.d: Likewise. * testsuite/gas/arm/group-reloc-alu.d: Likewise. * testsuite/gas/arm/group-reloc-ldc-encoding-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldc-parsing-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldc.d: Likewise. * testsuite/gas/arm/group-reloc-ldr-encoding-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldr-parsing-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldr.d: Likewise. * testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d: Likewise. * testsuite/gas/arm/group-reloc-ldrs.d: Likewise. * testsuite/gas/arm/insn-error-a.d: Likewise. * testsuite/gas/arm/insn-error-t.d: Likewise. * testsuite/gas/arm/inst-po-2.d: Likewise. * testsuite/gas/arm/inst-po-3.d: Likewise. * testsuite/gas/arm/inst-po-be.d: Likewise. * testsuite/gas/arm/inst-po.d: Likewise. * testsuite/gas/arm/ldconst.d: Likewise. * testsuite/gas/arm/ldgesb-bad.d: Likewise. * testsuite/gas/arm/ldgesh-bad.d: Likewise. * testsuite/gas/arm/ldst-offset0.d: Likewise. * testsuite/gas/arm/local_function.d: Likewise. * testsuite/gas/arm/local_label_coff.d: Likewise. * testsuite/gas/arm/local_label_elf.d: Likewise. * testsuite/gas/arm/mapping.d: Likewise. * testsuite/gas/arm/mapping2.d: Likewise. * testsuite/gas/arm/mapping3.d: Likewise. * testsuite/gas/arm/mapping4.d: Likewise. * testsuite/gas/arm/mapshort-elf.d: Likewise. * testsuite/gas/arm/mask_1-armv8-a.d: Likewise. * testsuite/gas/arm/mask_1-armv8-r.d: Likewise. * testsuite/gas/arm/movs-thumb1-reloc-local-armv7-m.d: Likewise. * testsuite/gas/arm/movs-thumb1-reloc-local.d: Likewise. * testsuite/gas/arm/movw-local.d: Likewise. * testsuite/gas/arm/mrs-msr-thumb-v6t2.d: Likewise. * testsuite/gas/arm/mrs-msr-thumb-v7-m.d: Likewise. * testsuite/gas/arm/mrs-msr-thumb-v7e-m.d: Likewise. * testsuite/gas/arm/msr-imm-bad.d: Likewise. * testsuite/gas/arm/msr-reg-bad.d: Likewise. * testsuite/gas/arm/msr-reg-thumb.d: Likewise. * testsuite/gas/arm/nomapping.d: Likewise. * testsuite/gas/arm/nops.d: Likewise. * testsuite/gas/arm/pic.d: Likewise. * testsuite/gas/arm/pinsn.d: Likewise. * testsuite/gas/arm/plt-1.d: Likewise. * testsuite/gas/arm/pr21458.d: Likewise. * testsuite/gas/arm/pr9722.d: Likewise. * testsuite/gas/arm/strex-t.d: Likewise. * testsuite/gas/arm/t2-branch-global.d: Likewise. * testsuite/gas/arm/target-reloc-1.d: Likewise. * testsuite/gas/arm/thumb-b-bad.d: Likewise. * testsuite/gas/arm/thumb-w-bad.d: Likewise. * testsuite/gas/arm/thumb-w-good.d: Likewise. * testsuite/gas/arm/thumb.d: Likewise. * testsuite/gas/arm/thumb2_it.d: Likewise. * testsuite/gas/arm/thumb2_it_auto.d: Likewise. * testsuite/gas/arm/thumb2_it_search.d: Likewise. * testsuite/gas/arm/thumb2_ldmstm.d: Likewise. * testsuite/gas/arm/thumb2_ldr_immediate_armv6.d: Likewise. * testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d: Likewise. * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Likewise. * testsuite/gas/arm/thumb2_pool.d: Likewise. * testsuite/gas/arm/thumb2_vpool.d: Likewise. * testsuite/gas/arm/thumb2_vpool_be.d: Likewise. * testsuite/gas/arm/thumb32.d: Likewise. * testsuite/gas/arm/thumbver.d: Likewise. * testsuite/gas/arm/tls.d: Likewise. * testsuite/gas/arm/tls_vxworks.d: Likewise. * testsuite/gas/arm/undefined.d: Likewise. * testsuite/gas/arm/undefined_coff.d: Likewise. * testsuite/gas/arm/unwind.d: Likewise. * testsuite/gas/arm/v4bx.d: Likewise. * testsuite/gas/arm/vcmp-noprefix-imm.d: Likewise. * testsuite/gas/arm/vcvt-bad.d: Likewise. * testsuite/gas/arm/vfma1.d: Likewise. * testsuite/gas/arm/vldconst.d: Likewise. * testsuite/gas/arm/vldconst_be.d: Likewise. * testsuite/gas/arm/vldm-arm.d: Likewise. * testsuite/gas/arm/vldr.d: Likewise. * testsuite/gas/arm/weakdef-1.d: Likewise. * testsuite/gas/arm/weakdef-2.d: Likewise. * config/te-riscix.h: Delete. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am: Remove arm-aout and arm-coff support. * configure.tgt: Likewise. * testsuite/ld-arm/attr-merge-div-00.d: Likewise. * testsuite/ld-arm/attr-merge-div-01-m3.d: Likewise. * testsuite/ld-arm/attr-merge-div-01.d: Likewise. * testsuite/ld-arm/attr-merge-div-02.d: Likewise. * testsuite/ld-arm/attr-merge-div-10-m3.d: Likewise. * testsuite/ld-arm/attr-merge-div-10.d: Likewise. * testsuite/ld-arm/attr-merge-div-11.d: Likewise. * testsuite/ld-arm/attr-merge-div-12.d: Likewise. * testsuite/ld-arm/attr-merge-div-120.d: Likewise. * testsuite/ld-arm/attr-merge-div-20.d: Likewise. * testsuite/ld-arm/attr-merge-div-21.d: Likewise. * testsuite/ld-arm/attr-merge-div-22.d: Likewise. * testsuite/ld-arm/attr-merge-hardfp-use-1.d: Likewise. * testsuite/ld-arm/attr-merge-hardfp-use-2.d: Likewise. * testsuite/ld-arm/attr-merge-nosection-1.d: Likewise. * testsuite/ld-arm/attr-merge-unknown-2.d: Likewise. * testsuite/ld-arm/attr-merge-unknown-2r.d: Likewise. * testsuite/ld-arm/attr-merge-unknown-3.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-1.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-10.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-10r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-11.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-11r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-12.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-12r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-13.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-13r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-14.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-14r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-1r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-2.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-2r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-3.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-3r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-4.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-4r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-5.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-5r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-6.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-6r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-7.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-7r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-8.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-8r.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-9.d: Likewise. * testsuite/ld-arm/attr-merge-vfp-9r.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-00-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-00.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-02-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-02.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-04-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-04.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-20-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-20.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-22-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-22.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-24-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-40-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-40.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-42-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-44-nowarn.d: Likewise. * testsuite/ld-arm/attr-merge-wchar-44.d: Likewise. * testsuite/ld-arm/eabi-hard-float.d: Likewise. * testsuite/ld-arm/eabi-soft-float-ABI4.d: Likewise. * testsuite/ld-arm/eabi-soft-float-r.d: Likewise. * testsuite/ld-arm/eabi-soft-float.d: Likewise. * testsuite/ld-arm/gc-hidden-1.d: Likewise. * emulparams/armaoutb.sh: Delete. * emulparams/armaoutl.sh: Delete. * emulparams/armcoff.sh: Delete. * emulparams/armnbsd.sh: Delete. * emulparams/riscix.sh: Delete. * scripttempl/armaout.sc: Delete. * scripttempl/armcoff.sc: Delete. * scripttempl/riscix.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-23Silence gcc-8 warningsAlan Modra4-6/+17
All of these warnings were false positives. -Wstringop-truncation is particularly annoying when it warns about strncpy used quite correctly. bfd/ * elf-linux-core.h (swap_linux_prpsinfo32_ugid32_out): Disable gcc-8 string truncation warning. (swap_linux_prpsinfo32_ugid16_out): Likewise. (swap_linux_prpsinfo64_ugid32_out): Likewise. (swap_linux_prpsinfo64_ugid16_out): Likewise. * elf.c (elfcore_write_prpsinfo): Likewise. gas/ * stabs.c (generate_asm_file): Use memcpy rather than strncpy. Remove call to strlen inside loop. * config/tc-cr16.c (getreg_image): Warning fix. * config/tc-crx.c (getreg_image): Warning fix.
2018-04-20RISC-V: Add new option -mrelax/-mno-relax.Jim Wilson7-0/+80
gas/ * config/tc-riscv.c (options): Add OPTION_RELAX and OPTION_NO_RELAX. (md_longopts): New option -mrelax and -mno-relax. (md_parse_option): Handle -mrelax and -mno-relax. * doc/c-riscv.texi: Document for -mrelax and -mno-relax. * testsuite/gas/riscv/no-relax-reloc.d: New. * testsuite/gas/riscv/no-relax-reloc.s: New. * testsuite/gas/riscv/relax-reloc.d: New. * testsuite/gas/riscv/relax-reloc.s: New.
2018-04-20Updated Spanish translation for gas sub-directoryNick Clifton2-923/+730
2018-04-18various i386-aout and i386-coff target removalAlan Modra13-239/+16
Also tidies some other aout leftovers in binutils-common.exp. bfd/ * Makefile.am: Remove support for assorted i386 aout and coff targets. * config.bfd: Likewise. * configure.ac: Likewise. * doc/bfdint.texi: Likewise. * targets.c: Likewise. * freebsd.h: Delete. * i386dynix.c: Delete. * i386freebsd.c: Delete. * i386linux.c: Delete. * i386mach3.c: Delete. * i386netbsd.c: Delete. * i386os9k.c: Delete. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/lib/binutils-common.exp: Remove support for assorted aout targets. gas/ * Makefile.am: Remove support for assorted i386 aout and coff targets. * config/obj-elf.c: Likewise. * config/tc-i386.h: Likewise. * configure.ac: Likewise. * configure.tgt: Likewise. * config/te-dynix.h: Delete. * config/te-i386aix.h: Delete. * config/te-mach.h: Delete. * Makefile.in: Regenerate. * config.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. include/ * aout/dynix3.h: Delete. ld/ * Makefile.am: Remove support for assorted i386 aout and coff targets. * configure.tgt: Likewise. * testsuite/ld-discard/discard.exp: Likewise. * testsuite/ld-elf/binutils.exp: Likewise. * testsuite/ld-elf/tls.exp: Likewise. * testsuite/ld-elf/tls_common.exp: Likewise. * testsuite/ld-elfvers/vers.exp: Likewise. * testsuite/ld-elfvsb/elfvsb.exp: Likewise. * testsuite/ld-elfweak/elfweak.exp: Likewise. * testsuite/ld-gc/abi-note.d: Likewise. * testsuite/ld-gc/pr19167.d: Likewise. * testsuite/ld-gc/pr20022.d: Likewise. * testsuite/ld-gc/start.d: Likewise. * testsuite/ld-gc/stop.d: Likewise. * testsuite/ld-i386/i386.exp: Likewise. * testsuite/ld-ifunc/binutils.exp: Likewise. * testsuite/ld-ifunc/ifunc.exp: Likewise. * testsuite/ld-linkonce/linkonce.exp: Likewise. * testsuite/ld-plugin/lto.exp: Likewise. * testsuite/ld-scripts/empty-address-2a.d: Likewise. * testsuite/ld-scripts/empty-address-2b.d: Likewise. * testsuite/ld-scripts/phdrs2.exp: Likewise. * testsuite/ld-scripts/section-match-1.d: Likewise. * testsuite/ld-shared/shared.exp: Likewise. * testsuite/ld-size/size.exp: Likewise. * testsuite/ld-sparc/sparc.exp: Likewise. * emulparams/i386coff.sh: Delete. * emulparams/i386linux.sh: Delete. * emulparams/i386mach.sh: Delete. * emulparams/i386nbsd.sh: Delete. * emulparams/vsta.sh: Delete. * scripttempl/i386coff.sc: Delete. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2018-04-18Tidy gas/configure.tgtAlan Modra2-1/+4
Should have been removed with m68k bsd support. * configure.tgt: Remove *-*-bsd* entry.
2018-04-18Correct ChangeLog dates for git commit 3f0a5f17d7fAlan Modra1-1/+1
2018-04-17[MicroBlaze] PIC data text relativeMichael Eager2-9/+55
Andrew Sadek <andrew.sadek.se@gmail.com> A new implemented feature in GCC Microblaze that allows Position Independent Code to run using Data Text Relative addressing instead of using Global Offset Table. Its aim was to make 'PIC' more efficient and flexible as elf size excess performance overhead were noticed when using GOT due to the indirect addressing. include/ChangeLog: * bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct. * elf/microblaze.h (Add 3 new relocations): R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64 and R_MICROBLAZE_TEXTREL_32_LO for relax function. bfd/ChangeLog: * bfd/reloc.c (2 new BFD relocations): BFD_RELOC_MICROBLAZE_64_TEXTPCREL & BFD_RELOC_MICROBLAZE_64_TEXTPCREL * bfd/bfd-in2.h: Regenerate * bfd/libbfd.h: Regenerate * bfd/elf32-microblaze.c (Handle new relocs): define 'HOWTO' of 3 new relocs and handle them in both relocate and relax functions. (microblaze_elf_reloc_type_lookup): add mapping between for new bfd relocs. (microblaze_elf_relocate_section): Handle new relocs in case of elf relocation. (microblaze_elf_relax_section): Handle new relocs for elf relaxation. gas/ChangeLog: * gas/config/tc-microblaze.c (Handle new relocs directives in assembler): Handle new relocs from compiler output. (imm_types): add new imm types for data text relative addressing TEXT_OFFSET, TEXT_PC_OFFSET (md_convert_frag): conversion for BFD_RELOC_MICROBLAZE_64_TEXTPCREL, BFD_RELOC_MICROBLAZE_64_TEXTPCREL (md_apply_fix): apply fix for BFD_RELOC_MICROBLAZE_64_TEXTPCREL, BFD_RELOC_MICROBLAZE_64_TEXTPCREL (md_estimate_size_before_relax): estimate size for BFD_RELOC_MICROBLAZE_64_TEXTPCREL, BFD_RELOC_MICROBLAZE_64_TEXTPCREL (tc_gen_reloc): generate relocations for BFD_RELOC_MICROBLAZE_64_TEXTPCREL, BFD_RELOC_MICROBLAZE_64_TEXTPCREL ld/ChangeLog: * ld/lexsup.c (Add 2 ld options): (ld_options): add disable-multiple-abs-defs @ 'ld_options' array (parse_args): parse new option and pass flag to 'link_info' struct. * ld/ldlex.h (Add enum): add new enum @ 'option_values' enum. * ld/ld.texinfo (Add new option): Add description for 'disable-multiple-abs-defs' * ld/main.c: Initialize flags with false @ 'main'. Handle disable-multiple-abs-defs @ 'mutiple_definition'.
2018-04-17Fix tests to avoid cldemote encoding.Igor Tsimbalist6-4/+19
gas/ * testsuite/gas/i386/nops.s: Revert back deleted lines and change encoding to 0x0f1c /1 to map to NOP. * testsuite/gas/i386/x86-64-nops.s: Likewise. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Likewis.
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist15-11/+118
gas/ * config/tc-i386.c (cpu_arch): Add .cldemote. * doc/c-i386.texi: Document cldemote/.cldemote. * testsuite/gas/i386/cldemote-intel.d: New. * testsuite/gas/i386/cldemote.d: Likewise. * testsuite/gas/i386/cldemote.s: Likewise. * testsuite/gas/i386/i386.exp: Run new tests. * testsuite/gas/i386/x86-64-cldemote-intel.d: New. * testsuite/gas/i386/x86-64-cldemote.d: Likewise. * testsuite/gas/i386/x86-64-cldemote.s: Likewise. * testsuite/gas/i386/ilp32/x86-64-nops.d: Remove 0x0f1c NOP encoding that maps to cldemote. * testsuite/gas/i386/nops.d: Likewise. * testsuite/gas/i386/nops.s: Likewise. * testsuite/gas/i386/x86-64-nops.d: Likewise. * testsuite/gas/i386/x86-64-nops.s: Likewise. opcode/ * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, PREFIX_0F1C. * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, (cpu_flags): Add CpuCLDEMOTE. * i386-init.h: Regenerate. * i386-opc.h (enum): Add CpuCLDEMOTE, (i386_cpu_flags): Add cpucldemote. * i386-opc.tbl: Add cldemote. * i386-tbl.h: Regenerate.
generated by cgit v1.1 at 2024-12-26 15:55:46 +0000