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authorJan Beulich <jbeulich@novell.com>2018-04-26 08:48:01 +0200
committerJan Beulich <jbeulich@suse.com>2018-04-26 08:48:01 +0200
commit6e041cf4b0b00e85bee85bee98c411f16bd15747 (patch)
tree18fa9d2b8f887fd446c18234972a0af0737553ba /gas
parent1adf7f5604558489bca6e3f8e6ee5e12089f06ef (diff)
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x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
It's not clear to me why they had been introduced - the respective comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers are very well supported (and necessary) with just AVX512F.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-i386.c24
-rw-r--r--gas/testsuite/gas/i386/avx512f-ymm.d14
-rw-r--r--gas/testsuite/gas/i386/avx512f-ymm.s9
-rw-r--r--gas/testsuite/gas/i386/i386.exp2
-rw-r--r--gas/testsuite/gas/i386/xmmhi32.d31
-rw-r--r--gas/testsuite/gas/i386/xmmhi32.s33
7 files changed, 110 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a13f86f..18c2f65 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
2018-04-26 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (parse_real_register): Re-write {,x,y,z}mm
+ and mask register handling.
+ * testsuite/gas/i386/avx512f-ymm.s, testsuite/gas/i386/avx512f-ymm.d,
+ testsuite/gas/i386/xmmhi32.s, testsuite/gas/i386/xmmhi32.d: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+
+2018-04-26 Jan Beulich <jbeulich@suse.com>
+
* config/tc-i386.c (parse_real_register): Check bnd<N>
registers.
* testsuite/gas/i386/bnd.s, testsuite/gas/i386/bnd.l: New.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ccecdda..723fc3e 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -10154,21 +10154,23 @@ parse_real_register (char *reg_string, char **end_op)
&& !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
+ if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
- return (const reg_entry *) NULL;
-
- if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
- return (const reg_entry *) NULL;
+ if (!cpu_arch_flags.bitfield.cpuavx512f)
+ {
+ if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
+ return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
- return (const reg_entry *) NULL;
+ if (!cpu_arch_flags.bitfield.cpuavx)
+ {
+ if (r->reg_type.bitfield.ymmword)
+ return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.regmask
- && !cpu_arch_flags.bitfield.cpuregmask)
- return (const reg_entry *) NULL;
+ if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
+ return (const reg_entry *) NULL;
+ }
+ }
if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
return (const reg_entry *) NULL;
diff --git a/gas/testsuite/gas/i386/avx512f-ymm.d b/gas/testsuite/gas/i386/avx512f-ymm.d
new file mode 100644
index 0000000..79a74b0
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f-ymm.d
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: i386 AVX512F YMM registers
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <ymm>:
+[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 31 c0[ ]*vpmovzxbd %xmm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 33 c0[ ]*vpmovzxwd %ymm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f1 7c 48 5a c0[ ]*vcvtps2pd %ymm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f1 fd 48 5a c0[ ]*vcvtpd2ps %zmm0,%ymm0
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f-ymm.s b/gas/testsuite/gas/i386/avx512f-ymm.s
new file mode 100644
index 0000000..5357ca2
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f-ymm.s
@@ -0,0 +1,9 @@
+ .text
+ .arch generic32
+ .arch .avx512f
+ymm:
+ vpmovzxbd %xmm0, %zmm0
+ vpmovzxwd %ymm0, %zmm0
+
+ vcvtps2pd %ymm0, %zmm0
+ vcvtpd2ps %zmm0, %ymm0
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 62c03d8..8bbe100 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -187,6 +187,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_list_test "noavx512-1" "-al"
run_list_test "noavx512-2" "-al"
run_dump_test "noextreg"
+ run_dump_test "xmmhi32"
run_dump_test "xsave"
run_dump_test "xsave-intel"
run_dump_test "aes"
@@ -209,6 +210,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx512f-opts-intel"
run_dump_test "avx512f-nondef"
run_list_test "avx512f-plain" "-al"
+ run_dump_test "avx512f-ymm"
run_dump_test "avx512cd"
run_dump_test "avx512cd-intel"
run_dump_test "avx512er"
diff --git a/gas/testsuite/gas/i386/xmmhi32.d b/gas/testsuite/gas/i386/xmmhi32.d
new file mode 100644
index 0000000..b3ba7a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/xmmhi32.d
@@ -0,0 +1,31 @@
+#objdump: -dwr
+#name: high/disabled XMM/mask registers in 32-bit mode
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <xmm>:
+[ ]*[a-f0-9]+: c5 f0 58 05 00 00 00 00 vaddps 0x0,%xmm1,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 f4 58 05 00 00 00 00 vaddps 0x0,%ymm1,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm8
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm16
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm24
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 fd 6f 05 00 00 00 00 vmovdqa 0x0,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f9 7f 05 00 00 00 00 vmovdqa %xmm0,0x0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 fd 7f 05 00 00 00 00 vmovdqa %ymm0,0x0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f0 58 05 00 00 00 00 vaddps 0x0,%xmm1,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 f4 58 05 00 00 00 00 vaddps 0x0,%ymm1,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 k0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 ymm0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 k0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 xmm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 ymm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 k0
+#pass
diff --git a/gas/testsuite/gas/i386/xmmhi32.s b/gas/testsuite/gas/i386/xmmhi32.s
new file mode 100644
index 0000000..3847fc4
--- /dev/null
+++ b/gas/testsuite/gas/i386/xmmhi32.s
@@ -0,0 +1,33 @@
+ .text
+ .intel_syntax noprefix
+ .code32
+xmm:
+ vaddps xmm0, xmm1, xmm8
+ vaddps ymm0, ymm1, ymm8
+ vaddps zmm0, zmm1, zmm8
+ vaddps zmm0, zmm1, zmm16
+ vaddps zmm0, zmm1, zmm24
+
+ vmovdqa xmm0, xmm8
+ vmovdqa ymm0, ymm8
+ vmovdqa xmm8, xmm0
+ vmovdqa ymm8, ymm0
+
+ .arch .noavx512f
+ vaddps xmm0, xmm1, xmm8
+ vaddps ymm0, ymm1, ymm8
+ vmovdqa xmm0, zmm0
+ vmovdqa xmm0, k0
+
+ .arch .noavx
+ addps xmm0, xmm8
+ addps xmm0, ymm0
+ addps xmm0, ymm8
+ addps xmm0, zmm0
+ addps xmm0, k0
+
+ .arch .nosse
+ mov eax, xmm0
+ mov eax, ymm0
+ mov eax, zmm0
+ mov eax, k0