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AgeCommit message (Expand)AuthorFilesLines
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel3-0/+31
2018-10-23S12Z: Handle 16 bit fixups which are constant.John Darrington2-0/+8
2018-10-22gas simple-forward testAlan Modra5-2/+36
2018-10-22Apply alpha BFD_RELOC_8 fixupsAlan Modra4-4/+15
2018-10-22PR23040, .uleb128 directive doesn't accept some valid expressionsAlan Modra4-20/+48
2018-10-20PR23800, .eqv doesn't always defer expression evaluationAlan Modra6-1/+55
2018-10-19Arm: Skip new binary decode tests on pe targetsTamar Christina3-2/+7
2018-10-19Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for...Tamar Christina4-0/+17
2018-10-19This set of changes clarifies the conditions for the R5900 short loop fix and...Fredrik Noring4-10/+71
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson4-0/+28
2018-10-15BFD_INIT_MAGICAlan Modra2-1/+8
2018-10-11x86: add {,V}MOVQ cases to xmmword testJan Beulich3-0/+19
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich2-6/+11
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das10-0/+220
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das4-0/+25
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das7-4/+95
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das6-1/+19
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das4-0/+9
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das9-0/+78
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das6-0/+40
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das3-0/+55
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das3-1/+9
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu5-0/+11
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das8-0/+63
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das10-0/+83
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das4-0/+27
2018-10-05or1k: Add OpenRISC gas documentationStafford Horne6-0/+321
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson3-0/+52
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne8-0/+73
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson8-8/+159
2018-10-03AArch64: Add MOVPRFX tests and update testsuiteTamar Christina72-0/+949
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina6-245/+261
2018-10-03AArch64: Close sequences at the end of sectionsTamar Christina3-0/+27
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina2-2/+8
2018-10-03AArch64: Wire through instr_sequenceTamar Christina3-8/+34
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt3-0/+18
2018-09-26Skip broken assembler test on Windows host.Sandra Loosemore2-1/+10
2018-09-25S/390: Fix symbolic displacement in layAndreas Krebbel4-1/+8
2018-09-21Correct ChangeLog entry for commit b8426d169d3f8aH.J. Lu1-1/+1
2018-09-21gas: Make bfin-parse.c/rl78-parse.c/rx-parse.c depend on bfd/reloc.cH.J. Lu3-6/+14
2018-09-21Fix more fallout from 17f6ade235fcAlan Modra2-3/+6
2018-09-20gas: Update expected outputs of "readelf -wL"H.J. Lu12-70/+86
2018-09-20S12Z/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki2-11/+18
2018-09-20PPC/GAS: Correct a signed vs unsigned comparison error with GCC 4.1Maciej W. Rozycki2-1/+6
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki2-2/+7
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton15-1643/+3027
2018-09-18Fix Aarch64 bug in warning filtering.Tamar Christina2-1/+6
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson3-0/+23
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu6-0/+79
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu12-336/+131