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2022-11-04x86: adjust recently introduced testcasesJan Beulich8-0/+8
The issue addressed by 2c02c72c62d2 ("re: Support Intel AMX-FP16") has been introduced once again in a number of new tests.
2022-11-04Support Intel AVX-NE-CONVERTkonglin110-0/+1023
gas/ChangeLog: * NEWS: Support Intel AVX-NE-CONVERT. * config/tc-i386.c: Add avx_ne_convert. * doc/c-i386.texi: Document .avx_ne_convert. * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. * testsuite/gas/i386/avx-ne-convert-intel.d: New test. * testsuite/gas/i386/avx-ne-convert.d: Ditto. * testsuite/gas/i386/avx-ne-convert.s: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Mw): New. (PREFIX_VEX_0F3872): Ditto. (PREFIX_VEX_0F38B0_W_0): Ditto. (PREFIX_VEX_0F38B1_W_0): Ditto. (VEX_W_0F3872_P_1): Ditto. (VEX_W_0F38B0): Ditto. (VEX_W_0F38B1): Ditto. (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, PREFIX_VEX_0F38B1_W_0. (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and CPU_ANY_AVX_NE_CONVERT_FLAGS. (cpu_flags): Add CpuAVX_NE_CONVERT. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX_NE CONVERT): New. (i386_cpu_flags): Add cpuavx_ne_convert. * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. * i386-tbl.h: Regenerated.
2022-11-04Support multiple .eh_frame sectionsJojo R3-3/+35
This patch is based on MULTIPLE_FRAME_SECTIONS and EH_FRAME_LINKONCE, it allows backend to enable this feature and use '--gc-sections' simply. * gas/dw2gencfi.h (TARGET_MULTIPLE_EH_FRAME_SECTIONS): New. (MULTIPLE_FRAME_SECTIONS): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS. * gas/dw2gencfi.c (EH_FRAME_LINKONCE): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS. (is_now_linkonce_segment): Likewise. (get_cfi_seg): Create relocation info between .eh_frame.* and .text.* section. * bfd/elf-bfd.h (elf_backend_can_make_multiple_eh_frame): New. * bfd/elfxx-target.h (elf_backend_can_make_multiple_eh_frame): Likewise. * bfd/elflink.c (_bfd_elf_default_action_discarded): Add checking for elf_backend_can_make_multiple_eh_frame.
2022-11-04gas/doc/internals.texi: fix typoJojo R1-2/+1
* gas/doc/internals.texi (md_emit_single_noop_insn): fix '@var missing closing brace' * gas/doc/internals.texi (Hash tables): fix '@menu reference to nonexistent node `Hash tables''
2022-11-02x86: simplify expressions in update_imm()Jan Beulich1-23/+14
Comparing the sum of the relevant .imm<N> fields against a constant imo makes more obvious what is actually meant. It allows dropping of two static variables, with a 3rd drop requiring two more minor adjustments elsewhere, utilizing that "i" is zeroed first thing in md_assemble(). This also increases the chances of the compiler doing the calculations all in registers.
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu4-38/+67
Consider the case, .option arch, rv32i .option norelax .option arch, +c .byte 1 .align 2 addi a0, zero, 1 Assembler adds $d for the odd .byte, and then adds $x+arch for the alignment. Since norelax, riscv_add_odd_padding_symbol will add the $d and $x for the odd alignment, but accidently remove the $x+arch because it has the same address as $d. Therefore, we will get the unexpected result before applying this patch, .byte 1 # $d .align 2 # odd alignment, $xrv32ic replaced by $d + $x After this patch, the expected result should be, .byte 1 # $d .align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic gas/ * config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol for odd alignment, then we probably will remove the $x+arch by accidently when it has the same address of $d. Try to add the removed $x+arch back after the $d rather than just $x. (riscv_mapping_state): Updated since parameters of make_mapping_symbol are changed. (riscv_add_odd_padding_symbol): Likewise. (riscv_remove_mapping_symbol): Removed and moved the code into the riscv_check_mapping_symbols. (riscv_check_mapping_symbols): Updated. * testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping.s: Likewise.
2022-11-02Support Intel MSRLISTHu, Lin19-1/+47
gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
2022-11-02Support Intel WRMSRNSHu, Lin19-1/+44
gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated.
2022-11-02Add handler for more i386_cpu_flagsKong Lingling1-0/+17
gas/ChangeLog: * config/tc-i386.c (cpu_flags_all_zero): Add new ARRAY_SIZE handle. (cpu_flags_equal): Ditto. (cpu_flags_and): Ditto. (cpu_flags_or): Ditto. (cpu_flags_and_not): Ditto.
2022-11-02Support Intel CMPccXADDHaochen Jiang9-1/+818
gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated.
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili10-1/+547
gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2022-11-02Support Intel AVX-IFMAHongyu Wang15-15/+252
x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-01opcodes/arm: use '@' consistently for the comment characterAndrew Burgess121-2291/+2291
Looking at the ARM disassembler output, every comment seems to start with a ';' character, so I assumed this was the correct character to start an assembler comment. I then spotted a couple of places where there was no ';', but instead, just a '@' character. I thought that this was a case of a missing ';', and proposed a patch to add the missing ';' characters. Turns out I was wrong, '@' is actually the ARM assembler comment character, while ';' is the statement separator. Thus this: nop ;@ comment is two statements, the first is the 'nop' instruction, while the second contains no instructions, just the '@ comment' comment text. This: nop @ comment is a single 'nop' instruction followed by a comment. And finally, this: nop ; comment is two statements, the first contains the 'nop' instruction, while the second contains the instruction 'comment', which obviously isn't actually an instruction at all. Why this matters is that, in the next commit, I would like to add libopcodes syntax styling support for ARM. The question then is how should the disassembler style the three cases above? As '@' is the actual comment start character then clearly the '@' and anything after it can be styled as a comment. But what about ';' in the second example? Style as text? Style as a comment? And the third example is even harder, what about the 'comment' text? Style as an instruction mnemonic? Style as text? Style as a comment? I think the only sensible answer is to move the disassembler to use '@' consistently as its comment character, and remove all the uses of ';'. Then, in the next commit, it's obvious what to do. There's obviously a *lot* of tests that get updated by this commit, the only actual code changes are in opcodes/arm-dis.c.
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich1-9/+8
Earlier tidying still missed an opportunity: There's no need for the "anyimm" static variable. Instead of using it in the loop to mask "allowed" (which is necessary to satisfy operand_type_or()'s assertions) simply use "mask", requiring it to be calculated first. That way the post-loop masking by "mask" ahead of the operand_type_all_zero() can be dropped.
2022-10-31x86: Silence GCC 12 warning on tc-i386.cH.J. Lu2-5/+5
Silence GCC 12 warning on tc-i386.c: gas/config/tc-i386.c: In function ‘md_assemble’: gas/config/tc-i386.c:5039:16: error: too many arguments for format [-Werror=format-extra-args] 5039 | as_warn (_("only support RIP-relative address"), i.tm.name); * config/tc-i386.c (md_assemble): Print mnemonic in RIP-relative warning. * estsuite/gas/i386/x86-64-prefetchi-warn.l: Updated.
2022-10-31Support Intel PREFETCHICui, Lili13-3/+103
gas/ChangeLog: * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. (md_assemble): Add warning for illegal input of PREFETCHI. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetch.d: New test. * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ChangeLog: * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and PREFIX_0F18_REG_7_MOD_0_X86_64. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2022-10-31RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato2-4/+8
2022-10-29RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu3-41/+0
Before figuring out the suppress rule of mapping symbol with architecture (changed back to $x), always generate them at the start of the sections. gas/ * config/tc-riscv.c (need_arch_map_symbol): Removed. (riscv_mapping_state): Updated. (riscv_check_mapping_symbols): Updated. * testsuite/gas/riscv/mapping-non-arch.d: Removed. * testsuite/gas/riscv/mapping-non-arch.s: Likewise.
2022-10-28gas: NEWS: Note support for RISC-V ZawrsPalmer Dabbelt1-0/+2
This has been supported since eb668e50036 ("RISC-V: Add Zawrs ISA extension support").
2022-10-28gas: NEWS: Add a missing newlinePalmer Dabbelt1-0/+1
2022-10-28RISC-V: Improve "bits undefined" diagnosticsTsukasa OI1-2/+2
This commit improves internal error message "internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s" to display actual unused bits (excluding non-instruction bits). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Exclude non- instruction bits from displaying internal diagnostics. Change error message slightly.
2022-10-28RISC-V: Fallback for instructions longer than 64bTsukasa OI1-5/+8
We don't support instructions longer than 64-bits yet. Still, we can modify validate_riscv_insn function to prevent unexpected behavior by limiting the "length" of an instruction to 64-bit (or less). gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Fix function description comment based on current spec. Limit instruction length up to 64-bit for now. Make sure that required_bits does not corrupt even if unsigned long long is longer than 64-bit.
2022-10-28RISC-V/gas: fix build with certain gcc versionsJan Beulich1-7/+7
Some versions of gcc warn by default about shadowed outer-scope declarations. This affects frag_align_code, which is declared in frags.h. Rename the offending function parameter. While there also switch to using true/false at the function call sites.
2022-10-28RISC-V: Fix build failure for -Werror=maybe-uninitializedTsukasa OI1-1/+1
Commit 40f1a1a4564b ("RISC-V: Output mapping symbols with ISA string.") caused a build failure on GCC 12 as follows: make[3]: Entering directory '$(builddir)/gas' CC config/tc-riscv.o In file included from $(srcdir)/gas/config/tc-riscv.c:23: $(srcdir)/gas/as.h: In function ‘make_mapping_symbol’: $(srcdir)/gas/as.h:123:15: error: ‘buff’ may be used uninitialized [-Werror=maybe-uninitialized] 123 | #define xfree free | ^~~~ $(srcdir)/gas/config/tc-riscv.c:487:9: note: ‘buff’ was declared here 487 | char *buff; | ^~~~ cc1: all warnings being treated as errors make[3]: *** [Makefile:1425: config/tc-riscv.o] Error 1 This is caused by a false positive of "maybe uninitialized" variable detection (-Wmaybe-uninitialized). To avoid this error, this commit initializes the local variable buff to NULL first in all cases. gas/ChangeLog: * config/tc-riscv.c (make_mapping_symbol): Initialize variable buff with NULL to avoid build failure caused by a GCC's false positive of maybe uninitialized variable detection.
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu24-328/+404
RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner4-2/+81
gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner6-65/+270
gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.
2022-10-27re: Support Intel AMX-FP16Alan Modra2-0/+2
Fix these fails due to the target padding out sections with nops. x86_64-w64-mingw32 +FAIL: x86_64 AMX-FP16 insns x86_64-w64-mingw32 +FAIL: x86_64 AMX-FP16 insns (Intel disassembly) * testsuite/gas/i386/x86-64-amx-fp16-intel.d: Accept trailing nops. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise.
2022-10-24x86: consolidate VPCLMUL testsJan Beulich15-268/+156
There's little point in having Intel syntax disassembler tests when the purpose of a test is assembler functionality: Drop all *avx512*_vpclmulqdq-wig1-intel. For *avx512*_vpclmulqdq-wig1 share source with *avx512*_vpclmulqdq. Finally put in place similar tests for -mvexwig=1.
2022-10-24x86: consolidate VAES testsJan Beulich15-352/+211
There's little point in having Intel syntax disassembler tests when the purpose of a test is assembler functionality: Drop all *avx512*_vaes-wig1-intel. For *avx512*_vaes-wig1 share source with *avx512*_vaes. This in particular makes sure that the 32-bit VL test actually tests any EVEX encodings in the first place. Finally put in place similar tests for -mvexwig=1.
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich31-361/+361
When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-21Support Intel AMX-FP16Cui,Lili9-1/+97
gas/ * NEWS: Add support for Intel AMX-FP16 instruction. * config/tc-i386.c: Add amx_fp16. * doc/c-i386.texi: Document .amx_fp16. * testsuite/gas/i386/i386.exp: Add AMX-FP16 tests. * testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16.s: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise. opcodes/ * i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New. (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F385C_X86_64_P_3): Likewise. (prefix_table): Add VEX_W_0F385C_X86_64_P_3. (vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0. (vex_w_table): Add VEX_W_0F385C_X86_64_P_3. (mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0. * i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS. (CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16. (cpu_flags): Add CpuAMX-FP16. * i386-opc.h (enum): Add CpuAMX-FP16. (i386_cpu_flags): Add cpuamx_fp16. * i386-opc.tbl: Add Intel AMX-FP16 instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2022-10-20x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu5-4/+8
Since commit 837e225ba1992f9745e5bbbd5e8443243a7f475f Author: Jan Beulich <jbeulich@suse.com> Date: Thu Oct 20 10:01:12 2022 +0200 x86: re-work AVX-VNNI support moved AVX-VNNI after AVX512-VNNI, vector Disp8 is applied even when VEX encoding is selected. Check VEX/EVEX encoding before checking vector operands to avoid vector Disp8 with VEX encoding. PR gas/29708 * config/tc-i386.c (match_template): Check VEX/EVEX encoding before checking vector operands. * testsuite/gas/i386/avx-vnni.d: Updated. * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise. * testsuite/gas/i386/avx-vnni.s: Add a Disp32 test. * testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
2022-10-20x86: re-work AVX-VNNI supportJan Beulich7-12/+36
By putting the templates after their AVX512 counterparts, the AVX512 flavors will be picked by default. That way the need to always use {vex} ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as a whole) have been disabled. This way the need for the PseudoVexPrefix attribute also disappears.
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson8-25/+108
Allows aarch64-pe to be targeted natively, not having to use objcopy to convert it from ELF to PE. Based on initial work by Jedidiah Thompson Co-authored-by: Jedidiah Thompson <wej22007@outlook.com> Co-authored-by: Zac Walker <zac.walker@linaro.org>
2022-10-18x86: generalize gas documentation for disabling of ISA extensionsJan Beulich1-49/+5
As of commit ae89daecb132 ("x86: generalize disabling of sub- architectures") there's no arbitrary subset of ISAs which can also be disabled. This should have been reflected in documentation right away. Since I failed to do so, correct this now.
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao5-205/+566
Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64, see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-. This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions. The existing behaviour of not requiring the specifier is preserved. And the disasembly is with the specifier with this patch. The GAS tests passed under our local tests. opcodes/ * aarch64-asm.c: Modify `sve_size_hsd` encoding. * aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD for decp, incp, sqdecp, sqincp, uqdecp and uqincp. gas/ * testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier. * testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's expected disassembly. * testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's expected assembler messages. * testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the predicate size specifier. * testsuite/gas/aarch64/sve.d: Update sve testcase's expected disassembly. Signed-off-by: CaiJingtao <caijingtao@huawei.com>
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra5-56/+55
I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
2022-10-14PowerPC SPE disassembly and testsAlan Modra4-14/+11
Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT.
2022-10-14e200 LSP supportAlan Modra5-12/+38
It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.
2022-10-14RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI1-0/+6
'H', 'Smstateen', 'Sscofpmf' and 'Sstc' are four privileged extensions with their CSR definitions and 'Smepmp' is a privileged extension with additional CSR bits. Volume II: Privileged Architecture of the RISC-V ISA Manual states that the privileged architecture requires the 'Zicsr' extension. However, current GNU Binutils has no direct way whether the program has dependency to the privileged architecture itself. As a workaround, we should add implications from privileged extensions that either add new CSRs, extend existing CSRs or depends on using CSRs. This commit adds such implications for existing privileged extensions that satisfy this condition. gas/ChangeLog: * testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr' implicications for privileged extensions 'H', 'Smstateen', 'Sscofpmf', 'Sstc' and 'Smepmp'.
2022-10-14RISC-V: Test DWARF register number for "fp"Tsukasa OI2-0/+4
This commit adds "fp" (x8 or s0) to dw-regnums.{s,d}. gas/ChangeLog: * testsuite/gas/riscv/dw-regnums.s: Add "fp". * testsuite/gas/riscv/dw-regnums.d: Likewise.
2022-10-12x86: drop "regmask" static variableJan Beulich1-3/+2
Replace its two uses by more direct checks, paralleling what's already there for SIMD registers.
2022-10-11Re: Error: attempt to get value of unresolved symbol `L0'Nick Clifton4-10/+26
* symbols.c (S_GET_VALUE): If the unresolved symbol is the fake label provide a more helpful error message to the user. (S_GET_VALUE_WHERE): Like S_GET_VALUE, but includes a file/line number for error reporting purposes. * symbols.h (S_GET_VALUE_WHERE): Prototype. * write.c (fixup_segment): Use S_GET_VALUE_WHERE.
2022-10-11add --enable-default-compressed-debug-sections-algorithm configure optionMartin Liska5-3/+40
ChangeLog: * configure.ac: Add --enable-default-compressed-debug-sections-algorithm. * configure: Regenerate. gas/ChangeLog: * NEWS: Document the new option. * as.c (flag_compress_debug): Set default algorithm based on the configure option. * configure.ac: Add --enable-default-compressed-debug-sections-algorithm. * configure: Regenerate. * config.in: Likewise. ld/ChangeLog: * NEWS: Document the new option. * configure.ac: Add --enable-default-compressed-debug-sections-algorithm. * configure: Regenerate. * config.in: Likewise. * ldmain.c: Set default algorithm based on the configure option.
2022-10-11refactor usage of compressed_debug_section_typeMartin Liska1-25/+9
bfd/ChangeLog: * bfd-in.h (bfd_hash_set_default_size): Add COMPRESS_UNKNOWN enum value. (struct compressed_type_tuple): New. * bfd-in2.h (bfd_hash_set_default_size): Regenerate. (struct compressed_type_tuple): Likewise. * libbfd.c (ARRAY_SIZE): New macro. (bfd_get_compression_algorithm): New function. (bfd_get_compression_algorithm_name): Likewise. gas/ChangeLog: * as.c: Do not special-case, use the new functions. ld/ChangeLog: * emultempl/elf.em: Do not special-case, use the new functions. * lexsup.c (elf_static_list_options): Likewise.
2022-10-11Error: attempt to get value of unresolved symbol `L0'Nick Clifton2-2/+12
* symbols.c (S_GET_VALUE): If the unresolved symbol is the fake label provide a more helpful error message to the user.
2022-10-05x86/gas: support quoted address scale factor in AT&T syntaxJan Beulich4-12/+35
An earlier attempt (e68c3d59acd0 ["x86: better respect quotes in parse_operands()"]) needed undoing (cc0f96357e0b ["x86: permit parenthesized expressions again as addressing scale factor"]) as far its effect here went. As indicated back then, the issue is the backwards scanning of the operand string to find the matching opening parenthesis. Switch to forward scanning, finding the last outermost unquoted opening parenthesis (which is the one matching the trailing closing one).
2022-10-05Arm64: support CLEARBHB aliasJan Beulich2-1/+3
While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is (typically via a macro) already in use in kernels and alike.
2022-10-04gas: NEWS: Mention the T-Head extensions that were recently addedPalmer Dabbelt1-0/+5
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