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2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich3-4/+82
While commits 9889cbb14e ("Check invalid mask registers") and abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich5-1/+13
Other than in 64-bit mode, in 32- and 16-bit modes operand size isn't ambiguous.
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu2-13/+13
Since .code64 directive isn't available for 32-bit BFD and ELF directive isn't available for non-ELF directive, we should avoid them. * testsuite/gas/i386/noextreg.s: Replace .code64/.code32 and 64-bit instructions with .byte. Remove ELF directive.
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a ↵Tamar Christina7-5/+24
into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory from Armv8.4-a. gas/ * config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New. (do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml. * doc/c-arm.texi (fp16, fp16fml): New. * testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml. include/ * opcode/arm.h: (ARM_EXT2_FP16_FML): New. (ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
2017-11-15Add support to readelf and objdump for following links to separate debug ↵Nick Clifton13-12/+29
information files. Hi Guys, I am applying the rather large patch attached to this email to enhance the readelf and objdump programs so that they now have the ability to follow links to separate debug info files. (As requested by PR 15152). So for example whereas before we had this output: $ readelf -wi main.exe Contents of the .debug_info section: [...] <15> DW_AT_comp_dir : (alt indirect string, offset: 0x30c) [...] With the new option enabled we get: $ readelf -wiK main.exe main.exe: Found separate debug info file: dwz.debug Contents of the .debug_info section (loaded from main.exe): [...] <15> DW_AT_comp_dir : (alt indirect string, offset: 0x30c) /home/nickc/Downloads/dwzm [...] The link following feature also means that we can get two lots of output if the same section exists in both the main file and the separate debug info file: $ readelf -wiK main.exe main.exe: Found separate debug info file: dwz.debug Contents of the .debug_info section (loaded from main.exe): [...] Contents of the .debug_info section (loaded from dwz.debug): [...] The patch also adds the ability to display the contents of debuglink sections: $ readelf -wk main.exe Contents of the .gnu_debugaltlink section: Separate debug info file: dwz.debug Build-ID (0x14 bytes): c4 a8 89 8d 64 cf 70 8a 35 68 21 f2 ed 24 45 3e 18 7a 7a 93 Naturally there are long versions of these options (=follow-links and =links). The documentation has been updated as well, and since both readelf and objdump use the same set of debug display options, I have moved the text into a separate file. There are also a couple of new binutils tests to exercise the new behaviour. There are a couple of missing features in the current patch however, although I do intend to address them in follow up submissions: Firstly the code does not check the build-id inside separate debug info files when it is searching for a file specified by a .gnu_debugaltlink section. It just assumes that if the file is there, then it contains the information being sought. Secondly I have not checked the DWARF-5 version of these link features, so there will probably be code to add there. Thirdly I have only implemented link following for the DW_FORM_GNU_strp_alt format. Other alternate formats (eg DW_FORM_GNU_ref_alt) have yet to be implemented. Lastly, whilst implementing this feature I found it necessary to move some of the global variables used by readelf (eg section_headers) into a structure that can be passed around. I have moved all of the global variables that were necessary to get the patch working, but I need to complete the operation and move the remaining, file-specific variables (eg dynamic_strings). Cheers Nick binutils PR 15152 * dwarf.h (enum dwarf_section_display_enum): Add gnu_debuglink, gnu_debugaltlink and separate_debug_str. (struct dwarf_section): Add filename field. Add prototypes for load_separate_debug_file, close_debug_file and open_debug_file. * dwarf.c (do_debug_links): New. (do_follow_links): New. (separate_debug_file, separate_debug_filename): New. (fetch_alt_indirect_string): New function. Retrieves a string from the debug string table in the separate debug info file. (read_and_display_attr_value): Use it with DW_FORM_GNU_strp_alt. (load_debug_section_with_follow): New function. Like load_debug_section, but if the first attempt fails, then tries again in the separate debug info file. (introduce): New function. (process_debug_info): Use load_debug_section_with_follow and introduce. (load_debug_info): Likewise. (display_debug_lines_raw): Likewise. (display_debug_lines_decoded): Likewise. (display_debug_macinfo): Likewise. (display_debug_macro): Likewise. (display_debug_abbrev): Likewise. (display_debug_loc): Likewise. (display_debug_str): Likewise. (display_debug_aranges): Likewise. (display_debug_addr); Likewise. (display_debug_frames): Likewise. (display_gdb_index): Likewise. (process_cu_tu_index): Likewise. (load_cu_tu_indexes): Likewise. (display_debug_links): New function. Displays the contents of a .gnu_debuglink or .gnu_debugaltlink section. (calc_gnu_debuglink_ctc32):New function. Calculates a CRC32 value. (check_gnu_debuglink): New function. Checks the CRC of a potential separate debug info file. (parse_gnu_debuglink): New function. Reads a CRC value out of a .gnu_debuglink section. (check_gnu_debugaltlink): New function. (parse_gnu_debugaltlink): New function. Reads the build-id value out of a .gnu_debugaltlink section. (load_separate_debug_info): New function. Finds and loads a separate debug info file. (load_separate_debug_file): New function. Attempts to find and follow a link to a separate debug info file. (free_debug_memory): Free the separate debug info file information. (opts_table): Add "follow-links" and "links". (dwarf_select_sections_by_letters): Add "k" and "K". (debug_displays): Reformat. Add .gnu-debuglink and .gnu_debugaltlink. Add an extra entry for .debug_str in a separate debug info file. * doc/binutils.texi: Move description of debug dump features common to both readelf and objdump into... * objdump.c (usage): Add -Wk and -WK. (load_specific_debug_section): Initialise the filename field in the dwarf_section structure. (close_debug_file): New function. (open_debug_file): New function. (dump_dwarf): Load and dump the separate debug info sections. * readelf.c (struct filedata): New structure. Contains various variables that used to be global: (current_file_size, string_table, string_table_length, elf_header) (section_headers, program_headers, dump_sects, num_dump_sects): Move into filedata structure. (cmdline): New global variable. Contains list of sections to dump by number, as specified on the command line. Add filedata parameter to most functions. (load_debug_section): Load the string table if it has not already been retrieved. (close_file): New function. (close_debug_file): New function. (open_file): New function. (open_debug_file): New function. (process_object): Process sections in any separate debug info files. * doc/debug.options.texi: New file. Add description of =links and =follow-links options. * NEWS: Mention the new feature. * elfcomm.c: Have the byte gte functions take a const pointer. * elfcomm.h: Update prototypes. * testsuite/binutils-all/dw5.W: Update expected output. * testsuite/binutils-all/objdump.WL: Update expected output. * testsuite/binutils-all/objdump.exp: Add test of -WK and -Wk. * testsuite/binutils-all/readelf.exp: Add test of -wK and -wk. * testsuite/binutils-all/readelf.k: New file. * testsuite/binutils-all/objdump.Wk: New file. * testsuite/binutils-all/objdump.WK2: New file. * testsuite/binutils-all/linkdebug.s: New file. * testsuite/binutils-all/debuglink.s: New file. gas * testsuite/gas/avr/large-debug-line-table.d: Update expected output. * testsuite/gas/elf/dwarf2-11.d: Likewise. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise. ld * testsuite/ld-avr/gc-section-debugline.d: Update expected output.
2017-11-15x86: use correct register namesJan Beulich3-0/+27
VEX.W may be legitimately set (and is then ignored by the CPU) for non-64-bit code. Don't print 64-bit register names in such a case, by utilizing that REX_W would never be set for non-64-bit code, and that it is being set from VEX.W by generic decoding. A test for this is going to be introduced in the next patch of this series.
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich4-0/+28
The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead.
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich9-0/+85
Just like %cxl can't be used as shift count register. Otherwise for consistency %cxl would need to gain "ShiftCount" and use of both ought to properly cause REX prefixes to be emitted.
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson2-0/+5
gas/ * testsuite/gas/lns/lns.exp (lns-common-1): Add riscv*-*-* to alt list.
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich4-1194/+1199
Matching up with the assembler, which already supports them.
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich7-0/+224
... matching up with VPCMP*{D,Q}.
2017-11-14x86: string insns don't allow displacementsJan Beulich6-33/+52
Remove the misleading indicators from the table.
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich2-5/+11
Without this change, all of mov z0.b, p0/m, wsp mov z0.b, wsp mov z0.d, p0/m, sp mov z0.d, sp insert stray symbols into the symbol table.
2017-11-13gas/ia64: fix testsuite failuresJan Beulich4-11/+18
Commit dd90581873 ("Place .shstrtab section after .symtab and .strtab, thus restoring monotonically incre... ") adjusted section numbers, but forgot to adjust sh_link references from relocation and group section table entries. Additionally some other (perhaps subsequent) change appears to have added .rel.* and .rela.* sections to their respective groups, which requires some further adjustments to group-2.d. I assume this additional breakage wasn't noticed because the test was already failing at that time. This makes the gas testsuite complete successfully again for me in a cross build on ix86-linux; there continue to be quite a few ld failures.
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich4-1/+20
Just like %dx in I/O instructions isn't suitable to derive operand size information, %cl source operands of shift instructions aren't.
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich4-1/+20
Just like we make rsp/esp a base register even if it comes second, make riz/eiz an index register even if it comes first.
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich5-29/+56
... rather than silently dropping it altogether. i386_finalize_displacement() expects baseindex to already be set, so the respective statement needs to be moved up. This then also allows a subsequent conditional to be simplified. For this to not regress on 32-bit addressing, break out address size guessing from i386_index_check(), invoking the new function earlier so that i386_finalize_displacement() has i.prefix[ADDR_PREFIX] available. i386_addressing_mode () in turn needs i.base_reg / i.index_reg set earlier.
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson2-1/+5
gas/ * testsuite/gas/elf/dwarf2-10.l: Accept optional line number in error.
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina3-0/+17
include/ * opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD. gas/testsuite * gas/aarch64/dotproduct_armv8_4.s: New. * gas/aarch64/dotproduct_armv8_4.d: New.
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for ↵Tamar Christina6-0/+555
AArch64. Some of these instructions have been back-ported as optional extensions to Armv8.2-a and higher, but others are only available for Armv8.4-a. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers; dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2, cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2, sder32_el2, vncr_el2. (aarch64_sys_reg_supported_p): Likewise. (aarch64_pstatefields): Add dit register. (aarch64_pstatefield_supported_p): Likewise. (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os, vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os, vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1, rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os, rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1, ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os, rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os. gas/testsuite * gas/aarch64/armv8_4-a-registers-illegal.d: New. * gas/aarch64/armv8_4-a-registers-illegal.l: New. * gas/aarch64/armv8_4-a-registers-illegal.s: New. * gas/aarch64/armv8_4-a-registers.d: New. * gas/aarch64/armv8_4-a-registers.s: New.
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2-0/+17
gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own ↵Tamar Christina2-0/+11
options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own ↵Nick Clifton2-1/+13
options (+aes and +sha2). The new options are: +aes: Enables the AES instructions of Armv8-a, enabled by default with +crypto. +sha2: Enables the SHA1 and SHA2 instructions of Armv8-a, enabled by default with +crypto. These options have been turned on by default when +crypto is used, as such no breakage is expected. The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. Backporting the split does not break any of the previous requirements and so is safe to do. gas * config/tc-aarch64.c (aarch64_features): Include AES and SHA2 in CRYPTO. Add SHA2 and AES. include * opcode/aarch64.h: (AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New. opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. (aarch64_feature_sha2, aarch64_feature_aes): New. (SHA2, AES): New. (AES_INSN, SHA2_INSN): New. (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. (sha1h, sha1su1, sha256su0, sha1c, sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1): Change to SHA2_INS.
2017-11-08Adds command line support for Armv8.4-A, via the new command line option ↵Jiong Wang12-3/+1552
-march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.
2017-11-08xtensa message pluralizationAlan Modra2-4/+18
* config/tc-xtensa.c (finish_vinsn): Properly pluralize error message.
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson5-0/+47
This fixes some EH failures for the medany code model in the g++ testsuite. The problem is that the assembler is computing some values in the eh_frame section as constants, that instead should have had relocs to be resolved by the linker. This happens in output_cfi_insn in the DW_CFA_advance_loc case where it compares label frags and immediately simplifies if they are the same. We can fix that by forcing a new frag after every instruction that the linker can reduce in size. I've also added a testcase to verify the fix. This was tested with binutils make check, and gcc/g++ make checks on qemu for medlow and medany code models. gas/ * config/tc-riscv.c (append_insn): Call frag_wane and frag_new at end for linker optimizable relocs. * testsuite/gas/riscv/eh-relocs.d: New. * testsuite/gas/riscv/eh-relocs.s: New. * testsuite/gas/riscv/riscv.exp: Run eh-relocs test.
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt5-0/+23
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page Table Base Register) to satp (Supervisor Address Translation and Protection) to reflect the fact it could be used for more than just paging. This patch adds an alias, as they're the same register. include/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * opcode/riscv-opc.h (sptbr): Rename to satp. (CSR_SPTBR): Rename to CSR_SATP. (sptbr): Alias to CSR_SATP. gas/ChangeLog 2017-11-06 Palmer Dabbelt <palmer@dabbelt.com> * testsuite/gas/riscv/satp.d: New test. testsuite/gas/riscv/satp.s: Likewise. testsuite/gas/riscv/riscv.exp: Likewise. config/tc-riscv.c (md_begin): Handle CSR aliases.
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by ↵Tamar Christina2-68/+87
default for the Cortex-A55 and Cortex-A75 which have hardware support for these instructions. gas * config/tc-arm.c (arm_cpus): Change FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 into FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD. include * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): New macro.
2017-11-07bundle_lock message tidyAlan Modra3-13/+20
I'd edited these thinking that there might be cases where the counts were one, but on further investigation it appears not. What's left here are some minor tweaks. * read.c (assemble_one, s_bundle_unlock): Formatting. Consistently add comma and "bytes" to error message. * testsuite/gas/i386/bundle-bad.l: Adjust to suit.
2017-11-07readelf ngettext fixesAlan Modra32-132/+167
This patch is a first pass at fixing readelf message pluralization. I've deliberately not fixed the "out of memory" errors since it's very unlikely that they will ever be complaining about not being able to allocate for a single entry, and a few others where the size is very unlikely to be 1 byte. Then there are messages like this one: "Out of %lu items there are %zu bucket clashes (longest of %zu entries).\n" I suppose this could be split into three parts, "Of %lu items ", "there are %zu bucket clashes ", and "(longest of %zu entries).\n", each part being printed separately, but that might not be ideal for sentence construction in other languages. For now I'm punting on this one. Changes to readelf output require lots of testsuite adjustment.. binutils/ * dwarf.c (read_uleb128): Properly pluralize messages. (display_debug_lines_raw, display_debug_loc): Likewise. (display_debug_names, process_cu_tu_index): Likewise. * od-macho.c (dump_code_signature_superblob): Likewise. * readelf.c (process_program_headers): Likewise. (process_section_header, process_relocs): Likewise. (hppa_process_unwind, arm_process_unwind): Likewise. (process_dynamic_section, process_version_sections): Likewise. (process_symbol_table, process_syminfo): Likewise. (apply_relocations, process_mips_specific): Likewise. (process_gnu_liblist, process_notes_at): Likewise. (process_archive): Likewise. * testsuite/binutils-all/dw2-1.W, * testsuite/binutils-all/dw2-3.W, * testsuite/binutils-all/dw2-3gabi.W, * testsuite/binutils-all/dw5.S, * testsuite/binutils-all/dw5.W, * testsuite/binutils-all/i386/compressed-1a.d, * testsuite/binutils-all/libdw2-compressedgabi.out, * testsuite/binutils-all/objdump.W, * testsuite/binutils-all/readelf.r, * testsuite/binutils-all/readelf.r-64, * testsuite/binutils-all/x86-64/compressed-1a.d: Update for pluralization fixes. gas/ * testsuite/gas/arm/got_prel.d, * testsuite/gas/elf/dwarf2-1.d, * testsuite/gas/elf/dwarf2-2.d, * testsuite/gas/elf/dwarf2-3.d, * testsuite/gas/elf/dwarf2-5.d, * testsuite/gas/elf/dwarf2-6.d, * testsuite/gas/i386/debug1.d, * testsuite/gas/i386/dw2-compress-1.d, * testsuite/gas/i386/dw2-compress-3a.d, * testsuite/gas/i386/dw2-compress-3b.d, * testsuite/gas/i386/dw2-compressed-1.d, * testsuite/gas/i386/dw2-compressed-3a.d, * testsuite/gas/i386/dw2-compressed-3b.d, * testsuite/gas/i386/ilp32/x86-64-localpic.d, * testsuite/gas/i386/localpic.d, * testsuite/gas/i386/x86-64-localpic.d, * testsuite/gas/ia64/pr13167.d, * testsuite/gas/mips/loc-swap-2.d, * testsuite/gas/mips/loc-swap.d, * testsuite/gas/mips/micromips@loc-swap-2.d, * testsuite/gas/mips/micromips@loc-swap.d, * testsuite/gas/mips/mips16-dwarf2-n32.d, * testsuite/gas/mips/mips16-dwarf2.d, * testsuite/gas/mips/mips16@loc-swap-2.d, * testsuite/gas/mips/mips16@loc-swap.d, * testsuite/gas/mips/mips16e@loc-swap.d, * testsuite/gas/mmix/bspec-1.d, * testsuite/gas/mmix/bspec-2.d, * testsuite/gas/tic6x/unwind-1.d, * testsuite/gas/tic6x/unwind-2.d, * testsuite/gas/tic6x/unwind-3.d: Update for pluralization fixes. ld/ * testsuite/ld-aarch64/ifunc-13.d, * testsuite/ld-aarch64/ifunc-15.d, * testsuite/ld-aarch64/ifunc-20.d, * testsuite/ld-alpha/tlsbin.rd, * testsuite/ld-alpha/tlspic.rd, * testsuite/ld-arm/ifunc-3.rd, * testsuite/ld-arm/ifunc-9.rd, * testsuite/ld-arm/unwind-mix.d, * testsuite/ld-arm/unwind-rel.d, * testsuite/ld-cris/hiddef1.d, * testsuite/ld-cris/libdso-13.d, * testsuite/ld-cris/libdso-2.d, * testsuite/ld-cris/pr16044.d, * testsuite/ld-cris/tls-local-63.d, * testsuite/ld-cris/tls-local-64.d, * testsuite/ld-cris/tls-und-38.d, * testsuite/ld-cris/tls-und-42.d, * testsuite/ld-cris/tls-und-46.d, * testsuite/ld-cris/tls-und-50.d, * testsuite/ld-cris/weakref3.d, * testsuite/ld-cris/weakref4.d, * testsuite/ld-elf/comm-data2r.rd, * testsuite/ld-elf/discard1.d, * testsuite/ld-elf/discard2.d, * testsuite/ld-elf/pr19539.d, * testsuite/ld-elf/pr22374-1.r, * testsuite/ld-elf/pr22374-2.r, * testsuite/ld-i386/combreloc.d, * testsuite/ld-i386/emit-relocs-nacl.rd, * testsuite/ld-i386/emit-relocs.rd, * testsuite/ld-i386/pr13302.d, * testsuite/ld-i386/pr17709-nacl.rd, * testsuite/ld-i386/pr17709.rd, * testsuite/ld-i386/pr19539.d, * testsuite/ld-i386/pr19615.d, * testsuite/ld-i386/pr19636-1a.d, * testsuite/ld-i386/pr19636-1e.d, * testsuite/ld-i386/pr19636-1f.d, * testsuite/ld-i386/pr19636-2a.d, * testsuite/ld-i386/pr19636-2b.d, * testsuite/ld-i386/pr19636-2d-nacl.d, * testsuite/ld-i386/pr19636-2e-nacl.d, * testsuite/ld-i386/pr19636-3a.d, * testsuite/ld-i386/pr19636-3d.d, * testsuite/ld-i386/pr19636-3e.d, * testsuite/ld-i386/pr19636-4a.d, * testsuite/ld-i386/pr19645.d, * testsuite/ld-i386/pr19827-nacl.rd, * testsuite/ld-i386/pr19827.rd, * testsuite/ld-i386/pr20253-4a.d, * testsuite/ld-i386/pr20253-4b.d, * testsuite/ld-i386/pr20253-5.d, * testsuite/ld-i386/tlsbin-nacl.rd, * testsuite/ld-i386/tlsbin.rd, * testsuite/ld-i386/tlspic-nacl.rd, * testsuite/ld-i386/tlspic.rd, * testsuite/ld-i386/undefweakb.d, * testsuite/ld-ia64/tlsbin.rd, * testsuite/ld-ia64/tlspic.rd, * testsuite/ld-ifunc/ifunc-13-i386.d, * testsuite/ld-ifunc/ifunc-13-x86-64.d, * testsuite/ld-ifunc/ifunc-15-i386.d, * testsuite/ld-ifunc/ifunc-15-x86-64.d, * testsuite/ld-ifunc/ifunc-20-i386.d, * testsuite/ld-ifunc/ifunc-20-x86-64.d, * testsuite/ld-ifunc/ifunc-23a-x86.d, * testsuite/ld-ifunc/ifunc-23b-x86.d, * testsuite/ld-ifunc/ifunc-23c-x86.d, * testsuite/ld-ifunc/ifunc-24a-x86.d, * testsuite/ld-ifunc/ifunc-24b-x86.d, * testsuite/ld-ifunc/ifunc-24c-x86.d, * testsuite/ld-ifunc/ifunc-25a-x86.d, * testsuite/ld-ifunc/ifunc-25b-x86.d, * testsuite/ld-ifunc/ifunc-25c-x86.d, * testsuite/ld-m68k/got-1.d, * testsuite/ld-mips-elf/vxworks1.rd, * testsuite/ld-powerpc/ambiguousv1.d, * testsuite/ld-powerpc/ambiguousv1b.d, * testsuite/ld-powerpc/ambiguousv2.d, * testsuite/ld-powerpc/ambiguousv2b.d, * testsuite/ld-powerpc/tlsexe.r, * testsuite/ld-powerpc/tlsexe32.r, * testsuite/ld-powerpc/tlsexetoc.r, * testsuite/ld-powerpc/tlsso.r, * testsuite/ld-powerpc/tlsso32.r, * testsuite/ld-powerpc/tlstocso.r, * testsuite/ld-powerpc/vle-multiseg-1.d, * testsuite/ld-powerpc/vle-multiseg-2.d, * testsuite/ld-powerpc/vle-multiseg-3.d, * testsuite/ld-s390/tlsbin.rd, * testsuite/ld-s390/tlsbin_64.rd, * testsuite/ld-s390/tlspic.rd, * testsuite/ld-s390/tlspic_64.rd, * testsuite/ld-sh/ld-r-1.d, * testsuite/ld-sh/sh64/gotplt.d, * testsuite/ld-sh/shared-1.d, * testsuite/ld-sh/tlsbin-2.d, * testsuite/ld-sh/tlspic-2.d, * testsuite/ld-sparc/gotop32.rd, * testsuite/ld-sparc/gotop64.rd, * testsuite/ld-sparc/tlssunpic32.rd, * testsuite/ld-sparc/tlssunpic64.rd, * testsuite/ld-sparc/vxworks1-lib.rd, * testsuite/ld-tic6x/shlib-app-1.rd, * testsuite/ld-tic6x/shlib-app-1b.rd, * testsuite/ld-tic6x/shlib-app-1r.rd, * testsuite/ld-tic6x/shlib-app-1rb.rd, * testsuite/ld-tic6x/shlib-noindex.rd, * testsuite/ld-vax-elf/export-class-data.rd, * testsuite/ld-x86-64/pr13082-1a.d, * testsuite/ld-x86-64/pr13082-1b.d, * testsuite/ld-x86-64/pr13082-2a.d, * testsuite/ld-x86-64/pr13082-2b.d, * testsuite/ld-x86-64/pr13082-3a.d, * testsuite/ld-x86-64/pr13082-3c.d, * testsuite/ld-x86-64/pr13082-4a.d, * testsuite/ld-x86-64/pr13082-5a.d, * testsuite/ld-x86-64/pr13082-5b.d, * testsuite/ld-x86-64/pr13082-6a.d, * testsuite/ld-x86-64/pr13082-6b.d, * testsuite/ld-x86-64/pr17709-nacl.rd, * testsuite/ld-x86-64/pr17709.rd, * testsuite/ld-x86-64/pr19539a.d, * testsuite/ld-x86-64/pr19539b.d, * testsuite/ld-x86-64/pr19615.d, * testsuite/ld-x86-64/pr19636-1a.d, * testsuite/ld-x86-64/pr19636-1d.d, * testsuite/ld-x86-64/pr19636-1e.d, * testsuite/ld-x86-64/pr19636-2a.d, * testsuite/ld-x86-64/pr19636-2e.d, * testsuite/ld-x86-64/pr19636-2f.d, * testsuite/ld-x86-64/pr19636-3a.d, * testsuite/ld-x86-64/pr19645.d, * testsuite/ld-x86-64/pr19807-2b.d, * testsuite/ld-x86-64/pr19807-2d.d, * testsuite/ld-x86-64/pr19827-nacl.rd, * testsuite/ld-x86-64/pr19827.rd, * testsuite/ld-x86-64/pr20253-4a.d, * testsuite/ld-x86-64/pr20253-4b.d, * testsuite/ld-x86-64/pr20253-4d.d, * testsuite/ld-x86-64/pr20253-4e.d, * testsuite/ld-x86-64/pr20253-5a.d, * testsuite/ld-x86-64/pr20253-5b.d, * testsuite/ld-x86-64/tlsbin-nacl.rd, * testsuite/ld-x86-64/tlsbin.rd, * testsuite/ld-x86-64/tlspic-nacl.rd, * testsuite/ld-x86-64/tlspic.rd, * testsuite/ld-x86-64/tlspic2-nacl.rd: Update for pluralization fixes.
2017-11-07gas and ld pluralization fixesAlan Modra15-42/+127
gas/ * as.c (main): Properly pluralize messages. * frags.c (frag_grow): Likewise. * read.c (emit_expr_with_reloc, emit_expr_fix): Likewise. (parse_bitfield_cons): Likewise. * write.c (fixup_segment, compress_debug, write_contents): Likewise. (relax_segment): Likewise. * config/tc-arm.c (s_arm_elf_cons): Likewise. * config/tc-cr16.c (l_cons): Likewise. * config/tc-i370.c (i370_elf_cons): Likewise. * config/tc-m68k.c (m68k_elf_cons): Likewise. * config/tc-msp430.c (msp430_operands): Likewise. * config/tc-s390.c (s390_elf_cons, s390_literals): Likewise. * config/tc-mcore.c (md_apply_fix): Likewise. * config/tc-tic54x.c (md_assemble): Likewise. * config/tc-xtensa.c (xtensa_elf_cons): Likewise. (xg_expand_assembly_insn): Likewise. * config/xtensa-relax.c (build_transition): Likewise. ld/ * ldlang.c (lang_size_sections_1): Properly pluralize messages. (lang_check_section_addresses): Likewise.
2017-11-07ngettext supportAlan Modra2-2/+13
binutils has lacked proper pluralization of output messages for a long time, for example, readelf will display information about a section that "contains 1 entries" or "There are 1 section headers". Fixing this properly requires us to use ngettext, because other languages have different rules to English. This patch defines macros for ngettext and friends to handle builds with --disable-nls, and tidies the existing nls support. I've redefined gettext rather than just defining "_" as dgettext in bfd and opcodes in case someone wants to use gettext there (which might conceivably happen with generated code). bfd/ * sysdep.h: Formatting, comment fixes. (gettext, ngettext): Redefine when ENABLE_NLS. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. (_): Define using gettext. (textdomain, bindtextdomain): Use safer "do nothing". * hosts/alphavms.h (textdomain, bindtextdomain): Likewise. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. opcodes/ * opintl.h: Formatting, comment fixes. (gettext, ngettext): Redefine when ENABLE_NLS. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. (_): Define using gettext. (textdomain, bindtextdomain): Use safer "do nothing". binutils/ * sysdep.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. gas/ * asintl.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. gold/ * system.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. ld/ * ld.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar3-0/+10
This adds an option for the Qualcomm saphira core, the corresponding gcc patch is here: https://gcc.gnu.org/ml/gcc-patches/2017-10/msg02055.html This was tested with an aarch64 build and make check and also by building and running SPEC2006. gas/ * config/tc-aarch64.c (aarch64_cpus): Add saphira. * doc/c-aarch64.texi: Likewise.
2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme3-2/+8
Object files other than ELF do not have mapping symbols to indicate the type of data for objdump to work reliably. This is why the following tests FAIL on arm-wince-pe targets: ARMv6T2 Thumb CoProcessor Instructions (1) ARMv6T2 Thumb CoProcessor Instructions (2) This patch adds the force-thumb disassembler option to objdump for this test to PASS on these targets as well. 2017-11-02 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: Add --disassembler-options=force-thumb to objdump options. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: Likewise.
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which ↵James Bowman21-375/+2909
requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 2 adds a relaxation pass, which actually implements the code compression scheme. bfd * archures.c: Add bfd_mach_ft32b. * cpu-ft32.c: Add arch_info_struct. * elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1, DIFF32. (ft32_elf_relocate_section): Add clauses for R_FT32_SC0, SC1, DIFF32. (ft32_reloc_shortable, elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value, elf32_ft32_adjust_reloc_if_spans_insn, elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target, ft32_elf_relax_section): New function. * reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-ft32.c (md_assemble): add relaxation reloc BFD_RELOC_FT32_RELAX. (md_longopts): Add "norelax" and "no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32. (relaxable_section, ft32_validate_fix_sub, ft32_force_relocation, ft32_allow_local_subtract): New function. * config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION. * testsuite/gas/ft32/insnsc.s: New test exercising all FT32B shortcodes. include * elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme26-35/+328
A few coprocessor instructions introduced in ARMv2 are currently accepted by GAS when targeting ARMv1 due to a typo in the code. This patch fixes the issue and introduce a more fine grained testing for coprocessor instructions availability. Coprocessor instructions are grouped as follows: * ARM coprocessor instructions introduced in ARMv2 Includes: ldc, stc, mcr, mrc, cdp, ldcl, stcl Guarded by: ARM_EXT_V2 Tests: copro-arm_v2plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5 Includes: ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2 Guarded by: ARM_EXT_V5 Tests: copro-arm_v5plus-arm_v*.d * ARM coprocessor instructions introduced in ARMv5TE Includes: mcrr, mrrc Guarded by: ARM_EXT_V5E Tests: copro-arm_v5teplus-arm_v*.d * ARM coprocessor instructions introduced in ARMv6 Includes: mcrr2, mrrc2 Guarded by: ARM_EXT_V6 Tests: copro-arm_v6plus-arm_v*.d * Thumb coprocessor instructions introduced in ARMv6T2 Includes: ldc, ldcl, stc, stcl, mcr, mrc, mcrr, mrrc, cdp, ldc2, ldc2l, stc2, stc2l, cdp2, mcr2, mrc2, mcrr2, mrrc2 Guarded by: ARM_EXT_V6T2 Tests: copro-thumb_v6t2plus-thumb_v*.d For each of these groups, at least 2 tests are performed: * instructions are not available in earlier architecture * instructions are available in architecture where they were introduced More tests need to be performed when instructions in a group span several assembly files. Note that an instruction in the original coprocessor testcase is changed to unified syntax to allow the testcase to be assembled for ARM and Thumb state. Correct processing of legacy syntax is covered in other testcases. 2017-11-01 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_v2): Define to ARM_EXT_V2 feature bit. * testsuite/gas/arm/copro.s: Split into ... * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus.s: This while changing it to unified syntax and ... * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus.s: this and ... * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus.s: This and ... * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus.s: This. * testsuite/gas/arm/copro.d: Split into ... * testsuite/gas/arm/copro-arm_v2plus-arm_v2.d: This but target ARMv2 and ... * testsuite/gas/arm/copro-arm_v5plus-arm_v5.d: this but target ARMv5 and ... * testsuite/gas/arm/copro-arm_v5teplus-arm_v5te.d: This but target ARMv5TE and ... * testsuite/gas/arm/copro-arm_v6plus-arm_v6.d: This but target ARMv6. * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d: New testcase. * testsuite/gas/arm/copro-arm_v2plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-2.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d: New testcase. * testsuite/gas/arm/copro-arm_v5teplus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-3.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d: New testcase. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d: New testcase. * testsuite/gas/arm/copro-arm_v6plus-thumb_v6t2plus-unavail.l: Expected errors for the above two testcases. * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-4.d: New testcase.
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu14-1/+41
Extend invalid register check for AVX512 gathers to XMM register. PR gas/22352 * config/tc-i386.c (check_VecOperands): Also check XMM register for invalid register in AVX512 gathers. * testsuite/gas/i386/vgather-check.s: Add tests for AVX512 gathers with XMM register. * testsuite/gas/i386/x86-64-vgather-check.s: Likewise. * testsuite/gas/i386/vgather-check-error.l: Updated. * testsuite/gas/i386/vgather-check-none.d: Likewise. * testsuite/gas/i386/vgather-check-warn.d: Likewise. * testsuite/gas/i386/vgather-check-warn.e: Likewise. * testsuite/gas/i386/vgather-check.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-error.l: Likewise. * testsuite/gas/i386/x86-64-vgather-check-none.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-warn.d: Likewise. * testsuite/gas/i386/x86-64-vgather-check-warn.e: Likewise. * testsuite/gas/i386/x86-64-vgather-check.d: Likewise.
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2-2/+6
For some targets, like mmix-knuth-mmixware, .L2 (and .L1) are invalid symbols.
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra2-10/+18
include/ PR 22348 * opcode/cr16.h (instruction): Delete. (cr16_words, cr16_allWords, cr16_currInsn): Delete. * opcode/crx.h (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. (instruction): Delete. opcodes/ PR 22348 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. (cr16_words, cr16_allWords, processing_argument_number): Likewise. (imm4flag, size_changed): Likewise. * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. (words, allWords, processing_argument_number): Likewise. (cst4flag, size_changed): Likewise. * crx-opc.c (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. gas/ PR 22348 * config/tc-crx.c (instruction, output_opcode): Make static. (relocatable, ins_parse, cur_arg_num): Likewise. (parse_insn): Adjust for renamed opcodes globals. (check_range): Likewise
2017-10-25Yet another fill-1 test fixAlan Modra3-11/+17
tic4x fails due to being a 4 octets per byte target, while tic54x is 2 octets per byte. mmix still fails with fill-1.s:4: Error: unknown pseudo-op: `.l1:' fill-1.s:6: Error: unknown pseudo-op: `.l2:' fill-1.s:3: Error: .space specifies non-absolute value and if the labels are changed to L1 and L2 then mep-elf fails with fill-1.s:3: Error: .space specifies non-absolute value Since both of those look like they ought to be investigated by the target maintainers, I'm tweaking the test to fail on both targets. * testsuite/gas/all/fill-1.d: Exclude tic4x and tic54x. * testsuite/gas/all/fill-1.s: Use L1 rather than .L1.
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman8-0/+26
These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) <addi>: Use the above functions. <add>: Likewise. <c.addi4spn>: Likewise. <c.addi16sp>: Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests.
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman5-0/+15
This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-24Fix my previous gas/ChangeLog entryPalmer Dabbelt1-2/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu7-4/+54
Without 64-bit bfd, we can't properly support .code64 directive in 32-bit mode. * config/tc-i386.c (md_pseudo_table): Add .code64 directive only if BFD64 is defined. * testsuite/gas/i386/code64-inval.l: New file. * gas/testsuite/gas/i386/code64-inval.s: Likewise. * gas/testsuite/gas/i386/code64.d: Likewise. * gas/testsuite/gas/i386/code64.s: Likewise. * testsuite/gas/i386/i386.exp: Run mixed-mode-reloc32, att-regs, intel-regs, intel-expr and string-ok tests only if assembler supports x86-64. Run code64 and code64-inval.
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2-1/+6
Systems without the C extension mandate 4-byte alignment for instructions, so there is no reason to allow for 2-byte alignment. This change avoids emitting lots of unimplemented instructions into object files on non-C targets, which users keep reporting as a bug. While this isn't actually a bug (as none of the offsets in object files are relevant until RISC-V), it is ugly. gas/ChangeLog 2017-10-23 Palmer Dabbelt <palmer@dabbelt.com> * config/tc-riscv.c (riscv_frag_align_code): Align code by 4 bytes on non-RVC systems.
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+162
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2-3/+6
Fix a bug in MIPS n32 ELF object file generation and make such objects consistent with the n32 BFD requested, by presetting the EF_MIPS_ABI2 flag in the `e_flags' member of the newly created ELF file header, as it is this flag that tells n32 objects apart from o32 objects. This flag will then stay set through to output file generation for writers such as GAS or GDB's `generate-core-file' command. Readers will overwrite the whole of `e_flags' along with the rest of the ELF file header in `elf_swap_ehdr_in' and then verify in `mips_elf_n32_object_p' that the flag is still set before accepting an input file as an n32 object. The issue was discovered with GDB's `generate-core-file' command making o32 core files out of n32 debuggees. bfd/ * elfn32-mips.c (mips_elf_n32_mkobject): New prototype and function. (bfd_elf32_mkobject): Use `mips_elf_n32_mkobject' rather than `_bfd_mips_elf_mkobject'. gas/ * config/tc-mips.c (mips_elf_final_processing): Don't set EF_MIPS_ABI2 in `e_flags'.
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist15-0/+1046
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist15-1/+977
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
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