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AgeCommit message (Expand)AuthorFilesLines
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich3-4/+82
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich5-1/+13
2017-11-16i386: Replace .code64/.code32 with .byteH.J. Lu2-13/+13
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina7-5/+24
2017-11-15Add support to readelf and objdump for following links to separate debug info...Nick Clifton13-12/+29
2017-11-15x86: use correct register namesJan Beulich3-0/+27
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich4-0/+28
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich9-0/+85
2017-11-14First part of fix for riscv gas lns-common-1 failure.Jim Wilson2-0/+5
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich4-1194/+1199
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich7-0/+224
2017-11-14x86: string insns don't allow displacementsJan Beulich6-33/+52
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich2-5/+11
2017-11-13gas/ia64: fix testsuite failuresJan Beulich4-11/+18
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich4-1/+20
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich4-1/+20
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich5-29/+56
2017-11-09Fix riscv dwarf2-10 gas testsuite failure.Jim Wilson2-1/+5
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina3-0/+17
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for AA...Tamar Christina6-0/+555
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2-0/+17
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina2-0/+11
2017-11-08Fix typo in changelogNick Clifton1-1/+1
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton2-1/+13
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang12-3/+1552
2017-11-08xtensa message pluralizationAlan Modra2-4/+18
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson5-0/+47
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt5-0/+23
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina2-68/+87
2017-11-07bundle_lock message tidyAlan Modra3-13/+20
2017-11-07readelf ngettext fixesAlan Modra32-132/+167
2017-11-07gas and ld pluralization fixesAlan Modra15-42/+127
2017-11-07ngettext supportAlan Modra2-2/+13
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar3-0/+10
2017-11-02[ARM] Help wince objdump on coproc testsThomas Preud'homme3-2/+8
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman21-375/+2909
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme26-35/+328
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu14-1/+41
2017-10-26testsuite/gas/all/fill-1.s: Use L2 rather than .L2.Hans-Peter Nilsson2-2/+6
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra2-10/+18
2017-10-25Yet another fill-1 test fixAlan Modra3-11/+17
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman8-0/+26
2017-10-24RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2Andrew Waterman5-0/+15
2017-10-24Fix my previous gas/ChangeLog entryPalmer Dabbelt1-2/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu7-4/+54
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt2-1/+6
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+162
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki2-3/+6
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist15-0/+1046
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist15-1/+977
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