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2019-04-29S12Z: Opcodes: Fix crash when trying to decode a truncated operation.John Darrington4-0/+27
opcodes/ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. gas/ * testsuite/gas/s12z/truncated.d: New file. * testsuite/gas/s12z/truncated.s: New file. * testsuite/gas/s12z/s12z.exp: Add new test.
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett14-10/+228
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu4-0/+22
The .code16gcc directive supports 16bit mode with 32-bit address. Since IRET (opcode 0xcf) in 16bit mode returns from an interrupt in 16bit mode, we shouldn't add 0x66 prefix for IRET. PR gas/24485 * config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE to IRET for .code16gcc. * testsuite/gas/i386/jump16.s: Add IRET tests. * testsuite/gas/i386/jump16.d: Updated.
2019-04-25Speed up locview resolution with relaxable fragsAlexandre Oliva4-1/+69
Targets such as xtensa incur a much higher overhead to resolve location view numbers than e.g. x86, because the expressions used to compute view numbers cannot be resolved soon enough. Each view number is computed by incrementing the previous view, if they are both at the same address, or by resetting it to zero otherwise. If PV is the previous view number, PL is its location, and NL is the location of the next view, its number is computed by evaluating NV = !(NL > PL) * (PV + 1). set_or_check_view uses resolve_expression to decide whether portions of this expression can be simplified to constants. The (NL > PL) subexpression is one that can often be resolved to a constant, breaking chains of view number computations at instructions of nonzero length, but not after alignment that might be unnecessary. Alas, when nearly every frag ends with a relaxable instruction, frag_offset_fixed_p will correctly fail to determine a known offset between two unresolved addresses in neighboring frags, so the unresolved symbolic operation will be constructed and used in the computation of most view numbers. This results in very deep expressions. As view numbers get referenced in location view lists, each operand in the list goes through symbol_clone_if_forward_ref, which recurses on every subexpression. If each view number were to be referenced, this would exhibit O(n^2) behavior, where n is the depth of the view number expressions, i.e., the length of view number sequences without an early resolution that cuts the expression short. This patch enables address compares used by view numbering to be resolved even when exact offsets are not known, using new logic to determine when the location either remained the same or changed for sure, even with the possibility of relaxation. This enables most view number expressions to be resolved with a small, reasonable depth. PR gas/24444 * frags.c (frag_gtoffset_p): New. * frags.h (frag_gtoffset_p): Declare it. * expr.c (resolve_expression): Use it.
2019-04-24resolve_symbol_value vs. .loc view resolutionAlan Modra3-29/+35
In most cases we don't want expression symbols, such as that created for an expression like "symbol + (1f - .)", resolved down to a constant. Instead we'd like to leave the expression as "symbol + constant" once the "1f - ." part has been resolved, and let the backend decide whether "symbol" can be reduced further. However, that doesn't work when trying to resolve .loc view symbols early. We get expression symbols left as an O_symbol expression pointing at an absolute symbol, and marked as sy_flags.sy_resolved. That wouldn't really be a problem, but when one of those expression symbols is used in further .loc view expressions, its value is taken as zero. This patch fixes the symbol value mistake, and stops creation of O_symbol expression symbols pointing to absolute symbols. Either of these fixes would cure the .loc view usage. PR 24444 * symbols.c (resolve_symbol_value): When handling symbols marked as sy_flags.resolved, return correct value for the case of expression symbols left as an O_symbol expression. Merge O_symbol code handling undefined and common symbols with code handling special cases of expression symbols. Use seg_left to test for undefined and common symbols. Don't leave an O_symbol expression when X_add_symbol resolves to the absolute_section. Init final_val later. * testsuite/gas/mmix/basep-7.d: Adjust expected output.
2019-04-24S12Z: Opcodes: Handle bit map operations with non-canonical operands.John Darrington3-1/+15
opcodes/ * s12z-opc.c (bm_decode): Handle the RESERVERD0 case. gas/ * testsuite/gas/s12z/bit-manip-invalid.d: Extend the test. * testsuite/gas/s12z/bit-manip-invalid.s: Extend the test.
2019-04-19RX Assembler: Ensure that the internal limit on the number of relaxation ↵Nick Clifton3-8/+31
iterations is not larger that the external limit. PR 24464 * config/tc-rx.h (md_relax_frag): Pass the max_iterations variable to the relaxation function. * config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum number of iterations. Make sure that our internal iteration limit does not exceed this external iteration limit.
2019-04-18Improve warning message for $0 constraint on MIPSR6 branchesMatthew Fortune3-11/+20
gas/ * config/tc-mips.c (match_non_zero_reg_operand): Update warning message. * testsuite/gas/mips/r6-branch-constraints.l: Likewise.
2019-04-18MSP430 Assembler: Define symbols for functions to run through.Jozef Lawrynowicz9-6/+141
gas * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_run_{preinit,init,fini}_array symbols if .{preinit,init,fini}_array sections exist. * testsuite/gas/msp430/fini-array.d: New test. * testsuite/gas/msp430/init-array.d: New test. * testsuite/gas/msp430/preinit-array.d: New test. * testsuite/gas/msp430/fini-array.s: New test source. * testsuite/gas/msp430/init-array.s: New test source. * testsuite/gas/msp430/preinit-array.s: New test source. * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
2019-04-17MSP430 Assembler: Leave placement of .lower and .upper sections to generic ↵Jozef Lawrynowicz1-0/+13
linker code. * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss symbol when .lower.bss or .either.bss sections exist. Define __crt0_movedata when .lower.data or .either.data sections exist. * testsuite/gas/msp430/either-data-bss-sym.d: New test. * testsuite/gas/msp430/low-data-bss-sym.d: New test. * testsuite/gas/msp430/either-data-bss-sym.s: New test source. * testsuite/gas/msp430/low-data-bss-sym.s: New test source. * testsuite/gas/msp430/msp430.exp: Run new tests. Enable large code model when running -mdata-region={upper,either} tests.
2019-04-17MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for ↵Jozef Lawrynowicz13-10/+198
unknown interrupt state changes gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS, OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops. (md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops accordingly. (md_show_usage): Likewise. (md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and "mU" for OPTION_NO_UNKNOWN_INTR_NOPS. (md_longopts): Likewise. (warn_eint_nop): Update comment. (warn_unsure_interrupt): Don't warn if prev_insn_is_nop or prev_insn_is_dint or we are assembling for 430 ISA. (msp430_operands): Only call warn_unsure_interrupt if do_unknown_interrupt_nops == TRUE. * testsuite/gas/msp430/nop-unknown-intr.s: New test source file. * testsuite/gas/msp430/nop-unknown-intr-430.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new test. * testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise. * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
2019-04-16xfail gas weakref1 test for nds32Alan Modra2-0/+5
Oops, I removed the wrong xfail from gas.exp in last commit, fix it here. * testsuite/gas/all/weakref1.d: xfail nds32.
2019-04-16ns32k testsuite tidyAlan Modra3-3/+6
Some of these tests were excluded for ns32k-netbsd, exclude for all ns32k instead. binutils/ * testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*. * testsuite/binutils-all/copy-3.d: Likewise. gas/ * testsuite/gas/all/gas.exp: Remove ns32k xfails. * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*. ld/ * testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*. * testsuite/ld-scripts/section-match-1.d: Likewise. * testsuite/ld-undefined/require-defined.exp: Likewise.
2019-04-16Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPEAlan Modra8-68/+66
These are only used by dlx and ns32k. * write.h: Don't include bit_fix.h. (struct fix): Rearrange some fields. Delete fx_im_disp and fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust. * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP. (fixup_segment): Don't exclude overflow checks on fx_bit_fixP. (print_fixup): Don't print im_disp. * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP and fx_im_disp. * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set fx_no_overflow when fx_bit_fixP. * config/tc-dlx.h: Include bit_fix.h. (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define. * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set fx_no_overflow when bit_fixP. * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp. (fix_im_disp, fix_bit_fixP): Adjust to suit. (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
2019-04-16Make fixup fx_where unsignedAlan Modra7-27/+36
Another field that only stores unsigned values. * write.h (struct fix <fx_where>): Make unsigned. (fix_new, fix_at_start, fix_new_exp): Adjust prototypes. * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and "size" parameters unsigned long. (fix_new_internal): Likewise. Adjust error format string to suit. * config/tc-mips.c (md_convert_frag): Remove cast of fx_where. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where. * config/tc-score7.c (s7_convert_frag): Likewise.
2019-04-16Make frag fr_fix unsignedAlan Modra13-23/+40
The field only stores unsigned values, so let's make it unsigned to stop people worrying about the possibility of negative values. * frags.h (struct frag <fr_fix>): Use unsigned type. * frags.c (frag_new): Assert that current size exceeds old_frags_var_max_size. * ehopt.c (get_cie_info): Adjust for unsigned fr_fix. * listing.c (calc_hex): Likewise. * write.c (cvt_frag_to_fill, write_relocs): Likewise. * config/tc-arc.c (md_convert_frag): Likewise. * config/tc-avr.c (avr_patch_gccisr_frag): Likewise. * config/tc-mips.c (md_convert_frag): Likewise. * config/tc-rl78.c (md_convert_frag): Likewise. * config/tc-rx.c (md_convert_frag): Likewise. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise. (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira6-4/+225
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira6-14/+158
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira7-29/+150
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions. In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators. parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand. Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function. Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (enum reg_list_els): Define earlier and add REGLIST_RN and REGLIST_CLRM enumerators. (parse_reg_list): Add etype parameter to distinguish between regular core register list and CLRM register list. Add logic to recognize CLRM register list. (parse_vfp_reg_list): Assert type is not for core register list. (s_arm_unwind_save_core): Update call to parse_reg_list to new prototype. (enum operand_parse_code): Declare OP_CLRMLST enumerator. (parse_operands): Update call to parse_reg_list to new prototype. Add logic for OP_CLRMLST. (encode_thumb2_ldmstm): Rename into ... (encode_thumb2_multi): This. Add do_io parameter. Add logic to encode CLRM and guard LDM/STM only code by do_io. (do_t_ldmstm): Adapt to use encode_thumb2_multi. (do_t_push_pop): Likewise. (do_t_clrm): New function. (insns): Define CLRM. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for CLRM. (print_insn_thumb32): Add logic to print %n CLRM register list.
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M ↵Andre Vieira7-0/+189
Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira4-0/+121
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc ↵Andre Vieira2-0/+42
R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira9-0/+102
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira2-0/+42
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira7-0/+69
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx.
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira9-0/+142
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BF instruction. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instructions for bf.
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc ↵Andre Vieira2-0/+42
R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ↵Andre Vieira2-271/+310
arm_it This patch is part of a series of patches to add support for ARMv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. Their external relocations can be found in the 'ELF for the Arm Architecture - ABI 2019Q1' document on developer.arm.com This is the second infrastructure patch that adds support to allow up to 3 relocations in an instruction. This is done by changing the reloc member of struct arm_it to an array instead (relocs[3]). All the previous occurrences of reloc can now to referring to relocs[0]. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro. (arm_it): Member reloc renamed relocs and updated to an array. Rest: Replace all occurrences of reloc to relocs[0].
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real ↵Andre Vieira2-0/+64
for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira6-4/+585
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline. This patch also removes the fp-armv8 check from the half-precision move instructions 'do_neon_movhf', as checking that the FP16 instructions extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough. gas/ChangeLog: 2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check. (armv8_1m_main_ext_table): New extension table. (arm_archs): Use the new extension table. * doc/c-arm.texi: Add missing arch and document new extensions. * testsuite/gas/arm/armv8.1-m.main-fp.d: New. * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New. * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira3-45/+68
The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune6-1/+63
gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2019-04-13[MIPS] Apply ASE information for the selected processorMatthew Fortune4-7/+51
GAS does not enable implicit ASEs for most MIPS processors. The rework of option handling done as part of .module implementation left the implicit ASE logic broken and default enabled ASEs for most processors did not get applied. This patch ensures the ASE information is carried forward to the point where it is required. gas/ * config/tc-mips.c (mips_set_options) <init_ase>: New field. (file_mips_opts, mips_opts) <init_ase>: Initialize new field. (file_mips_check_options): Propagate initial ASE settings. (mips_after_parse_args, parse_code_option): Track the initial ASE settings for a CPU. (s_mipsset): Restore the initial ASE settings when reverting to the default arch. * testsuite/gas/mips/elf_mach_p6600.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2019-04-12GAS: S12Z: Remove definition of macro TC_M68K.John Darrington2-3/+4
gas/config: * tc-s12z.h: Remove inappropriate macro definition.
2019-04-12GAS: tc-s12z.c: int -> bfd_booleanJohn Darrington2-206/+210
Use bfd_boolean where appropriate.
2019-04-11xtensa: gas: add relaxations testsMax Filippov13-0/+179
gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/loop-relax-2.d: New test definition. * testsuite/gas/xtensa/loop-relax.d: New test definition. * testsuite/gas/xtensa/loop-relax.s: New test source. * testsuite/gas/xtensa/text-section-literals-1a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.s: New test source. * testsuite/gas/xtensa/text-section-literals-2a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.s: New test source. * testsuite/gas/xtensa/text-section-literals-4.d: New test definition. * testsuite/gas/xtensa/text-section-literals-4.s: New test source. * testsuite/gas/xtensa/text-section-literals-4a.d: New test definition.
2019-04-11xtensa: gas: convert tests to run_dump_testsMax Filippov13-105/+63
gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/all.exp: Remove all expect-based tests and all explicit run_dump_test / run_list_test invocations. Add run_dump_tests for all .d files in the test subdirectory. * testsuite/gas/xtensa/entry_align.d: New test definition. * testsuite/gas/xtensa/entry_align.l: New test output. * testsuite/gas/xtensa/entry_misalign.d: New test definition. * testsuite/gas/xtensa/entry_misalign2.d: New test definition. * testsuite/gas/xtensa/j_too_far.d: New test definition. * testsuite/gas/xtensa/j_too_far.l: New test output. * testsuite/gas/xtensa/loop_align.d: New test definition. * testsuite/gas/xtensa/loop_misalign.d: New test definition. * testsuite/gas/xtensa/trampoline-2.d: New test definition. * testsuite/gas/xtensa/trampoline-2.l: Remove empty output. * testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
2019-04-11xtensa: gas: clean up literal management codeMax Filippov2-60/+65
gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has no effect. (get_literal_pool_location): Only search for the literal pool when auto litpools is used, otherwise take one recorded in the tc_segment_info_data. (xtensa_assign_litpool_addresses): New function. (xtensa_move_literals): Don't duplicate 'literal pool location required...' error message. Call xtensa_assign_litpool_addresses.
2019-04-11xtensa: gas: put .literal_position at section startMax Filippov5-25/+34
Provide literal position at the beginning of each section for literal space reserved by relaxations when text-section-literals or auto-litpools options are used. Remove code that adds fill frag to the literal section for every .literal_position directive to avoid creation of empty literal sections. Fix auto-litpools tests that got literal pool address changes. gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_is_init_fini): Add declaration. (xtensa_mark_literal_pool_location): Don't add fill frag to literal section that records literal pool location. (md_begin): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used. (xtensa_elf_section_change_hook): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used, there's no literal pool location defined for the current section and it's not .init or .fini. * testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses. * testsuite/gas/xtensa/auto-litpools-first2.d: Likewise. * testsuite/gas/xtensa/auto-litpools.d: Likewise.
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das6-33/+45
This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das5-0/+39
This patch adds the new LDGM/STGM instructions of the Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release The instructions are as follows: LDGM Xt, [<Xn|SP>] STGM Xt, [<Xn|SP>] *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2019-04-10Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86Rainer Orth21-0/+426
The fix H.J. implemented for PR gas/22791 in the thread starting at [PATCH] x86-64: Treat PC32 relocation with branch as PLT32 https://sourceware.org/ml/binutils/2018-02/msg00065.html is causing problems on Solaris/x86. The native linker is strongly preferred there, and there's no intention of implementing the linker optimization he plans there. Besides, the kernel runtime linker, otherwise has no need to deal with that reloc at all, and instead of adding (possibly even more) workarounds with no benefit, it seems appropriate to disable the R_X86_64_PLT32 generation as branch marker on Solaris/x86 in the first place. The patch itself is trivial, the only complication is adapting the testsuite. Since I've found no way to have conditional sections in the .d files, I've instead used the solution already found elsewhere of having separate .d files for the affected tests in an i386/solaris subdirectory and skipping the original ones. Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without regressions. * config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE. * testsuite/gas/i386/solaris/solaris.exp: New driver. * testsuite/gas/i386/solaris/reloc64.d, testsuite/gas/i386/solaris/x86-64-jump.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d, testsuite/gas/i386/solaris/x86-64-nop-3.d, testsuite/gas/i386/solaris/x86-64-nop-4.d, testsuite/gas/i386/solaris/x86-64-nop-5.d, testsuite/gas/i386/solaris/x86-64-relax-2.d, testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests. * testsuite/gas/i386/reloc64.d, testsuite/gas/i386/x86-64-jump.d, testsuite/gas/i386/x86-64-mpx-branch-1.d, testsuite/gas/i386/x86-64-mpx-branch-2.d, testsuite/gas/i386/x86-64-nop-3.d, testsuite/gas/i386/x86-64-nop-4.d, testsuite/gas/i386/x86-64-nop-5.d, testsuite/gas/i386/x86-64-relax-2.d, testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
2019-04-10te-cloudabi.hAlan Modra5-6/+41
This patch is aimed a fixing large numbers of x86_64-cloudabi failures caused by gas selecting the wrong target name. * config/te-cloudabi.h: New file. * config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI rather than TARGET_OS to select cloudabi. * config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI. * configure.tgt (*-*-cloudabi*): Set em=cloudabi.
2019-04-09[MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek4-0/+71
In Release 6 of the MIPS architecture [1], instruction RDHWR supports a 3rd operand to serve as the 3-bit select field for the hardware register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 332-334 opcodes/ * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. gas/ * testsuite/gas/mips/mips.exp: Run hwr-names test. * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with the SEL field. * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu5-2/+13
Update assembler and readelf to support #define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 (1U << 24) for AVX512_BF16. binutils/ * readelf.c (decode_x86_isa): Handle GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. gas/ * config/tc-i386.c (output_insn): Support GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/gas/i386/property-2.s: Add AVX512_BF16 test. * testsuite/gas/i386/property-2.d: Updated. * testsuite/gas/i386/x86-64-property-2.d: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
2019-04-08x86: Remove i386-*-kaos* and i386-*-chaos targetsH.J. Lu3-4/+6
Remove i386-*-kaos* and i386-*-chaos targets since they are no longer supported by config.sub: $ .../config.sub i386-kaos Invalid configuration `i386-kaos': system `kaos' not recognized $ .../config.sub i386-chaos Invalid configuration `i386-chaos': system `chaos' not recognized $ bfd/ * config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets. gas/ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets. * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos* check. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c. (eelf_i386_chaos.c): Removed. * Makefile.in: Regenerated. * configure.tgt: Remove i[3-7]86-*-kaos*. * emulparams/elf_i386_chaos.sh: Removed.
2019-04-05x86: Add assembler -mx86-used-note=yes testH.J. Lu5-0/+59
Check assembler -mx86-used-note=yes option and readelf -n output. * testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests. * testsuite/gas/i386/property-2.d: New file. * testsuite/gas/i386/property-2.s: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo16-1/+499
Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-04-05PowerPC conditional branch testAlan Modra9-0/+421
Adds a new test checking conditional branch BO values. * testsuite/gas/ppc/bc.s, * testsuite/gas/ppc/bcat.d, * testsuite/gas/ppc/bcaterr.d, * testsuite/gas/ppc/bcaterr.l, * testsuite/gas/ppc/bcy.d, * testsuite/gas/ppc/bcyerr.d, * testsuite/gas/ppc/bcyerr.l: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2019-04-05PowerPC disassembler: Don't emit trailing spacesAlan Modra13-56/+71
When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
generated by cgit v1.1 at 2024-10-14 23:37:40 +0000