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2020-07-22MIPS/GAS/testsuite: Fix JALR relocation tests for IRIX targetsMaciej W. Rozycki26-12/+1857
With IRIX targets the JALR hint relocation is not produced for the o32 ABI, where it is considered a GNU extension. Consequently several tests fail as the output produced by GAS fails to match patterns expecting the relocation to be present where appropriate, even though output produced is indeed correct. As the absence of the relocation is expected, fix the tests by providing respective alternative dump patterns with any JALR relocations removed, removing numerous failures with `*-*-irix*' targets: FAIL: MIPS jal-svr4pic (interaptiv-mr2) FAIL: MIPS jal-svr4pic (micromips) FAIL: MIPS jal-svr4pic (mips1) FAIL: MIPS jal-svr4pic (mips2) FAIL: MIPS jal-svr4pic (mips3) FAIL: MIPS jal-svr4pic (mips4) FAIL: MIPS jal-svr4pic (mips5) FAIL: MIPS jal-svr4pic (mips32) FAIL: MIPS jal-svr4pic (mips32r2) FAIL: MIPS jal-svr4pic (mips32r3) FAIL: MIPS jal-svr4pic (mips32r5) FAIL: MIPS jal-svr4pic (mips32r6) FAIL: MIPS jal-svr4pic (mips64) FAIL: MIPS jal-svr4pic (mips64r2) FAIL: MIPS jal-svr4pic (mips64r3) FAIL: MIPS jal-svr4pic (mips64r5) FAIL: MIPS jal-svr4pic (mips64r6) FAIL: MIPS jal-svr4pic (octeon) FAIL: MIPS jal-svr4pic (octeon2) FAIL: MIPS jal-svr4pic (octeon3) FAIL: MIPS jal-svr4pic (octeonp) FAIL: MIPS jal-svr4pic (r3000) FAIL: MIPS jal-svr4pic (r3900) FAIL: MIPS jal-svr4pic (r4000) FAIL: MIPS jal-svr4pic (r5900) FAIL: MIPS jal-svr4pic (sb1) FAIL: MIPS jal-svr4pic (vr5400) FAIL: MIPS jal-svr4pic (xlr) FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2) FAIL: MIPS jal-svr4pic noreorder (micromips) FAIL: MIPS jal-svr4pic noreorder (mips1) FAIL: MIPS jal-svr4pic noreorder (mips2) FAIL: MIPS jal-svr4pic noreorder (mips3) FAIL: MIPS jal-svr4pic noreorder (mips4) FAIL: MIPS jal-svr4pic noreorder (mips5) FAIL: MIPS jal-svr4pic noreorder (mips32) FAIL: MIPS jal-svr4pic noreorder (mips32r2) FAIL: MIPS jal-svr4pic noreorder (mips32r3) FAIL: MIPS jal-svr4pic noreorder (mips32r5) FAIL: MIPS jal-svr4pic noreorder (mips32r6) FAIL: MIPS jal-svr4pic noreorder (mips64) FAIL: MIPS jal-svr4pic noreorder (mips64r2) FAIL: MIPS jal-svr4pic noreorder (mips64r3) FAIL: MIPS jal-svr4pic noreorder (mips64r5) FAIL: MIPS jal-svr4pic noreorder (mips64r6) FAIL: MIPS jal-svr4pic noreorder (octeon) FAIL: MIPS jal-svr4pic noreorder (octeon2) FAIL: MIPS jal-svr4pic noreorder (octeon3) FAIL: MIPS jal-svr4pic noreorder (octeonp) FAIL: MIPS jal-svr4pic noreorder (r3000) FAIL: MIPS jal-svr4pic noreorder (r3900) FAIL: MIPS jal-svr4pic noreorder (r4000) FAIL: MIPS jal-svr4pic noreorder (r5900) FAIL: MIPS jal-svr4pic noreorder (sb1) FAIL: MIPS jal-svr4pic noreorder (vr5400) FAIL: MIPS jal-svr4pic noreorder (xlr) FAIL: MIPS R3000 jal-xgot FAIL: MIPS -mabi=32 test 2 (SVR4 PIC) FAIL: gas/mips/jalr2 FAIL: Relax microMIPS branches (pic) FAIL: Relax microMIPS branches (insn32 mode, pic) Strictly speaking no MIPSr6 or microMIPS target is supported by IRIX, but GAS supports such configurations on the basis of uniformity, so provide the relevant patterns too rather than excluding the combinations from testing. gas/ * testsuite/gas/mips/jal-svr4pic-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/mipsr6@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-local-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/mips1@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/micromips@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/r3000@jal-svr4pic-noreorder-irix.d: New file. * testsuite/gas/mips/jal-xgot-irix.d: New file. * testsuite/gas/mips/jalr2-irix.d: New file. * testsuite/gas/mips/micromips-branch-relax-insn32-pic-irix.d: New file. * testsuite/gas/mips/micromips-branch-relax-pic-irix.d: New file. * testsuite/gas/mips/mips-abi32-pic2-irix.d: New file. * testsuite/gas/mips/jal-svr4pic-local.d: Don't exclude `*-*-irix*' targets. Add source file designator. * testsuite/gas/mips/mips1@jal-svr4pic-local.d: Don't exclude `*-*-irix*' targets. * testsuite/gas/mips/r3000@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/jalr2.d: Add name designator. * testsuite/gas/mips/mips.exp: Use respective IRIX variants for tests involving the JALR relocation throughout.
2020-07-22MIPS/GAS/testsuite: Use a helper variable for IRIX/non-IRIX test selectionMaciej W. Rozycki2-5/+7
Define a helper variable for IRIX/non-IRIX test selection and use it with the PR 14798 test case. gas/ * testsuite/gas/mips/mips.exp: Use a helper variable for IRIX/non-IRIX test selection.
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich4-13/+20
This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7. In my underlying suggestion I neglected the fact that in those cases (,%eiz,1) is the only visible indication that 32-bit addressing is in effect.
2020-07-21Fix Unreasonable arch and cpu conflict warning for ther CSky architecture.Cooper Qu2-2/+8
* config/tc-csky.c (md_begin): Fix tests of arch and mach flags.
2020-07-21Revert "x86: Replace evex-no-scale.s with evex-no-scale-[32|64].s"Jan Beulich6-9/+26
This reverts commit 19449d7c67690c641b1ec9c13ff3531677a5afcc, addressing the issue that was run into back then: There was no relationship to i686-* and/or cross builds on 64-bit hosts. The sole problem was the use of / as as comment character in certain ELF targets. Instead of division, use a comparison operation. At the same time also revert the ELF related part of 99c2d522f7a7 ("x86: Update assembler tests for non-ELF targets") by replacing the construct that's problematic for non-ELF, and by adding the "#pass" patterns to the expected output files to cover for the tail padding generated into COFF output.
2020-07-21MIPS/GAS: Remove stale `prev_reloc_op_frag' variableMaciej W. Rozycki2-11/+7
Ever since commit 4d7206a284ee ("Rework MIPS macro relaxation, fix string merging bug"), <https://sourceware.org/ml/binutils/2004-01/msg00248.html>, `prev_reloc_op_frag' has only been set and never used. Remove it then. gas/ * config/tc-mips.c (prev_reloc_op_frag): Remove variable. (my_getSmallExpression): Adjust accordingly.
2020-07-20x86: handle SVR4 escaped binary operatorsJan Beulich6-7/+95
PR gas/4572 When / is a comment character, its use as binary "divide" operator needs escaping by a backslash. Besides the scrubber needing to support this (addressed in an earlier change), there are also a few provisions needed in target specific operator handling. As the spec calls for % and * to also be escaped because of being "overloaded", also recognize these, despite the overloading there not really preventing their use as operators in most (%) or all (*) cases, given the way how the rest of the assembler works. To bring source and testsuite in line, also drop the TE_I386AIX part of the respective conditional, as i?86-*-aix* support had been removed a while ago.
2020-07-20gas: generalize comment character escaping recognitionJan Beulich2-18/+15
PR gas/4572 Generalize what ab1fadc6b2f0 ("PR22714, Assembler preprocessor loses track of \@") did to always honor escaped comment chars. Use this then to support escaped /, %, and * operators on x86, when / is a comment char (to match the Sun assembler's behavior).
2020-07-20x86: honor absolute section when emitting codeJan Beulich6-32/+189
Various provisions exist for insns to be placed in the absolute section, yet actually trying to do so didn't work. While data emission (of non- zero values) is not allowed by generic code, I think this functionality is useful for the programmer to be able to determine the size of insns. Therefore, rather than turning the silnet failure into a verbose one, make things mostly work; the one class of insns not supported (yet) are branches (JMP and Jcc) with dynamically determined displacement widths. In this one case, an error now gets reported instead of silently ignoring the code. Also avoid recording ISA / feature usage for insns emitted to the absolute section.
2020-07-20ix86: enable more ELF tests for VxWorksJan Beulich2-9/+19
The tree-wide is_elf_format predicate excludes VxWorks, but the majority of ELF specific tests is quite fine for this target.
2020-07-19x86: Change PLT32 reloc against section to PC32H.J. Lu4-6/+25
Commit 292676c1 resolved PLT32 reloc aganst local symbol to section. Since PLT32 relocation must be against symbols, turn such PLT32 relocation into PC32 relocation. gas/ PR gas/26263 * config/tc-i386.c (i386_validate_fix): Change PLT32 reloc against section to PC32 reloc. * testsuite/gas/i386/relax-5.d: Updated. * testsuite/gas/i386/x86-64-relax-4.d: Likewise. ld/ PR gas/26263 * testsuite/ld-i386/i386.exp: Run PR gas/26263 test. * testsuite/ld-x86-64/x86-64.exp: Likewise. * testsuite/ld-i386/pr26263.d: New file. * testsuite/ld-x86-64/pr26263.d: Likewise. * testsuite/ld-x86-64/pr26263.s: Likewise.
2020-07-15x86: Don't display eiz with no scaleH.J. Lu4-13/+21
Change 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx to 67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx in AT&T syntax and 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef] to 67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef in Intel syntax. gas/ PR gas/26237 * testsuite/gas/i386/evex-no-scale-64.d: Updated. * testsuite/gas/i386/addr32.d: Likewise. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Don't display eiz with no scale without base nor index registers.
2020-07-15Fix the generation of relocs for missing build notes.Nick Clifton2-9/+24
* write.c (create_note_reloc): Add desc2_size parameter. Zero out the addend field of REL relocations. Store the full addend into the note for REL relocations.
2020-07-15x86-64: adjust stack insn test caseJan Beulich5-17/+25
The value chosen for the 16-/32-bit immediate cases didn't work well with the subsequent insn's REX prefix - we ought to pick a value the upper two bytes of which evaluate to a 2-byte insn. Bump the values accordingly, allowing the subsequent insn to actually have the intended REX.W.
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich72-487/+560
"Unambiguous" is is in particular taking as reference the assembler, which also accepts certain insns - despite them allowing for varying operand size, and hence in principle being ambiguous - without any suffix. For example, from the very beginning of the life of x86-64 I had trouble understanding why a plain and simple RET had to be printed as RETQ. In case someone really used the 16-bit form, RETW disambiguates the two quite fine.
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu8-54/+48
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.
2020-07-14x86/Intel: debug registers are named DRnJan Beulich5-7/+14
%db<n> is an AT&T invention; the Intel documentation and MASM have only ever specified DRn (in line with CRn and TRn). (In principle gas also shouldn't accept the names in Intel mode, but at least for now I've kept things as they are. Perhaps as a first step this should just be warned about.)
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich2-4/+8
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich3-4/+9
The operands don't allow disambiguating the insn in 64-bit mode, and hence suffixes need to be emitted not just in AT&T mode. Achieve this by re-using %LQ while dropping PCMPESTR_Fixup().
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich4-0/+58
MOVBE_Fixup() is entirely redundant with the S macro already used on the mnemonics, leading to double suffixes in suffix-always mode. Drop the function.
2020-07-14x86: avoid attaching suffix to register-only CRC32Jan Beulich33-675/+164
Just like other insns with GPR operands, CRC32 with only register operands should not get a suffix added unless in suffix-always mode. Do away with CRC32_Fixup() altogether, using other more generic logic instead.
2020-07-14x86-64: don't hide an empty but meaningless REX prefixJan Beulich5-8/+22
Unlike for non-zero values passed to USED_REX(), where rex_used gets updated only when the respective bit was actually set in the encoding, zero getting passed in is not further guarded, yet such a (potentially "empty") REX prefix takes effect only when there are registers numbered 4 and up.
2020-07-14x86: drop dead code from OP_IMREG()Jan Beulich3-0/+10
There's only a very limited set of modes that this function gets invoked with - avoid it being more generic than it needs to be. This may, down the road, allow actually doing away with the function altogether. This eliminates a first improperly used "USED_REX (0)".
2020-07-14x86-64: fold ILP32 test expectationsJan Beulich17-7806/+36
Various of the test expectations get adjusted later in this and a subsequent series, so in order to avoid having to adjust more instances than necessary fold respective test ILP32 expectations with their main 64-bit counterparts where they're identical anyway.
2020-07-13x86: Remove 32-bit sign extension in offset_in_rangeH.J. Lu2-8/+5
When encoding a 32-bit offset, there is no need to sign-extend it to 64 bits since only the lower 32 bits are used. * config/tc-i386.c (offset_in_range): Remove 32-bit sign extension.
2020-07-13Updated French translation for the gas/ and binutils/ sub-directoriesNick Clifton2-2261/+2649
2020-07-13gas DWARF2 test XPASSesAlan Modra5-8/+11
git commit af2b318648 introduced a number of XPASSes. This removes them. (It also introduces a FAIL on ft32-elf but the comment in the .d file didn't adequately explain why the failure should be expected.) * testsuite/gas/elf/dwarf2-7.d: Remove most xfails. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise.
2020-07-11x86: Support GNU_PROPERTY_X86_FEATURE_2_TMMH.J. Lu9-0/+53
Support GNU_PROPERTY_X86_FEATURE_2_TMM in https://gitlab.com/x86-psABIs/x86-64-ABI/-/merge_requests/1 #define GNU_PROPERTY_X86_FEATURE_2_TMM (1U << 10) binutils/ * readelf.c (decode_x86_feature_2): Handle GNU_PROPERTY_X86_FEATURE_2_TMM. gas/ * config/tc-i386.c (output_insn): Check i.xstate to set GNU_PROPERTY_X86_FEATURE_2_TMM. * testsuite/gas/i386/i386.exp: Run x86-64-property-7, x86-64-property-8 and x86-64-property-9. * testsuite/gas/i386/x86-64-property-7.d: New file. * testsuite/gas/i386/x86-64-property-7.s: Likewise. * testsuite/gas/i386/x86-64-property-8.d: Likewise. * testsuite/gas/i386/x86-64-property-8.s: Likewise. * testsuite/gas/i386/x86-64-property-9.d: Likewise. * testsuite/gas/i386/x86-64-property-9.s: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_TMM): New.
2020-07-10x86: Extract extended states from instruction templateH.J. Lu6-73/+91
Extract extended states from operand types in instruction template. Set xstate_zmm for master register move. * config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm, has_regymm, has_regzmm and has_regtmm. Add xstate. (md_assemble): Set i.xstate from operand types in instruction template. (build_modrm_byte): Updated. (output_insn): Check i.xstate. * testsuite/gas/i386/i386.exp: Run property-6 and x86-64-property-6. * testsuite/gas/i386/property-6.d: New file. * testsuite/gas/i386/property-6.s: Updated. * testsuite/gas/i386/x86-64-property-6.d: Likewise.
2020-07-10gas/i386/property-5.d: Correct test nameH.J. Lu2-1/+5
* testsuite/gas/i386/property-5.d: Correct test name.
2020-07-10x86: Add support for Intel AMX instructionsLili Cui14-13/+460
gas/ * doc/c-i386.texi: Document amx_int8, amx_bf16 and amx_tile. * config/tc-i386.c (i386_error): Add invalid_sib_address. (cpu_arch): Add .amx_int8, .amx_bf16 and .amx_tile. (cpu_noarch): Add noamx_int8, noamx_bf16 and noamx_tile. (match_simd_size): Add tmmword check. (operand_type_match): Add tmmword. (type_names): Add rTMM. (i386_error): Add invalid_tmm_register_set. (check_VecOperands): Handle invalid_sib_address and invalid_tmm_register_set. (match_template): Handle invalid_sib_address. (build_modrm_byte): Handle non-vector SIB and zmmword. (i386_index_check): Disallow RegIP for non-vector SIB. (check_register): Handle zmmword. * testsuite/gas/i386/i386.exp: Add AMX new tests. * testsuite/gas/i386/intel-regs.d: Add tmm. * testsuite/gas/i386/intel-regs.s: Add tmm. * testsuite/gas/i386/x86-64-amx-intel.d: New. * testsuite/gas/i386/x86-64-amx-inval.l: New. * testsuite/gas/i386/x86-64-amx-inval.s: New. * testsuite/gas/i386/x86-64-amx.d: New. * testsuite/gas/i386/x86-64-amx.s: New. * testsuite/gas/i386/x86-64-amx-bad.d: New. * testsuite/gas/i386/x86-64-amx-bad.s: New. opcodes/ * i386-dis.c (TMM): New. (EXtmm): Likewise. (VexTmm): Likewise. (MVexSIBMEM): Likewise. (tmm_mode): Likewise. (vex_sibmem_mode): Likewise. (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise. (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise. (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise. (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise. (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise. (PREFIX_VEX_0F3849_X86_64): Likewise. (PREFIX_VEX_0F384B_X86_64): Likewise. (PREFIX_VEX_0F385C_X86_64): Likewise. (PREFIX_VEX_0F385E_X86_64): Likewise. (X86_64_VEX_0F3849): Likewise. (X86_64_VEX_0F384B): Likewise. (X86_64_VEX_0F385C): Likewise. (X86_64_VEX_0F385E): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise. (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise. (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise. (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F3849_X86_64_P_0): Likewise. (VEX_W_0F3849_X86_64_P_2): Likewise. (VEX_W_0F3849_X86_64_P_3): Likewise. (VEX_W_0F384B_X86_64_P_1): Likewise. (VEX_W_0F384B_X86_64_P_2): Likewise. (VEX_W_0F384B_X86_64_P_3): Likewise. (VEX_W_0F385C_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_0): Likewise. (VEX_W_0F385E_X86_64_P_1): Likewise. (VEX_W_0F385E_X86_64_P_2): Likewise. (VEX_W_0F385E_X86_64_P_3): Likewise. (names_tmm): Likewise. (att_names_tmm): Likewise. (intel_operand_size): Handle void_mode. (OP_XMM): Handle tmm_mode. (OP_EX): Likewise. (OP_VEX): Likewise. * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (operand_type_shorthands): Add RegTMM. (operand_type_init): Likewise. (operand_types): Add Tmmword. (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE. * i386-opc.h (CpuAMX_INT8): New. (CpuAMX_BF16): Likewise. (CpuAMX_TILE): Likewise. (SIBMEM): Likewise. (Tmmword): Likewise. (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile. (i386_opcode_modifier): Extend width of fields vexvvvv and sib. (i386_operand_type): Add tmmword. * i386-opc.tbl: Add AMX instructions. * i386-reg.tbl: Add AMX registers. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2020-07-10[readelf] Fix end_seq entry in -wL. Specifically stop the display of a line ↵Tom de Vries13-12/+28
number and is_statement/has-view fields for the End of Sequence operator, as these have no meaning. binutils* dwarf.c (display_debug_lines_decoded): Don't emit meaningless information in the end_sequence row. * testsuite/binutils-all/dw5.W: Update. * testsuite/binutils-all/objdump.WL: Update. gas * testsuite/gas/elf/dwarf2-11.d: Update expected output from readelf's line table decoding. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-19.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise.
2020-07-09x86: Properly set YMM/ZMM featuresH.J. Lu9-2/+64
Since VEX/EVEX vector instructions will always update the full YMM/ZMM registers, set YMM/ZMM features for VEX/EVEX vector instructions. * config/tc-i386.c (output_insn): Set YMM/ZMM features for VEX/EVEX vector instructions. * testsuite/gas/i386/property-4.d: New file. * testsuite/gas/i386/property-4.s: Likewise. * testsuite/gas/i386/property-5.d: Likewise. * testsuite/gas/i386/property-5.s: Likewise. * testsuite/gas/i386/x86-64-property-4.d: Likewise. * testsuite/gas/i386/x86-64-property-5.d: Likewise.
2020-07-09Linux/x86: Configure gas with --enable-x86-used-note by defaultH.J. Lu4-0/+23
* configure.ac: Configure with --enable-x86-used-note by default for Linux/x86. * configure: Regenerated.
2020-07-09Remove powerpc PE supportAlan Modra7-889/+26
Plus some leftover powerpc lynxos support. bfd/ * coff-ppc.c: Delete. * pe-ppc.c: Delete. * pei-ppc.c: Delete. * Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Remove PE PPC. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags): Remove PPCMAGIC code. (coff_write_object_contents): Remove PPC_PE code. * config.bfd: Move powerpcle-pe to removed targets. * configure.ac: Remove powerpc PE entries. * libcoff-in.h (ppc_allocate_toc_section): Delete. (ppc_process_before_allocation): Delete. * peXXigen.c: Remove POWERPC_LE_PE code and comments. * targets.c: Remove powerpc PE vectors. * po/SRC-POTFILES.in: Regenerate. * libcoff.h: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * dlltool.c: Remove powerpc PE support and comments. * configure.ac: Remove powerpc PE dlltool config. * configure: Regenerate. gas/ * config/obj-coff.h: Remove TE_PE support. * config/tc-ppc.c: Likewise. * config/tc-ppc.h: Likewise. * configure.tgt: Remove powerpc PE and powerpc lynxos. * testsuite/gas/cfi/cfi.exp (cfi-common-6): Remove powerpc PE condition. * testsuite/gas/macros/macros.exp: Don't xfail powerpc PE. include/ * coff/powerpc.h: Delete. ld/ * emulparams/ppcpe.sh: Delete. * scripttempl/ppcpe.sc: Delete. * emulparams/ppclynx.sh: Delete. * Makefile.am (ALL_EMULATION_SOURCES): Remove ppc PE and lynxos. * configure.tgt: Likewise. * emultempl/beos.em: Remove powerpc PE support. * emultempl/pe.em: Likewise. * po/BLD-POTFILES.in: Regenerate. * Makefile.in: Regenerate.
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich4-0/+110
Just like other VEX-encoded scalar insns do. Besides a testcase for this behavior also introduce one to verify that XOP scalar insns don't honor -mavxscalar=256, as they don't ignore XOP.L.
2020-07-07arc: Improve error messages when assemblingClaudiu Zissulescu7-30/+63
gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (find_opcode_match): Add error messages. * testsuite/gas/arc/add_s-err.s: Update test. * testsuite/gas/arc/asm-errors.err: Likewise. * testsuite/gas/arc/cpu-em-err.s: Likewise. * testsuite/gas/arc/hregs-err.s: Likewise. * testsuite/gas/arc/warn.s: Likewise.
2020-07-07arc: Update vector instructions.Claudiu Zissulescu1-2/+2
Update vadd2, vadd4h, vmac2h, vmpy2h, vsub4h vector instructions arguments to discriminate between double/single register operands. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rbd): New function. (RBD): Define. (RBDdup): Likewise. * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update instructions. Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-07-07x86: Remove an incorrect AVX2 entryH.J. Lu2-10/+5
The upper 16 vector registers were added by AVX512. PR gas/26212 * doc/c-i386.texi: Remove an incorrect AVX2 entry.
2020-07-07Use is_xcoff_format in gas testsuiteAlan Modra4-5/+11
* testsuite/gas/all/gas.exp: Use is_xcoff_format. * testsuite/gas/ppc/ppc.exp: Likewise. * testsuite/gas/all/weakref1l.d: Likewise.
2020-07-07Fix recent failures in the ARM assembler testsuite due to the correction of ↵Nick Clifton2-92/+97
a spelling mistake. * testsuite/gas/arm/cde-missing-fp.l: Fix spelling mistake in expected output.
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich5-36/+44
Just like their AVX counterparts do for VEX.L. At this occasion also make EVEX.W have the same effect as VEX.W on the printing of VPINSR{B,W}'s operands, bringing them also in sync with VPEXTR{B,W}.
2020-07-06x86: replace EXqScalarS by EXqVexScalarSJan Beulich7-4/+21
There's only a single user, that that one can do fine with the alternative, as the "Vex" aspect of the other operand kind is meaningful only on 3-operand insns. While doing this I noticed that I didn't need to do the same adjustment in the EVEX tables, and voilà - there was a bug, which gets fixed at the same time (see the testsuite changes).
2020-07-06Fix spelling mistakes in some of the binutils sub-directories.Nick Clifton5-12/+20
PR 26204 gas * config/tc-arm.c: Fix spelling mistake. * config/tc-riscv.c: Likewise. * config/tc-z80.c: Likewise. * po/gas.pot: Regenerate. ld * lexsup.c: Fix spelling mistake. * po/ld.pot: Regenerate. opcodes * arc-dis.c: Fix spelling mistake. * po/opcodes.pot: Regenerate.
2020-07-06Updated translations for various binutils sub-directoriesNick Clifton2-2255/+2647
2020-07-04Update version to 2.35.50 and regenerate filesNick Clifton3-1581/+1608
2020-07-04Add markers for binutils 2.35 branchNick Clifton2-0/+6
2020-07-03Re: Change readelf's display of symbol namesAlan Modra2-1/+6
Fixes some fallout from git commit 0942c7ab94e5. PR 26028 gas/ * testsuite/gas/ia64/unwind-ilp32.d: Add -T to readelf options. gold/ * testsuite/Makefile.am (file_in_many_sections.stdout): Add -W to readelf options. * testsuite/Makefile.in: Regenerate. ld/ * testsuite/ld-arm/arm-elf.exp (vxworks1): Pass --wide to readelf when dumping relocs. * testsuite/ld-i386/i386.exp (vxworks1): Likewise. * testsuite/ld-sh/sh-vxworks.exp (vxworks1): Likewise. * testsuite/ld-sparc/sparc.exp (vxworks1): Likewise. * testsuite/ld-arm/vxworks1.rd: Adjust to suit. * testsuite/ld-i386/vxworks1.rd: Adjust. * testsuite/ld-sh/vxworks1.rd: Adjust. * testsuite/ld-sparc/vxworks1.rd: Adjust.
2020-07-02x86: Add SwapSourcesH.J. Lu2-4/+7
We check register-only source operand to decide if two source operands of VEX encoded instructions should be swapped. But source operands in AMX instructions with two source operands swapped are all register-only operand. Add SwapSources to indicate two source operands should be swapped. gas/ * config/tc-i386.c (build_modrm_byte): Check vexswapsources to swap two source operands. opcodes/ * i386-gen.c (opcode_modifiers): Add VexSwapSources. * i386-opc.h (VexSwapSources): New. (i386_opcode_modifier): Add vexswapsources. * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions with two source operands swapped. * i386-tbl.h: Regenerated.
2020-07-02Skip fill-1 gas test for MeP targets.Nick Clifton2-1/+7
* testsuite/gas/all/fill-1.d: Skip for MeP targets.
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