arc: Improve error messages when assembling

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Add error messages.
	* testsuite/gas/arc/add_s-err.s: Update test.
	* testsuite/gas/arc/asm-errors.err: Likewise.
	* testsuite/gas/arc/cpu-em-err.s: Likewise.
	* testsuite/gas/arc/hregs-err.s: Likewise.
	* testsuite/gas/arc/warn.s: Likewise.

7 files changed, 63 insertions, 30 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5954e0c..0be7fa3f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-07-07  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/tc-arc.c (find_opcode_match): Add error messages.
+	* testsuite/gas/arc/add_s-err.s: Update test.
+	* testsuite/gas/arc/asm-errors.err: Likewise.
+	* testsuite/gas/arc/cpu-em-err.s: Likewise.
+	* testsuite/gas/arc/hregs-err.s: Likewise.
+	* testsuite/gas/arc/warn.s: Likewise.
+
 2020-07-07  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/26212
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index f8d469c..0a22d38 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1758,8 +1758,9 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
   int ntok = *pntok;
   int got_cpu_match = 0;
   expressionS bktok[MAX_INSN_ARGS];
-  int bkntok;
+  int bkntok, maxerridx = 0;
   expressionS emptyE;
+  const char *tmpmsg = NULL;
 
   arc_opcode_hash_entry_iterator_init (&iter);
   memset (&emptyE, 0, sizeof (emptyE));
@@ -1806,7 +1807,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 	    {
             case ARC_OPERAND_ADDRTYPE:
 	      {
-		*errmsg = NULL;
+		tmpmsg = NULL;
 
 		/* Check to be an address type.  */
 		if (tok[tokidx].X_op != O_addrtype)
@@ -1817,8 +1818,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 		   address type.  */
 		gas_assert (operand->insert != NULL);
 		(*operand->insert) (0, tok[tokidx].X_add_number,
-				    errmsg);
-		if (*errmsg != NULL)
+				    &tmpmsg);
+		if (tmpmsg != NULL)
 		  goto match_failed;
 	      }
               break;
@@ -1844,11 +1845,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 	      /* Special handling?  */
 	      if (operand->insert)
 		{
-		  *errmsg = NULL;
+		  tmpmsg = NULL;
 		  (*operand->insert)(0,
 				     regno (tok[tokidx].X_add_number),
-				     errmsg);
-		  if (*errmsg)
+				     &tmpmsg);
+		  if (tmpmsg)
 		    {
 		      if (operand->flags & ARC_OPERAND_IGNORE)
 			{
@@ -1957,26 +1958,35 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 			}
 
 		      if (val < min || val > max)
-			goto match_failed;
+			{
+			  tmpmsg = _("immediate is out of bounds");
+			  goto match_failed;
+			}
 
 		      /* Check alignments.  */
 		      if ((operand->flags & ARC_OPERAND_ALIGNED32)
 			  && (val & 0x03))
-			goto match_failed;
+			{
+			  tmpmsg = _("immediate is not 32bit aligned");
+			  goto match_failed;
+			}
 
 		      if ((operand->flags & ARC_OPERAND_ALIGNED16)
 			  && (val & 0x01))
-			goto match_failed;
+			{
+			  tmpmsg = _("immediate is not 16bit aligned");
+			  goto match_failed;
+			}
 		    }
 		  else if (operand->flags & ARC_OPERAND_NCHK)
 		    {
 		      if (operand->insert)
 			{
-			  *errmsg = NULL;
+			  tmpmsg = NULL;
 			  (*operand->insert)(0,
 					     tok[tokidx].X_add_number,
-					     errmsg);
-			  if (*errmsg)
+					     &tmpmsg);
+			  if (tmpmsg)
 			    goto match_failed;
 			}
 		      else if (!(operand->flags & ARC_OPERAND_IGNORE))
@@ -1997,11 +2007,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 		      regs |= get_register (tok[tokidx].X_op_symbol);
 		      if (operand->insert)
 			{
-			  *errmsg = NULL;
+			  tmpmsg = NULL;
 			  (*operand->insert)(0,
 					     regs,
-					     errmsg);
-			  if (*errmsg)
+					     &tmpmsg);
+			  if (tmpmsg)
 			    goto match_failed;
 			}
 		      else
@@ -2044,7 +2054,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 		      || t->X_op == O_absent
 		      || t->X_op == O_register
 		      || (t->X_add_number != tok[tokidx].X_add_number))
-		    goto match_failed;
+		    {
+		      tmpmsg = _("operand is not duplicate of the "
+				 "previous one");
+		      goto match_failed;
+		    }
 		}
 	      t = &tok[tokidx];
 	      break;
@@ -2060,7 +2074,10 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 
       /* Setup ready for flag parsing.  */
       if (!parse_opcode_flags (opcode, nflgs, first_pflag))
-	goto match_failed;
+	{
+	  tmpmsg = _("flag mismatch");
+	  goto match_failed;
+	}
 
       pr_debug ("flg");
       /* Possible match -- did we use all of our input?  */
@@ -2070,12 +2087,19 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 	  pr_debug ("\n");
 	  return opcode;
 	}
+      tmpmsg = _("too many arguments");
 
     match_failed:;
       pr_debug ("\n");
       /* Restore the original parameters.  */
       memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
       ntok = bkntok;
+      if (tokidx >= maxerridx
+	  && tmpmsg)
+	{
+	  maxerridx = tokidx;
+	  *errmsg = tmpmsg;
+	}
     }
 
   if (*pcpumatch)
diff --git a/gas/testsuite/gas/arc/add_s-err.s b/gas/testsuite/gas/arc/add_s-err.s
index 95fcf64..b7b7082 100644
--- a/gas/testsuite/gas/arc/add_s-err.s
+++ b/gas/testsuite/gas/arc/add_s-err.s
@@ -6,5 +6,5 @@
         ;; The following insns are accepted by ARCv2 only
         add_s r4,r4,-1          ; { dg-error "Error: register must be either r0-r3 or r12-r15 for instruction" }
         add_s 0,0xAAAA5555,-1   ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
-        add_s r0,r15,0x20       ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
-        add_s r1,r15,0x20       ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+        add_s r0,r15,0x20       ; { dg-error "Error: immediate is out of bounds for instruction 'add_s'" }
+        add_s r1,r15,0x20       ; { dg-error "Error: immediate is out of bounds for instruction 'add_s'" }
diff --git a/gas/testsuite/gas/arc/asm-errors.err b/gas/testsuite/gas/arc/asm-errors.err
index e889eb8..ccc65fe 100644
--- a/gas/testsuite/gas/arc/asm-errors.err
+++ b/gas/testsuite/gas/arc/asm-errors.err
@@ -1,6 +1,6 @@
 [^:]*: Assembler messages:
-[^:]*:2: Error: inappropriate arguments for opcode 'adc'
-[^:]*:3: Error: inappropriate arguments for opcode 'adc'
-[^:]*:4: Error: inappropriate arguments for opcode 'adc'
+[^:]*:2: Error: flag mismatch for instruction 'adc'
+[^:]*:3: Error: flag mismatch for instruction 'adc'
+[^:]*:4: Error: flag mismatch for instruction 'adc'
 [^:]*:5: Error: extra comma
 [^:]*:5: Error: syntax error
diff --git a/gas/testsuite/gas/arc/cpu-em-err.s b/gas/testsuite/gas/arc/cpu-em-err.s
index 4faaae7..49b2951 100644
--- a/gas/testsuite/gas/arc/cpu-em-err.s
+++ b/gas/testsuite/gas/arc/cpu-em-err.s
@@ -1,4 +1,4 @@
 ;;; Check if .cpu em doesn't have code-density ops.
 ; { dg-do assemble { target arc*-*-* } }
 	.cpu	em
-	sub_s r15,r2,r15	; { dg-error "Error: inappropriate arguments for opcode 'sub_s'" }
+	sub_s r15,r2,r15 ; { dg-error "Error: register must be SP for instruction 'sub_s'" }
diff --git a/gas/testsuite/gas/arc/hregs-err.s b/gas/testsuite/gas/arc/hregs-err.s
index f5fa5e8..a76415b 100644
--- a/gas/testsuite/gas/arc/hregs-err.s
+++ b/gas/testsuite/gas/arc/hregs-err.s
@@ -1,11 +1,11 @@
 ; { dg-do assemble { target arc*-*-* } }
 	.cpu	HS
 	.text
-	ld_s	r0,[r32,28]	; { dg-error "Error: register must be R1 for instruction 'ld_s'" }
+	ld_s	r0,[r32,28]	; { dg-error "Error: register must be GP for instruction 'ld_s'" }
 	ld_s	r0,[r28,28]
 	ld_s	r1,[r32,28]	; { dg-error "Error: register must be GP for instruction 'ld_s'" }
-	ld_s	r2,[r32,28]	; { dg-error "Error: register must be R1 for instruction 'ld_s'" }
+	ld_s	r2,[r32,28]	; { dg-error "Error: register must be PCL for instruction 'ld_s'" }
 	ld_s	r3,[pcl,0x10]
-	add_s	r0,r0,r32	; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
+	add_s	r0,r0,r32	; { dg-error "Error: register out of range for instruction 'add_s'" }
 	add_s	r0,r0,r28
-	mov_s.ne r0,r32		; { dg-error "Error: inappropriate arguments for opcode 'mov_s'" }
+	mov_s.ne r0,r32		; { dg-error "Error: register out of range for instruction 'mov_s'" }
diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s
index deec175..592ee31 100644
--- a/gas/testsuite/gas/arc/warn.s
+++ b/gas/testsuite/gas/arc/warn.s
@@ -3,9 +3,9 @@
 ; { dg-do assemble { target arc*-*-* } }
 
 	b.d foo
-	mov r0,256	
+	mov r0,256
 
-	j.d foo		; { dg-warning "inappropriate arguments for opcode" "inappropriate arguments for opcode" }
+	j.d foo		; { dg-error "Error: flag mismatch for instruction 'j'" }
 	mov r0,r1
 
 foo: