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2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor ↵Jin Ma2-0/+358
extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds floating-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for floating-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor ↵Jin Ma2-0/+178
extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds fixed-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for fixed-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAADDVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma2-0/+657
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds integer arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for integer arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VADCVVM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma3-0/+161
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvamo" for the "XTheadVector" extension, and it provides AMO instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvamo" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-zvamo.d: New test. * testsuite/gas/riscv/x-thead-vector-zvamo.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma2-0/+1708
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds provides load/store segment instructions for T-Head VECTOR vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector extension, but belongs to the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add test. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma2-0/+268
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds load/store instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for load/store instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLBV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2023-11-23RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor ↵Jin Ma2-0/+15
extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds configuration-setting instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. opcodes/ChangeLog: * riscv-opc.c: Likewise..
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma5-0/+57
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the CSRs for XTheadVector. Because of the conflict between encoding and teh 'V' extension, it is implemented by alias. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add the class for the CSRs of the "XTheadVector" extension. (riscv_csr_address): Likewise. * testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test. * testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test. * testsuite/gas/riscv/x-thead-vector-csr.d: New test. * testsuite/gas/riscv/x-thead-vector-csr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma5-0/+13
T-Head has a range of vendor-specific instructions ([2]). Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 [2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class):
2023-11-22LoongArch: fix internal error when as handling unsupported modifier.Lulu Cai4-1/+13
2023-11-21bpf: Fixed register parsing disambiguating with possible symbol.Cupertino Miranda2-0/+7
This changes parse_bpf_register to detect possible symbols that start with valid register name, however due some following characters are not. Also changed the regs-for-symbols-pseudo.s, adding some entries that should not error if parser is properly detecting the symbol.
2023-11-18gas: bpf: do not allow referring to register names as symbols in operandsJose E. Marchesi7-49/+102
2023-11-18 Jose E. Marchesi <jemarch@gnu.org> * config/tc-bpf.c (parse_bpf_register): Move before bpf_parse_name. (bpf_parse_name): Do not allow using symbols that are also register names as operands in pseudo-c syntax. * testsuite/gas/bpf/regs-for-symbols-pseudoc.d: New file. * testsuite/gas/bpf/regs-for-symbols-pseudoc.s: Likewise. * testsuite/gas/bpf/regs-for-symbols-pseudoc.l: Likewise. * doc/c-bpf.texi (BPF Registers): Document that it is not possible to refer to register names as symbols in instruction operands.
2023-11-17bpf: avoid creating wrong symbols while parsingDavid Faust5-0/+107
To support the "pseudo-C" asm dialect in BPF, the BPF parser must often attempt multiple different templates for a single instruction. In some cases this can cause the parser to incorrectly parse part of the instruction opcode as an expression, which leads to the creation of a new undefined symbol. Once the parser recognizes the error, the expression is discarded and it tries again with a new instruction template. However, symbols created during the process are added to the symbol table and are not removed even if the expression is discarded. This is a problem for BPF: generally the assembled object will be loaded directly to the Linux kernel, without being linked. These erroneous parser-created symbols are rejected by the kernel BPF loader, and the entire object is refused. This patch remedies the issue by tentatively creating symbols while parsing instruction operands, and storing them in a temporary list rather than immediately inserting them into the symbol table. Later, after the parser is sure that it has correctly parsed the instruction, those symbols are committed to the real symbol table. This approach is modeled directly after Jan Beulich's patch for RISC-V: commit 7a29ee290307087e1749ce610207e93a15d0b78d RISC-V: adjust logic to avoid register name symbols Many thanks to Jan for recognizing the problem as similar, and pointing me to that patch. gas/ * config/tc-bpf.c (parsing_insn_operands): New. (parse_expression): Set it here. (deferred_sym_rootP, deferred_sym_lastP): New. (orphan_sym_rootP, orphan_sym_lastP): New. (bpf_parse_name): New. (parse_error): Clear deferred symbol list on error. (md_assemble): Clear parsing_insn_operands. Commit deferred symbols to symbol table on successful parse. * config/tc-bpf.h (md_parse_name): Define to... (bpf_parse_name): ...this. New prototype. * testsuite/gas/bpf/asm-extra-sym-1.s: New test source. * testsuite/gas/bpf/asm-extra-sym-1.d: New test. * testsuite/gas/bpf/bpf.exp: Run new test.
2023-11-17x86: improve a few diagnosticsJan Beulich9-84/+93
PR gas/31043 "unsupported instruction ..." can mean about anything, and can also be mistaken to mean something that isn't meant. Replace most of its uses by more specific diagnostics, While there also take the opportunity and purge the no longer used invalid_register_operand enumerator.
2023-11-17x86: don't allow pseudo-prefixes to be overridden by legacy suffixesJan Beulich1-3/+19
Deprecated functionality would better not win over its modern counterparts.
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich5-19/+68
{disp16} is invalid to use in 64-bit mode, while {disp32} is invalid to use on pre-386 CPUs. The latter, also affecting other (real) prefixes, further requires that like for insns we fully check the CPU flags; till now only Cpu64/CpuNo64 were taken into consideration.
2023-11-17x86: use IS_ELFJan Beulich2-7/+4
... instead of (inefficiently) open-coding it.
2023-11-17x86: conditionally hide object-format-specific functionsJan Beulich2-23/+31
ELF-only functions don't need to be built when dealing with a non-ELF target. md_section_align() also doesn't need to be a function when dealing with non-AOUT targets. Similarly tc_fix_adjustable() can be a simple macro when building non-ELF targets. Furthermore x86_elf_abi is already used in ELF-only code sections, with one exception. By adjusting that, the otherwise bogusly named variable can also be confined to just ELF builds.
2023-11-17x86: fold conditionals in check_long_reg()Jan Beulich1-13/+5
Simplify the code follow ing what check_{,q}word_reg() already do. This the also eliminates a stale comment talking about a warning when an error is raised. While there, correct a similarly stale comment in check_qword_reg() while there.
2023-11-17x86-64: extend expected-size check in check_qword_reg()Jan Beulich3-19/+26
Due to a missing check "crc32q %al, %rax" was wrongly translated to the encoding of "crc32q %rax, %rax", rather than being rejected as invalid. (The mnemonic suffix describes the source operand, not the destination one.) Note that check_{word,long}_reg() do not (currently) appear to require similar amending, as there are no insn templates permitting an L or W suffix and having an operand which allows for Reg8 and Reg64, but neither Reg16 nor Reg32.
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni3-0/+166
This patch adds the permission model enhancement and memory attribute index enhancement features and their corresponding system registers in AArch64 assembler. Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE) Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE) Memory Attribute Index Enhancement (FEAT_AIE) Extension to Translation Control Registers (FEAT_TCR2) These features are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni3-0/+11
This patch adds 3 new AT system instructions through FEAT_ATS1A feature, which are available by default from Armv9.4-A architecture.
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni8-5/+87
This patch also adds support for: 1. FEAT_RASv2 feature and "ERXGSR_EL1" system register. RASv2 feature is enabled by passing +rasv2 to -march (eg: -march=armv8-a+rasv2). 2. FEAT_SCTLR2 and following system registers. SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3. 3. FEAT_FGT2 and following system registers. HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2 4. FEAT_PFAR and following system registers. PFAR_EL1, PFAR_EL2 and PFAR_EL12. FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default enabled from Armv9.4-A architecture. This patch also adds support for two read only system registers id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from Armv8-A Architecture.
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni4-0/+18
This patch adds features to the Statistical Profiling Extension, identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which are enabled by default from Armv9.4-A. Also adds support for system register "pmsdsfr_el1".
2023-11-16aarch64: Add SLC target for PRFM instruction.Srinath Parvathaneni2-26/+32
This patch adds support for FEAT_PRFMSLC feature which enables SLC target for PRFM instructions.
2023-11-15GAS/MIPS: add "--defsym r6=" for default when it's r6YunQiang Su2-0/+10
* testsuite/gas/mips/mips.exp (mips_arch_create): Add "--defsym r6=" to as_flags for r6 targets.
2023-11-15Finalized intl-update patchesArsen Arsenovi?6-1358/+3522
* intl: Remove directory. Replaced with out-of-tree GNU gettext. * .gitignore: Add '/gettext*'. * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag. Skips appending current flag to bbaseargs. <library exemptions>: Exempt --with-libintl-{type,prefix} from target and build machine argument passing. * configure: Regenerate. * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext. * Makefile.in: Regenerate. * src-release.sh: Remove references to the intl/ directory.
2023-11-15MIPS: Fix Irix gas testcases about pdr sectionYunQiang Su10-7/+40
* testsuite/gas/elf/elf.exp (section2): Add -mpdr option to assembler command line for mips-irix targets. * testsuite/gas/mips/elf-rel26.d: Add -mpdr command line option. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-f.d: Likewise. * testsuite/gas/mips/mips16-hilo-match.d: Likewise. * testsuite/gas/mips/mips16-e-irix.d: Likewise. * testsuite/gas/mips/call-nonpic-1.d: Adjust regexp to allow for mips-irix targets. * testsuite/gas/mips/irix-no-pdr.d: New test file. * testsuite/gas/mips/mips.exp: Run new test for mips-irix targets.
2023-11-13Regenerate gas/config.in and ld/configureMark Wielaard1-3/+3
commit d173146d9 "MIPS: Change all E_MIPS_* to EF_MIPS_*" changed gas/config.in to rename USE_E_MIPS_ABI_O32 to USE_EF_MIPS_ABI_O32 this new name sorts differently when regenerating gas/config.in commit e922d1eaa "Add ability to change linker warning messages into errors when reporting executable stacks and/or executable segments." Introduced two new help strings for --enable-error-execstack and --enable-error-rwx-segments in configure.ac which weren't included in ld/configure when regenerated. * gas/config.in: Regenerate. * ld/configure: Likewise.
2023-11-13Add documentation for the MIPS assembler's -march=from-abi command line optionNick Clifton1-0/+5
2023-11-10GAS/MIPS: Fix testcase module-defer-warn2 for r2+ triplesYunQiang Su4-1/+14
2023-11-10GAS/MIPS: Add mips16-e-irix.d testcaseYunQiang Su2-1/+51
2023-11-10MIPS: Change all E_MIPS_* to EF_MIPS_*Ying Huang4-16/+16
2023-11-10Add support for ilp32 register alias.Lulu Cai1-23/+18
2023-11-09aarch64: Fix error in THE system register checkingVictor Do Nascimento2-0/+10
The erroneous omission of a "reg_value == " in the THE system register encoding check added in [1] led to an error which was not picked up in GCC but which was flagged in Clang due to its use of [-Werror,-Wconstant-logical-operand] check. Together with this fix we add a new test for the THE registers to pick up their illegal use, adding an extra and important layer of validation. Furthermore, in separating system register from instruction implementation (with which only the former was of concern in the cited patch), additions made to `aarch64-tbl.h' are rolled back so that these can be added later when adding THE instructions to the codebase, a more natural place for these changes. [1] https://sourceware.org/pipermail/binutils/2023-November/130314.html opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Fix typo. * aarch64-tbl.h (THE): Remove. (aarch64_feature_set aarch64_feature_the): Likewise. gas/ChangeLog: * testsuite/gas/aarch64/illegal-sysreg-8.l: Add tests for THE system registers. * testsuite/gas/aarch64/illegal-sysreg-8.s: Likewise.
2023-11-09x86: rework UWRMSR operand swappingJan Beulich1-15/+8
As indicated during review already, doing the swapping early is overall cheaper than doing it only after operand matching.
2023-11-09x86: do away with is_evex_encoding()Jan Beulich1-30/+15
As we have grown more uses of it, it becomes increasingly more desirable to replace it by a simpler check. Have i386-gen do at build time what so far was done at runtime: Deal with templates indicating EVEX-encoding by other than the EVex attribute, and set that to "dynamic" in such cases. This then allows simplifying a number of other conditionals as well.
2023-11-09x86: split insn templates' CPU fieldJan Beulich1-92/+81
Right now the opcode table has entries with ISA restrictions of the form FEAT1|FEAT2, the meaning of which depends on context and requires special treatment in tc-i386.c: Sometimes this means "both features requires", whereas originally it was intended to solely mean "all of these features required". Split the field, with the original one regaining its original meaning. The new field now truly means "any of these". The combination of both fields is still and &&-type check, i.e. (all of these) && (any of these). In the opcode table more involved combinations of features then also need expressing this way: "all" entities first, follow by "any" entities enclosed in parentheses, e.g. x64&(AVX|AVX512F). If the "all" part is empty, parentheses may not be added around the "any" part (unless parsing logic was further relaxed). Note that this way AVX512VL no longer needs as much special treatment, and hence templates previously using AVX512F|AVX512VL are switched to just AVX512VL. Note further that this requires FMA handling as resulting from da0784f961d8 ("x86: fold FMA VEX and EVEX templates") to be slightly re-done: FMA now becomes more similar to AVX and AVX2.
2023-11-09x86: Cpu64 handling improvementsJan Beulich1-5/+13
First of all we want to also accumulate its reverse dependencies, such that we can use them in cpu_flags_match(). This is in particular in preparation of APX additions, such that e.g. BMI VEX-encoding templates can become combined VEX/EVEX ones. Once we have the reverse dependencies, we can further leverage them to omit explicit "&x64" from any insn templates dealing with 64-bit-mode- only ISA extensions. Besides helping readability for several insn templates we already have, this will also help with what is going to be added for APX (as all of the new templates would otherwise need to have "&x64"). Note that rather than leaving a meaningless CPU_64_FLAGS (which is unused anyway), its emitting is now also suppressed.
2023-11-08gas: S_GET_{NAME,SEGMENT}() don't alter their input symbolJan Beulich2-4/+4
Make their parameters pointer-to-const, thus allowing callers to also be const-correct where possible.
2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento3-0/+67
Implement, together with the necessary tests, the following new LSE128 atomic instructions: * Atomic bit clear on quadword in memory (ldclrp{a|l|al}); * Atomic bit set on quadword in memory (ldsetp{a|l|al}); * Swap quadword in memory (swpp{a|l|al}); gas/ChangeLog: * testsuite/gas/aarch64/lse128-atomic.d: New. * testsuite/gas/aarch64/lse128-atomic.s: Likewise. opcodes/ChangeLog: * aarch64-tbl.h (ldclrp): new _LSE128_INSN entry. (ldclrpa): Likewise. (ldclrpal): Likewise. (ldclrpl): Likewise. (ldsetp): Likewise. (ldsetpa): Likewise. (ldsetpal): Likewise. (ldsetpl): Likewise. (swpp): Likewise. (swppa): Likewise. (swppal): Likewise. (swppl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento2-0/+3
Enable the `+lse128' feature modifier which, together with new internal feature flags, enables LSE128 instructions, which are represented via the new `_LSE128_INSN' macro. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add new "lse128" entry. include/ChangeLog: * include/opcode/aarch64.h (enum aarch64_feature_bit): New AARCH64_FEATURE_LSE128 feature bit. (enum aarch64_insn_class): New lse128_atomic instruction class. opcodes/ChangeLog: * opcodes/aarch64-tbl.h (aarch64_feature_lse128): New. (LSE128): Likewise. (_LSE128_INSN): Likewise.
2023-11-07aarch64: Add LSE128 instruction operand supportVictor Do Nascimento1-0/+5
Given the particular encoding of the LSE128 instructions, create the necessary shared input+output operand register description and handling in the code to allow for the encoding of the LSE128 128-bit atomic operations. gas/ChangeLog: * config/tc-aarch64.c (parse_operands): include/ChangeLog: * opcode/aarch64.h (enum aarch64_opnd): opcodes/ChangeLog: * aarch64-opc.c (fields): (aarch64_print_operand): * aarch64-opc.h (enum aarch64_field_kind): * aarch64-tbl.h (AARCH64_OPERANDS):
2023-11-07aarch64: Add THE system register supportVictor Do Nascimento4-0/+13
Add Binutils support for system registers associated with the Translation Hardening Extension (THE). In doing so, we also add core feature support for THE, enabling its associated feature flag and implementing the necessary feature-checking machinery. Regression tested on aarch64-linux-gnu, no regressions. gas/ChangeLog: * config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier. * doc/c-aarch64.texi (AArch64 Extensions): Update documentation for `the' option. * testsuite/gas/aarch64/sysreg-8.s: Add tests for `the' associated system registers. * testsuite/gas/aarch64/sysreg-8.d: Likewise. include/ChangeLog: * opcode/aarch64.h (enum aarch64_feature_bit): Add AARCH64_FEATURE_THE. opcode/ChangeLog: * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the' system register check support. * aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1' * aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett31-0/+671
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCValu as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-alu-boundaries.d: New test. * testsuite/gas/riscv/cv-alu-boundaries.l: New test. * testsuite/gas/riscv/cv-alu-boundaries.s: New test. * testsuite/gas/riscv/cv-alu-fail-march.d: New test. * testsuite/gas/riscv/cv-alu-fail-march.l: New test. * testsuite/gas/riscv/cv-alu-fail-march.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test. * testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test. * testsuite/gas/riscv/cv-alu-insns.d: New test. * testsuite/gas/riscv/cv-alu-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble xcb operand. * riscv-opc.c: Defined the MASK and added XCValu instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCValu. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for XCValu. (enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett10-0/+557
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Added the necessary operands for the extension. (riscv_ip): Likewise. * doc/c-riscv.texi: Noted XCVmac as an additional ISA extension for CORE-V. * testsuite/gas/riscv/cv-mac-fail-march.d: New test. * testsuite/gas/riscv/cv-mac-fail-march.l: New test. * testsuite/gas/riscv/cv-mac-fail-march.s: New test. * testsuite/gas/riscv/cv-mac-fail-operand.d: New test. * testsuite/gas/riscv/cv-mac-fail-operand.l: New test. * testsuite/gas/riscv/cv-mac-fail-operand.s: New test. * testsuite/gas/riscv/cv-mac-insns.d: New test. * testsuite/gas/riscv/cv-mac-insns.s: New test. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Disassemble information with the EXTRACT macro implemented. * riscv-opc.c: Defined the MASK and added XCVmac instructions. include/ChangeLog: * opcode/riscv-opc.h: Added corresponding MATCH and MASK macros for XCVmac. * opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros for uimm. (enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-06RISC-V: Make sure rv32q conflict won't affect the fp-q-insns-32 gas testcase.Nelson Chu1-1/+1
Same as commit 4352c0ac04a. gas/ * testsuite/gas/riscv/fp-q-insns-32.d: Set q to v2.2.
2023-11-03gas: correct ignoring of C-style number suffixesJan Beulich4-4/+116
First of all the respective original changes didn't deal with just 0 having such a suffix - this needs additional logic outside of integer_constant(). Further bogus suffixes having more than two L-s were accepted, while valid suffixes with U following the L(s) weren't. Finally respective tests were introduced for Sparc only. Reviewed-by: Neal Frager <neal.frager@amd.com>
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-85/+6
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and FS{H,W,D,Q} the sole difference between the handling is the insn mnemonic passed to the common handling functions. The intended mnemonic, however, can easily be retrieved. Furthermore leverags that Sx and FSx are then handled identically, too, and hence their cases can also be folded.
2023-11-03RISC-V: Lx/Sx macro insn testsJan Beulich2-0/+70
Make sure these (continue to) work as intended.
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