x86: Cpu64 handling improvements

First of all we want to also accumulate its reverse dependencies, such
that we can use them in cpu_flags_match(). This is in particular in
preparation of APX additions, such that e.g. BMI VEX-encoding templates
can become combined VEX/EVEX ones.

Once we have the reverse dependencies, we can further leverage them to
omit explicit "&x64" from any insn templates dealing with 64-bit-mode-
only ISA extensions. Besides helping readability for several insn
templates we already have, this will also help with what is going to be
added for APX (as all of the new templates would otherwise need to have
"&x64").

Note that rather than leaving a meaningless CPU_64_FLAGS (which is
unused anyway), its emitting is now also suppressed.

1 files changed, 13 insertions, 5 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c7b9a95..c6a1521 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -804,6 +804,9 @@ static char *cpu_sub_arch_name = NULL;
 /* CPU feature flags.  */
 i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
 
+/* ISA extensions available in 64-bit mode only.  */
+static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS;
+
 /* If we have selected a cpu we are generating instructions for.  */
 static int cpu_arch_tune_set = 0;
 
@@ -1874,7 +1877,12 @@ cpu_flags_match (const insn_template *t)
   else
     {
       /* This instruction is available only on some archs.  */
-      i386_cpu_flags cpu = cpu_arch_flags;
+      i386_cpu_flags active, cpu;
+
+      if (flag_code != CODE_64BIT)
+	active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags);
+      else
+	active = cpu_arch_flags;
 
       /* Dual VEX/EVEX templates may need stripping of one of the flags.  */
       if (t->opcode_modifier.vex && t->opcode_modifier.evex)
@@ -1895,14 +1903,14 @@ cpu_flags_match (const insn_template *t)
 		{
 		  x.bitfield.cpuavx512f = 0;
 		  x.bitfield.cpuavx512vl = 0;
-		  if (x.bitfield.cpufma && !cpu.bitfield.cpufma)
+		  if (x.bitfield.cpufma && !active.bitfield.cpufma)
 		    x.bitfield.cpuavx = 0;
 		}
 	    }
 	}
 
       /* AVX512VL is no standalone feature - match it and then strip it.  */
-      if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
+      if (x.bitfield.cpuavx512vl && !active.bitfield.cpuavx512vl)
 	return match;
       x.bitfield.cpuavx512vl = 0;
 
@@ -1912,7 +1920,7 @@ cpu_flags_match (const insn_template *t)
       if (x.bitfield.cpuavx && x.bitfield.cpuavx2)
 	x.bitfield.cpuavx2 = 0;
 
-      cpu = cpu_flags_and (x, cpu);
+      cpu = cpu_flags_and (x, active);
       if (!cpu_flags_all_zero (&cpu))
 	{
 	  if (t->cpu.bitfield.cpuavx && t->cpu.bitfield.cpuavx512f)
@@ -1921,7 +1929,7 @@ cpu_flags_match (const insn_template *t)
 		   ? cpu.bitfield.cpuavx512f
 		   : cpu.bitfield.cpuavx)
 		  && (!x.bitfield.cpufma || cpu.bitfield.cpufma
-		      || cpu_arch_flags.bitfield.cpuavx512f)
+		      || active.bitfield.cpuavx512f)
 		  && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
 		  && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
 		  && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))