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2024-02-29PR23877, bad value (n32r5900) for default CPUAlan Modra1-1/+3
Catching this at configure time would be nicer, but we'd need to exactly match mips_parse_cpu in configure.ac and keep it all in sync. PR 23877 * config/tc-mips.c (mips_after_parse_args): Don't assert that mips_parse_cpu returns non-NULL, call as_fatal with an informative message instead.
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their ↵Matthieu Longo1-2/+2
naming for coherency Hi, Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion. Regression tested on aarch64-none-elf, and no regression found. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu. From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001 From: Matthieu Longo <matthieu.longo@arm.com> Date: Fri, 23 Feb 2024 11:30:40 +0000 Subject: [PATCH] aarch64: rename internals related to PAuth feature to use pauth in their naming for coherency Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.
2024-02-24PR25333, GAS is slow processing -fdebug-types-sectionsAlan Modra9-126/+173
gas needs to build lists of sections for each group. This arranges to build the lists earlier, so they can be used when looking for sections that belong to a group. Using the section hash table to find sections by name, then by group isn't efficient when there are numerous groups with the same section names. Using a hash table to quickly find a group, then searching by section name on a list for the group results in a 100-fold speed improvement assembling the testcase in this PR. To reduce the number of times we traverse the section list, the patch also moves some processing done in elf_adjust_symtab for linked-to section, to elf_frob_file. This requires a testsuite change because processing will stop before elf_frob_file if there is a parse error in section21.s, ie. you'll only get the "junk at end of line" error, not the "undefined linked-to symbol" errors. PR 25333 * config/obj-elf.c (struct group_list, groups): Move earlier. (match_section): New function, extracted from.. (get_section_by_match): ..here. (free_section_idx): Move earlier. (group_section_find, group_section_insert): New functions. (change_section): Use the above. (elf_set_group_name): New function. (obj_elf_attach_to_group): Use elf_set_group_name. (set_additional_section_info): Handle linked_to_symbol_name and stabs code, extracted from.. (adjust_stab_sections): ..here,.. (build_additional_section_info): ..and here. (elf_adjust_symtab): Don't call build_additional_section_info. (elf_frob_file): Adjust. * config/obj-elf.h (elf_set_group_name): Declare. * config/tc-xtensa.c (cache_literal_section): Use elf_set_group_name. (xtensa_make_property_section): Likewise. * testsuite/gas/elf/attach-1.d: Stricter group section matching, and changed group section ordering. * testsuite/gas/elf/attach-2.d: Stricter group section matching. * testsuite/gas/elf/attach-2.s: Provide section bar type. * testsuite/gas/elf/elf.exp: Run attach-2. * testsuite/gas/elf/section21.l: Update. * testsuite/gas/elf/section21.s: Don't check for a parse error.
2024-02-24xtensa: move xtensa_make_property_section from bfd to gasAlan Modra1-0/+30
This function is only used by gas, so move it there. Necessary for gas to keep track of group sections as they are created. PR 25333 bfd/ * elf32-xtensa.c (xtensa_make_property_section): Delete. (xtensa_property_section_name): Make public. include/ * elf/xtensa.h (xtensa_make_property_section): Delete. (xtensa_property_section_name): Declare gas/ * config/tc-xtensa.c (xtensa_make_property_section): New, moved from elf32-xtensa.c.
2024-02-23x86: rename vec_encoding and vex_encoding_*Jan Beulich2-76/+76
Even with just VEX these weren't limited to vector insns. With APX the set of non-vector ones covered has greatly increased. Drop the vec_ prefix. Also drop the vex_ ones off of the enumerators, as they weren't appropriate anyway: Should have been vec_ then, too.
2024-02-23x86: document -moperand-check=Jan Beulich1-0/+15
PR gas/31388 Like other command line options this should be mentioned in documentation as well, not just in "as --help" output.
2024-02-23x86: also permit YMM/ZMM use in CFI directivesJan Beulich5-34/+422
Next to code using %ymm<N> or %zmm<N> it is more natural to have .cfi_* directives also reference those, not the corresponding %xmm<N>. Accept their names as kind of aliases, i.e. resolving to the same numbers. While extending the respective 64-bit testcase, also add %bnd<N> there (should have happened right with 633789901c83 ["x86-64: Dwarf2 register numbers for %bnd<N>"], sorry), requiring binutils/dwarf.c to be adjusted accordingly as well.
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich4-12/+342
While various other entries in version 003 of the spec aren't quite as explicit (due to simply leaving the respective field blank), all three have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0 by default (and respect -mevexwig=).
2024-02-23LoongArch: gas: Try to avoid R_LARCH_ALIGN associate with a symbolmengqinggang3-39/+72
The R_LARCH_ALIGN need to associated with a symbol if .align has the first and third expressions. If R_LARCH_ALIGN associate with a symbol, the addend can represent the first and third expression of .align. For '.align 3', the addend of R_LARCH_ALIGN only need to represent the alignment and R_LARCH_ALIGN not need to associate with a symbol. For '.align x, , y', R_LARCH_ALIGN need to associate with a symbol if 0 < y < 2^x - 4.
2024-02-22Leak in i386_elf_section_change_hookAlan Modra1-1/+1
notes_alloc is perfect for assorted memory you can't free easily and/or would rather leave freeing until just before exit. * config/tc-i386.c (i386_elf_section_change_hook): Use notes_alloc.
2024-02-21aarch64: testsuite: move sysreg tests into sysreg sub-directoryMatthieu Longo79-0/+23
This patch moves the existing sysreg tests for AArch64 into a subdirectory (sysreg). The number of test files related to system registers grew relatively big with time and makes the browsing of those files difficult. Moreover, the difference of naming for the failure, working, and feature-specific scenarios causes the tests not to appear next to one another in the exploration tree when it is ordered alphabetically.
2024-02-21RISC-V: Don't generate branch/jump relocation if symbol is local when no-relax.Nelson Chu1-0/+8
Refer to commit, dff565fcca8137954d6ad571ef39f6aec5c0429c. Theoretically, assembler don't need to generate the pc-relative relocation and the refered local .L symbol when relaxation is disabled. The above commit improved the pcrel_hi/pcrel_lo relocations, and this commit improves branch and jump relocations. Passed the gcc/binutils regressions of riscv-gnu-toolchain. gas/ * config/tc-riscv.c (md_apply_fix): Raise fixP->fx_done for all branch and jump relocations when -mno-relax.
2024-02-20kvx: gas: missing aliases for $r14r15 in assembler.Paul Iannetta1-60/+60
Most registers from a register-pair suffixed by .lo and .hi suffixes. This was not the case of $r14 and $r15 since they are defined by the ABI: $r14 is the frame pointer, and $r15 is used to return aggregates from functions. We do not add aliases for $r12 (the stack pointer) and $r13 (the tls register). opcodes/ChangeLog: * kvx-opc.c: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: enable magic immediates for integer multiply-accumulate and CMOVE*Paul Iannetta1-2582/+2582
Affected instructions: - alu unit: cmovewp cmovehq - mau unit: maddwdp madduwdp maddsuwdp mma msbfwdp msbfuwdp msbfsuwdp mms mulwdp muluwdp mulsuwdp mm opcodes/ChangeLog: * kvx-opc.c (struct kvxopc): Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: gas: rename: or -> ior, xor -> eorPaul Iannetta13-6084/+6756
TCA instructions start with an X, this introduces ambiguities when it comes to XOR (Is it the OR on the TCA or the XOR of the core?). For this reason, we rename OR to IOR and XOR to EOR. OR and XOR variants are still valid on KV3-1 and KV3-2. However, they have been completely removed from KV4-1. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: move the splat modifier to the immediatePaul Iannetta13-9994/+10655
The position of the splat modifier is now after the operand it modifies and not attached directly to the opcode. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: fix leakPaul Iannetta1-0/+1
gas/ChangeLog: * config/tc-kvx.c (md_apply_fix): Free memory at this end.
2024-02-20kvx: Improve lexing & parsingPaul Iannetta1-18/+35
Up until now, we used ENV.PROMOTE_IMMEDIATE to get the next candidates, however this candidate can be directly extracted from the array (in kvx-parse.h) registering all the immediates. During lexing, we ignored trailing characters after a number, this is not good enough since now number can be followed by a modifier. The function READ_TOKEN and GET_TOKEN_CLASS have been update to take this into account. gas/ChangeLog: * config/kvx-parse.c (promote_token): Do not rely on env.promote_immediate anymore. (get_token_class): Do not ignore trailing characters after a number. (read_token): Likewise. (print_token_list): THIS SHOULD NOT BE HERE.
2024-02-20kvx: gas: fix the detection of negative powers of 2Paul Iannetta3-1/+20
The detection of negative powers of 2 was wrong and could lead to well-formed bundles ending up taking more syllables than necessary. gas/ChangeLog: * config/kvx-parse.c (get_token_class): Use the signed value. * testsuite/gas/kvx/np2-detection.d: New test. * testsuite/gas/kvx/np2-detection.s: New test.
2024-02-20bpf: gas: add missing indcall-badoperand.* test filesJose E. Marchesi3-0/+14
This adds teh following files that were missing in the previous commit ecd16ae4e47118f66447641d93a6aa1334e550d4 testsuite/gas/bpf/indcall-badoperand.d testsuite/gas/bpf/indcall-badoperand.l testsuite/gas/bpf/indcall-badoperand.s
2024-02-19bpf: fix bpf expression parsing regression in GASWill Hawkins3-1/+13
As a result of a switch instead of an if, as would issue non-specific error messages when it encountered an operand it could not parse in bpf. This patch fixes that regression and adds a test to prevent it from reoccurring. Tested for bpf-unknown-none on x86_64-redhat-linux. gas/ChangeLog: * config/tc-bpf.c (parse_expression): Change switch to if so that error * condition is handled. * testsuite/gas/bpf/bpf.exp: Invoke new test. * testsuite/gas/bpf/indcall-badoperand.d: New test. * testsuite/gas/bpf/indcall-badoperand.l: New test. * testsuite/gas/bpf/indcall-badoperand.s: New test.
2024-02-19bpf: gas: avoid UB in pointer subtractionJose E. Marchesi2-12/+31
The PARSE_ERROR macro in md_assemble performs pointer subtraction. If parse_expression returns NULL then the later will be part of the subtraction and therefore UB will be incurred. This patch changes md_assemble to: 1. Accommodate all invocations to parse_expression to the fact it will return NULL when a parse error occurs. 2. Avoid UB in PARSE_ERROR. Tested in bpf-unknown-none target / x86_64-linux-gnu host. gas/ChangeLog: * config/tc-bpf.c (md_assemble): Fix to take into account that parse_expression can return NULL. (PARSE_ERROR): Avoid passing invalid length to parse_error.
2024-02-19arm: Add support for Armv9.5-AClaudio Bantaloukas5-0/+28
2024-02-19aarch64: Add support for the id_aa64isar3_el1 system registerYury Khrustalev5-0/+8
Hi, [PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register AArch64 defines a read-only system register called id_aa64isar3_el1. This patch also adds relevant tests. Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets and no regressions was found. Is this Ok for trunk? I do not have commit rights, if OK, can someone commit on my behalf? Thanks, Yury Khrustalev From e42c835e8f2ee81150f498675f2faf108bbe79f8 Mon Sep 17 00:00:00 2001 From: Yury Khrustalev <yury.khrustalev@arm.com> Date: Tue, 6 Feb 2024 11:05:39 +0000 Subject: [PATCH] [PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register AArch64 defines a read-only system register called id_aa64isar3_el1. This patch also adds relevant tests. Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets and no regressions was found.
2024-02-19aarch64: Add new relocations and limit COFF AArch64 relocation offsetsZac Walker1-1/+12
The patch adds support for the IMAGE_REL_ARM64_REL32 coff relocation type. This is needed for 32-bit relative address. It also adds a check for relocation offsets over 21 bits. Offsets inside coff files are stored in instruction code. In the case of ADRP the actual value is stored, not a downshifted page offset. This means values over 21 bits would otherwise be truncated. Finally it adds a mapping for BFD_RELOC_AARCH64_ADR_GOT_PAGE and BFD_RELOC_AARCH64_LD64_GOT_LO12_NC that were previously skipped. ChangeLog: * bfd/coff-aarch64.c (coff_aarch64_reloc_type_lookup): Add BFD_RELOC_AARCH64_ADR_GOT_PAGE, BFD_RELOC_AARCH64_LD64_GOT_LO12_NC and IMAGE_REL_ARM64_REL32 relocations. (coff_pe_aarch64_relocate_section): Likewise. * gas/write.c (adjust_reloc_syms): COFF AArch64 relocation offsets need to be limited to 21bits (defined): Likewise.
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich1-2/+2
Several years ago it was decided that SSE2AVX templates should not be sensitive to -mvexwig= (upon my suggestion to consistently make all sensitive as long as they don't require a specific setting of VEX.W). Adjust the four that still are, switching to use of Vex128 at the same time.
2024-02-16SCFI: correct test namesJan Beulich2-2/+2
Having multiple tests with the same name is confusing.
2024-02-15x86: Display -msse-check= default as noneH.J. Lu1-1/+1
Display -msse-check= default as none for "as --help" since its default is none, not warning. PR gas/31389 * config/tc-i386.c (md_show_usage): Change -msse-check= default to none.
2024-02-15objdump, as: add callx support for BPF CPU v1Will Hawkins3-4/+10
Albeit not being a currently valid BPF instruction, callx is generated by both clang and GCC when BPF programs are compiled unoptimized. Until now, GCC would emit it only whe using the experimental compiler-testing cpu version xbpf, whereas clang would emit it from v1. This patch makes GAS to accept callx also starting with cpu v1. opcodes/ChangeLog * bpf-opc.c: Move callx into the v1 BPF CPU variant. gas/ChangeLog * testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu version. * testsuite/gas/bpf/indcall-1.d: Likewise.
2024-02-15Make various gas symbol predicates and accessors take const argsAlan Modra2-57/+56
* symbols.c (S_IS_FUNCTION, S_IS_EXTERNAL, S_IS_WEAK), (S_IS_WEAKREFR, S_IS_WEAKREFD, S_IS_COMMON, S_IS_DEFINED), (S_FORCE_RELOC, S_IS_DEBUG, S_IS_LOCAL, S_IS_STABD), (symbol_previous, symbol_next, symbol_X_add_number), (symbol_get_frag, symbol_used_p, symbol_used_in_reloc_p), (symbol_mri_common_p, symbol_written_p, symbol_removed_p), (symbol_resolved_p, symbol_resolving_p, symbol_section_p), (symbol_equated_p, symbol_equated_reloc_p, symbol_constant_p), (symbol_shadow_p, symbol_same_p): Constify sym args. * symbols.h: Update prototypes.
2024-02-15PR30308, infinite recursion in i386_intel_simplifyAlan Modra3-10/+39
This patch exposes the symbol "resolving" flag for use in i386_intel_simplify, not only preventing infinite recursion on the testcase in the PR but also more complicated cases like: .intel_syntax b = a a = b mov eax, [a] PR 30308 * symbols.c (symbol_mark_resolving, symbol_clear_resolving), (symbol_resolving_p): New functions. * symbols.h: Declare them. * config/tc-i386-intel.c (i386_intel_simplify): Delete forward declaration. Formatting. (i386_intel_simplify_symbol): Use resolving flag to prevent infinite recursion.
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov2-0/+5
DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-02-09PowerPC: Add support for Power11 optionsPeter Bergner2-0/+5
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11. gas/ * config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries. (powerpc_init_dialect): Default to "power11".
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich3-0/+18
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't even present in the x86-64-apx-egpr-inval testcase, hence why I overlooked that these can actually be encoded, (again) using suitable AVX512 counterparts. While there also "modernize" the adjacent AVX/AVX2 entries.
2024-02-09x86: change type of Dwarf2 register numbers in register tableJan Beulich1-8/+6
Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are all out of reach for "signed char", at least when CHAR_BITS=8. Switch to "unsigned char", covering appropriately in places where the value returned for "none" actually matters (in tc_x86_parse_to_dw2regnum() this is actually achieved by altering how X_op is set).
2024-02-08gas: scfi: fix failing test on Solaris2Indu Bhagat1-2/+22
It has been observed that the run of scfi-unsupported-1 test with --x32 arg on a Solaris2 x86_64 system fails: Executing on host: sh -c {../as-new --x32 --scfi=experimental \ <...>/scfi-unsupported-1.s 2>&1} /dev/null dump.out (timeout = 300) Assembler messages: Fatal error: no compiled in support for 32bit x86_64 regexp_diff match failure regexp "^Fatal error: SCFI is not supported for this ABI$" line "Fatal error: no compiled in support for 32bit x86_64" FAIL: x86_64 scfi-unsupported-1 Fix the above by adding a check for --x32 support before running the test. While at it, also include a similar check for --32 support. gas/testsuite/ * gas/scfi/x86_64/scfi-x86-64.exp: Add gas_x32_check and gas_32_check. Conditionalize the execution of affected testcases.
2024-02-08x86-64: Add R_X86_64_CODE_6_GOTTPOFFH.J. Lu3-22/+94
For add %reg1, name@gottpoff(%rip), %reg2 and add name@gottpoff(%rip), %reg1, %reg2 add #define R_X86_64_CODE_6_GOTTPOFF 50 if the instruction starts at 6 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF. Linker can covert GOTTPOFF to add $name@tpoff, %reg1, %reg2 Rewrite fx_tcbit, fx_tcbit2 and fx_tcbit3 usage to generate R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX, R_X86_64_CODE_4_GOTPCRELX, R_X86_64_CODE_4_GOTTPOFF, R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_6_GOTTPOFF. NB: There is no need to check BFD_RELOC_X86_64_CODE_4_GOTTPOFF in md_assemble since there is only BFD_RELOC_X86_64_GOTTPOFF at this stage, which will be converted to BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_6_GOTTPOFF in i386_validate_fix. 5 relocations: #define R_X86_64_CODE_5_GOTPCRELX 46 #define R_X86_64_CODE_5_GOTTPOFF 47 #define R_X86_64_CODE_5_GOTPC32_TLSDESC 48 #define R_X86_64_CODE_6_GOTPCRELX 49 #define R_X86_64_CODE_6_GOTPC32_TLSDESC 51 are added for completeness and they are unused. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_6_GOTTPOFF. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Handle R_X86_64_CODE_6_GOTTPOFF. Issue an error for R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX and R_X86_64_CODE_6_GOTPC32_TLSDESC. (elf_x86_64_relocate_section): Handle R_X86_64_CODE_6_GOTTPOFF. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_5_GOTPCRELX, BFD_RELOC_X86_64_CODE_5_GOTTPOFF, BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC, BFD_RELOC_X86_64_CODE_6_GOTPCRELX, BFD_RELOC_X86_64_CODE_6_GOTTPOFF and BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. elfcpp/ * x86_64.h (R_X86_64_CODE_5_GOTPCRELX): New. (R_X86_64_CODE_5_GOTTPOFF): Likewise. (R_X86_64_CODE_5_GOTPC32_TLSDESC): Likewise. (R_X86_64_CODE_6_GOTPCRELX): Likewise. (R_X86_64_CODE_6_GOTTPOFF): Likewise. (R_X86_64_CODE_6_GOTPC32_TLSDESC): Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (md_assemble): Don't check BFD_RELOC_X86_64_CODE_4_GOTTPOFF. Allow "add %reg1, foo@gottpoff(%rip), %reg2". (output_disp): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. Rewrite setting fx_tcbitX bits for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (md_apply_fix): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. (i386_validate_fix): Rewrite fx_tcbitX bit checking for BFD_RELOC_X86_64_GOTTPOFF, BFD_RELOC_X86_64_GOTPC32_TLSDESC and BFD_RELOC_32_PCREL. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_6_GOTTPOFF. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". gold/ * x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle R_X86_64_CODE_6_GOTTPOFF. (Target_x86_64::Scan::get_reference_flags): Likewise. (Target_x86_64::Scan::local): Likewise. (Target_x86_64::Scan::global): Likewise. (Target_x86_64::Relocate::relocate): Likewise. (Target_x86_64::Relocate::relocate_tls): Likewise. (Target_x86_64::Relocate::tls_ie_to_le): Handle. R_X86_64_CODE_6_GOTTPOFF. * testsuite/x86_64_ie_to_le.s: Add tests for "add %reg1, foo@gottpoff(%rip), %reg2" and "add foo@gottpoff(%rip), %reg, %reg2". * testsuite/x86_64_ie_to_le.sh: Updated. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_5_GOTPCRELX, R_X86_64_CODE_5_GOTTPOFF, R_X86_64_CODE_5_GOTPC32_TLSDESC, R_X86_64_CODE_6_GOTPCRELX, R_X86_64_CODE_6_GOTTPOFF and R_X86_64_CODE_6_GOTPC32_TLSDESC. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF tests. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-02-06gas: x86: ginsn: handle sub-QWORD ALU with imm and MOV ops correctlyIndu Bhagat5-96/+149
PR gas/31326 SCFI must handle non QWORD ALU with imm and MOV ops correctly As per the x86 ISA manual: - 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose register. - 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the destination general-purpose register are not modified by the operation. Unlike previously thought, sub-QWORD ALU/imm and MOV ops do have implications on SCFI. SCFI/ginsn machinery does not track operation size in the ginsn representation. But given that these sub-QWORD ops update only a portion of a 64-bit destination register, for SCFI purposes, this needs to be deemed as an untraceable update (when the destination is REG_SP / REG_FP). Although in most cases, sub-QWORD ops are not expected for stack management, but the SCFI machinery must behave correctly, when such ops are indeed present. As mentioned earlier, ginsn representation does not carry operation size information. To resolve the issue raised in PR gas/31326, an option is to force the generation of GINSN_TYPE_OTHER for all cases when there is a 8/16/32 bit op. But this may dilute the utility of ginsn for other use-cases, when they pop up in future. The current approach is less disruptive than above in that it generates GINSN_TYPE_OTHER for all cases only when: - there is a 8/16/32 bit op, and - the 64-bit op is otherwise traceable. In other words this means: - For add/sub ops where dest is reg and src is reg/mem: these always make dest reg untraceable; So, the current handling is unchanged. We simply skip detecting 8/16/32-bit ops. - An x86 pop instruction is translated to a load ginsn followed by a stack increment add op. A load op always makes dest reg untraceable. Hence, if the pop instruction is sub-QWORD, we continue to (skip detecting 8/16/32-bit op, and) generate the load instruction as usual. This means that if input asm does have save and restore of unequal sized registers, gas/SCFI will not detect nor warn. - For ALU imm or MOV reg,reg, however, a GINSN_TYPE_OTHER is generated when a 8/16/32-bit op is seen. gas/ PR gas/31326 * config/tc-i386.c (x86_ginsn_addsub_reg_mem): Add a code comment. (x86_ginsn_addsub_mem_reg): Likewise. (x86_ginsn_alu_imm): Detect sub-QWORD opsize and exit early. (x86_ginsn_move): Likewise. (x86_ginsn_new): Add comment for 8-bit add/sub opcodes (in opcode_space SPACE_BASE) about skipped handling. gas/testsuite/: PR gas/31326 * gas/scfi/x86_64/ginsn-add-1.l: Update. * gas/scfi/x86_64/ginsn-add-1.s: Add some sub-QWORD add ops. * gas/scfi/x86_64/ginsn-dw2-regnum-1.l: Update. * gas/scfi/x86_64/ginsn-dw2-regnum-1.s: Use mov ops instead of add to invoke and test the ginsn_dw2_regnum code path.
2024-02-06x86: Warn .insn instruction with length > 15 bytesH.J. Lu3-2/+19
Change .insn instruction with length > 15 bytes from error to warning. PR gas/31323 * config/tc-i386.c (output_insn): Issue a warning when .insn instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized64.s: Add a test for .insn * testsuite/gas/i386/oversized64.l: Updated.
2024-02-04LoongArch: gas: Fix the types of symbols referred with %le_*_r in the symtabXi Ruoyao3-0/+12
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a TLS symbol and we should set its type to TLS in the symtab. Otherwise when building Perl with gcc-14 -flto, we get: /usr/bin/ld: PL_current_context: TLS definition in ./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference in ./miniperl.ltrans1.ltrans.o A minimal reproducer: $ cat t1.s .section .tbss .globl x x: .word 0 $ cat t2.s f: lu12i.w $a0, %le_hi20_r(x) add.d $a0, $a0, $tp, %le_add_r(x) li.w $a1, 1 st.w $a1, $a0, %le_lo12_r(x) $ gas/as-new t1.s -o t1.o $ gas/as-new t2.s -o t2.o $ ld/ld-new t1.o t2.o ld/ld-new: x: TLS definition in t1.o section .tbss mismatches non-TLS reference in t2.o Unfortunately this was undetected before Binutils-2.42 release because GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a TLS LE definition and its reference in two different translation units. So this fix should be backported to Binutils-2.42 branch too. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-02-02x86: Disallow instructions with length > 15 bytesH.J. Lu6-32/+40
It is a hard error when an instruction length exceeds the limit of 15 bytes: [hjl@gnu-cfl-3 tmp]$ cat x.s .text xacquire lock addq $0x11223344, %fs:(,%eax) [hjl@gnu-cfl-3 tmp]$ gcc -c x.s x.s: Assembler messages: x.s:2: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw x.o x.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 67 f2 f0 48 81 04 05 00 00 00 00 44 33 22 xacquire lock (bad) f: 11 .byte 0x11 [hjl@gnu-cfl-3 tmp]$ and [hjl@gnu-cfl-3 tmp]$ cat z.s addq $0xe0, %fs:0, %rdx [hjl@gnu-cfl-3 tmp]$ as -o z.o z.s z.s: Assembler messages: z.s:1: Warning: instruction length of 16 bytes exceeds the limit of 15 [hjl@gnu-cfl-3 tmp]$ objdump -dw z.o z.o: file format elf64-x86-64 Disassembly of section .text: 0000000000000000 <.text>: 0: 64 62 f4 ec 18 81 04 25 00 00 00 00 e0 00 00 (bad) ... [hjl@gnu-cfl-3 pr31323]$ Instructions with length > 15 bytes are always invalid. It is quite easy to generate invalid instructions with AVX now. We should issue an error when instruction length exceeds the limit of 15 bytes. PR gas/31323 * config/tc-i386.c (output_insn): Issue an error when instruction length exceeds the limit of 15 bytes. * testsuite/gas/i386/oversized16.l: Updated. * testsuite/gas/i386/oversized64.l: Likewise. * testsuite/gas/i386/x86-64-apx-inval.l: New file. * testsuite/gas/i386/x86-64-apx-inval.s: Likewise.
2024-02-02x86: move Q-suffix-to-REX.W translation logicJan Beulich1-17/+20
By pulling it ahead of the SHORT_MNEM_SUFFIX case label we can drop a part of another conditional there. While moving, also drop a pointless check: With QWORD_MNEM_SUFFIX, register operands of XCHG necessarily have both been 64-bit ones.
2024-02-02x86: actually implement .nooptJan Beulich7-19/+51
For quite some time we've had support for -O command line options. With that ignoring at least .noopt isn't really a good idea. Re-purpose the optimize-3 test for testing this directive's effect as well. As to the doc addition - this uses the same text as is there for the {nooptimize} pseudo-prefix, despite me not being convinced of the "size" part being fully accurate there (and hence also here).
2024-02-01gas: x86: ginsn: adjust ginsns for certain lea opsIndu Bhagat4-65/+134
A review comment on the SCFI V4 series was to handle ginsn creation for certain lea opcodes more precisely. Specifically, we should preferably handle the following two cases of lea opcodes similarly: - #1 lea with "index register and scale factor of 1, but no base register", - #2 lea with "no index register, but base register present". Currently, a ginsn of type GINSN_TYPE_OTHER is generated for the case of #1 above. For #2, however, the lea insn is translated to either a GINSN_TYPE_ADD or GINSN_TYPE_MOV depending on whether the immediate for displacement is non-zero or not respectively. Change the handling in x86_ginsn_lea so that both of the above lea manifestations are handled similarly. While at it, remove the code paths creating GINSN_TYPE_OTHER altogether from the function. It makes sense to piggy back on the x86_ginsn_unhandled code path to create GINSN_TYPE_OTHER if the destination register is interesting. This was also suggested in one of the previous review rounds; the other functions already follow that model, so this keeps functions symmetrical looking. gas/ * gas/config/tc-i386.c (x86_ginsn_lea): Handle select lea ops with no base register similar to the case of no index register. Remove creation of GINSN_TYPE_OTHER from the function. gas/testsuite/ * gas/scfi/x86_64/ginsn-lea-1.l: New test. * gas/scfi/x86_64/ginsn-lea-1.s: Likewise. * gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
2024-01-31Mention support for AMD/znver5 in GASNick Clifton1-0/+2
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi8-105/+95
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.
2024-01-26gas: scfi: untraceable control flow should be a hard errorIndu Bhagat3-11/+13
PR gas/31284 Currently, if an indirect jump is seen, GCFG (a CFG of ginsns) cannot be created, and the SCFI machinery bails out with a warning: "Warning: Untraceable control flow for func 'foo'; Skipping SCFI" It is, however, better suited if this is a hard error. Change it to a hard error. Also change the message to skip mentioning "SCFI", because the error itself may also useful when ginsns are used for other passes (distinct from SCFI) involving GCFG, like a pass to detect if there is unreachable code. Hence, simply say: "Error: untraceable control flow for func 'foo'" gas/ PR gas/31284 * ginsn.c (ginsn_data_end): Use as_bad instead of as_warn. gas/testsuite/ PR gas/31284 * gas/scfi/x86_64/ginsn-cofi-1.l: Adjust to the expected output in case of errors. * gas/scfi/x86_64/scfi-unsupported-cfg-1.l: Error not Warning.
2024-01-26x86: testsuite: scfi: adjust COFI testcaseIndu Bhagat5-14/+37
The testcase for change of flow instructions in its current shape is not doing much: it checks that SCFI issues an appropriate warning. The same warning is covered by another testcase (scfi-unsupported-cfg-1); It is better to test the ginsn translation instead, for these 'change of flow instructions'. gas/testsuite/ * gas/scfi/x86_64/scfi-cofi-1.s: Moved to... * gas/scfi/x86_64/ginsn-cofi-1.s: ...here. * gas/scfi/x86_64/scfi-x86-64.exp: Adjust tests. * gas/scfi/x86_64/scfi-cofi-1.d: Removed. * gas/scfi/x86_64/scfi-cofi-1.l: Removed. * gas/scfi/x86_64/ginsn-cofi-1.l: New test.
2024-01-26x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix"Jan Beulich6-11/+27
Adjustments made for the directive (by set_intel_syntax()) need also making for the command line option. Break out respective code into a new helper function, to also be invoked during command line processing. Further also set register_prefix when processing -mnaked-reg.
2024-01-26x86/APX: optimize MOVBEJan Beulich3-4/+17
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
generated by cgit v1.1 at 2024-11-21 22:51:01 +0000