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2025-01-06gas: special-case division / modulo by ±1Jan Beulich7-0/+121
2025-01-03macro nesting testcasesAlan Modra3-22/+25
2025-01-03nesting[123].d: Replace Sone with Some in commentH.J. Lu3-3/+3
2025-01-02gas: Revert PR 32391 related commits to fix 3 regressionsH.J. Lu9-133/+61
2025-01-02Support Intel AMX-TF32Haochen Jiang8-0/+98
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang12-0/+219
2025-01-01Update year range in copyright notice of binutils filesAlan Modra197-197/+197
2024-12-24PR 32391 testcaseAlan Modra1-60/+60
2024-12-23Support Intel AVX10.2 minmax, vector copy and compare instructionsHaochen Jiang14-0/+940
2024-12-20arm: fix incorrect assembly of stm{,ia} as push [PR32363]Richard Earnshaw2-2/+4
2024-12-19Fix the handling or arguments and macro pseudo-variables inside nested assemb...Nick Clifton3-0/+133
2024-12-19Adjust expected loongarch32 test resultsAlan Modra2-17/+17
2024-12-18Support Intel SM4 AVX10.2 extensionHaochen Jiang18-0/+386
2024-12-17aarch64: testsuite: remove macro expansion messages from expected error outputMatthieu Longo10-502/+6
2024-12-13Give unique names to s390 assembler opcode tests.Nick Clifton17-17/+17
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai2-0/+686
2024-12-05Support Intel AVX10.2 satcvt instructionsHu, Lin114-0/+2416
2024-12-05x86: Eliminate unnecessary {evex} prefixesH.J. Lu6-0/+86
2024-12-03gas: Re-enable .org test 1 on all targets except kvxJens Remus1-1/+1
2024-12-03s390: Enable .bss/.struct data allocation directives testsJens Remus2-2/+2
2024-12-03PowerPC: Add support for RFC02680 - PQC Acceleration InstructionsSurya Kumari Jangala2-0/+20
2024-12-03Support Intel AVX10.2 BF16 instructionsKong Lingling14-0/+2323
2024-12-02x86: default to not accepting MPX insnsJan Beulich28-30/+36
2024-12-02x86: always set ISA_1_BASELINE property for 64-bit objectsJan Beulich1-2/+2
2024-12-02x86/COFF: support section-index relocations in insn operandsJan Beulich5-1/+55
2024-12-02x86/COFF: support RVA (image-relative) relocations in insn operandsJan Beulich6-1/+147
2024-12-02RISC-V: Add support for ssdbltrp and smdbltrp extension.Dongyan Chen3-0/+7
2024-11-29s390: Treat addressing operand sequence as one in disassemblerJens Remus1-1/+1
2024-11-29s390: Fix disassembly of optional addressing operandsJens Remus2-8/+84
2024-11-29x86/Solaris: support Sun form of CMOVccJan Beulich3-0/+53
2024-11-29x86: purge most *avx512*ig*-intel testsJan Beulich24-6996/+4
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore222-7133/+0
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclip...Nelson Chu6-0/+56
2024-11-20PowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner2-0/+2
2024-11-20arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira2-0/+214
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei13-0/+64
2024-11-19Support x86 Intel MSR_IMMHu, Lin19-0/+126
2024-11-18x86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich15-244/+287
2024-11-18x86: generalize "implicit quad group" handlingJan Beulich5-18/+39
2024-11-18s390: Add arch15 Concurrent-Functions Facility insnsJens Remus2-0/+8
2024-11-13gas: add .cv_ucomp and .cv_scomp pseudo-directivesMark Harmstone3-0/+124
2024-11-08aarch64: testsuite: remove hard-coded instruction addressesMatthieu Longo1-26/+26
2024-11-08arm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira5-76/+36
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira4-17/+19
2024-11-07arm: Skip two failing tests for wince & pe targetsAndre Simoes Dias Vieira2-0/+2
2024-11-06PowerPC: Merge rfc2655 and rfc2656 test cases into one future test casePeter Bergner5-32/+18
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich3-3/+26
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich2-0/+10
2024-10-28RISC-V: Fix typo in gas/testsuite/gas/riscv/mapping.sJim Lin3-6/+6
2024-10-22LoongArch: Force relocation for every reference to the global offset tableLulu Cai2-0/+48
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