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AgeCommit message (Expand)AuthorFilesLines
2022-11-30x86: extend FPU test coverage for AT&T / Intel mnemonic differencesJan Beulich5-0/+44
2022-11-28RISC-V: Better support for long instructions (tests)Tsukasa OI4-1/+48
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner11-0/+860
2022-11-24x86: widen applicability and use of CheckRegSizeJan Beulich2-0/+60
2022-11-24x86: correct handling of LAR and LSLJan Beulich5-19/+63
2022-11-23gas: Add --gcodeview optionMark Harmstone4-0/+342
2022-11-21Fix ARM and AArch64 assembler tests to work in a multi-arch environment.Nick Clifton4-4/+4
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI8-97/+154
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner2-0/+14
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2-0/+14
2022-11-15gas: testsuite: add new tests for SFrame unwind infoIndu Bhagat29-0/+533
2022-11-16Re: [gas] arm: Add support for new unwinder directive ".pacspval".Alan Modra1-4/+5
2022-11-15Add AMD znver4 processor supportTejas Joshi9-0/+127
2022-11-15aarch64, testsuite: Fixed recently added cssc.dAndre Vieira1-7/+0
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2-0/+334
2022-11-14[gas] arm: Add support for new unwinder directive ".pacspval".Srinath Parvathaneni2-0/+53
2022-11-14arm: Add support for Cortex-X1C CPU.Srinath Parvathaneni1-0/+6
2022-11-12PowerPC64 paddi -MrawAlan Modra2-0/+3
2022-11-10i386: Check invalid (%dx) usageH.J. Lu4-0/+28
2022-11-09x86/Intel: don't accept malformed EXTRQ / INSERTQJan Beulich3-15/+15
2022-11-09RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner4-48/+50
2022-11-08Support Intel RAO-INTKong Lingling7-0/+110
2022-11-07RISC-V: Remove RV32EF conflictTsukasa OI2-5/+0
2022-11-04x86: adjust recently introduced testcasesJan Beulich8-0/+8
2022-11-04Support Intel AVX-NE-CONVERTkonglin17-0/+1018
2022-11-02RISC-V: Fixed the missing $x+arch when adding odd paddings for alignment.Nelson Chu3-9/+31
2022-11-02Support Intel MSRLISTHu, Lin16-0/+42
2022-11-02Support Intel WRMSRNSHu, Lin16-0/+39
2022-11-02Support Intel CMPccXADDHaochen Jiang6-0/+812
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili7-0/+542
2022-11-02Support Intel AVX-IFMAHongyu Wang12-12/+245
2022-11-01opcodes/arm: use '@' consistently for the comment characterAndrew Burgess121-2291/+2291
2022-10-31x86: Silence GCC 12 warning on tc-i386.cH.J. Lu1-4/+4
2022-10-31Support Intel PREFETCHICui, Lili10-0/+91
2022-10-31RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato1-4/+4
2022-10-29RISC-V: Always generate mapping symbols at the start of the sections.Nelson Chu2-28/+0
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu22-291/+273
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner3-0/+80
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner5-64/+258
2022-10-27re: Support Intel AMX-FP16Alan Modra2-0/+2
2022-10-24x86: consolidate VPCLMUL testsJan Beulich15-268/+156
2022-10-24x86: consolidate VAES testsJan Beulich15-352/+211
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich31-361/+361
2022-10-21Support Intel AMX-FP16Cui,Lili6-0/+92
2022-10-20x86: Check VEX/EVEX encoding before checking vector operandsH.J. Lu4-0/+4
2022-10-20x86: re-work AVX-VNNI supportJan Beulich6-6/+36
2022-10-19aarch64-pe support for LD, GAS and BFDJedidiah Thompson3-0/+31
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao5-205/+566
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra4-0/+15
2022-10-14PowerPC SPE disassembly and testsAlan Modra4-14/+11
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