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AgeCommit message (Expand)AuthorFilesLines
2024-06-11MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos2-1/+3
2024-06-11MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos4-0/+30
2024-06-10aarch64: warn on unpredictable results for new rcpc3 instructionsMatthieu Longo5-25/+267
2024-06-10Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki3-27/+0
2024-06-10Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki2-3/+1
2024-06-10MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos2-1/+3
2024-06-10MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos3-0/+27
2024-06-10x86: disassembler macro for condition codeJan Beulich6-276/+276
2024-06-10x86/APX: support extended SETcc formJan Beulich3-0/+9
2024-06-10gas: extend \+ support to .reptJan Beulich3-0/+26
2024-06-06arm: fix testsuite fallout on arm-elf and arm-nto from FPA removalRichard Earnshaw5-3/+7
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng3-0/+20
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng3-0/+20
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng3-0/+18
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw2-6/+6
2024-06-05arm: redirect fp constant data directives through a wrapperRichard Earnshaw11-5/+35
2024-06-05arm: remove FPA related testsRichard Earnshaw27-1858/+119
2024-06-05RISC-V: Tidy vendor core-v extension gas testcasesNelson Chu146-1629/+1393
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett67-0/+725
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett17-0/+86
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett9-0/+186
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang3-3/+38
2024-06-04arm: testsuite: fix msdos line endings in testsRichard Earnshaw2-18/+18
2024-05-31aarch64, testsuite: avoid regexes in opcode fieldClaudio Bantaloukas2-493/+493
2024-05-31gas, aarch64: Fixes in texi and tests following faminmax and lut changessaurabh.jha@arm.com3-154/+154
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich31-157/+101
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich3-0/+74
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com8-1/+461
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com7-0/+428
2024-05-24Re: LoongArch: gas: Adjust DWARF CIE alignment factorsAlan Modra1-22/+22
2024-05-24gas: extend \+ support to .irp / .irpcJan Beulich4-14/+10
2024-05-24gas: adjust handling of quotes for .irpcJan Beulich3-0/+26
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich2-0/+9
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-2/+2
2024-05-22Support APX zero-upperCui, Lili6-0/+285
2024-05-22Add check for 8-bit old registers in EVEX formatCui, Lili2-0/+5
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas4-0/+23
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich1-1/+1
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich3-13/+13
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento6-2/+623
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento7-0/+313
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento5-0/+581
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo3-0/+27
2024-05-16Move assembler "IRP \+" test into a separate file. Add XFAILs for targets th...Nick Clifton6-9/+19
2024-05-16Fix FAIL: macros altmacroAlan Modra1-5/+5
2024-05-15gas: Fix \+ expansion for .irp and .irpcFangrui Song2-0/+9
2024-05-15aarch64: testsuite: share test utils macros and use themMatthieu Longo23-519/+576
2024-05-15aarch64: testsuite: reorder write and read to match macro orderMatthieu Longo11-292/+286
2024-05-15aarch64: testsuite: use same regs for read and write testsMatthieu Longo8-377/+377
2024-05-15aarch64: testsuite: replace instruction addresses by regexMatthieu Longo1-28/+28
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