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2022-08-05gas: fix a testcase broken by new ZSTD supportTsukasa OI2-3/+2
The commit 1369522f36eece1b37139a81f7f2139ba3915172 ("Recognize the new ELF compression type for ZSTD.") added the new ELF compression type but it accidentally broke a GAS testcase. Since testing for the section type "2048" (SHF_COMPRESSED) is not going to be portable in the long term, it now tests SHF_LINK_ORDER ("128") instead. Using SHF_LINK_ORDER (with possibly sh_link == 0) is an idea by Jan Beulich. gas/ChangeLog: * testsuite/gas/elf/section10.s: Use SHF_LINK_ORDER to test mixed numeric and alpha values. * testsuite/gas/elf/section10.d: Reflect the change above.
2022-08-02arm: Add cfi expression support for ra_auth_codeVictor Do Nascimento2-0/+53
This patch extends assembler support for the use of register names to allow for pseudo-registers, e.g. ra_auth_code register. This is done particularly with CFI directives in mind, allowing for expressions of the type: .cfi_register ra_auth_code, 12 gas/Changelog: * config/tc-arm.c (tc_arm_regname_to_dw2regnum): Add REG_TYPE_PSEUDO handling. * testsuite/gas/arm/cfi-pacbti-m-readelf.d: New. * testsuite/gas/arm/cfi-pacbti-m.s: New.
2022-08-02arm: Use DWARF numbering convention for pseudo-register representationVictor Do Nascimento2-3/+3
This patch modifies the internal `struct reg_entry' numbering of DWARF pseudo-registers to match values assigned in DWARF standards (see "4.1 DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and amends the unwinder .save directive-processing code to correctly handle mixed register-type save directives. The mechanism for splitting the register list is also re-written to comply with register ordering on push statements, being that registers are stored on the stack in numerical order, with the lowest numbered register at the lowest address [2]. Consequently, the parsing of the hypothetical directive .save{r4-r7, r10, ra_auth_core, lr} has been changed such as rather than producing .save{r4-r7, r10} .save{ra_auth_code} .save{lr} as was the case with previous implementation, now produces: .save{lr} .save{ra_auth_code} .save{r4-r7, r10} [1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst> [2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push> gas/Changelog: * config/tc-arm.c (REG_RA_AUTH_CODE): New. (parse_dot_save): Likewise. (parse_reg_list): Remove obsolete code. (reg_names): Set ra_auth_code to 143. (s_arm_unwind_save): Handle core and pseudo-register lists via parse_dot_save. (s_arm_unwind_save_mixed): Deleted. (s_arm_unwind_save_pseudo): Handle one register at a time. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
2022-08-01x86: SKINIT with operand needs IgnoreSizeJan Beulich3-0/+45
Without it in 16-bit mode a pointless operand size prefix would be emitted.
2022-08-01opcodes: LoongArch: add "ret" instruction to reduce typingWANG Xuerui2-0/+2
This syntactic sugar is present in both classical and emerging architectures, like Alpha, SPARC and RISC-V, and assembler macros doing the same thing can already be found in the wild e.g. [1], proving the feature's popularity. It's better to provide support directly in the assembler so downstream users wouldn't have to re-invent this over and over again. [1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
2022-08-01opcodes: LoongArch: make all non-native jumps desugar to canonical ↵WANG Xuerui1-3/+3
b{lt/ge}[u] forms Also re-order the jump/branch opcodes while at it, so that insns are sorted in ascending order according to opcodes, and the label form preceding the real definition.
2022-08-01Get rid of fprintf_vma and sprintf_vmaAlan Modra4-230/+230
These two macros print either a 16 digit hex number or an 8 digit hex number. Unfortunately they depend on both target and host, which means that the output for 32-bit targets may be either 8 or 16 hex digits. Replace them in most cases with code that prints a bfd_vma using PRIx64. In some cases, deliberately lose the leading zeros. This change some output, notably in base/offset fields of m68k disassembly which I think looks better that way, and in error messages. I've kept leading zeros in symbol dumps (objdump -t) and in PE header dumps. bfd/ * bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete. * bfd-in2.h: Regenerate. * bfd.c (bfd_sprintf_vma): Don't use sprintf_vma. (bfd_fprintf_vma): Don't use fprintf_vma. * coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (xcoff_ppc_relocate_section): Likewise. * cofflink.c (_bfd_coff_write_global_sym): Likewise. * mmo.c (mmo_write_symbols_and_terminator): Likewise. * srec.c (srec_write_symbols): Likewise. * elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma. * pei-x86_64.c (pex64_dump_xdata): Likewise. (pex64_bfd_print_pdata_section): Likewise. * som.c (som_print_symbol): Likewise. * ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma. opcodes/ * dis-buf.c (perror_memory, generic_print_address): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. * i386-dis.c (print_operand_value, print_displacement): Likewise. * m68k-dis.c (print_base, print_indexed): Likewise. * ns32k-dis.c (print_insn_arg): Likewise. * ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete. (opcode_fprintf_vma): Delete. (print_main_table): Use PRIx64 to print opcode. binutils/ * od-macho.c: Replace all uses of printf_vma with bfd_printf_vma. * objcopy.c (copy_object): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (copy_main): Likewise. * readelf.c (CHECK_ENTSIZE_VALUES): Likewise. (dynamic_section_mips_val): Likewise. (print_vma): Don't use printf_vma. Instead use PRIx64 to print bfd_vma values. (dump_ia64_vms_dynamic_fixups): Likewise. (process_version_sections): Likewise. * rddbg.c (stab_context): Likewise. gas/ * config/tc-i386.c (offset_in_range): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. (md_assemble): Likewise. * config/tc-mips.c (load_register, macro): Likewise. * messages.c (as_internal_value_out_of_range): Likewise. * read.c (emit_expr_with_reloc): Likewise. * config/tc-ia64.c (note_register_values): Don't use fprintf_vma. Instead use PRIx64 to print bfd_vma values. (print_dependency): Likewise. * listing.c (list_symbol_table): Use bfd_sprintf_vma. * symbols.c (print_symbol_value_1): Use %p to print pointers. (print_binary): Likewise. (print_expr_1): Use PRIx64 to print bfd_vma values. * write.c (print_fixup): Use %p to print pointers. Don't use fprintf_vma. * testsuite/gas/all/overflow.l: Update expected output. * testsuite/gas/m68k/mcf-mov3q.d: Likewise. * testsuite/gas/m68k/operands.d: Likewise. * testsuite/gas/s12z/truncated.d: Likewise. ld/ * deffilep.y (def_file_print): Don't use fprintf_vma. Instead use PRIx64 to print bfd_vma values. * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use sprintf_vma. Instead use PRIx64 to print bfd_vma values. * emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise. * ldlang.c (lang_map): Use %V to print region origin. (lang_one_common): Don't use sprintf_vma. * ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma. * pe-dll.c (pe_dll_generate_def_file): Likewise. gdb/ * remote.c (remote_target::trace_set_readonly_regions): Replace uses of sprintf_vma with bfd_sprintf_vma.
2022-07-29Arm64: re-work PR gas/27217 fixJan Beulich1-3/+3
The original approach has resulted in anomalies when . is involved in an operand of one of the affected insns. We cannot leave . unresolved, or else it'll be resolved at the end of assembly, then pointing to the address of a section rather than at the insn of interest. Undo part of the original change and instead check whether a relocation cannot be omitted in md_apply_fix(). By resolving the expressions again, equates (see the adjustment of the respective testcase) will now be evaluated, and hence relocations against absolute addresses be emitted. This ought to be okay as long as the equates aren't global (and hence can't be overridden). If a need for such arises, quite likely the only way to address this would be to invent yet another expression evaluation mode, leaving everything _except_ . un-evaluated. There's a further anomaly in how transitive equates are handled. In .set x, 0x12345678 .eqv bar, x foo: adrp x0, x add x0, x0, :lo12:x adrp x0, bar add x0, x0, :lo12:bar the first two relocations are now against *ABS*:0x12345678 (as said above), whereas the latter two relocations would be against x. (Before the change here, the first two relocations are against x and the latter two against bar.) But this is an issue seen elsewhere as well, and would likely require adjustments in the target-independent parts of the assembler instead of trying to hack around this for every target.
2022-07-29RISC-V: Add `OP_V' to .insn named opcodesTsukasa OI3-9/+13
This commit adds `OP_V' (OP-V: vector instruction opcode for now ratified `V' extension) to .insn opcode name list. Although vector instruction encoding is not implemented in `.insn' directive, it will help future implementation of custom vector `.insn'. gas/ChangeLog: * config/tc-riscv.c (opcode_name_list): Add `OP_V'. * testsuite/gas/riscv/insn.s: Add testcase. * testsuite/gas/riscv/insn.d: Likewise. * testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update.
2022-07-25LoongArch: Add testcases for new relocate types.liuzhensong13-836/+664
gas/testsuite/gas/all/ gas.exp gas/testsuite/gas/loongarch/ jmp_op.d jmp_op.s macro_op.d macro_op.s macro_op_32.d macro_op_32.s macro_op_large_abs.d macro_op_large_abs.s macro_op_large_pc.d macro_op_large_pc.s reloc.d reloc.s ld/testsuite/ld-elf/ pr26936.d shared.exp ld/testsuite/ld-loongarch-elf/ attr-ifunc-4.c attr-ifunc-4.out disas-jirl.d ifunc.exp jmp_op.d jmp_op.s libnopic-global.s macro_op.d macro_op.s macro_op_32.d macro_op_32.s nopic-global-so.rd nopic-global-so.sd nopic-global.out nopic-global.s nopic-global.sd nopic-global.xd nopic-local.out nopic-local.rd nopic-local.s nopic-local.sd nopic-local.xd nopic-weak-global-so.rd nopic-weak-global-so.sd nopic-weak-global.out nopic-weak-global.s nopic-weak-global.sd nopic-weak-global.xd nopic-weak-local.out nopic-weak-local.rd nopic-weak-local.s nopic-weak-local.sd nopic-weak-local.xd pic.exp pic.ld
2022-07-21x86/Intel: correct AVX512F scatter insn element sizesJan Beulich2-32/+32
I clearly screwed up in 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") giving all AVX512F scatter insns Dword element size. Update testcases (also their gather parts), utilizing that there previously were two identical lines each (for no apparent reason).
2022-07-21PR29390, DW_CFA_AARCH64_negate_ra_state vs. DW_CFA_GNU_window_saveAlan Modra2-3/+3
PR 29390 binutils/ * dwarf.c (is_aarch64, DW_CFA_GNU_window_save_name): New. (display_debug_frames): Use them. (init_dwarf_regnames_aarch64): Set is_aarch64. (init_dwarf_regnames_by_elf_machine_code): Clear is_aarch64. (init_dwarf_regnames_by_bfd_arch_and_mach): Likewise. gas/ * testsuite/gas/aarch64/pac_ab_key.d: Adjust expected output. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
2022-07-18x86: correct VMOVSH attributesJan Beulich3-0/+30
Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by suitable means, which would cause #UD). The memory operand form further was using the wrong Masking value, thus allowing zeroing-masking to be encoded for the store form (which would again cause #UD).
2022-07-14PowerPC: implement md_operand to parse register namesAlan Modra3-0/+15
Allows register names to appear in symbol assignments, so for example tocp = %r2 mr %r3,tocp now assembles. * gas/config/tc-ppc.c (REG_NAME_CNT): Delete, replace uses with ARRAY_SIZE. (register_name): Rename to.. (md_operand): ..this. Only handle %reg. (cr_names): Rename to.. (cr_cond): ..this. Just keep conditions. (ppc_parse_name): Add mode param. Search both cr_cond and pre_defined_registers. Handle absolute and register symbol values here rather than in expr.c:operand(). (md_assemble): Don't special case register name matching in operands, except to set cr_operand as appropriate. * gas/config/tc-ppc.h (md_operand): Don't define. (md_parse_name, ppc_parse_name): Update. * read.c (pseudo_set): Copy over entire O_register value. * testsuite/gas/ppc/regsyms.d. * testsuite/gas/ppc/regsyms.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2022-07-09gas: arm -mwarn-syms duplicatesAlan Modra1-0/+1
arm gas is only supposed to warn once per symbol for -mwarn-syms, but doesn't because the str_hash_find added with commit 629310abec88 always returns NULL. That's so because the str_hash_insert inserts a NULL value for the key,value pair. Let str_hash_insert do the job instead. * config/tc-arm.c (arm_tc_equal_in_insn): Correct already_warned logic. * testsuite/gas/arm/pr18347.s: Modify to generate duplicate warning without this patch.
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI13-32/+64
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and Zhinx extensions, respectively). In the process supporting Zfhmin and Zhinxmin extension, this commit also changes how instructions are categorized considering Zfhmin, Zhinx and Zhinxmin extensions. Detailed changes, * From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN: flh, fsh, fmv.x.h and fmv.h.x. * From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX: fmv.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX: fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h, fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h, fmadd.h, fnmadd.h, fmsub.h, fnmsub.h, fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu, fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu, feq.h, flt.h, fle.h, fgt.h, fge.h, fclass.h. * From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN: fcvt.s.h and fcvt.h.s. * From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D: fcvt.d.h and fcvt.h.d. * From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q: fcvt.q.h and fcvt.h.q. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Change implicit subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and Zhinxmin->Zfinx. (riscv_supported_std_z_ext): Added zfhmin and zhinxmin. (riscv_multi_subset_supports): Rewrite handling for new instruction classes. (riscv_multi_subset_supports_ext): Updated. (riscv_parse_check_conflicts): Change error message to include zfh and zfhmin extensions. gas/ChangeLog: * testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex error handling test. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise. * testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise. * testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d and refactored. * testsuite/gas/riscv/zhinx.s: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction classes for Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction (two operand variant) mask.
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI2-0/+12
This commit fixes floating point operand register names from ABI ones to dynamically set ones. gas/ChangeLog: * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of Zfinx extension and -M numeric disassembler option. * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR names to disassemble Zfinx instructions.
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-1/+1
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx. fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)). bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate on INSN_CLASS_{D,Q}_AND_ZFH_INX. (riscv_multi_subset_supports_ext): Fix feature gate diagnostics on INSN_CLASS_{D,Q}_AND_ZFH_INX. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march for proper testing.
2022-07-06x86: fix 3-operand insn reverse-matchingJan Beulich2-16/+15
The middle operand would have gone entirely unchecked, allowing e.g. vmovss %xmm0, %esp, %xmm2 to assemble successfully, or e.g. vmovss %xmm0, $4, %xmm2 causing an internal error. Alongside dealing with this also drop a related comment, which hasn't been applicable anymore since the introduction of 3-operand patterns with D set (and which perhaps never had been logical to be there, as reverse-matched insns don't make it there in the first place).
2022-07-06x86: introduce a state stack for .archJan Beulich3-0/+78
When using just slightly non-trivial combinations of .arch, it can be quite useful to be able to go back to prior state without needing to re-invoke perhaps many earlier directives and without needing to invoke perhaps many "negative" ones. Like some other architectures allow saving (pushing) and restoring (popping) present/prior state. For now require the same .code<N> to be in effect for ".arch pop" that was in effect for the corresponding ".arch push". Also change the global "no_cond_jump_promotion" to be bool, to match the new struct field.
2022-07-06x86: permit "default" with .archJan Beulich3-0/+34
So far there was no way to reset the architecture to that assembly would start with in the absence of any overrides (command line or directives). Note that for Intel MCU "default" is merely an alias of "iamcu". While there also zap a stray @item from the doc section, as noticed when inspecting the generated output (which still has some quirks, but those aren't easy to address without re-flowing almost the entire section).
2022-07-04gas/testsuite: properly exclude aout in all/weakref1uJan Beulich1-1/+1
Use the (wider) predicate rather than a triplet. This eliminates the sole i386-msdos failure in the testsuite.
2022-07-04x86-64: improve handling of branches to absolute addressesJan Beulich4-0/+47
There are two related problems here: The use of "addr32" on a direct branch would, besides causing a warning, result in operands to be permitted which mistakenly are refused without "addr32". Plus at some point not too long ago I'm afraid it may have been me who regressed the relocation addends emitted for such branches. Correct both problems, adding a testcase to guard against regressing this again.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess6-56/+56
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI11-0/+111
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI11-0/+809
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI11-0/+511
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-27drop XC16x bitsJan Beulich46-2169/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu6-15/+0
This patch has been pending for almost a year... However, I noticed that llvm can already re-order the extensions, even if they are out of orders. Not really sure if they can also re-order the single letter extensions, but at least we can do this for the multi-letter extensions in binutils. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are used to check the prefixed extension orders. gas/ * testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help tp reorder the prefixed extensions for now. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.d: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Likewise. * testsuite/gas/riscv/march-fail-order-z.d: Likewise. * testsuite/gas/riscv/march-fail-order-z.l: Likewise.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu11-308/+352
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-16Restore readelf -wFAlan Modra1-1/+1
Commit 94585d6d4495 resulted in readelf -wF failing with Unrecognized debug letter option 'F' binutils/ * dwarf.c (debug_dump_long_opts): Add letter. (debug_option_table): New, replacing.. (opts_table, letter_table): ..these. (dwarf_select_sections_by_names): Adjust to suit. Set do_debug_frames outside of loop. (dwarf_select_sections_by_letters): Similarly. gas/ * testsuite/gas/i386/ehinterp.d: Use readelf -wF.
2022-06-16PR29250, readelf erases CIE initial register stateAlan Modra3-1/+56
PR 29250 binutils/ * dwarf.c (display_debug_frames): Set col_type[reg] on sizing pass over FDE to cie->col_type[reg] if CIE specifies reg. Handle DW_CFA_restore and DW_CFA_restore_extended on second pass using the same logic. Remove unnecessary casts. Don't call frame_need_space on second pass over FDE. gas/ * testsuite/gas/i386/ehinterp.d, * testsuite/gas/i386/ehinterp.s: New test. * testsuite/gas/i386/i386.exp: Run it.
2022-06-03x86: exclude certain ISA extensions from v3/v4 ISAJan Beulich7-0/+36
Like TBM and LWP, XOP and FMA4 also shouldn't be included in v3. Like AVX512-4VNNIW, AVX512-4FMAPS also shouldn't be included in v4.
2022-05-31Trailing spaces in objdump -r headerAlan Modra106-142/+142
git commit 202be274a4 went a little wild in removing trailing spaces in gas/testsuite/gas/i386/{secidx.d,secrel.d}, causing x86_64-w64-mingw32 +FAIL: i386 secrel reloc x86_64-w64-mingw32 +FAIL: i386 secidx reloc I could have just replaced the trailing space, but let's fix the objdump output instead. Touches lots of testsuite files.
2022-05-30Fix failing test for armeb-gnu-eabiLuis Machado1-18/+2
The following test fails on the armeb-gnu-eabi target: FAIL: Unwind information for Armv8.1-M.Mainline PACBTI extension This patch adjusts the expected output for big endian.
2022-05-30RISC-V: Add zhinx extension supports.jiawei2-0/+125
The zhinx extension is a sub-extension in zfinx, corresponding to zfh extension but use GPRs instead of FPRs. This patch expanded the zfh insn class define, since zfh and zhinx use the same opcodes, thanks for Nelson's works. changelog in V2: Add missing classes of 'zfh' and 'zhinx' in "riscv_multi_subset_supports_ext". bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extensions. (riscv_multi_subset_supports_ext): New extensions. gas/ChangeLog: * testsuite/gas/riscv/fp-zhinx-insns.d: New test. * testsuite/gas/riscv/fp-zhinx-insns.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): New INSN classes. opcodes/ChangeLog: * riscv-opc.c: Modify INSN_CLASS.
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess203-1666/+1666
While working on another patch[1] I had need to touch this code in i386-dis.c: ins->obufp = ins->mnemonicendp; for (i = strlen (ins->obuf) + prefix_length; i < 6; i++) oappend (ins, " "); oappend (ins, " "); (*ins->info->fprintf_styled_func) (ins->info->stream, dis_style_mnemonic, "%s", ins->obuf); What this code does is add whitespace after the instruction mnemonic and before the instruction operands. The problem I ran into when working on this code can be seen by assembling this input file: .text nop retq Now, when I disassemble, here's the output. I've replaced trailing whitespace with '_' so that the issue is clearer: Disassembly of section .text: 0000000000000000 <.text>: 0: 90 nop 1: c3 retq___ Notice that there's no trailing whitespace after 'nop', but there are three spaces after 'retq'! What happens is that instruction mnemonics are emitted into a buffer instr_info::obuf, then instr_info::mnemonicendp is setup to point to the '\0' character at the end of the mnemonic. When we emit the whitespace, this is then added starting at the mnemonicendp position. Lets consider 'retq', first the buffer is setup like this: 'r' 'e' 't' 'q' '\0' Then we add whitespace characters at the '\0', converting the buffer to this: 'r' 'e' 't' 'q' ' ' ' ' ' ' '\0' However, 'nop' is actually an alias for 'xchg %rax,%rax', so, initially, the buffer is setup like this: 'x' 'c' 'h' 'g' '\0' Then in NOP_Fixup we spot that we have an instruction that is an alias for 'nop', and adjust the buffer to this: 'n' 'o' 'p' '\0' '\0' The second '\0' is left over from the original buffer contents. However, when we rewrite the buffer, we don't afjust mnemonicendp, which still points at the second '\0' character. Now, when we insert whitespace we get: 'n' 'o' 'p' '\0' ' ' ' ' ' ' ' ' '\0' Notice the whitespace is inserted after the first '\0', so, when we print the buffer, the whitespace is not printed. The fix for this is pretty easy, I can change NOP_Fixup to adjust mnemonicendp, but now a bunch of tests start failing, we now produce whitespace after the 'nop', which the tests don't expect. So, I could update the tests to expect the whitespace.... ...except I'm not a fan of trailing whitespace, so I'd really rather not. Turns out, I can pretty easily update the whitespace emitting code to spot instructions that have zero operands and just not emit any whitespace in this case. So this is what I've done. I've left in the fix for NOP_Fixup, I think updating mnemonicendp is probably a good thing, though this is not really required any more. I've then updated all the tests that I saw failing to adjust the expected patterns to account for the change in whitespace. [1] https://sourceware.org/pipermail/binutils/2022-April/120610.html
2022-05-27x86/Intel: allow MASM representation of embedded rounding / SAEJan Beulich10-1938/+1977
MASM doesn't support the separate operand form; the modifier belongs after the instruction instead. Accept this form alongside the original (now legacy) one. Short of having access to a MASM version to actually check in how far "after the instruction" is a precise statement in their documentation, allow both that and the SDM mandated form where the modifier is on the last register operand (with a possible immediate operand following). Sadly the split out function, at least for the time being, needs to cast away constness at some point, as the two callers disagree in this regard. Adjust some, but not all of the testcases.
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich2-0/+46
As a preparatory step to allowing proper non-operand forms of specifying embedded rounding / SAE, convert the internal representation to non- operand form. While retaining properties (and in a few cases perhaps providing more meaningful diagnostics), this means doing away with a few hundred standalone templates, thus - as a nice side effect - reducing memory consumption / cache occupancy.
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich36-9924/+9924
MASM doesn't consider {sae} and alike a separate operand; it is attached to the last register operand instead, just like spelled out by the SDM. Make the disassembler follow this first, before also adjusting the assembler (such that it'll be easy to see that the assembler change doesn't alter generated code).
2022-05-27x86/Intel: allow MASM representation of embedded broadcastJan Beulich22-4128/+4158
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Accept these forms alongside the original (now legacy) ones. Acceptance of the original {1to<n>} operand suffix is retained both for backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes. I have no insight (yet) into how MASM expects those to be disambiguated. Adjust some, but not all of the testcases.
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich50-16765/+16765
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Make the disassembler follow this first, before also adjusting the assembler (such that it'll be easy to see that the assembler change doesn't alter generated code). For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes the original {1to<n>} operand suffix is retained, to disambiguate output. I have no insight (yet) into how MASM expects those to be disambiguated.
2022-05-25RISC-V: Fix RV32Q conflictTsukasa OI7-3/+19
This commit makes RV32 + 'Q' extension (version 2.2 or later) not conflicting since this combination is no longer prohibited by the specification. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict detection that prohibits RV32Q on 'Q' version 2.2 or later. gas/ChangeLog: * testsuite/gas/riscv/march-fail-rv32iq.d: Removed. * testsuite/gas/riscv/march-fail-rv32iq.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test showing RV32IQ fails on 'Q' extension version 2.0. * testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise. * testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise. * testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test showing RV32IQ fails on ISA specification version 2.2. * testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test showing RV32IQ succesds on 'Q' extension version 2.2. * testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test showing RV32IQ succesds on ISA specification 20190608.
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin4-4/+4
Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB field present in binutils sources. Also, per 1.6.2, BC has the same semantics as BA and BB fields, so this should keep the same flags and mask, only with the different offset. opcodes/ * ppc-opc.c (BC): Define new field, with the same definition as CRB field, but with the PPC_OPERAND_CR_BIT flag present. gas/ * testsuite/gas/ppc/476.d: Update. * testsuite/gas/ppc/a2.d: Update. * testsuite/gas/ppc/e500.d: Update. * testsuite/gas/ppc/power7.d: Update.
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-0/+36
Update zfinx implement with zicsr, fix missing fcsr use by zfinx. add zicsr imply by zfinx. bfd/ChangeLog: * elfxx-riscv.c: New imply. gas/ChangeLog: * testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test. opcodes/ChangeLog: * riscv-opc.c: Update insn class.
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI3-0/+8
As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only), it should be removed until RV128 support for GNU Binutils is required again. gas/ChangeLog: * testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test. * testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise. * testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q, MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
2022-05-19arm: Fix system register fpcxt_ns and fpcxt_s naming convention.Srinath Parvathaneni2-0/+77
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M Mainline Instructions VSTR, VLDR, VMRS and VMSR. Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s and fpcxts. This patch fixes the issue.
2022-05-18arm: Add unwind support for mixed register listsVictor Do Nascimento3-9/+23
* config/tc-arm.c (parse_reg_list): Add handling of mixed register types. (reg_names): Enumerate pseudoregister according to mapped physical register number. (s_arm_unwind_save_pseudo): Modify function signature. (s_arm_unwind_save_core): Likewise. (s_arm_unwind_save_mixed): New function. (s_arm_unwind_save): Generate register list mask to pass to nested functions. * testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed register type lists. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
2022-05-18gas: avoid octal numbers being accepted when processing .linefileJan Beulich2-0/+4
Compilers would put decimal numbers there, so I think we should treat finding octal numbers the same as finding bignums - ignore them as actually being comments of some very specific form.
2022-05-18gas: avoid bignum related errors when processing .linefileJan Beulich3-0/+12
Any construct which to the scrubber looks like a C preprocessor line/file "directive" is converted to .linefile, but the amount of checking the scrubber does is minimal (albeit it does let through only decimal digits for the line part of the contruct). Since the scrubber conversion is further tied to # being a line comment character, anything which upon closer inspection turns out not to be a line/file "directive" is supposed to be treated as a comment, i.e. ignored. Therefore we cannot use get_absolute_expression(), as this may raise errors. Open- code the function instead, treating everything not resulting in O_constant as a comment as well. Furthermore also bounds-check the parsed value. This bounds check tries to avoid implementation defined behavior (which may be the raising of an implementation defined signal), but for now makes the assumption that int has less than 64 bits. The way bfd_signed_vma (which is what offsetT aliases) is defined in bfd.h for the BFD64 case I cannot really see a clean way of avoiding this assumption. Omitting the #ifdef, otoh, would risk "condition is always false" warnings by compilers. Convert get_linefile_number() to return bool at this occasion as well.
generated by cgit v1.1 at 2024-11-22 10:39:44 +0000