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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-06-27 11:03:44 +0900 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-07-07 12:06:02 +0800 |
| commit | 3d5d6bd55433735c4fc620a47b543065582d06ae (patch) | |
| tree | 7de69e8d4565d68c1eda18aaae0ac7185abf36d3 /gas/testsuite | |
| parent | 37cf60c6a6d36bbf5cf1523697906c4bdb4eb468 (diff) | |
| download | gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.zip gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.tar.gz gdb-3d5d6bd55433735c4fc620a47b543065582d06ae.tar.bz2 | |
RISC-V: Fix disassembling Zfinx with -M numeric
This commit fixes floating point operand register names from ABI ones
to dynamically set ones.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
Zfinx extension and -M numeric disassembler option.
* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
names to disassemble Zfinx instructions.
Diffstat (limited to 'gas/testsuite')
| -rw-r--r-- | gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 |
2 files changed, 12 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d new file mode 100644 index 0000000..ba3f622 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d @@ -0,0 +1,10 @@ +#as: -march=rv64ima_zfinx +#source: zfinx-dis-numeric.s +#objdump: -dr -Mnumeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s new file mode 100644 index 0000000..b55cbd5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s @@ -0,0 +1,2 @@ +target: + feq.s a0, a1, a2 |