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2023-12-29x86: Append "#pass" to APX testsH.J. Lu5-0/+5
2023-12-29x86: Don't use .insn with '/'H.J. Lu1-3/+3
2023-12-29LoongArch: gas: Add support for tls le relax.changjiachen4-0/+53
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma2-0/+24
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESCH.J. Lu5-0/+67
2023-12-28x86-64: Add R_X86_64_CODE_4_GOTPCRELXH.J. Lu5-2/+39
2023-12-28Support APX JMPABS for disassemblerHu, Lin16-0/+87
2023-12-28Support APX NDD optimized encoding.Hu, Lin13-0/+258
2023-12-28Support APX pushp/poppCui, Lili6-0/+51
2023-12-28Support APX Push2/Pop2Mo, Zewei11-0/+183
2023-12-28Support APX NDDkonglin17-0/+407
2023-12-28Add tests for APX GPR32 with extend evex prefixCui, Lili12-0/+1498
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili2-2/+2
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili15-139/+413
2023-12-25LoongArch: Add testsuit for DESC and tls transition and tls relaxation.Lulu Cai10-0/+214
2023-12-25LoongArch: Add support for TLS LD/GD/DESC relaxationmengqinggang4-278/+290
2023-12-22x86: properly respect rex/{rex}Jan Beulich5-0/+27
2023-12-22LoongArch: Add support for the third expression of .align for R_LARCH_ALIGNmengqinggang2-19/+31
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus2-0/+4
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-0/+28
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo4-0/+17
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-2/+13
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo4-0/+22
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang2-227/+25
2023-12-18LoongArch: Add call36 and tail36 pseudo instructions for medium code modelmengqinggang2-2/+10
2023-12-18LoongArch: Add new relocation R_LARCH_CALL36mengqinggang2-0/+21
2023-12-15aarch64: Enable Cortex-X3 CPUMatthieu Longo1-0/+6
2023-12-15x86: last-insn recording should be per-subsectionJan Beulich3-0/+39
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-4/+4
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich6-49/+22
2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma2-3/+3
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili13-128/+128
2023-12-12RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instructionRui Ueyama1-0/+3
2023-12-12RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'Lifang Xia3-0/+76
2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang2-0/+15
2023-12-01x86: i386_cons_align() badly affects diagnosticsJan Beulich2-8/+2
2023-12-01gas: no md_cons_align() for .nop{,s}Jan Beulich3-1/+17
2023-12-01x86: last-insn recording should be per-sectionJan Beulich4-0/+52
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich1-4/+4
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+70
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner6-58/+48
2023-11-30MIPS/GAS: Add -march=loongson2f to loongson-2f-3 testYunQiang Su1-1/+1
2023-11-30MIPS: Set r6 as default arch if vendor is imgYunQiang Su2-2/+2
2023-11-30gas: support double-slash line comments in BPF assemblyJose E. Marchesi5-0/+38
2023-11-28gas: change meaning of ; in the BPF assemblerJose E. Marchesi9-30/+30
2023-11-28testsuite: Clean up .allow_index_reg in i386 testsHaochen Jiang234-574/+350
2023-11-28testsuite: Clean up #as in dump file for i386 testsHaochen Jiang262-262/+0
2023-11-27as: Add new estimated reciprocal instructions in LoongArch v1.1Jiajie Chen4-0/+24
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen2-0/+84
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich2-7/+48