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AgeCommit message (Expand)AuthorFilesLines
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks1-2/+2
2019-07-24Complain about mbind, ifunc, and unique in final_writeAlan Modra1-0/+3
2019-07-23SHF_GNU_MBIND requires ELFOSABI_GNUAlan Modra1-26/+43
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks1-5/+0
2019-07-19gas: make .lcomm to accept an optional aligmnet in eBPF targetsJose E. Marchesi1-1/+43
2019-07-19[AArch64] Rename +bitperm to +sve2-bitpermRichard Sandiford1-1/+1
2019-07-19[PowerPC64] pc-relative TLS relocationsAlan Modra1-5/+39
2019-07-18gas: .lcomm gets an alignment argument in eBPFJose E. Marchesi1-1/+2
2019-07-17gas: support .half, .word and .dword directives in eBPFJose E. Marchesi1-0/+3
2019-07-17x86: replace "anymem" checks where possibleJan Beulich1-8/+14
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-12/+18
2019-07-16x86: fold SReg{2,3}Jan Beulich2-23/+22
2019-07-09Re: gas/ELF: don't accumulate .type settingsAlan Modra3-29/+23
2019-07-04x86: correct "-Q" option handlingJan Beulich1-1/+3
2019-07-04gas/ELF: don't accumulate .type settingsJan Beulich2-1/+40
2019-07-02This patch fixes a bug in the AArch64 assembler where an incorrect structural...Barnaby Wilks1-0/+9
2019-07-01x86: drop Vec_Imm4Jan Beulich1-25/+11
2019-07-01x86: limit ImmExt abuseJan Beulich1-13/+10
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+23
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+43
2019-07-01x86: StaticRounding implies SAEJan Beulich1-6/+3
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-11/+19
2019-07-01x86: use encoding_length() also elsewhereJan Beulich1-32/+4
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich1-0/+32
2019-06-27This fixes a bug in the ARm assembler where an immediate operand larger than ...Barnaby Wilk s1-4/+9
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-2/+2
2019-06-25MIPS/gas: Fix order of instructions in LI macro expansionFaraz Shahbazker1-11/+29
2019-06-25x86: correct / adjust debug printingJan Beulich1-9/+10
2019-06-25x86: don't open code is_any_vex_encoding()Jan Beulich1-3/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+5
2019-06-25Fix logical expression in last commitAlan Modra1-1/+1
2019-06-25PowerPC nopsAlan Modra2-19/+54
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu1-0/+3
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+3
2019-05-30RISC-V: Fix lui argument parsing.Jim Wilson1-5/+4
2019-05-27Fix failure on powerpc 32-bit only targetsAlan Modra1-50/+120
2019-05-24aarch64: override default elf .set handling in gasSzabolcs Nagy2-0/+38
2019-05-24aarch64: handle .variant_pcs directive in gasSzabolcs Nagy1-0/+23
2019-05-24PowerPC relocations for prefix insnsAlan Modra2-23/+149
2019-05-24PowerPC D-form prefixed loads and storesPeter Bergner1-1/+4
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner2-40/+177
2019-05-23gas: add support for eBPFJose E. Marchesi2-0/+405
2019-05-22S12Z: GAS: New option --mdollar-hex.John Darrington1-8/+59
2019-05-21[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructionsSudakshina Das1-11/+95
2019-05-21[binutils, Arm] Add support for conditional instructions in Armv8.1-M MainlineSudakshina Das1-1/+81
2019-05-21[binutils, Arm] Add support for shift instructions in MVESudakshina Das1-0/+50
2019-05-21[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M BaselineAndre Vieira1-0/+5
2019-05-21GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value.John Darrington6-3/+6
2019-05-21Revert "GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value."John Darrington6-6/+3
2019-05-20[MIPS] PR gas/14798: Limit IRIX5 specific default typing to IRIX targetsFaraz Shahbazker1-0/+4
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