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author | Jan Beulich <jbeulich@novell.com> | 2019-06-27 08:49:40 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2019-06-27 08:49:40 +0200 |
commit | c1dc7af52143966da8065b527e7a7000cf9f7705 (patch) | |
tree | ce51bfa565271617a9381fe6ab37639feb8818fd /gas/config | |
parent | 65bd27298d31c6733b68d0cd6b7a4fc26e0598be (diff) | |
download | gdb-c1dc7af52143966da8065b527e7a7000cf9f7705.zip gdb-c1dc7af52143966da8065b527e7a7000cf9f7705.tar.gz gdb-c1dc7af52143966da8065b527e7a7000cf9f7705.tar.bz2 |
x86: allow VEX et al encodings in 16-bit (protected) mode
These encodings aren't valid in real and VM86 modes, but they are very
well usable in 16-bit protected mode.
A few adjustments in the disassembler tables are needed where Ev or Gv
were wrongly used. Additionally an adjustment is needed to avoid
printing "addr32" when that's already recognizable by the use of %eiz.
Furthermore the Iq operand template was wrong for XOP:0Ah encoding
insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
Id instead.
Clone a few existing test cases to exercise assembler and disassembler.
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/tc-i386.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 6c5d5b4..4e55188 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4388,9 +4388,9 @@ md_assemble (char *line) if (is_any_vex_encoding (&i.tm)) { - if (flag_code == CODE_16BIT) + if (!cpu_arch_flags.bitfield.cpui286) { - as_bad (_("instruction `%s' isn't supported in 16-bit mode."), + as_bad (_("instruction `%s' isn't supported outside of protected mode."), i.tm.name); return; } |