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AgeCommit message (Expand)AuthorFilesLines
2019-05-10Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker1-6/+14
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-4/+48
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+13
2019-05-08xtensa ignores option --no-link-relaxAlan Modra1-3/+4
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-1/+18
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra1-0/+20
2019-05-04m32c padding with nopsAlan Modra2-20/+5
2019-05-02i386: Issue a warning to IRET without suffix for .code16gccH.J. Lu1-7/+13
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-0/+3
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-9/+57
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu1-0/+6
2019-04-19RX Assembler: Ensure that the internal limit on the number of relaxation iter...Nick Clifton2-8/+22
2019-04-18Improve warning message for $0 constraint on MIPSR6 branchesMatthew Fortune1-1/+4
2019-04-18MSP430 Assembler: Define symbols for functions to run through.Jozef Lawrynowicz1-6/+38
2019-04-17MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unk...Jozef Lawrynowicz1-8/+37
2019-04-16Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPEAlan Modra5-36/+30
2019-04-16Make fixup fx_where unsignedAlan Modra4-6/+6
2019-04-16Make frag fr_fix unsignedAlan Modra7-13/+11
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira1-4/+120
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira1-14/+103
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira1-29/+85
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma...Andre Vieira1-0/+113
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira1-0/+83
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira1-0/+35
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira1-0/+21
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira1-0/+35
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira1-0/+9
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira1-0/+61
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira1-0/+35
2019-04-15[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct ...Andre Vieira1-271/+304
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo...Andre Vieira1-0/+54
2019-04-15[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M MainlineAndre Vieira1-4/+16
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira1-45/+47
2019-04-13[MIPS] Add i6500 CPU and fix i6400 default ASEsMatthew Fortune1-1/+3
2019-04-13[MIPS] Apply ASE information for the selected processorMatthew Fortune1-7/+15
2019-04-12GAS: S12Z: Remove definition of macro TC_M68K.John Darrington1-3/+0
2019-04-12GAS: tc-s12z.c: int -> bfd_booleanJohn Darrington1-206/+206
2019-04-11xtensa: gas: clean up literal management codeMax Filippov1-60/+54
2019-04-11xtensa: gas: put .literal_position at section startMax Filippov1-13/+9
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+2
2019-04-10Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86Rainer Orth1-0/+6
2019-04-10te-cloudabi.hAlan Modra3-5/+32
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu1-0/+2
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+3
2019-04-03gas: use literals/const16 for xtensa loop relaxationMax Filippov2-142/+55
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