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2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+64
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford1-4/+52
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-31/+130
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford1-0/+5
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford1-4/+1
2016-09-21[AArch64][SVE 12/32] Remove boolean parameters from parse_address_mainRichard Sandiford1-24/+21
2016-09-21[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interfaceRichard Sandiford1-106/+108
2016-09-21[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_floatRichard Sandiford1-8/+6
2016-09-21[AArch64][SVE 09/32] Improve error messages for invalid floatsRichard Sandiford1-6/+14
2016-09-21[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovableRichard Sandiford1-33/+29
2016-09-21[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_VRichard Sandiford1-22/+31
2016-09-21[AArch64][SVE 06/32] Generalise parse_neon_reg_listRichard Sandiford1-5/+8
2016-09-21[AArch64][SVE 05/32] Rename parse_neon_type_for_operandRichard Sandiford1-2/+2
2016-09-21[AArch64][SVE 04/32] Rename neon_type_el to vector_type_elRichard Sandiford1-16/+16
2016-09-21[AArch64][SVE 03/32] Rename neon_el_type to vector_el_typeRichard Sandiford1-4/+4
2016-09-21[AArch64][SVE 01/32] Remove parse_neon_operand_typeRichard Sandiford1-27/+4
2016-09-14gas: improve architecture mismatch diagnostics in sparcJose E. Marchesi1-1/+1
2016-09-14gas: detect DCTI couples in sparcJose E. Marchesi1-11/+45
2016-09-14[ARC] Fix parsing dtpoff relocation expression.Claudiu Zissulescu1-1/+1
2016-09-12S/390: Add alternate processor names.Andreas Krebbel1-13/+31
2016-09-12S/390: Fix facility bit default.Andreas Krebbel1-1/+4
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu1-1/+1
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-21/+2
2016-09-07[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs.Richard Earnshaw1-9/+9
2016-08-31PowerPC VLE sh_flags and p_flagsAlan Modra1-5/+9
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme1-18/+27
2016-08-25Remove _S version of ARM MSR/MRS special registersThomas Preud'homme1-2/+2
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+2
2016-08-19ARM: Issue a warning when the MRRC and MRRC2 instructions are used with the s...Tamar Christina1-0/+8
2016-08-11[AArch64] Reject -0.0 as an 8-bit FP immediateRichard Sandiford1-1/+1
2016-08-05Ensure ARM VPUSH and VPOP instructions do not affect more than 16 registers.Nick Clifton2-37/+53
2016-08-05Fix the generation of alignment frags in code sections for AArch64.Nick Clifton1-3/+7
2016-08-04Fix generation of relocs for 32-bit Sparc Solaris targets.Stefan Trleman1-0/+16
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki1-51/+203
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall1-35/+117
2016-07-26MIPS/GAS: Respect the `insn32' mode in branch relaxationMaciej W. Rozycki1-45/+85
2016-07-20MIPS/GAS: Remove erroneous ELF relocation referencesMaciej W. Rozycki1-7/+5
2016-07-19MIPS: Convert cross-mode BAL to JALXMaciej W. Rozycki1-4/+14
2016-07-19MIPS: Verify the ISA mode and alignment of branch and jump targetsMaciej W. Rozycki1-16/+264
2016-07-19make the type of nds32_pseudo_opcode::pseudo_val unsignedTrevor Saunders1-32/+62
2016-07-19sparc: make a field type bfd_reloc_code_real_typeTrevor Saunders1-1/+1
2016-07-19sparc: remove a sentinalTrevor Saunders1-16/+11
2016-07-19tc-z8k.c: make some argument types bfd_reloc_code_real_typeTrevor Saunders1-3/+8
2016-07-16Don't include libbfd.h outside of bfd, part 2Alan Modra8-8/+0
2016-07-16Don't include libbfd.h outside of bfd, part 1Alan Modra5-8/+3
2016-07-14MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbolsMaciej W. Rozycki2-0/+19
2016-07-14MIPS/GAS: Keep the ISA bit in the addend of branch relocationsMaciej W. Rozycki1-9/+1
2016-07-11TLS: DTPOFF can accept offsets, stored into addendum. Remove the need of baseClaudiu Zissulescu1-23/+2
2016-07-08MIPS/GAS: Remove extraneous `install_insn' call from `append_insn'Maciej W. Rozycki1-1/+0
2016-07-05x86: fix register check in check_qword_reg()Jan Beulich1-1/+1
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