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2018-07-21gas/config/tc-i386.c: Break long lineH.J. Lu1-4/+6
* config/tc-i386.c (match_simd_size): Break long line. (match_mem_size): Likewise.
2018-07-20x86: Rename match_reg_size to match_operand_sizeH.J. Lu1-11/+12
match_reg_size checks size for both memory and register operands. This patch renamed match_reg_size to match_operand_size and updated comments for commit 3ac21baa8498d3aa9951f79e2c3336d532eeff7b Author: Jan Beulich <jbeulich@novell.com> Date: Mon Jul 16 08:19:21 2018 +0200 x86: fix operand size checking which added one argument to match_reg_size, match_simd_size and match_mem_size. * config/tc-i386.c (match_reg_size): Renamed to ... (match_operand_size): This. Update comments. (match_simd_size): Update comments. Replace match_reg_size with match_operand_size. (match_mem_size): Likewise. (operand_size_match): Replace match_reg_size with match_operand_size.
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-2/+16
The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI instructions.
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-1/+19
These are special because they may not have a register operand to derive the vector length from, which requires to also deal with the braodcast case when determining vector length in build_evex_prefix(). Also drop IgnoreSize (and the now redundant size specifiers) from their suffixed counterparts.
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-2/+43
2018-07-16x86: fix operand size checkingJan Beulich1-54/+61
Currently mov to/from control, debug, and test register insns accept any size GPR operand (general pattern: templates with D set and both operands being registers in distinct register files). This is due to improper checking of the reverse case, including not informing the caller whether a straight and/or reverse match was successful. The helper functions need to be told two indexes: One to index the given operand types array, and the other to index the template one. The caller must attempt a further straight match only if the function reported a straight match (and respectively for reverse matches).
2018-07-13Allow bit-patterns in the immediate field of ARM neon mov instructions.Nick Clifton1-4/+15
* config/tc-arm.c (do_neon_mov): When converting an integer immediate into a floating point value, check that the conversion is valid. Also warn if the immediate is valid as both a floating point value and a bit pattern. * testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use floating point bit patterns. * testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly of the new insns.
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das1-0/+2
See: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move csdb together with them. (thumb32_opcodes): Likewise. gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions. * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb. * testsuite/gas/arm/csdb.d: Likewise * testsuite/gas/arm/thumb2_it_bad.s: Likewise. * testsuite/gas/arm/thumb2_it_bad.l: Likewise. * testsuite/gas/arm/barrier.d: Update with ssbb. * testsuite/gas/arm/barrier-thumb.d: Likewise.
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich1-7/+2
The checking against reg16_inoutportreg can be had with a simple test of a bit, and the value setting from inoutportreg can be replaced by using the actual register's reg_type field. Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG is left in place, for its use in type_names[].
2018-07-11x86: simplify legacy prefix emissionJan Beulich1-10/+4
The check_prefix label was bogus from the beginning: The special checking is supposed to happen for PadLock insns only; no 3-opcode-byte insn should go this path.
2018-07-11x86: fix "REP RET" with -madd-bnd-prefixJan Beulich1-4/+10
Just like any other branches, RET should gain a BND prefix also when already prefixed in source by REP.
2018-07-02microMIPS/GAS: Handle several percent-ops with macrosMaciej W. Rozycki1-1/+20
In the microMIPS mode also accept %half, %got, %call, %got_hi, %got_lo, %call_hi, %call_lo, %neg, %got_page, %highest, %got_disp, %tlsgd, %tlsldm, %dtprel_hi, %dtprel_lo, %gottprel, %tprel_hi and %tprel_lo percent-ops with macros, so that they can be used with instructions that expand into sequences if relocation is required due to their limited offset span, such as LL, LWL, etc., fixing GAS assertions: .../gas/testsuite/gas/mips/elf-rel28.s: Assembler messages: .../gas/testsuite/gas/mips/elf-rel28.s:17: Internal error in macro_build at .../gas/config/tc-mips.c:8854. Please report this bug. observed if an attempt is made to assemble the `elf-rel28.s' test case modified to use one of the affected instructions to microMIPS code. gas/ * config/tc-mips.c (macro_build) <'i', 'j'>: Also accept BFD_RELOC_16, BFD_RELOC_MIPS_GOT16, BFD_RELOC_MIPS_CALL16, BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MIPS_SUB, BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MIPS_TLS_TPREL_HI16 and BFD_RELOC_MIPS_TLS_TPREL_LO16 relocations if in the microMIPS mode. * testsuite/gas/mips/elf-rel28-lldscd-n32.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-micromips-n32.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-n64.d: New test. * testsuite/gas/mips/elf-rel28-lldscd-micromips-n64.d: New test. * testsuite/gas/mips/elf-rel28.s: Add instruction selection. * testsuite/gas/mips/mips.exp: Run the new tests.
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme1-42/+42
BFD's bfd_get_mach () function returns a bfd specific value representing the architecture of the target which is populated from the Tag_CPU_arch build attribute value of that target. Among other users of that interfacem, objdump which uses it to print the architecture version of the binary being examinated and to decide what instruction is available if run with "-m arm" via its own mapping from bfd_mach_arm_X values to feature bits available. However, both BFD and objdump's most recent known architecture is Armv5TE. When encountering a newer architecture bfd_get_mach will return bfd_mach_arm_unknown. This is unfortunate since objdump uses that value to allow all instructions on all architectures which is already what it does by default, making the "-m arm" trick useless. This patch updates BFD and objdump's knowledge of Arm architecture versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A) share the same Tag_CPU_arch build attribute value and bfd_mach_arm values, the mapping from bfd machine value to feature bits need to return the most featureful feature bits that would yield the given bfd machine value otherwise some instruction would not disassemble under "-m arm" mode. The patch rework that mapping to make this clearer and simplify writing the mapping rules. In particular, for simplicity all FPU instructions are allowed in all cases. Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the TAG_CPU_ARCH_X macros rather than hardcode their value. 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entries for above new bfd_mach_arm values. * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later architectures. Force assert failure for any new Tag_CPU_arch value. gas/ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros rather than hardcode their values. ld/ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow all FPU features and add mapping from new bfd_mach_arm values to allowed CPU feature bits. opcodes/ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in expected result. * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. * testsuite/ld-arm/tls-longplt-lib.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise.
2018-06-29RISC-V: Add gas support for "fp" register.Jim Wilson1-0/+3
gas/ * config/tc-riscv.c (md_begin): Call hash_reg_name for "fp".
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan1-0/+16
A recent case in golang highlighted that gas wasn't warning on these unpredictable cases in the architecture. Fixed thusly. I need to audit gcc to make sure we have early clobbers on the patterns but that's a separate patch. Tested aarch64-none-elf and gas Ok ? Ramana 2018-06-29 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Add unpredictable cases for ldxp, stlxrb, stlxrh, stlxr. * testsuite/gas/aarch64/diagnostic.s: New tests. * testsuite/gas/aarch64/diagnostic.l: Adjust.
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+2
Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton1-8/+18
PR 23335 * config/tc-msp430.c (check_reg): Only accept register name strings that do not end in an alphanumeric character. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only ↵Nick Clifton1-4/+6
set the bottom bit of imported thumb function symbols if the -mthumb-interwork option is active. For more information see the email thread starting here: https://www.sourceware.org/ml/binutils/2018-05/msg00348.html PR 21458 * tc-arm.c (do_adr): Only set the bottom bit of an imported thumb function symbol address if -mthumb-interwork is active. (do_adrl): Likewise. * doc/c-arm.texi: Update descriptions of the -mthumb-interwork option and the ADR and ADRL pseudo-ops. * NEWS: Mention the new behaviour of the ADR and ADRL pseudo-ops. * testsuite/gas/arm/pr21458.d: Add -mthumb-interwork option to assembler command line. * testsuite/gas/arm/adr.d: Likewise. * testsuite/gas/arm/adrl.d: Likewise.
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber1-0/+11
opcodes/ PR gas/23305 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for la and lla. gas/ PR gas/23305 * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for constants and symbols. * testsuite/gas/riscv/lla32.d: New file. * testsuite/gas/riscv/lla32.s: Likewise. * testsuite/gas/riscv/lla64-fail.d: Likewise. * testsuite/gas/riscv/lla64-fail.l: Likewise. * testsuite/gas/riscv/lla64-fail.s: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/lla64.s: Likewise.
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-0/+14
Add support for the Global INValidate Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 187-191 bfd/ * elfxx-mips.c (print_mips_ases): Add GINV extension. binutils/ * readelf.c (print_mips_ases): Add GINV extension. gas/ * NEWS: Mention MIPS Global INValidate ASE support. * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV. (md_longopts): Likewise. (mips_ases): Define availability for GINV. (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV. (md_show_usage): Add help for -mginv and -mno-ginv. * doc/as.texinfo: Document -mginv, -mno-ginv. * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and .set noginv. * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV ASE. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Likewise. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ginv.d: New test. * testsuite/gas/mips/ginv-err.d: New test. * testsuite/gas/mips/ginv-err.l: New test stderr output. * testsuite/gas/mips/ginv.s: New test source. * testsuite/gas/mips/ginv-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. (AFL_ASE_MASK): Update to include AFL_ASE_GINV. * opcode/mips.h: Document "+\" operand format. (ASE_GINV): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and mips64r6 descriptors. (parse_mips_ase_option): Handle -Mginv option. (print_mips_disassembler_options): Document -Mginv. * mips-opc.c (decode_mips_operand) <+\>: New operand format. (GINV): New macro. (mips_opcodes): Define ginvi and ginvt.
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+14
Add support for the CRC Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 143-148 [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 165-170 ChangeLog: bfd/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elfxx-mips.c (print_mips_ases): Add CRC. binutils/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * readelf.c (print_mips_ases): Add CRC. gas/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> Maciej W. Rozycki <macro@mips.com> * config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC. (md_longopts): Likewise. (md_show_usage): Add help for -mcrc and -mno-crc. (mips_ases): Define availability for CRC and CRC64. (mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC. * doc/as.texinfo: Document -mcrc, -mno-crc. * doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and .set no-crc. * testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC ASE. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ase-errors-1.s: Likewise. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/crc.d: New test. * testsuite/gas/mips/crc64.d: New test. * testsuite/gas/mips/crc-err.d: New test. * testsuite/gas/mips/crc64-err.d: New test. * testsuite/gas/mips/crc-err.l: New test stderr output. * testsuite/gas/mips/crc64-err.l: New test stderr output. * testsuite/gas/mips/crc.s: New test source. * testsuite/gas/mips/crc64.s: New test source. * testsuite/gas/mips/crc-err.s: New test source. * testsuite/gas/mips/crc64-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elf/mips.h (AFL_ASE_CRC): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_CRC. * opcode/mips.h (ASE_CRC): New macro. * opcode/mips.h (ASE_CRC64): Likewise. opcodes/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. * mips-opc.c (CRC, CRC64): New macros. (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, crc32cb, crc32ch and crc32cw for CRC. Define crc32d and crc32cd for CRC64.
2018-06-11MIPS/GAS: Correct `-O0' and `-O' option help, add `-O1' and `-O2'Maciej W. Rozycki1-2/+3
Match commit 4ffff32f75b1 ("Match mips_optimize to the -O option supplied") and adjust `--help' output for `-O0', `-O', `-O1' and `-O2' options. gas/ * config/tc-mips.c (md_show_usage): Correct help text for `-O0' and `-O'. Mention `-O1'. Add `-O2' and its description.
2018-06-08[arm][gas] Add support for Arm Cortex-A76kyrtka011-0/+3
This patch adds support to gas for -mcpu=cortex-a76 in the usual way. make check-gas passes without problems. 2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add Cortex-A76 entry. * doc/c-arm.texi (-mcpu): Document cortex-a76.
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka011-0/+3
This patch adds support to gas for -mcpu=cortex-a76 in the usual way. make check-gas passes without problems. 2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add Cortex-A76 entry. * doc/c-aarch64.texi (-mcpu): Document cortex-a76.
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina1-0/+2
This patch fixes an uninitialized memory issue that can under certain circumstances turn an error into a warning because non_fatal was not initialised in all cases. Verified using valgrind. gas/config/tc-aarch64.c PR binutils/21446 * tc-aarch64.c (record_operand_error, record_operand_error_with_data): Initialize non_fatal.
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports ↵Sameera Deshpande1-1/+1
ARMv8.4 gas * config/tc-aarch64.c (aarch64_cpus): Add support of ARMv8.4 in saphira.
2018-06-04xtensa: add separate property sections optionMax Filippov1-1/+21
It is currently not possible to correctly match .xt.prop information for sections with identical VMA. Allow creation of separate property sections in the BFD. Add assembler option --separate-prop-tables to allow creation of separate property sections. 2018-06-04 Volodymyr Arbatov <arbatov@cadence.com> bfd/ * elf32-xtensa.c (elf32xtensa_separate_props): New global variable. (xtensa_add_names): New function. (xtensa_property_section_name): Add new parameter separate_sections, use it to choose property section name. (xtensa_get_separate_property_section): New function. (xtensa_get_property_section): Invoke xtensa_get_separate_property_section to get individual property section if it exists, common property section otherwise. (xtensa_make_property_section): Pass elf32xtensa_separate_props to xtensa_property_section_name. gas/ * config/tc-xtensa.c (elf32xtensa_separate_props): New declaration. (option_separate_props, option_no_separate_props): New enumeration constants. (md_longopts): Add separate-prop-tables option. (md_parse_option): Add cases for option_separate_props and option_no_separate_props. (md_show_usage): Add help for [no-]separate-prop-tables options.
2018-06-01x86: relax redundant REX prefix checkJan Beulich1-2/+3
All REX bits can be specified via individual prefixes. Redundancy should only be reported on a per-bit basis. Note that I originally had further checks added to the test case, checking the effect also on PDEP. I had to strip those, because my patch to correctly handle those (https://sourceware.org/ml/binutils/2017-02/msg00280.html) was rejected. I continue to think that there should not be any new prefix introduced to handle the VEX case - whether the encoding of an insn requires VEX et al should not be of immediate interest to the programmer.
2018-06-01x86: simplify control register checkJan Beulich1-5/+2
... as is already done elsewhere: There's no need for the use of operand_type_equal() here - the bit identifying control registers isn't used for any other purposes.
2018-06-01x86: tighten condition for emitting LOCK on control register accessesJan Beulich1-4/+3
The control register is never expressed by REX.B; this bit only affects the involved GPR. Also only one of the operands can have its "control" flag set, so only check the correct operand.
2018-05-30Add znver2 support.Amit Pawar1-0/+2
gas/ * config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. * doc/c-i386.texi : Document znver2. * gas/testsuite/gas/i386/arch-13.s: Updated for znver2. * gas/testsuite/gas/i386/arch-13.d: Updated. * gas/testsuite/gas/i386/arch-13-znver1.d: Updated. * gas/testsuite/gas/i386/arch-13-znver2.d: New file. * gas/testsuite/gas/i386/x86-64-arch-3.s: Updated for znver2. * gas/testsuite/gas/i386/x86-64-arch-3.d: Updated. * gas/testsuite/gas/i386/x86-64-arch-3-znver1.d: Updated. * gas/testsuite/gas/i386/x86-64-arch-3-znver2.d: New file. * gas/testsuite/gas/i386/i386.exp: Updated for new test. opcode/ * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. * i386-init.h : Regenerated.
2018-05-24RISC-V: Fix .align handling when .option norelax.Jim Wilson2-10/+22
gas/ PR gas/23219 * config/tc-riscv.c (riscv_frag_align_code): Move frag_more call after !riscv_opts.relax check. (riscv_handle_align): Rewrite !riscv_opts.relax support. * config/tc-riscv (MAX_MEM_FOR_RS_ALIGN_CODE): Update. * testsuite/gas/riscv/no-relax-align.d: New * testsuite/gas/riscv/no-relax-align.s: New * testsuite/gas/riscv/no-relax-align-2.d: New * testsuite/gas/riscv/no-relax-align-2.s: New
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-14/+2
opcodes/ * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. (insert_bab, extract_bab, insert_btab, extract_btab, insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. (BAT, BBA VBA RBS XB6S): Delete macros. (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. (BB, BD, RBX, XC6): Update for new macros. (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, e_crnot, e_crclr, e_crset, e_crmove>: Likewise. * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. include/ * opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro. gas/ * config/tc-ppc.c (md_assemble): Delete handling of fake operands. * testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add test of extended mnemonics. * testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset. * testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics. * testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-18RISC-V: Add RV32E support.Jim Wilson1-10/+56
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle EF_RISCV_RVE. binutils/ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE. gas/ * config/tc-riscv.c (rve_abi): New. (riscv_set_options): Add rve field. Initialize it. (riscv_set_rve) New function. (riscv_set_arch): Support 'e' ISA subset. (reg_lookup_internal): If rve, check register is available. (riscv_set_abi): New parameter rve. (md_parse_option): Pass new argument to riscv_set_abi. (riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set EF_RISCV_RVE. * doc/c-riscv.texi (-mabi): Document new ilp32e argument. include/ * elf/riscv.h (EF_RISCV_RVE): New define.
2018-05-18Add support for the Freescale s12z processor.John Darrington2-0/+3945
bfd * Makefile.am: Add s12z files. * Makefile.in: Regenerate. * archures.c: Add bfd_s12z_arch. * bfd-in.h: Add exports of bfd_putb24 and bfd_putl24. * bfd-in2.h: Regenerate. * config.bfd: Add s12z target. * configure.ac: Add s12z target. * configure: Regenerate. * cpu-s12z.c: New file. * elf32-s12z.c: New file. * libbfd.c (bfd_putb24): New function. (bfd_putl24): New function. * libbfd.h: Regenerate. * reloc.c: Add s12z relocations. (bfd_get_reloc_size): Handle size 5 relocs. * targets.c: Add s12z_elf32_vec. opcodes * Makefile.am: Add support for s12z architecture. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * s12z-dis.c: New file. * s12z.h: New file. include * elf/s12z.h: New header. ld * Makefile.am: Add support for s12z architecture. * configure.tgt: Likewise. * Makefile.in: Regenerate. * emulparams/m9s12zelf.sh: New file. * scripttempl/elfm9s12z.sc: New file. * testsuite/ld-discard/static.d: Expect to fail for the s12z target. * testsuite/ld-elf/endsym.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/pr14926.d: Skip for the s12z target. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-s12z: New directory. * testsuite/ld-s12z/opr-linking.d: New file. * testsuite/ld-s12z/opr-linking.s: New file. * testsuite/ld-s12z/relative-linking.d: New file. * testsuite/ld-s12z/relative-linking.s: New file. * testsuite/ld-s12z/z12s.exp: New file. gas * Makefile.am: Add support for s12z target. * Makefile.in: Regenerate. * NEWS: Mention the new support. * config/tc-s12z.c: New file. * config/tc-s12z.h: New file. * configure.tgt: Add s12z support. * doc/Makefile.am: Likewise. * doc/Makefile.in: Regenerate. * doc/all.texi: Add s12z documentation. * doc/as.textinfo: Likewise. * doc/c-s12z.texi: New file. * testsuite/gas/s12z: New directory. * testsuite/gas/s12z/abs.d: New file. * testsuite/gas/s12z/abs.s: New file. * testsuite/gas/s12z/adc-imm.d: New file. * testsuite/gas/s12z/adc-imm.s: New file. * testsuite/gas/s12z/adc-opr.d: New file. * testsuite/gas/s12z/adc-opr.s: New file. * testsuite/gas/s12z/add-imm.d: New file. * testsuite/gas/s12z/add-imm.s: New file. * testsuite/gas/s12z/add-opr.d: New file. * testsuite/gas/s12z/add-opr.s: New file. * testsuite/gas/s12z/and-imm.d: New file. * testsuite/gas/s12z/and-imm.s: New file. * testsuite/gas/s12z/and-opr.d: New file. * testsuite/gas/s12z/and-opr.s: New file. * testsuite/gas/s12z/and-or-cc.d: New file. * testsuite/gas/s12z/and-or-cc.s: New file. * testsuite/gas/s12z/bfext-special.d: New file. * testsuite/gas/s12z/bfext-special.s: New file. * testsuite/gas/s12z/bfext.d: New file. * testsuite/gas/s12z/bfext.s: New file. * testsuite/gas/s12z/bit-manip.d: New file. * testsuite/gas/s12z/bit-manip.s: New file. * testsuite/gas/s12z/bit.d: New file. * testsuite/gas/s12z/bit.s: New file. * testsuite/gas/s12z/bra-expression-defined.d: New file. * testsuite/gas/s12z/bra-expression-defined.s: New file. * testsuite/gas/s12z/bra-expression-undef.d: New file. * testsuite/gas/s12z/bra-expression-undef.s: New file. * testsuite/gas/s12z/bra.d: New file. * testsuite/gas/s12z/bra.s: New file. * testsuite/gas/s12z/brclr-symbols.d: New file. * testsuite/gas/s12z/brclr-symbols.s: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file. * testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file. * testsuite/gas/s12z/clb.d: New file. * testsuite/gas/s12z/clb.s: New file. * testsuite/gas/s12z/clr-opr.d: New file. * testsuite/gas/s12z/clr-opr.s: New file. * testsuite/gas/s12z/clr.d: New file. * testsuite/gas/s12z/clr.s: New file. * testsuite/gas/s12z/cmp-imm.d: New file. * testsuite/gas/s12z/cmp-imm.s: New file. * testsuite/gas/s12z/cmp-opr-inc.d: New file. * testsuite/gas/s12z/cmp-opr-inc.s: New file. * testsuite/gas/s12z/cmp-opr-rdirect.d: New file. * testsuite/gas/s12z/cmp-opr-rdirect.s: New file. * testsuite/gas/s12z/cmp-opr-reg.d: New file. * testsuite/gas/s12z/cmp-opr-reg.s: New file. * testsuite/gas/s12z/cmp-opr-rindirect.d: New file. * testsuite/gas/s12z/cmp-opr-rindirect.s: New file. * testsuite/gas/s12z/cmp-opr-sxe4.d: New file. * testsuite/gas/s12z/cmp-opr-sxe4.s: New file. * testsuite/gas/s12z/cmp-opr-xys.d: New file. * testsuite/gas/s12z/cmp-opr-xys.s: New file. * testsuite/gas/s12z/cmp-s-imm.d: New file. * testsuite/gas/s12z/cmp-s-imm.s: New file. * testsuite/gas/s12z/cmp-s-opr.d: New file. * testsuite/gas/s12z/cmp-s-opr.s: New file. * testsuite/gas/s12z/cmp-xy.d: New file. * testsuite/gas/s12z/cmp-xy.s: New file. * testsuite/gas/s12z/com-opr.d: New file. * testsuite/gas/s12z/com-opr.s: New file. * testsuite/gas/s12z/complex-shifts.d: New file. * testsuite/gas/s12z/complex-shifts.s: New file. * testsuite/gas/s12z/db-tb-cc-opr.d: New file. * testsuite/gas/s12z/db-tb-cc-opr.s: New file. * testsuite/gas/s12z/db-tb-cc-reg.d: New file. * testsuite/gas/s12z/db-tb-cc-reg.s: New file. * testsuite/gas/s12z/dbCC.d: New file. * testsuite/gas/s12z/dbCC.s: New file. * testsuite/gas/s12z/dec-opr.d: New file. * testsuite/gas/s12z/dec-opr.s: New file. * testsuite/gas/s12z/dec.d: New file. * testsuite/gas/s12z/dec.s: New file. * testsuite/gas/s12z/div.d: New file. * testsuite/gas/s12z/div.s: New file. * testsuite/gas/s12z/eor.d: New file. * testsuite/gas/s12z/eor.s: New file. * testsuite/gas/s12z/exg.d: New file. * testsuite/gas/s12z/exg.s: New file. * testsuite/gas/s12z/ext24-ld-xy.d: New file. * testsuite/gas/s12z/ext24-ld-xy.s: New file. * testsuite/gas/s12z/inc-opr.d: New file. * testsuite/gas/s12z/inc-opr.s: New file. * testsuite/gas/s12z/inc.d: New file. * testsuite/gas/s12z/inc.s: New file. * testsuite/gas/s12z/inh.d: New file. * testsuite/gas/s12z/inh.s: New file. * testsuite/gas/s12z/jmp.d: New file. * testsuite/gas/s12z/jmp.s: New file. * testsuite/gas/s12z/jsr.d: New file. * testsuite/gas/s12z/jsr.s: New file. * testsuite/gas/s12z/ld-imm-page2.d: New file. * testsuite/gas/s12z/ld-imm-page2.s: New file. * testsuite/gas/s12z/ld-imm.d: New file. * testsuite/gas/s12z/ld-imm.s: New file. * testsuite/gas/s12z/ld-immu18.d: New file. * testsuite/gas/s12z/ld-immu18.s: New file. * testsuite/gas/s12z/ld-large-direct.d: New file. * testsuite/gas/s12z/ld-large-direct.s: New file. * testsuite/gas/s12z/ld-opr.d: New file. * testsuite/gas/s12z/ld-opr.s: New file. * testsuite/gas/s12z/ld-s-opr.d: New file. * testsuite/gas/s12z/ld-s-opr.s: New file. * testsuite/gas/s12z/ld-small-direct.d: New file. * testsuite/gas/s12z/ld-small-direct.s: New file. * testsuite/gas/s12z/lea-immu18.d: New file. * testsuite/gas/s12z/lea-immu18.s: New file. * testsuite/gas/s12z/lea.d: New file. * testsuite/gas/s12z/lea.s: New file. * testsuite/gas/s12z/mac.d: New file. * testsuite/gas/s12z/mac.s: New file. * testsuite/gas/s12z/min-max.d: New file. * testsuite/gas/s12z/min-max.s: New file. * testsuite/gas/s12z/mod.d: New file. * testsuite/gas/s12z/mod.s: New file. * testsuite/gas/s12z/mov.d: New file. * testsuite/gas/s12z/mov.s: New file. * testsuite/gas/s12z/mul-imm.d: New file. * testsuite/gas/s12z/mul-imm.s: New file. * testsuite/gas/s12z/mul-opr-opr.d: New file. * testsuite/gas/s12z/mul-opr-opr.s: New file. * testsuite/gas/s12z/mul-opr.d: New file. * testsuite/gas/s12z/mul-opr.s: New file. * testsuite/gas/s12z/mul-reg.d: New file. * testsuite/gas/s12z/mul-reg.s: New file. * testsuite/gas/s12z/mul.d: New file. * testsuite/gas/s12z/mul.s: New file. * testsuite/gas/s12z/neg-opr.d: New file. * testsuite/gas/s12z/neg-opr.s: New file. * testsuite/gas/s12z/not-so-simple-shifts.d: New file. * testsuite/gas/s12z/not-so-simple-shifts.s: New file. * testsuite/gas/s12z/opr-18u.d: New file. * testsuite/gas/s12z/opr-18u.s: New file. * testsuite/gas/s12z/opr-expr.d: New file. * testsuite/gas/s12z/opr-expr.s: New file. * testsuite/gas/s12z/opr-ext-18.d: New file. * testsuite/gas/s12z/opr-ext-18.s: New file. * testsuite/gas/s12z/opr-idx-24-reg.d: New file. * testsuite/gas/s12z/opr-idx-24-reg.s: New file. * testsuite/gas/s12z/opr-idx3-reg.d: New file. * testsuite/gas/s12z/opr-idx3-reg.s: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.d: New file. * testsuite/gas/s12z/opr-idx3-xysp-24.s: New file. * testsuite/gas/s12z/opr-indirect-expr.d: New file. * testsuite/gas/s12z/opr-indirect-expr.s: New file. * testsuite/gas/s12z/opr-symbol.d: New file. * testsuite/gas/s12z/opr-symbol.s: New file. * testsuite/gas/s12z/or-imm.d: New file. * testsuite/gas/s12z/or-imm.s: New file. * testsuite/gas/s12z/or-opr.d: New file. * testsuite/gas/s12z/or-opr.s: New file. * testsuite/gas/s12z/p2-mul.d: New file. * testsuite/gas/s12z/p2-mul.s: New file. * testsuite/gas/s12z/page2-inh.d: New file. * testsuite/gas/s12z/page2-inh.s: New file. * testsuite/gas/s12z/psh-pul.d: New file. * testsuite/gas/s12z/psh-pul.s: New file. * testsuite/gas/s12z/qmul.d: New file. * testsuite/gas/s12z/qmul.s: New file. * testsuite/gas/s12z/rotate.d: New file. * testsuite/gas/s12z/rotate.s: New file. * testsuite/gas/s12z/s12z.exp: New file. * testsuite/gas/s12z/sat.d: New file. * testsuite/gas/s12z/sat.s: New file. * testsuite/gas/s12z/sbc-imm.d: New file. * testsuite/gas/s12z/sbc-imm.s: New file. * testsuite/gas/s12z/sbc-opr.d: New file. * testsuite/gas/s12z/sbc-opr.s: New file. * testsuite/gas/s12z/shift.d: New file. * testsuite/gas/s12z/shift.s: New file. * testsuite/gas/s12z/simple-shift.d: New file. * testsuite/gas/s12z/simple-shift.s: New file. * testsuite/gas/s12z/single-ops.d: New file. * testsuite/gas/s12z/single-ops.s: New file. * testsuite/gas/s12z/specd6.d: New file. * testsuite/gas/s12z/specd6.s: New file. * testsuite/gas/s12z/st-large-direct.d: New file. * testsuite/gas/s12z/st-large-direct.s: New file. * testsuite/gas/s12z/st-opr.d: New file. * testsuite/gas/s12z/st-opr.s: New file. * testsuite/gas/s12z/st-s-opr.d: New file. * testsuite/gas/s12z/st-s-opr.s: New file. * testsuite/gas/s12z/st-small-direct.d: New file. * testsuite/gas/s12z/st-small-direct.s: New file. * testsuite/gas/s12z/st-xy.d: New file. * testsuite/gas/s12z/st-xy.s: New file. * testsuite/gas/s12z/sub-imm.d: New file. * testsuite/gas/s12z/sub-imm.s: New file. * testsuite/gas/s12z/sub-opr.d: New file. * testsuite/gas/s12z/sub-opr.s: New file. * testsuite/gas/s12z/tfr.d: New file. * testsuite/gas/s12z/tfr.s: New file. * testsuite/gas/s12z/trap.d: New file. * testsuite/gas/s12z/trap.s: New file. binutils* readelf.c: Add support for s12z architecture. * testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z targets.
2018-05-16NDS32/GAS: Correct an `expr' global shadowing error for pre-4.8 GCCMaciej W. Rozycki1-2/+2
Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../gas/config/tc-nds32.c: In function 'md_assemble': .../gas/config/tc-nds32.c:5212: error: declaration of 'expr' shadows a global declaration .../gas/expr.h:180: error: shadowed declaration is here make[4]: *** [tc-nds32.o] Error 1 which for versions of GCC before 4.8 prevent support for NDS32 targets from being built. See also GCC PR c/53066. gas/ * tc-nds32.c (md_assemble): Rename `expr' local variable to `insn_expr'.
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on ↵Tamar Christina1-51/+81
AArch64 This patch adds a new platform option "notes" that can be used to indicate if disassembly notes should be placed in the disassembly as comments. These notes can contain information about a failing constraint such as reading from a write-only register. The disassembly will not be blocked because of this but -M notes will emit a comment saying that the operation is not allowed. For assembly this patch adds a new non-fatal status for errors. This is essentially a warning. The reason for not creating an actual warning type is that this causes the interaction between the ordering of warnings and errors to be problematic. Currently the error buffer is almost always filled because of the way operands are matched during assembly. An earlier template may have put an error there that would only be displayed if no other template matches or generates a higher priority error. But by definition a warning is lower priority than a warning, so the error (which is incorrect if another template matched) will supersede the warning. By treating warnings as errors and only later relaxing the severity this relationship keeps working and the existing reporting infrastructure can be re-used. binutils/ PR binutils/21446 * doc/binutils.texi (-M): Document AArch64 options. * NEWS: Document notes and warnings. gas/ PR binutils/21446 * config/tc-aarch64.c (print_operands): Indicate no notes. (output_operand_error_record): Support non-fatal errors. (output_operand_error_report, warn_unpredictable_ldst, md_assemble): Likewise. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_operand_error): Add non_fatal. (aarch64_print_operand): Support notes. opcodes/ PR binutils/21446 * aarch64-dis.c (no_notes: New. (parse_aarch64_dis_option): Support notes. (aarch64_decode_insn, print_operands): Likewise. (print_aarch64_disassembler_options): Document notes. * aarch64-opc.c (aarch64_print_operand): Support notes.
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and ↵Tamar Christina1-10/+19
report why. This patch if the first patch in a series to add the ability to add constraints to system registers that an instruction must adhere to in order for the register to be usable with that instruction. These constraints can also be used to disambiguate between registers with the same encoding during disassembly. This patch adds a new flags entry in the sysreg structures and ensures it is filled in and read out during assembly/disassembly. It also adds the ability for the assemble and disassemble functions to be able to gracefully fail and re-use the existing error reporting infrastructure. The return type of these functions are changed to a boolean to denote success or failure and the error structure is passed around to them. This requires aarch64-gen changes so a lot of the changes here are just mechanical. gas/ PR binutils/21446 * config/tc-aarch64.c (parse_sys_reg): Return register flags. (parse_operands): Fill in register flags. gdb/ PR binutils/21446 * aarch64-tdep.c (aarch64_analyze_prologue, aarch64_software_single_step, aarch64_displaced_step_copy_insn): Indicate not interested in errors. include/ PR binutils/21446 * opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct. (aarch64_decode_insn): Accept error struct. opcodes/ PR binutils/21446 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean and take error struct. * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, aarch64_ins_reglist, aarch64_ins_ldst_reglist, aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, aarch64_ext_reglist, aarch64_ext_ldst_reglist, aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. (determine_disassembling_preference, aarch64_decode_insn, print_insn_aarch64_word, print_insn_data): Take errors struct. (print_insn_aarch64): Use errors. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-gen.c (print_operand_inserter): Use errors and change type to boolean in aarch64_insert_operan. (print_operand_extractor): Likewise. * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-12score gcc-8 warning fixesAlan Modra1-70/+66
Rather than just silencing the gcc-8 warnings, I decided to rewrite the buffer handling in the two functions where gcc was warning. The rest of the file could do with the same treatment. * config/tc-score.c (s3_do_macro_bcmp): Don't use fixed size buffers. (s3_do_macro_bcmpz): Likewise.
2018-05-10Allow integer immediates for AArch64 fmov instructions.Tamar Christina1-21/+4
This patch makes it possible to use an integer immediate with the fmov instructions allowing you to simply write fmov d0, #2 instead of needing fmov d0, #2.0. The parse double function already know to deal with this so we just need to list the restriction put in place in parser. The is considered a QoL improvement for hand assembly writers and allows more code portability between assembler. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Remove restrictions. * testsuite/gas/aarch64/diagnostic.s: Move fmov int test to.. * testsuite/gas/aarch64/fpmov.s: Here. * testsuite/gas/aarch64/fpmov.d: Update results with fmov. * testsuite/gas/aarch64/diagnostic.l: Remove fmov values. * testsuite/gas/aarch64/sve-invalid.s: Update test files. * testsuite/gas/aarch64/sve-invalid.l: Likewise
2018-05-10Allow integer immediate for VFP vmov instructions.Tamar Christina1-0/+8
This patch fixes the case where you want to use an integer value the floating point immediate to a VFP vmov instruction such as vmovmi.f32 s27, #11. If the immediate is not a float we convert it and copy it's representation into the imm field and then carry on validating as if we originally entered a floating point immediate. The is considered a QoL improvement for hand assembly writers and allows more code portability between assembler. gas/ * gas/config/tc-arm.c (do_neon_mov): Allow integer literal for float immediate. * testsuite/gas/arm/vfp-mov-enc.s: New. * testsuite/gas/arm/vfp-mov-enc.d: New.
2018-05-09gas: xtensa: fix literal movementMax Filippov1-21/+30
Not all literals need to be moved in the presence of --text-section-literals or --auto-litpools, but only those created by .literal pseudo op or generated as a result of relaxation. Attempts to move other literals may result in abnormal termination of the assembler due to the following assertion failure: Internal error in xg_find_litpool at gas/config/tc-xtensa.c:11209. The same assertion may also be triggered by attempting to assign literal pools to literals in .init and .fini sections; don't try to do that. gas/ 2018-05-09 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_is_init_fini): New function. (xtensa_move_literals): Only attempt to assign literal pool to literals with tc_frag_data.is_literal mark and not in .init or .fini sections. Join nested 'if' conditions to simplify function structure. (xtensa_switch_to_non_abs_literal_fragment): Use xtensa_is_init_fini to test for .init/.fini sections. * testsuite/gas/xtensa/all.exp (auto-litpools-3) (auto-litpools-4, text-section-literals-1): New tests. * testsuite/gas/xtensa/auto-litpools-3.d: New test results. * testsuite/gas/xtensa/auto-litpools-3.s: New test source. * testsuite/gas/xtensa/auto-litpools-4.d: New test results. * testsuite/gas/xtensa/auto-litpools-4.s: New test source. * testsuite/gas/xtensa/text-section-literals-1.d: New test results. * testsuite/gas/xtensa/text-section-literals-1.s: New test source.
2018-05-09Fix binary compatibility between GCC and the TI compiler for the PRU target.Dimitar Dimitrov1-5/+13
My original implementation for LDI32 pseudo does not conform to the TI ABI. I wrongly documented my TI PRU ELF object files inspection, which got propagated into my binutils implementation. Issue was exposed when running the GCC ABI testsuite against TI toolchain. According to TI ABI, LDI32 must use first LDI instruction to load the MSB 16bits, and second LDI instruction for the LSB 16bits. This patch will break binary compatibility with previously released binutils versions for PRU. Still, I think it is better to fix binutils to conform to the chip vendor ABI. bfd * elf32-pru.c (pru_elf32_do_ldi32_relocate): Make LDI32 relocation conformant to TI ABI. (pru_elf32_relax_section): Likewise. (pru_elf_relax_delete_bytes): Fix offsets for new LDI32 code. * elf32-pru.c (pru_elf32_do_ldi32_relocate): Ignore addend. (pru_elf32_pmem_relocate): Trap - should not get here. (pru_elf32_relocate_section): Add support for REL relocations. (elf_info_to_howto_rel): Enable REL. (elf_backend_may_use_rel_p): Likewise. (elf_backend_may_use_rela_p): Likewise. (elf_backend_default_use_rela_p): Likewise. gas * config/tc-pru.c (md_apply_fix): Make LDI32 relocation conformant to TI ABI. (pru_assemble_arg_i): Likewise. (output_insn_ldi32): Likewise. * testsuite/gas/pru/ldi.d: Update test for the now fixed LDI32. * gas/config/tc-pru.c (pru_assemble_arg_b): Check imm8 operand range. * gas/testsuite/gas/pru/illegal2.l: New test. * gas/testsuite/gas/pru/illegal2.s: New test. * gas/testsuite/gas/pru/pru.exp: Register new illegal2 test. ld * scripttempl/pru.sc: Add LD sections to allow linking TI toolchain object files. * scripttempl/pru.sc: Switch to init_array. * testsuite/ld-pru/ldi32.d: Update LDI32 test to conform to TI ABI. * testsuite/ld-pru/norelax_ldi32-data.d: Likewise. * testsuite/ld-pru/norelax_ldi32-dis.d: Likewise. * testsuite/ld-pru/relax_ldi32-data.d: Likewise. * testsuite/ld-pru/relax_ldi32-dis.d: Likewise.
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+41
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New file. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (Gva): New. (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). (OP_G): Handle va_mode. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-3/+7
This patch replaces AddrPrefixOp0 with AddrPrefixOpReg to indicate that the size of register operand is controlled by the address size prefix. This will be used by Intel MOVDIRI and MOVDIR64B instructions later. gas/ * config/tc-i386.c (process_suffix): Check addrprefixopreg instead of addrprefixop0. opcodes/ * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with AddrPrefixOpReg. * i386-opc.h (AddrPrefixOp0): Renamed to ... (AddrPrefixOpReg): This. (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner1-38/+26
include/ * opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. opcodes/ * ppc-opc.c (powerpc_num_opcodes): Likewise. (vle_num_opcodes): Likewise. (spe2_num_opcodes): Likewise. * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite initialization loop. (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize only once. gas/ * config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code to dump the entire opcode table. (ppc_setup_opcodes) <spe2_opcodes>: Likewise. (ppc_setup_opcodes) <vle_opcodes>: Likewise. Fix calculation of opcode index.
2018-05-04-Wstringop-truncation warningsAlan Modra2-9/+11
This patch is aimed at silencing gcc8 -Wstringop-truncation warnings. Unfortunately adding __attribute__ ((__nonstring)) doesn't work in a number of the places patched here, (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643) so if you have recent glibc headers installed you'll need to configure binutils with --disable-werror to compile using gcc8 or gcc9. include/ * ansidecl.h: Import from gcc. * coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING to s_name. (struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name. bfd/ * elf-linux-core.h (struct elf_external_linux_prpsinfo32_ugid32), (struct elf_external_linux_prpsinfo32_ugid16), (struct elf_external_linux_prpsinfo64_ugid32), (struct elf_external_linux_prpsinfo64_ugid16): Add ATTRIBUTE_NONSTRING to pr_fname and pr_psargs fields. Remove GCC diagnostic pragmas. Move comment to.. * elf.c (elfcore_write_prpsinfo): ..here. Indent nested preprocessor directives. * elf32-arm.c (elf32_arm_nabi_write_core_note): Add ATTRIBUTE_NONSTRING to data. * elf32-ppc.c (ppc_elf_write_core_note): Likewise. * elf32-s390.c (elf_s390_write_core_note): Likewise. * elf64-s390.c (elf_s390_write_core_note): Likewise. * elfxx-aarch64.c (_bfd_aarch64_elf_write_core_note): Likewise. * elf64-x86-64.c (elf_x86_64_write_core_note): Add GCC diagnostic pragmas. * peXXigen.c (_bfd_XXi_swap_scnhdr_out): Use strnlen to avoid false positive gcc-8 warning. gas/ * config/obj-evax.c (shorten_identifier): Use memcpy in place of strncpy. * config/obj-macho.c (obj_mach_o_make_or_get_sect): Ensure segname and sectname fields are NUL terminated.
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-40/+0
This reverts commit a914a7c95895161c99533d5919b8504b37ea54a0.
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+40
gas/ * config/tc-i386.c (cpu_arch): Add .movdir, .movdir64b. (cpu_noarch): Likewise. (process_suffix): Add check for register size. * doc/c-i386.texi: Document movdiri, movdir64b. * testsuite/gas/i386/i386.exp: Run MOVDIR{I,64B} tests. * testsuite/gas/i386/movdir-intel.d: New test. * testsuite/gas/i386/movdir.d: Likewise. * testsuite/gas/i386/movdir.s: Likewise. * testsuite/gas/i386/movdir64b-reg.s: Likewise. * testsuite/gas/i386/movdir64b-reg.l: Likewise. * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise. * testsuite/gas/i386/x86-64-movdir.d: Likewise. * testsuite/gas/i386/x86-64-movdir.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.s: Likewise. * testsuite/gas/i386/x86-64-movdir64b-reg.l: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38F8, PREFIX_0F38F9. (prefix_table): New instructions (see prefix above). Add Gva macro and handling in OP_G. * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, CPU_MOVDIR64B_FLAGS. (cpu_flags): Likewise. (opcode_modifiers): Add AddrPrefixOpReg. (i386_opcode_modifier): Likewise. * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. (i386_cpu_flags): Likewise. * i386-opc.tbl: Add movidir{i,64b}. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-17/+54
There's little point carrying up to three templates per insn flavor when the sole difference is operand size and the dependency on AVX512VL being enabled. Instead the need for AVX512VL can be derived from an operand allowing for ZMMword as well as one or both or XMMword and YMMword (irrespective of whether this is a register or memory operand). Without further abstraction to deal with the different Disp8MemShift values between the templates, only a limited set (mostly ones only allowing for non-memory operands) can be folded, which is being done here. Also drop IgnoreSize wherever possible from anything that's being touched anyway.
generated by cgit v1.1 at 2025-02-07 13:21:43 +0000