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authorRamana Radhakrishnan <ramana.radhakrishnan@arm.com>2018-06-29 13:06:05 +0100
committerRamana Radhakrishnan <ramana.radhakrishnan@arm.com>2018-06-29 13:06:05 +0100
commitee9439704485a1e9413470fe2634b164fa31644f (patch)
treeaa4dfee972fab72f9fa0ab1732a246bc39dd388f /gas/config
parent369c9167d47e69aad2e260cc1db17f8c894c138b (diff)
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[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.
A recent case in golang highlighted that gas wasn't warning on these unpredictable cases in the architecture. Fixed thusly. I need to audit gcc to make sure we have early clobbers on the patterns but that's a separate patch. Tested aarch64-none-elf and gas Ok ? Ramana 2018-06-29 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Add unpredictable cases for ldxp, stlxrb, stlxrh, stlxr. * testsuite/gas/aarch64/diagnostic.s: New tests. * testsuite/gas/aarch64/diagnostic.l: Adjust.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-aarch64.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f8b2152..3198596 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6705,6 +6705,22 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
&& opnds[0].reg.regno == opnds[1].reg.regno)
as_warn (_("unpredictable load of register pair -- `%s'"), str);
break;
+
+ case ldstexcl:
+ /* It is unpredictable if the destination and status registers are the
+ same. */
+ if ((aarch64_get_operand_class (opnds[0].type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && (aarch64_get_operand_class (opnds[1].type)
+ == AARCH64_OPND_CLASS_INT_REG)
+ && (opnds[0].reg.regno == opnds[1].reg.regno
+ || opnds[0].reg.regno == opnds[2].reg.regno))
+ as_warn (_("unpredictable: identical transfer and status registers"
+ " --`%s'"),
+ str);
+
+ break;
+
default:
break;
}