riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-06-11	RISC-V: Update the riscv_opts.[rvc\|rve] in the riscv_set_arch.	Nelson Chu	1	-10/+8
2021-05-26	RISC-V: Allow to link the objects with unknown prefixed extensions.	Nelson Chu	1	-0/+1
2021-05-24	RISC-V: PR25212, Report errors for invalid march and mabi combinations.	Nelson Chu	1	-0/+18
2021-04-16	RISC-V: PR27436, make operand C> work the same as >.	Nelson Chu	1	-3/+2
2021-03-31	Use bool in gas	Alan Modra	1	-114/+114
2021-03-16	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions	Kuan-Lin Chen	1	-0/+13
2021-02-19	Fix compile time warnings when building riscv assembler.	Nick Clifton	1	-3/+3
2021-02-19	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.	Nelson Chu	1	-89/+92
2021-02-18	RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.	Nelson Chu	1	-24/+113
2021-02-04	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.	Nelson Chu	1	-10/+0
2021-01-15	RISC-V: Indent and GNU coding standards tidy, also aligned the code.	Nelson Chu	1	-56/+52
2021-01-15	RISC-V: Error and warning messages tidy.	Nelson Chu	1	-58/+66
2021-01-15	RISC-V: Comments tidy and improvement.	Nelson Chu	1	-161/+130
2021-01-07	RISC-V: Add pause hint instruction.	Philipp Tomsich	1	-0/+2
2021-01-07	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).	Claire Xenia Wolf	1	-1/+13
2021-01-06	RISC-V: Implement support for big endian targets.	Marcus Comstedt	1	-7/+25
2021-01-01	PR27116, Spelling errors found by Debian style checker	Alan Modra	1	-2/+2
2021-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2020-12-10	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	Nelson Chu	1	-0/+33
2020-12-10	RISC-V: Control fence.i and csr instructions by zifencei and zicsr.	Nelson Chu	1	-4/+10
2020-12-01	RISC-V: Support to add implicit extensions.	Nelson Chu	1	-1/+3
2020-12-01	RISC-V: Improve the version parsing for arch string.	Nelson Chu	1	-13/+10
2020-11-09	RISC-V: Update ABI to the elf_flags after parsing elf attributes.	Nelson Chu	1	-47/+55
2020-09-24	RISC-V: Error for relaxable branch in absolute section.	Jim Wilson	1	-0/+7
2020-09-21	PR26569, R_RISCV_RVC_JUMP results in buffer overflow	Alan Modra	1	-3/+7
2020-08-31	PR26493 UBSAN: tc-riscv.c left shift negative and not representable	Alan Modra	1	-17/+17
2020-08-23	PR26513, 629310abec breaks assembling PowerPC Linux kernels	Alan Modra	1	-5/+9
2020-08-21	Rearrange symbol_create parameters	Alan Modra	1	-2/+2
2020-08-20	Port gas/config/* to str_htab.	Martin Liska	1	-66/+27
2020-07-06	Fix spelling mistakes in some of the binutils sub-directories.	Nick Clifton	1	-1/+1
2020-06-30	RISC-V: Support debug and float CSR as the unprivileged ones.	Nelson Chu	1	-29/+24
2020-06-23	RISC-V: Generate ELF priv attributes if priv instruction are explicited used.	Nelson Chu	1	-6/+42
2020-06-22	RISC-V: Report warning when linking the objects with different priv specs.	Nelson Chu	1	-27/+9
2020-06-05	RISC-V: Don't generate the ELF privilege attributes when no CSR are used.	Nelson Chu	1	-0/+9
2020-05-27	RISC-V: Fix missing initialization of riscv_csr_extra structs	Simon Cook	1	-0/+1
2020-05-24	RISC-V: Gas inserts cfa relocs in wrong section.	Jim Wilson	1	-1/+12
2020-05-20	[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...	Nelson Chu	1	-89/+425
2020-03-04	RISC-V: Support assembler modifier %got_pcrel_hi.	Nelson Chu	1	-0/+1
2020-02-26	Indent labels	Alan Modra	1	-9/+9
2020-02-20	RISC-V: Support the read-only CSR checking.	Nelson Chu	1	-0/+69
2020-02-20	RISC-V: Disable the CSR checking by default.	Nelson Chu	1	-1/+21
2020-02-20	RISC-V: Support the ISA-dependent CSR checking.	Nelson Chu	1	-7/+92
2020-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2019-12-12	gas signed overflow fixes	Alan Modra	1	-2/+2
2019-11-28	gas/riscv: Produce version 3 DWARF CIE by default	Andrew Burgess	1	-0/+6
2019-11-28	binutils/gas/riscv: Add DWARF register numbers for CSRs	Andrew Burgess	1	-0/+4
2019-11-28	gas/riscv: Remove unneeded structure	Andrew Burgess	1	-7/+1
2019-09-17	RISC-V: Gate opcode tables by enum rather than string.	Jim Wilson	1	-7/+20
2019-08-25	RISC-V: Improve li expansion for better code density.	Kito Cheng	1	-5/+33
2019-05-30	RISC-V: Fix lui argument parsing.	Jim Wilson	1	-5/+4