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path: root/gas/config/tc-i386.c
AgeCommit message (Expand)AuthorFilesLines
2019-09-21tc-i386.c gcc10 warning fixAlan Modra1-2/+2
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich1-2/+2
2019-09-19bfd_section_* macrosAlan Modra1-5/+4
2019-07-17x86: replace "anymem" checks where possibleJan Beulich1-8/+14
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-12/+18
2019-07-16x86: fold SReg{2,3}Jan Beulich1-20/+20
2019-07-04x86: correct "-Q" option handlingJan Beulich1-1/+3
2019-07-01x86: drop Vec_Imm4Jan Beulich1-25/+11
2019-07-01x86: limit ImmExt abuseJan Beulich1-13/+10
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+23
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+43
2019-07-01x86: StaticRounding implies SAEJan Beulich1-6/+3
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-11/+19
2019-07-01x86: use encoding_length() also elsewhereJan Beulich1-32/+4
2019-07-01x86: warn about insns exceeding the 15-byte limitJan Beulich1-0/+32
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-2/+2
2019-06-25x86: correct / adjust debug printingJan Beulich1-9/+10
2019-06-25x86: don't open code is_any_vex_encoding()Jan Beulich1-3/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+5
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu1-0/+3
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+3
2019-05-14A series of fixes to addres problems detected by compiling the assembler with...Nick Clifton1-1/+10
2019-05-02i386: Issue a warning to IRET without suffix for .code16gccH.J. Lu1-7/+13
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu1-0/+6
2019-04-10Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86Rainer Orth1-0/+6
2019-04-08x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16H.J. Lu1-0/+2
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+3
2019-03-19x86: Correct EVEX vector load/store optimizationH.J. Lu1-13/+30
2019-03-19x86: Correct EVEX to 128-bit EVEX optimizationH.J. Lu1-9/+2
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-0/+50
2019-03-18x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEXH.J. Lu1-11/+11
2019-03-17x86: Set optimize to INT_MAX for -OsH.J. Lu1-1/+12
2019-03-17x86: Correctly optimize EVEX to 128-bit VEX/EVEXH.J. Lu1-5/+13
2019-03-15Fix a potential illegal memory access whilt parsing an x86 insn.Li Hao1-32/+36
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-19x86: Properly handle PLT expression in directiveH.J. Lu1-3/+14
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu1-1/+0
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-2/+2
2018-11-05x86: Disable GOT relaxation with data prefixH.J. Lu1-6/+7
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-6/+6
2018-09-17x86: Add -mvexwig=[0|1] option to assemblerH.J. Lu1-11/+34
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-17/+14
2018-09-14x86: fold CRC32 templatesJan Beulich1-11/+7
2018-09-13x86: Swap destination/source to encode VEX only if possibleH.J. Lu1-3/+4
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-19/+22
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-9/+25
2018-09-13x86: improve operand reversalJan Beulich1-7/+33
2018-09-13x86: add code comment on deprecated status of pseudo-suffixesJan Beulich1-1/+2
2018-08-31x86: Extend assembler to generate GNU property notesH.J. Lu1-12/+291
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-0/+6
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