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path: root/gas/config/tc-i386.c
AgeCommit message (Expand)AuthorFilesLines
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich1-3/+9
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-5/+1
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-2/+2
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-7/+1
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-1/+1
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-1/+2
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich1-5/+17
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu1-1/+2
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu1-0/+2
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-0/+20
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-40/+19
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-7/+2
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu1-17/+58
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu1-44/+114
2017-03-06Add support for Intel CET instructionsH.J. Lu1-0/+2
2017-01-23Fix spelling mistakes and typos in the GAS sources.Nick Clifton1-8/+8
2017-01-20Fix potential array overrun in x86 assembler.Nick Clifton1-1/+1
2017-01-12Enable Intel AVX512_VPOPCNTDQ instructionsIgor Tsimbalist1-0/+3
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-11-02Enable Intel AVX512_4VNNIW instructionsIgor Tsimbalist1-0/+3
2016-11-02Enable Intel AVX512_4FMAPS instructionsIgor Tsimbalist1-0/+22
2016-10-21X86: Remove pcommit instructionH.J. Lu1-2/+0
2016-10-06-Wimplicit-fallthrough warning fixesAlan Modra1-0/+35
2016-09-08Allow PROCESSOR_IAMCU for Intel MCUH.J. Lu1-1/+1
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu1-21/+2
2016-08-24X86: Add ptwrite instructionH.J. Lu1-0/+2
2016-07-05x86: fix register check in check_qword_reg()Jan Beulich1-1/+1
2016-07-01x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich1-0/+17
2016-07-01x86/MPX: fix address size handlingJan Beulich1-4/+9
2016-07-01x86/Intel: don't accept bogus instructionsJan Beulich1-5/+27
2016-07-01x86/Intel: fix operand checking for MOVSDJan Beulich1-1/+53
2016-05-29Add .noavx512XX directives to x86 assemblerH.J. Lu1-0/+9
2016-05-27Update x86 CPU_XXX_FLAGS handlingH.J. Lu1-5/+20
2016-05-27Replace CpuAMD64/CpuIntel64 with AMD64/Intel64H.J. Lu1-7/+4
2016-05-27Correct CpuMax in i386-opc.hH.J. Lu1-8/+11
2016-05-27Don't clear cpu64 nor cpuno64H.J. Lu1-2/+0
2016-05-25Require another match for AVX512VLH.J. Lu1-0/+15
2016-05-25Reimplement .no87/.nommx/.nosse/.noavx directivesH.J. Lu1-163/+253
2016-05-20Preserve addend for R_386_GOT32 and R_X86_64_GOT32H.J. Lu1-5/+0
2016-05-13use XNEW and related macros moreTrevor Saunders1-7/+7
2016-05-10Enable Intel RDPID instruction.Alexander Fomin1-0/+2
2016-04-04Don't use vec_disp8 encoding with the .d32 suffixH.J. Lu1-1/+3
2016-04-01Constify moreAlan Modra1-2/+2
2016-03-29make md_parse_option () take a const char *Trevor Saunders1-1/+1
2016-03-20tc-i386.c: store encoded instructions in unsigned char[]Trevor Saunders1-33/+33
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