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AgeCommit message (Expand)AuthorFilesLines
2017-11-24x86: reject further invalid AVX-512 masking constructsJan Beulich1-3/+9
2017-11-23Fix build error with --enable-targets=all.Jim Wilson1-0/+3
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich1-5/+1
2017-11-23x86-64: always use unsigned 32-bit reloc for 32-bit addressing w/o base regJan Beulich1-2/+2
2017-11-23x86: drop redundant VSIB handling codeJan Beulich1-7/+1
2017-11-23x86/Intel: don't report multiple errors for a single insn operandJan Beulich1-2/+4
2017-11-22Riscv ld-elf/stab failure and fake label cleanup.Jim Wilson1-0/+3
2017-11-22[GAS/ARM] Clarify relation between reg_expected_msgs and arm_reg_typeThomas Preud'homme1-23/+26
2017-11-21xtensa error messageAlan Modra1-16/+6
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+3
2017-11-16ix86/Intel: don't require memory operand size specifier for PTWRITEJan Beulich1-1/+1
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-1/+8
2017-11-13gas/arm64: don't emit stack pointer symbol table entriesJan Beulich1-5/+6
2017-11-13x86: don't default variable shift count insns to 8-bit operand sizeJan Beulich1-1/+2
2017-11-13x86/Intel: don't mistake riz/eiz as base registerJan Beulich1-1/+3
2017-11-13x86-64/Intel: issue diagnostic for out of range displacementJan Beulich2-29/+42
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina1-0/+8
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options...Tamar Christina1-0/+6
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio...Nick Clifton1-1/+7
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang1-3/+165
2017-11-08xtensa message pluralizationAlan Modra1-4/+14
2017-11-07RISC-V: Fix riscv g++ testsuite EH failures.Jim Wilson1-0/+15
2017-11-07RISC-V: Add satp as an alias for sptbrPalmer Dabbelt1-0/+1
2017-11-07This patch similarly to the AArch64 one enables Dot Product support by defaul...Tamar Christina1-68/+81
2017-11-07gas and ld pluralization fixesAlan Modra10-17/+52
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar1-0/+3
2017-11-01FT32B is a new FT32 family member. It has a code compression scheme, which re...James Bowman2-115/+303
2017-11-01[ARM] Fix Coprocessor instructions availabilityThomas Preud'homme1-1/+1
2017-10-26x86: Check invalid XMM register in AVX512 gathersH.J. Lu1-1/+2
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra1-10/+10
2017-10-24i386: Support .code64 directive only with 64-bit bfdH.J. Lu1-0/+2
2017-10-23RISC-V: Don't emit 2-byte NOPs if the C extension is disabledPalmer Dabbelt1-1/+1
2017-10-23MIPS: Preset EF_MIPS_ABI2 with n32 ELF objectsMaciej W. Rozycki1-3/+1
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-0/+20
2017-10-20Improve handling of REPT pseudo op with a negative count.Nick Clifton2-2/+2
2017-10-19RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*Palmer Dabbelt1-1/+4
2017-10-19Fix the AVR assembler so that it will correctly issue warnings about skipped ...Nick Clifton2-4/+15
2017-10-16Fix segfault processing nios2 pseudo-instructions with too few arguments.Sandra Loosemore1-30/+54
2017-10-12FT32: support for FT32B processor - part 1James Bowman1-3/+14
2017-10-05Fix the MSP430 assembler so that it detects and reports extraneous text at th...Nick Clifton1-27/+83
2017-10-05PR21167, relocation sections not included in groupsAlan Modra1-26/+39
2017-09-22PR gas/21762: MIPS: Fix .stabs directive marking labels as MIPS16James Cowgill1-0/+1
2017-09-21Reduce excessive .eh_frame alignment for powerpcAlan Modra1-0/+1
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-40/+19
2017-09-07RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC codePalmer Dabbelt1-17/+8
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