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R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on
@notoc cals from non-power10 code in the rare case that using such a
construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas
rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch
instruction if power10 instructions are not enabled at that point.
The new relocation tells the linker to not use power10 instructions on
any stub emitted for that branch, unless overridden by
--power10-stubs=yes.
The current linker heuristic of only generating power10 instructions
for stubs if power10-only relocations are detected, continues to be
used.
include/
* elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc.
(ppc64_elf_reloc_type_lookup): Handle it.
(enum ppc_stub_type): Delete.
(enum ppc_stub_main_type, ppc_stub_sub_type): New.
(struct ppc_stub_type): New.
(struct ppc_stub_hash_entry): Use the above new type.
(struct ppc_link_hash_table): Update stub_count.
(is_branch_reloc, ppc64_elf_check_relocs),
(toc_adjusting_stub_needed): Handle new reloc.
(stub_hash_newfunc, select_alt_stub, ppc_merge_stub),
(ppc_type_of_stub, plt_stub_size, build_plt_stub),
(build_tls_get_addr_head, build_tls_get_addr_tail),
(ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs),
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new
reloc. Modify stub handling to suit new scheme.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled
return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc.
(fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle
BFD_RELOC_PPC64_REL24_P9NOTOC.
ld/
* testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
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For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string. This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed. Consider the following case,
nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add a0, a0, a0
.byte 0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 nop
8: 00000013 nop
c: 00000013 nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong. After
applying this patch, I get the following result,
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 .2byte 0x1
8: 00000013 nop
c: 00000013 nop
For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.
However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes. We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized. Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.
This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains. Also, tested by --enable-targets=all and can build
riscv-gdb successfully.
bfd/
* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
codes for riscv_parse_subset_t setting.
* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
(riscv_multi_subset_supports): Likewise.
* elfxx-riscv.h: Added extern for riscv_subset_supports and
riscv_multi_subset_supports.
gas/
* config/tc-riscv.c (riscv_subset_supports): Moved to
bfd/elfxx-riscv.c.
(riscv_multi_subset_supports): Likewise.
(riscv_rps_as): Defined for architectrue parser.
(riscv_set_arch): Updated.
(riscv_set_abi_by_arch): Likewise.
(riscv_csr_address): Likewise.
(reg_lookup_internal): Likewise.
(riscv_ip): Likewise.
(s_riscv_option): Updated.
* testsuite/gas/riscv/mapping-04b.d: Updated.
* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
* riscv-dis.c: Include elfxx-riscv.h since we need the
architecture parser. Also removed the cpu-riscv.h, it
is already included in elfxx-riscv.h.
(default_isa_spec): Defined since the parser need this
to set the default architecture string.
(xlen): Moved out from riscv_disassemble_insn as a global
variable, it is more convenient to initialize riscv_rps_dis.
(riscv_subsets): Defined to recoed the supported
extensions.
(riscv_rps_dis): Defined for architectrue parser.
(riscv_disassemble_insn): Call riscv_multi_subset_supports
to make sure if the instructions are valid or not.
(print_insn_riscv): Initialize the riscv_subsets by parsing
the elf architectrue attribute. Otherwise, set the default
architectrue string to rv64gc.
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This patch is adding support for Cortex-A710 CPU in Arm.
bfd/
* cpu-arm.c (processors): Add cortex-a710.
gas/
* NEWS: Update docs.
* config/tc-arm.c (arm_cpus): Add cortex-a710 to -mcpu.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/cpu-cortex-a710.d: New test.
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On XCOFF, ".file" pseudo-op allows 3 extras parameters to provide
additional information to AIX linker, or its debugger. These are
stored in auxiliary entries of the C_FILE symbol.
bfd/
PR 28447
* coffcode.h (combined_entry_type): Add extrap field.
(coff_bigobj_swap_aux_in): Adjust names of x_file fields.
(coff_bigobj_swap_aux_out): Likewise.
* coffgen.c (coff_write_auxent_fname): New function.
(coff_fix_symbol_name): Write x_file using
coff_write_auxent_fname.
(coff_write_symbol): Likewise.
(coff_write_symbols): Add C_FILE auxiliary entries to
string table if needed.
(coff_get_normalized_symtab): Adjust names of x_file fields.
Normalize C_FILE auxiliary entries.
(coff_print_symbol): Print C_FILE auxiliary entries.
* coff-rs6000.c (_bfd_xcoff_swap_aux_in): Adjust names of
x_file fields.
(_bfd_xcoff_swap_aux_out): Likewise.
* coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Likewise.
(_bfd_xcoff64_swap_aux_out): Likewise.
* cofflink.c (_bfd_coff_final_link): Likewise.
(_bfd_coff_link_input_bfd): Likewise.
* coffswap.h (coff_swap_aux_in): Likewise.
* peXXigen.c (_bfd_XXi_swap_aux_in): Likewise.
(_bfd_XXi_swap_aux_out): Likewise.
* xcofflink.c (xcoff_link_input_bfd): Likewise.
* libcoff.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_file): New function.
* config/tc-ppc.h (OBJ_COFF_MAX_AUXENTRIES): Change to 4.
* testsuite/gas/ppc/aix.exp: Add tests.
* testsuite/gas/ppc/xcoff-file-32.d: New test.
* testsuite/gas/ppc/xcoff-file-64.d: New test.
* testsuite/gas/ppc/xcoff-file.s: New test.
include/
* coff/internal.h (union internal_auxent): Change x_file to be a
struct instead of a union. Add x_ftype field.
* coff/rs6000.h (union external_auxent): Add x_resv field.
* coff/xcoff.h (XFT_FN): New define.
(XFT_CT): Likewise.
(XFT_CV): Likewise.
(XFT_CD): Likewise.
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This one was logically wrong too. If file_ptr was 64 bits, then -1U
is extended to 0x00000000ffffffff, probably not what was intended
here.
* mach-o.c (FILE_ALIGN): Correct expression.
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readelf -r dumping support is not added in this patch.
include/
* elf/common.h: Add SHT_RELR, DT_RELR{,SZ,ENT}
bfd/
* elf.c (_bfd_elf_print_private_bfd_data): Add DT_RELR{,SZ,ENT}.
binutils/
* readelf.c (get_dynamic_type): Add DT_RELR{,SZ,ENT}.
(get_section_type_name): Add SHT_RELR.
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Investigating the PR28530 testcase, which has a fuzzed compression
header with an enormous size, I noticed that decompress_contents is
broken when the size doesn't fit in strm.avail_out. It wouldn't be
too hard to support larger sizes (patches welcome!) but for now just
stop decompress_contents from returning rubbish.
PR 28530
* compress.c (decompress_contents): Fail when uncompressed_size
is too big.
(bfd_init_section_decompress_status): Likewise.
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* vms-alpha.c (evax_bfd_print_desc): Sanity check buffer access.
(evax_bfd_print_valspec, evax_bfd_print_typspec): Likewise.
(evax_bfd_print_dst): Likewise.
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This reverts commit e0f7ea91436dd308a094c4c101fd4169e8245a91.
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Always check sections with the corrupt size for non-MMO files. Skip MMO
files for compress_status == COMPRESS_SECTION_NONE since MMO has special
handling for COMPRESS_SECTION_NONE.
PR binutils/28530
* compress.c (bfd_get_full_section_contents): Always check
sections with the corrupt size.
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Add/Remove the rvc extension to/from the riscv_subsets once the
.option rvc/norvc is set. So that we don't need to always check
the riscv_opts.rvc in the riscv_subset_supports, just call the
riscv_lookup_subset to search the subset list is enough.
Besides, we will need to dump the instructions according to the
elf architecture attributes. That means the dis-assembler needs
to parse the architecture string from the elf attribute before
dumping any instructions, and also needs to recognized the
INSN_CLASS* classes from riscv_opcodes. Therefore, I suppose
some functions will need to be moved from gas/config/tc-riscv.c
to bfd/elfxx-riscv.c, including riscv_multi_subset_supports and
riscv_subset_supports. This is one of the reasons why we need
this patch.
This patch passes the gcc/binutils regressions of rv32emc-elf,
rv32i-elf, rv64gc-elf and rv64gc-linux toolchains.
bfd/
* elfxx-riscv.c (riscv_remove_subset): Remove the extension
from the subset list.
(riscv_update_subset): Add/Remove an extension to/from the
subset list. This is used for the .option rvc or norvc.
* elfxx-riscv.h: Added the extern bool riscv_update_subset.
gas/
* config/tc-riscv.c (riscv_set_options): Removed the unused
rve flag.
(riscv_opts): Likewise.
(riscv_set_rve): Removed.
(riscv_subset_supports): Removed the riscv_opts.rvc check.
(riscv_set_arch): Don't need to call riscv_set_rve.
(reg_lookup_internal): Call riscv_subset_supports to check
whether the rve is supported.
(s_riscv_option): Add/Remove the rvc extension to/from the
subset list once the .option rvc/norvc is set.
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This patch removes any fake (linker created) function descriptor
symbol if its code entry symbol isn't dynamic, to ensure bogus dynamic
symbols are not created. The change to func_desc_adjust requires that
it be run only once, which means ppc64_elf_tls_setup can't call it for
just a few selected symbols.
PR 28523
* elf64-ppc.c (func_desc_adjust): If a function entry sym is
not dynamic and has no plt entry, hide any associated fake
function descriptor symbol.
(ppc64_elf_edit): Move func_desc_adjust iteration over syms to..
(ppc64_elf_tls_setup): ..here.
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Anti-fuzzing checks.
* mach-o.c (bfd_mach_o_fat_archive_p): Sanity check entry offset
and size against file size.
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Update also include:
+ New value of Tag_CPU_arch EABI attribute (22) is added.
+ Updated missing Tag_CPU_arch EABI attributes.
+ Updated how we combine archs 'v4t_plus_v6_m' as this mechanism
have to handle new Armv9 as well.
Regression tested on `arm-none-eabi` cross Binutils and no issues.
bfd/
* archures.c: Define bfd_mach_arm_9.
* bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9.
* cpu-arm.c: Add 'armv9-a' option to -march.
* elf32-arm.c (using_thumb2_bl): Update assert check.
(arch_has_arm_nop): Add TAG_CPU_ARCH_V9.
(bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9.
Update assert.
(tag_cpu_arch_combine): Updated table.
(v9): New table..
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Update with
elfcpp/
* arm.h: Update TAG_CPU_ARCH_ enums with correct values.
gas/
* NEWS: Update docs.
* config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a
for -amarch=all.
(aeabi_set_public_attributes): Update assert.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/armv9-a_arch.d: New test.
* testsuite/gas/arm/attr-march-all.d: Update test with v9.
include/
* elf/arm.h Update TAG_CPU_ARCH_ defines with correct values.
* opcode/arm.h (ARM_EXT3_V9A): New macro.
(ARM_ARCH_NONE): Updated with arm_feature_set.core size.
(FPU_NONE): Updated.
(ARM_ANY): Updated.
(ARM_ARCH_UNKNOWN): New macro.
(ARM_FEATURE_LOW): Updated.
(ARM_FEATURE_CORE): Updated.
(ARM_FEATURE_CORE_LOW): Updated.
(ARM_FEATURE_CORE_HIGH): Updated.
(ARM_FEATURE_COPROC): Updated.
(ARM_FEATURE): Updated.
(ARM_FEATURE_ALL): New macro.
opcodes/
* arm-dis.c (select_arm_features): Support bfd_mach_arm_9.
Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
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This (and other) code from coffcode.h is broken for x86_64_coff_vec,
and has been ever since support was added in 2006 commit 99ad839030c1
Here, bfd_coff_aoutsz must match coff_swap_aouthdr_out otherwise we
end up writing garbage.
/* Note that peicode.h fills in a PEAOUTHDR, not an AOUTHDR.
include/coff/pe.h sets AOUTSZ == sizeof (PEAOUTHDR)). */
char * buff;
bfd_size_type amount = bfd_coff_aoutsz (abfd);
buff = (char *) bfd_malloc (amount);
if (buff == NULL)
return false;
coff_swap_aouthdr_out (abfd, & internal_a, buff);
amount = bfd_bwrite (buff, amount, abfd);
We have removed support for --target=x86_64-coff, likely because it
never worked properly, but still produce coff-x86_64.o with
--enable-targets=all. This means objcopy can recognize x86_64 COFF
files but will write garbage to the output file, a fact found by
fuzzers. I suspect x86_64 COFF is still broken after this fix, and
mention of coff-x86_64.* should be removed from bfd/Makefile.am.
* coff-x86_64.c: Don't include coff/pe.h.
(COFF_WITH_pex64): Don't define here.
* pe-x86_64.c: Include coff/pe.h and other headers.
(PEI_HEADERS): Define.
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sym_ptr_ptr NULL results in segfaults.
PR 28420
* ecoff.c (ecoff_slurp_reloc_table): Don't leave sym_ptr_ptr NULL.
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* vms-alpha.c (evax_bfd_print_image): Shift left 1u.
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PR 28518
* vms-alpha.c (build_module_list): Don't lose malloc buffer address.
Use unsigned variables.
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Catch fuzzed segments where p_offset + p_filesz wraps, and limit error
output.
* elfcore.h (elf_core_file_p): Rewrite segment checks using
bfd_get_file_size. Set read_only on file size errors.
* elfcode.h (elf_swap_shdr_in): Don't repeat error message.
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We already ignore stupid segment alignment when rewriting headers,
ignore section alignment too.
* elf.c (rewrite_elf_program_header): Ignore section alignment
power greater than 62.
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mmo_get_loc can return NULL. It's commented even, and that the caller
then must handle a split field. mmo_xore_* don't handle split fields,
instead just segfault. Stop that happening, and refuse to recognise
fuzzed mmo files that trigger this problem.
* mmo.c (mmo_get_loc): Don't declare inline.
(mmo_xore_64, mmo_xore_32, mmo_xore_16): Remove forward decls.
Return pointer, don't dereference NULL.
(mmo_scan): Return error on mmo_get_loc returning NULL.
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No need to use anything fancy, plain inline works just as well.
* bfd-in.h (INLINE): Don't define.
* bfd-in2.h: Regenerate.
* aoutx.h: Replace use of INLINE with inline.
* elf-eh-frame.c: Likewise.
* elf32-score7.c: Likewise.
* elfxx-mips.c: Likewise.
* ihex.c: Likewise.
* mach-o.c: Likewise.
* mmo.c: Likewise.
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Yet more anti-fuzzer sanity checking
* vms-alpha.c (evax_bfd_print_egsd): Sanity check record and
name lengths before access.
(evax_bfd_print_etir_stc_ir, evax_bfd_print_etir): Likewise.
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* coff64-rs6000.c (_bfd_xcoff64_swap_aux_in): Use bfd_vma for h.
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* vms-alpha.c (evax_bfd_print_image): Sanity check printing of
"image activator fixup" section.
(evax_bfd_print_relocation_records): Sanity check buffer offsets.
(evax_bfd_print_address_fixups): Likewise.
(evax_bfd_print_reference_fixups): Likewise.
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Sometimes the investigation of a fuzzing bug report leads into areas
you'd rather not go. In this instance by the time I'd figured out the
real cause was a target variant that had never been properly supported
in binutils, the time needed to fix it was less than the time needed
to rip it out.
* coffcode.h (coff_set_alignment_hook): Call bfd_coff_swap_reloc_in
not coff_swap_reloc_in.
(coff_slurp_reloc_table): Likewise. Don't use RELOC type.
(ticoff0_swap_table): Use coff_swap_reloc_v0_out and
coff_swap_reloc_v0_in.
* coffswap.h (coff_swap_reloc_v0_in, coff_swap_reloc_v0_out): New.
* coff-tic54x.c (tic54x_lookup_howto): Don't abort.
* coffgen.c (coff_get_normalized_symtab): Use PTR_ADD.
* bfd-in.h (PTR_ADD, NPTR_ADD): Avoid warnings when passing an
expression.
* bfd-in2.h: Regenerate.
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PR 21813
* mach-o-arm.c (bfd_mach_o_arm_canonicalize_one_reloc): Sanity
check PAIR reloc in other branch of condition as was done for
PR21813. Formatting. Delete debug printf.
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* aoutx.h (aout_get_external_symbols): Sanity check before writing
zero index entry. Remove outdated comment.
* pdp11.c (aout_get_external_symbols): Likewise.
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