arm: add armv9-a architecture to -march

Update also include:
	+ New value of Tag_CPU_arch EABI attribute (22) is added.
	+ Updated missing Tag_CPU_arch EABI attributes.
	+ Updated how we combine archs 'v4t_plus_v6_m' as this mechanism
	  have to handle new Armv9 as well.

Regression tested on `arm-none-eabi` cross Binutils and no issues.

bfd/

	* archures.c: Define bfd_mach_arm_9.
	* bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9.
	* cpu-arm.c: Add 'armv9-a' option to -march.
	* elf32-arm.c (using_thumb2_bl): Update assert check.
	(arch_has_arm_nop): Add TAG_CPU_ARCH_V9.
	(bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9.
	Update assert.
	(tag_cpu_arch_combine): Updated table.
	(v9): New table..

binutils/

	* readelf.c (arm_attr_tag_CPU_arch): Update with

elfcpp/

	* arm.h: Update TAG_CPU_ARCH_ enums with correct values.

gas/

	* NEWS: Update docs.
	* config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a
	for -amarch=all.
	(aeabi_set_public_attributes): Update assert.
	* doc/c-arm.texi: Update docs.
	* testsuite/gas/arm/armv9-a_arch.d: New test.
	* testsuite/gas/arm/attr-march-all.d: Update test with v9.

include/

	* elf/arm.h Update TAG_CPU_ARCH_ defines with correct values.
	* opcode/arm.h (ARM_EXT3_V9A): New macro.
	(ARM_ARCH_NONE): Updated with arm_feature_set.core size.
	(FPU_NONE): Updated.
	(ARM_ANY): Updated.
	(ARM_ARCH_UNKNOWN): New macro.
	(ARM_FEATURE_LOW): Updated.
	(ARM_FEATURE_CORE): Updated.
	(ARM_FEATURE_CORE_LOW): Updated.
	(ARM_FEATURE_CORE_HIGH): Updated.
	(ARM_FEATURE_COPROC): Updated.
	(ARM_FEATURE): Updated.
	(ARM_FEATURE_ALL): New macro.

opcodes/

	* arm-dis.c (select_arm_features): Support bfd_mach_arm_9.
	Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.

4 files changed, 52 insertions, 5 deletions

diff --git a/bfd/archures.c b/bfd/archures.c
index 6c9be91..441283b 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -337,6 +337,7 @@ DESCRIPTION
 .#define bfd_mach_arm_8M_BASE   25
 .#define bfd_mach_arm_8M_MAIN   26
 .#define bfd_mach_arm_8_1M_MAIN 27
+.#define bfd_mach_arm_9         28
 .  bfd_arch_nds32,     {* Andes NDS32.  *}
 .#define bfd_mach_n1		1
 .#define bfd_mach_n1h		2
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 9bdbe04..912d9a4 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1711,6 +1711,7 @@ enum bfd_architecture
 #define bfd_mach_arm_8M_BASE   25
 #define bfd_mach_arm_8M_MAIN   26
 #define bfd_mach_arm_8_1M_MAIN 27
+#define bfd_mach_arm_9         28
   bfd_arch_nds32,     /* Andes NDS32.  */
 #define bfd_mach_n1            1
 #define bfd_mach_n1h           2
diff --git a/bfd/cpu-arm.c b/bfd/cpu-arm.c
index 7a1ed46..c870625 100644
--- a/bfd/cpu-arm.c
+++ b/bfd/cpu-arm.c
@@ -258,6 +258,7 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (bfd_mach_arm_8M_BASE,   "armv8-m.base",   false, & arch_info_struct[25]),
   N (bfd_mach_arm_8M_MAIN,   "armv8-m.main",   false, & arch_info_struct[26]),
   N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", false, & arch_info_struct[27]),
+  N (bfd_mach_arm_9,         "armv9-a",        false, & arch_info_struct[28]),
   N (bfd_mach_arm_unknown,   "arm_any",        false, NULL)
 };
 
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 2cb8768..1655d52 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -3941,7 +3941,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
     bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
 
   /* Force return logic to be reviewed for each new architecture.  */
-  BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
+  BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
 
   /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M).  */
   return (arch == TAG_CPU_ARCH_V6T2
@@ -4130,13 +4130,14 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
 					     Tag_CPU_arch);
 
   /* Force return logic to be reviewed for each new architecture.  */
-  BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
+  BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
 
   return (arch == TAG_CPU_ARCH_V6T2
 	  || arch == TAG_CPU_ARCH_V6K
 	  || arch == TAG_CPU_ARCH_V7
 	  || arch == TAG_CPU_ARCH_V8
-	  || arch == TAG_CPU_ARCH_V8R);
+	  || arch == TAG_CPU_ARCH_V8R
+	  || arch == TAG_CPU_ARCH_V9);
 }
 
 static bool
@@ -13852,6 +13853,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
 	return bfd_mach_arm_8M_MAIN;
     case TAG_CPU_ARCH_V8_1M_MAIN:
 	return bfd_mach_arm_8_1M_MAIN;
+    case TAG_CPU_ARCH_V9:
+	return bfd_mach_arm_9;
 
     default:
       /* Force entry to be added for any new known Tag_CPU_arch value.  */
@@ -14202,7 +14205,14 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
       T(V8),		/* V6_M.  */
       T(V8),		/* V6S_M.  */
       T(V8),		/* V7E_M.  */
-      T(V8)		/* V8.  */
+      T(V8),		/* V8.  */
+      T(V8),		/* V8-R.  */
+      T(V8),		/* V8-M.BASE.  */
+      T(V8),		/* V8-M.MAIN.  */
+      T(V8),		/* V8.1.  */
+      T(V8),		/* V8.2.  */
+      T(V8),		/* V8.3.  */
+      T(V8),		/* V8.1-M.MAIN.  */
     };
   const int v8r[] =
     {
@@ -14289,6 +14299,32 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
       -1,		/* Unused (20).  */
       T(V8_1M_MAIN)	/* V8.1-M MAINLINE.  */
     };
+  const int v9[] =
+    {
+      T(V9),		/* PRE_V4.  */
+      T(V9),		/* V4.  */
+      T(V9),		/* V4T.  */
+      T(V9),		/* V5T.  */
+      T(V9),		/* V5TE.  */
+      T(V9),		/* V5TEJ.  */
+      T(V9),		/* V6.  */
+      T(V9),		/* V6KZ.  */
+      T(V9),		/* V6T2.  */
+      T(V9),		/* V6K.  */
+      T(V9),		/* V7.  */
+      T(V9),		/* V6_M.  */
+      T(V9),		/* V6S_M.  */
+      T(V9),		/* V7E_M.  */
+      T(V9),		/* V8.  */
+      T(V9),		/* V8-R.  */
+      T(V9),		/* V8-M.BASE.  */
+      T(V9),		/* V8-M.MAIN.  */
+      T(V9),		/* V8.1.  */
+      T(V9),		/* V8.2.  */
+      T(V9),		/* V8.3.  */
+      T(V9),		/* V8.1-M.MAIN.  */
+      T(V9),		/* V9.  */
+     };
   const int v4t_plus_v6_m[] =
     {
       -1,		/* PRE_V4.  */
@@ -14313,6 +14349,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
       -1,		/* Unused (19).  */
       -1,		/* Unused (20).  */
       T(V8_1M_MAIN),	/* V8.1-M MAINLINE.  */
+      T(V9),		/* V9.  */
       T(V4T_PLUS_V6_M)	/* V4T plus V6_M.  */
     };
   const int *comb[] =
@@ -14331,6 +14368,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
       NULL,
       NULL,
       v8_1m_mainline,
+      v9,
       /* Pseudo-architecture.  */
       v4t_plus_v6_m
     };
@@ -14547,10 +14585,16 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
 		"ARM v7",
 		"ARM v6-M",
 		"ARM v6S-M",
+		"ARM v7E-M",
 		"ARM v8",
-		"",
+		"ARM v8-R",
 		"ARM v8-M.baseline",
 		"ARM v8-M.mainline",
+		"ARM v8.1-A",
+		"ARM v8.2-A",
+		"ARM v8.3-A",
+		"ARM v8.1-M.mainline",
+		"ARM v9",
 	    };
 
 	    /* Merge Tag_CPU_arch and Tag_also_compatible_with.  */