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path: root/bfd/elfxx-riscv.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-23RISC-V: Relax the order checking for the architecture stringNelson Chu1-135/+75
2022-11-25riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner1-0/+4
2022-11-23RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standardXiao Zeng1-0/+4
2022-11-19RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI1-1/+3
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner1-0/+5
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner1-0/+5
2022-11-07RISC-V: Remove RV32EF conflictTsukasa OI1-7/+0
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+7
2022-10-14RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()Jan Beulich1-0/+6
2022-10-14RISC-V: Imply 'Zicsr' from privileged extensions with CSRsTsukasa OI1-0/+5
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-15/+14
2022-09-30RISC-V: Add privileged extensions without instructions/CSRsTsukasa OI1-0/+3
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+15
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+5
2022-09-22RISC-V: Add generic support for vendor extensionsChristoph Müllner1-2/+7
2022-09-21RISC-V: Implement Ztso extensionShihua1-0/+1
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu1-1/+1
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-0/+6
2022-08-10RISC-V: Remove R_RISCV_GNU_VTINHERIT/R_RISCV_GNU_VTENTRYFangrui Song1-29/+3
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-45/+52
2022-07-07RISC-V: Fix requirement handling on Zhinx+{D,Q}Tsukasa OI1-5/+25
2022-07-04RISC-V: Update Zihintpause extension versionTsukasa OI1-1/+1
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+1
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+1
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+1
2022-06-22RISC-V: Reorder the prefixed extensions which are out of order.Nelson Chu1-23/+0
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu1-11/+5
2022-06-22RISC-V: Add 'H' to canonical extension orderingTsukasa OI1-1/+1
2022-06-22RISC-V: Prepare i18n for required ISA extensionsTsukasa OI1-13/+14
2022-06-08Revert reloc howto nitsAlan Modra1-1/+1
2022-06-08HOWTO size encodingAlan Modra1-55/+55
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-4/+20
2022-05-25RISC-V: Fix RV32Q conflictTsukasa OI1-2/+3
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-0/+1
2022-05-19RISC-V: Fix canonical extension order (K and J)Tsukasa OI1-1/+1
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu1-0/+11
2022-03-18RISC-V: Cache management instructionsTsukasa OI1-0/+6
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+3
2022-02-25RISC-V: Remove a loop in the ISA parserTsukasa OI1-7/+4
2022-02-23RISC-V: PR28733, add missing extension info to 'unrecognized opcode' errorPatrick O'Neill1-0/+94
2022-02-22RISC-V: Maintain a string to hold the canonical orderKito Cheng1-17/+5
2022-01-07RISC-V: Updated the default ISA spec to 20191213.Nelson Chu1-1/+3
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1