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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-28 17:45:14 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 27cfd142d0a7e378d19aa9a1278e2137f849b71b (patch) | |
| tree | 24085d28b88f38be9763c9384c0dfd4029fff548 /bfd/elfxx-riscv.c | |
| parent | f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20 (diff) | |
| download | gdb-27cfd142d0a7e378d19aa9a1278e2137f849b71b.zip gdb-27cfd142d0a7e378d19aa9a1278e2137f849b71b.tar.gz gdb-27cfd142d0a7e378d19aa9a1278e2137f849b71b.tar.bz2 | |
RISC-V: Add T-Head MemIdx vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'bfd/elfxx-riscv.c')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d8f68fa..a4e90e6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1231,6 +1231,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadcondmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadfmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2408,6 +2409,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadfmemidx"); case INSN_CLASS_XTHEADMAC: return riscv_subset_supports (rps, "xtheadmac"); + case INSN_CLASS_XTHEADMEMIDX: + return riscv_subset_supports (rps, "xtheadmemidx"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); default: @@ -2551,6 +2554,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadfmemidx"; case INSN_CLASS_XTHEADMAC: return "xtheadmac"; + case INSN_CLASS_XTHEADMEMIDX: + return "xtheadmemidx"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; default: |