diff options
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 18 | ||||
-rw-r--r-- | opcodes/i386-dis.c | 62 |
2 files changed, 79 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8131817..d0f8846 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,23 @@ 2016-11-03 H.J. Lu <hongjiu.lu@intel.com> + PR binutils/20754 + * i386-dis.c (REG_82): New. + (X86_64_82_REG_0): Likewise. + (X86_64_82_REG_1): Likewise. + (X86_64_82_REG_2): Likewise. + (X86_64_82_REG_3): Likewise. + (X86_64_82_REG_4): Likewise. + (X86_64_82_REG_5): Likewise. + (X86_64_82_REG_6): Likewise. + (X86_64_82_REG_7): Likewise. + (dis386): Use REG_82. + (reg_table): Add REG_82. + (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, + X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, + X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7. + +2016-11-03 H.J. Lu <hongjiu.lu@intel.com> + * i386-dis.c (REG_82): Renamed to ... (REG_83): This. (dis386): Updated. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 8fb607c..b0bb5e8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -706,6 +706,7 @@ enum { REG_80 = 0, REG_81, + REG_82, REG_83, REG_8F, REG_C0, @@ -1694,6 +1695,14 @@ enum X86_64_63, X86_64_6D, X86_64_6F, + X86_64_82_REG_0, + X86_64_82_REG_1, + X86_64_82_REG_2, + X86_64_82_REG_3, + X86_64_82_REG_4, + X86_64_82_REG_5, + X86_64_82_REG_6, + X86_64_82_REG_7, X86_64_9A, X86_64_C4, X86_64_C5, @@ -2662,7 +2671,7 @@ static const struct dis386 dis386[] = { /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, - { Bad_Opcode }, + { REG_TABLE (REG_82) }, { REG_TABLE (REG_83) }, { "testB", { Eb, Gb }, 0 }, { "testS", { Ev, Gv }, 0 }, @@ -3400,6 +3409,17 @@ static const struct dis386 reg_table[][8] = { { "xorQ", { Evh1, Iv }, 0 }, { "cmpQ", { Ev, Iv }, 0 }, }, + /* REG_82 */ + { + { X86_64_TABLE (X86_64_82_REG_0) }, + { X86_64_TABLE (X86_64_82_REG_1) }, + { X86_64_TABLE (X86_64_82_REG_2) }, + { X86_64_TABLE (X86_64_82_REG_3) }, + { X86_64_TABLE (X86_64_82_REG_4) }, + { X86_64_TABLE (X86_64_82_REG_5) }, + { X86_64_TABLE (X86_64_82_REG_6) }, + { X86_64_TABLE (X86_64_82_REG_7) }, + }, /* REG_83 */ { { "addQ", { Evh1, sIb }, 0 }, @@ -6887,6 +6907,46 @@ static const struct dis386 x86_64_table[][2] = { { "outs{G|}", { indirDXr, Xz }, 0 }, }, + /* X86_64_82_REG_0 */ + { + { "addA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_1 */ + { + { "orA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_2 */ + { + { "adcA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_3 */ + { + { "sbbA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_4 */ + { + { "andA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_5 */ + { + { "subA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_6 */ + { + { "xorA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_7 */ + { + { "cmpA", { Eb, Ib }, 0 }, + }, + /* X86_64_9A */ { { "Jcall{T|}", { Ap }, 0 }, |