diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 20 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex-mod.h | 35 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex-prefix.h | 4 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex-w.h | 8 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex.h | 2 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 116 |
6 files changed, 122 insertions, 63 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3769588..73b31e5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,25 @@ 2020-07-14 Jan Beulich <jbeulich@suse.com> + * i386-dis.c (Rd, Rdq, MaskR): Delete. + (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1, + MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0, + MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0, + MOD_EVEX_0F387C): New enumerators. + (reg_table): Use Edq for rdssp. + (prefix_table): Use Edq for incssp. + (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*, + kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*, + ktest*, and kshift*. Use Edq / MaskE for kmov*. + * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C. + * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A, + 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C. + * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes + 0F3828_P_1 and 0F3838_P_1. + * i386-dis-evex-w.h: Reference mod_table[] for opcodes + 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3, PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8, PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h index acb497d..4259368 100644 --- a/opcodes/i386-dis-evex-mod.h +++ b/opcodes/i386-dis-evex-mod.h @@ -44,6 +44,26 @@ { { EVEX_LEN_TABLE (EVEX_LEN_0F381B_W_1_M_0) }, }, + /* MOD_EVEX_0F3828_P_1 */ + { + { Bad_Opcode }, + { "vpmovm2%BW", { XM, MaskE }, 0 }, + }, + /* MOD_EVEX_0F382A_P_1_W_1 */ + { + { Bad_Opcode }, + { "vpbroadcastmb2q", { XM, MaskE }, 0 }, + }, + /* MOD_EVEX_0F3838_P_1 */ + { + { Bad_Opcode }, + { "vpmovm2%DQ", { XM, MaskE }, 0 }, + }, + /* MOD_EVEX_0F383A_P_1_W_0 */ + { + { Bad_Opcode }, + { "vpbroadcastmw2d", { XM, MaskE }, 0 }, + }, /* MOD_EVEX_0F385A_W_0 */ { { EVEX_LEN_TABLE (EVEX_LEN_0F385A_W_0_M_0) }, @@ -60,6 +80,21 @@ { { EVEX_LEN_TABLE (EVEX_LEN_0F385B_W_1_M_0) }, }, + /* MOD_EVEX_0F387A_W_0 */ + { + { Bad_Opcode }, + { "vpbroadcastb", { XM, Ed }, PREFIX_DATA }, + }, + /* MOD_EVEX_0F387B_W_0 */ + { + { Bad_Opcode }, + { "vpbroadcastw", { XM, Ed }, PREFIX_DATA }, + }, + /* MOD_EVEX_0F387C */ + { + { Bad_Opcode }, + { "vpbroadcastK", { XM, Edq }, PREFIX_DATA }, + }, { /* MOD_EVEX_0F38C6_REG_1 */ { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_R_1_M_0) }, diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index a9581ee..fa54400 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -250,7 +250,7 @@ /* PREFIX_EVEX_0F3828 */ { { Bad_Opcode }, - { "vpmovm2%BW", { XM, MaskR }, 0 }, + { MOD_TABLE (MOD_EVEX_0F3828_P_1) }, { VEX_W_TABLE (EVEX_W_0F3828_P_2) }, }, /* PREFIX_EVEX_0F3829 */ @@ -304,7 +304,7 @@ /* PREFIX_EVEX_0F3838 */ { { Bad_Opcode }, - { "vpmovm2%DQ", { XM, MaskR }, 0 }, + { MOD_TABLE (MOD_EVEX_0F3838_P_1) }, { "vpminsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_EVEX_0F3839 */ diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index 59ff1d4..a046d11 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -455,7 +455,7 @@ /* EVEX_W_0F382A_P_1 */ { { Bad_Opcode }, - { "vpbroadcastmb2q", { XM, MaskR }, 0 }, + { MOD_TABLE (MOD_EVEX_0F382A_P_1_W_1) }, }, /* EVEX_W_0F382A_P_2 */ { @@ -500,7 +500,7 @@ }, /* EVEX_W_0F383A_P_1 */ { - { "vpbroadcastmw2d", { XM, MaskR }, 0 }, + { MOD_TABLE (MOD_EVEX_0F383A_P_1_W_0) }, }, /* EVEX_W_0F3852_P_1 */ { @@ -544,11 +544,11 @@ }, /* EVEX_W_0F387A */ { - { "vpbroadcastb", { XM, Rd }, PREFIX_DATA }, + { MOD_TABLE (MOD_EVEX_0F387A_W_0) }, }, /* EVEX_W_0F387B */ { - { "vpbroadcastw", { XM, Rd }, PREFIX_DATA }, + { MOD_TABLE (MOD_EVEX_0F387B_W_0) }, }, /* EVEX_W_0F3883 */ { diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 54176af..c933942 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -432,7 +432,7 @@ static const struct dis386 evex_table[][256] = { { VEX_W_TABLE (VEX_W_0F3879) }, { VEX_W_TABLE (EVEX_W_0F387A) }, { VEX_W_TABLE (EVEX_W_0F387B) }, - { "vpbroadcastK", { XM, Rdq }, PREFIX_DATA }, + { MOD_TABLE (MOD_EVEX_0F387C) }, { "vpermt2%BW", { XM, Vex, EXx }, PREFIX_DATA }, { "vpermt2%DQ", { XM, Vex, EXx }, PREFIX_DATA }, { "vpermt2p%XW", { XM, Vex, EXx }, PREFIX_DATA }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 2f748b8..35399bc 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -274,8 +274,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Gm { OP_G, m_mode } #define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } -#define Rd { OP_R, d_mode } -#define Rdq { OP_R, dq_mode } #define Rm { OP_R, m_mode } #define Ib { OP_I, b_mode } #define sIb { OP_sI, b_mode } /* sign extened byte */ @@ -412,7 +410,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define MaskG { OP_G, mask_mode } #define MaskE { OP_E, mask_mode } #define MaskBDE { OP_E, mask_bd_mode } -#define MaskR { OP_R, mask_mode } #define MaskVex { OP_VEX, mask_mode } #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } @@ -912,10 +909,17 @@ enum MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1, + MOD_EVEX_0F3828_P_1, + MOD_EVEX_0F382A_P_1_W_1, + MOD_EVEX_0F3838_P_1, + MOD_EVEX_0F383A_P_1_W_0, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, + MOD_EVEX_0F387A_W_0, + MOD_EVEX_0F387B_W_0, + MOD_EVEX_0F387C, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, @@ -2884,7 +2888,7 @@ static const struct dis386 reg_table[][8] = { /* REG_0F1E_P_1_MOD_3 */ { { "nopQ", { Ev }, 0 }, - { "rdsspK", { Rdq }, PREFIX_OPCODE }, + { "rdsspK", { Edq }, PREFIX_OPCODE }, { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, @@ -3425,7 +3429,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0FAE_REG_5_MOD_3 */ { { "lfence", { Skip_MODRM }, 0 }, - { "incsspK", { Rdq }, PREFIX_OPCODE }, + { "incsspK", { Edq }, PREFIX_OPCODE }, }, /* PREFIX_0FAE_REG_6_MOD_0 */ @@ -7990,12 +7994,12 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0F24 */ { Bad_Opcode }, - { "movL", { Rd, Td }, 0 }, + { "movL", { Rm, Td }, 0 }, }, { /* MOD_0F26 */ { Bad_Opcode }, - { "movL", { Td, Rd }, 0 }, + { "movL", { Td, Rm }, 0 }, }, { /* MOD_0F2B_PREFIX_0 */ @@ -8286,157 +8290,157 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ { Bad_Opcode }, - { "kandw", { MaskG, MaskVex, MaskR }, 0 }, + { "kandw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ { Bad_Opcode }, - { "kandq", { MaskG, MaskVex, MaskR }, 0 }, + { "kandq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ { Bad_Opcode }, - { "kandb", { MaskG, MaskVex, MaskR }, 0 }, + { "kandb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ { Bad_Opcode }, - { "kandd", { MaskG, MaskVex, MaskR }, 0 }, + { "kandd", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ { Bad_Opcode }, - { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, + { "kandnw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ { Bad_Opcode }, - { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, + { "kandnq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ { Bad_Opcode }, - { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, + { "kandnb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ { Bad_Opcode }, - { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, + { "kandnd", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ { Bad_Opcode }, - { "knotw", { MaskG, MaskR }, 0 }, + { "knotw", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ { Bad_Opcode }, - { "knotq", { MaskG, MaskR }, 0 }, + { "knotq", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ { Bad_Opcode }, - { "knotb", { MaskG, MaskR }, 0 }, + { "knotb", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ { Bad_Opcode }, - { "knotd", { MaskG, MaskR }, 0 }, + { "knotd", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ { Bad_Opcode }, - { "korw", { MaskG, MaskVex, MaskR }, 0 }, + { "korw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ { Bad_Opcode }, - { "korq", { MaskG, MaskVex, MaskR }, 0 }, + { "korq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ { Bad_Opcode }, - { "korb", { MaskG, MaskVex, MaskR }, 0 }, + { "korb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ { Bad_Opcode }, - { "kord", { MaskG, MaskVex, MaskR }, 0 }, + { "kord", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ { Bad_Opcode }, - { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, + { "kxnorw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ { Bad_Opcode }, - { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, + { "kxnorq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ { Bad_Opcode }, - { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, + { "kxnorb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ { Bad_Opcode }, - { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, + { "kxnord", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ { Bad_Opcode }, - { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, + { "kxorw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ { Bad_Opcode }, - { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, + { "kxorq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ { Bad_Opcode }, - { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, + { "kxorb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ { Bad_Opcode }, - { "kxord", { MaskG, MaskVex, MaskR }, 0 }, + { "kxord", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ { Bad_Opcode }, - { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, + { "kaddw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ { Bad_Opcode }, - { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, + { "kaddq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ { Bad_Opcode }, - { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, + { "kaddb", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ { Bad_Opcode }, - { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, + { "kaddd", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ { Bad_Opcode }, - { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, + { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ { Bad_Opcode }, - { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, + { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ { Bad_Opcode }, - { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, + { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 }, }, { /* MOD_VEX_0F50 */ @@ -8516,72 +8520,72 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ { Bad_Opcode }, - { "kmovw", { MaskG, Rdq }, 0 }, + { "kmovw", { MaskG, Edq }, 0 }, }, { /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ { Bad_Opcode }, - { "kmovb", { MaskG, Rdq }, 0 }, + { "kmovb", { MaskG, Edq }, 0 }, }, { /* MOD_VEX_0F92_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovK", { MaskG, Rdq }, 0 }, + { "kmovK", { MaskG, Edq }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ { Bad_Opcode }, - { "kmovw", { Gdq, MaskR }, 0 }, + { "kmovw", { Gdq, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ { Bad_Opcode }, - { "kmovb", { Gdq, MaskR }, 0 }, + { "kmovb", { Gdq, MaskE }, 0 }, }, { /* MOD_VEX_0F93_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovK", { Gdq, MaskR }, 0 }, + { "kmovK", { Gdq, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ { Bad_Opcode }, - { "kortestw", { MaskG, MaskR }, 0 }, + { "kortestw", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ { Bad_Opcode }, - { "kortestq", { MaskG, MaskR }, 0 }, + { "kortestq", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ { Bad_Opcode }, - { "kortestb", { MaskG, MaskR }, 0 }, + { "kortestb", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ { Bad_Opcode }, - { "kortestd", { MaskG, MaskR }, 0 }, + { "kortestd", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ { Bad_Opcode }, - { "ktestw", { MaskG, MaskR }, 0 }, + { "ktestw", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ { Bad_Opcode }, - { "ktestq", { MaskG, MaskR }, 0 }, + { "ktestq", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ { Bad_Opcode }, - { "ktestb", { MaskG, MaskR }, 0 }, + { "ktestb", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ { Bad_Opcode }, - { "ktestd", { MaskG, MaskR }, 0 }, + { "ktestd", { MaskG, MaskE }, 0 }, }, { /* MOD_VEX_0FAE_REG_2 */ @@ -8643,22 +8647,22 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0F3A30_L_0 */ { Bad_Opcode }, - { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, + { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, }, { /* MOD_VEX_0F3A31_L_0 */ { Bad_Opcode }, - { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, + { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, }, { /* MOD_VEX_0F3A32_L_0 */ { Bad_Opcode }, - { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, + { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, }, { /* MOD_VEX_0F3A33_L_0 */ { Bad_Opcode }, - { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, + { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, }, { /* MOD_VEX_0FXOP_09_12 */ |