diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/bfdlink.h | 3 | ||||
| -rw-r--r-- | include/bout.h | 192 | ||||
| -rw-r--r-- | include/coff/xcoff.h | 24 | ||||
| -rw-r--r-- | include/elf/aarch64.h | 2 | ||||
| -rw-r--r-- | include/elf/common.h | 5 | ||||
| -rw-r--r-- | include/libiberty.h | 22 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 201 | ||||
| -rw-r--r-- | include/opcode/kvx.h | 4 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 61 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 45 |
10 files changed, 301 insertions, 258 deletions
diff --git a/include/bfdlink.h b/include/bfdlink.h index ae45107..3d4d71b 100644 --- a/include/bfdlink.h +++ b/include/bfdlink.h @@ -877,6 +877,9 @@ struct bfd_link_callbacks (struct bfd_link_info *, struct bfd_link_hash_entry *h, struct bfd_link_hash_entry *inh, bfd *abfd, asection *section, bfd_vma address, flagword flags); + /* Fatal error. */ + void (*fatal) + (const char *fmt, ...) ATTRIBUTE_NORETURN; /* Error or warning link info message. */ void (*einfo) (const char *fmt, ...); diff --git a/include/bout.h b/include/bout.h deleted file mode 100644 index 01b2c23..0000000 --- a/include/bout.h +++ /dev/null @@ -1,192 +0,0 @@ -/* This file is a modified version of 'a.out.h'. It is to be used in all - GNU tools modified to support the i80960 (or tools that operate on - object files created by such tools). - - Copyright (C) 2001-2025 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* All i80960 development is done in a CROSS-DEVELOPMENT environment. I.e., - object code is generated on, and executed under the direction of a symbolic - debugger running on, a host system. We do not want to be subject to the - vagaries of which host it is or whether it supports COFF or a.out format, - or anything else. We DO want to: - - o always generate the same format object files, regardless of host. - - o have an 'a.out' header that we can modify for our own purposes - (the 80960 is typically an embedded processor and may require - enhanced linker support that the normal a.out.h header can't - accommodate). - - As for byte-ordering, the following rules apply: - - o Text and data that is actually downloaded to the target is always - in i80960 (little-endian) order. - - o All other numbers (in the header, symbols, relocation directives) - are in host byte-order: object files CANNOT be lifted from a - little-end host and used on a big-endian (or vice versa) without - modification. - ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER - FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO - USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== - - o The downloader ('comm960') takes care to generate a pseudo-header - with correct (i80960) byte-ordering before shipping text and data - off to the NINDY monitor in the target systems. Symbols and - relocation info are never sent to the target. */ - -#define BMAGIC 0415 -/* We don't accept the following (see N_BADMAG macro). - They're just here so GNU code will compile. */ -#define OMAGIC 0407 /* old impure format */ -#define NMAGIC 0410 /* read-only text */ -#define ZMAGIC 0413 /* demand load format */ - -/* FILE HEADER - All 'lengths' are given as a number of bytes. - All 'alignments' are for relinkable files only; an alignment of - 'n' indicates the corresponding segment must begin at an - address that is a multiple of (2**n). */ -struct external_exec - { - /* Standard stuff */ - unsigned char e_info[4]; /* Identifies this as a b.out file */ - unsigned char e_text[4]; /* Length of text */ - unsigned char e_data[4]; /* Length of data */ - unsigned char e_bss[4]; /* Length of uninitialized data area */ - unsigned char e_syms[4]; /* Length of symbol table */ - unsigned char e_entry[4]; /* Runtime start address */ - unsigned char e_trsize[4]; /* Length of text relocation info */ - unsigned char e_drsize[4]; /* Length of data relocation info */ - - /* Added for i960 */ - unsigned char e_tload[4]; /* Text runtime load address */ - unsigned char e_dload[4]; /* Data runtime load address */ - unsigned char e_talign[1]; /* Alignment of text segment */ - unsigned char e_dalign[1]; /* Alignment of data segment */ - unsigned char e_balign[1]; /* Alignment of bss segment */ - unsigned char e_relaxable[1];/* Assembled with enough info to allow linker to relax */ - }; - -#define EXEC_BYTES_SIZE (sizeof (struct external_exec)) - -/* These macros use the a_xxx field names, since they operate on the exec - structure after it's been byte-swapped and realigned on the host machine. */ -#define N_BADMAG(x) (((x)->a_info)!=BMAGIC) -#define N_TXTOFF(x) EXEC_BYTES_SIZE -#define N_DATOFF(x) ( N_TXTOFF(x) + (x)->a_text ) -#define N_TROFF(x) ( N_DATOFF(x) + (x)->a_data ) -#define N_TRELOFF N_TROFF -#define N_DROFF(x) ( N_TROFF(x) + (x)->a_trsize ) -#define N_DRELOFF N_DROFF -#define N_SYMOFF(x) ( N_DROFF(x) + (x)->a_drsize ) -#define N_STROFF(x) ( N_SYMOFF(x) + (x)->a_syms ) -#define N_DATADDR(x) ( (x)->a_dload ) - -/* Address of text segment in memory after it is loaded. */ -#if !defined (N_TXTADDR) -#define N_TXTADDR(x) 0 -#endif - -/* A single entry in the symbol table. */ -struct nlist - { - union - { - char* n_name; - struct nlist * n_next; - long n_strx; /* Index into string table */ - } n_un; - - unsigned char n_type; /* See below */ - char n_other; /* Used in i80960 support -- see below */ - short n_desc; - unsigned long n_value; - }; - - -/* Legal values of n_type. */ -#define N_UNDF 0 /* Undefined symbol */ -#define N_ABS 2 /* Absolute symbol */ -#define N_TEXT 4 /* Text symbol */ -#define N_DATA 6 /* Data symbol */ -#define N_BSS 8 /* BSS symbol */ -#define N_FN 31 /* Filename symbol */ - -#define N_EXT 1 /* External symbol (OR'd in with one of above) */ -#define N_TYPE 036 /* Mask for all the type bits */ -#define N_STAB 0340 /* Mask for all bits used for SDB entries */ - -/* MEANING OF 'n_other' - - If non-zero, the 'n_other' fields indicates either a leaf procedure or - a system procedure, as follows: - - 1 <= n_other <= 32 : - The symbol is the entry point to a system procedure. - 'n_value' is the address of the entry, as for any other - procedure. The system procedure number (which can be used in - a 'calls' instruction) is (n_other-1). These entries come from - '.sysproc' directives. - - n_other == N_CALLNAME - the symbol is the 'call' entry point to a leaf procedure. - The *next* symbol in the symbol table must be the corresponding - 'bal' entry point to the procedure (see following). These - entries come from '.leafproc' directives in which two different - symbols are specified (the first one is represented here). - - - n_other == N_BALNAME - the symbol is the 'bal' entry point to a leaf procedure. - These entries result from '.leafproc' directives in which only - one symbol is specified, or in which the same symbol is - specified twice. - - Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry, - but not every N_BALNAME entry must have an N_CALLNAME entry. */ -#define N_CALLNAME ((char)-1) -#define N_BALNAME ((char)-2) -#define IS_CALLNAME(x) (N_CALLNAME == (x)) -#define IS_BALNAME(x) (N_BALNAME == (x)) -#define IS_OTHER(x) ((x)>0 && (x) <=32) - -#define b_out_relocation_info relocation_info -struct relocation_info - { - int r_address; /* File address of item to be relocated. */ - unsigned -#define r_index r_symbolnum - r_symbolnum:24, /* Index of symbol on which relocation is based, - if r_extern is set. Otherwise set to - either N_TEXT, N_DATA, or N_BSS to - indicate section on which relocation is - based. */ - r_pcrel:1, /* 1 => relocate PC-relative; else absolute - On i960, pc-relative implies 24-bit - address, absolute implies 32-bit. */ - r_length:2, /* Number of bytes to relocate: - 0 => 1 byte - 1 => 2 bytes -- used for 13 bit pcrel - 2 => 4 bytes. */ - r_extern:1, - r_bsr:1, /* Something for the GNU NS32K assembler. */ - r_disp:1, /* Something for the GNU NS32K assembler. */ - r_callj:1, /* 1 if relocation target is an i960 'callj'. */ - r_relaxable:1; /* 1 if enough info is left to relax the data. */ -}; diff --git a/include/coff/xcoff.h b/include/coff/xcoff.h index 8688742..cae0029 100644 --- a/include/coff/xcoff.h +++ b/include/coff/xcoff.h @@ -204,30 +204,30 @@ struct internal_ldhdr /* The version number: 1 : 32 bit 2 : 64 bit */ - unsigned long l_version; + unsigned int l_version; /* The number of symbol table entries. */ - bfd_size_type l_nsyms; + size_t l_nsyms; /* The number of relocation table entries. */ - bfd_size_type l_nreloc; + size_t l_nreloc; /* The length of the import file string table. */ - bfd_size_type l_istlen; + size_t l_istlen; /* The number of import files. */ - bfd_size_type l_nimpid; + size_t l_nimpid; + + /* The length of the string table. */ + size_t l_stlen; /* The offset from the start of the .loader section to the first entry in the import file table. */ - bfd_size_type l_impoff; - - /* The length of the string table. */ - bfd_size_type l_stlen; + bfd_vma l_impoff; /* The offset from the start of the .loader section to the first entry in the string table. */ - bfd_size_type l_stoff; + bfd_vma l_stoff; /* The offset to start of the symbol table, only in XCOFF64 */ bfd_vma l_symoff; @@ -248,11 +248,11 @@ struct internal_ldsym struct { /* Zero if the symbol name is more than SYMNMLEN characters. */ - long _l_zeroes; + uint32_t _l_zeroes; /* The offset in the string table if the symbol name is more than SYMNMLEN characters. */ - long _l_offset; + uint32_t _l_offset; } _l_l; } diff --git a/include/elf/aarch64.h b/include/elf/aarch64.h index d7904bb..e218e07 100644 --- a/include/elf/aarch64.h +++ b/include/elf/aarch64.h @@ -30,6 +30,8 @@ /* MTE memory tag segment type. */ #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2) +/* Name of the ELF section holding the attributes. */ +#define SEC_AARCH64_ATTRIBUTES ".ARM.attributes" /* Additional section types. */ /* Section holds attributes. */ #define SHT_AARCH64_ATTRIBUTES (SHT_LOPROC + 3) diff --git a/include/elf/common.h b/include/elf/common.h index fd032d1..01812b4 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -1041,6 +1041,11 @@ #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1) #define GNU_PROPERTY_AARCH64_FEATURE_1_GCS (1U << 2) +/* RISC-V specific GNU PROPERTY. */ +#define GNU_PROPERTY_RISCV_FEATURE_1_AND 0xc0000000 +#define GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED (1U << 0) +#define GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS (1U << 1) + /* Values used in GNU .note.ABI-tag notes (NT_GNU_ABI_TAG). */ #define GNU_ABI_TAG_LINUX 0 #define GNU_ABI_TAG_HURD 1 diff --git a/include/libiberty.h b/include/libiberty.h index e39f187..b88eb64 100644 --- a/include/libiberty.h +++ b/include/libiberty.h @@ -133,6 +133,18 @@ extern const char *dos_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIB extern const char *unix_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1); +/* A dirname () that is always compiled in. */ + +extern char *ldirname (const char *) ATTRIBUTE_NONNULL(1); + +/* Same, but assumes DOS semantics regardless of host. */ + +extern char *dos_ldirname (const char *) ATTRIBUTE_NONNULL(1); + +/* Same, but assumes Unix semantics regardless of host. */ + +extern char *unix_ldirname (const char *) ATTRIBUTE_NONNULL(1); + /* A well-defined realpath () that is always compiled in. */ extern char *lrealpath (const char *); @@ -199,6 +211,16 @@ extern int fdmatch (int fd1, int fd2); extern int ffs(int); #endif +#if defined (HAVE_DECL_MKSTEMPS) && !HAVE_DECL_MKSTEMPS +extern int mkstemps(char *, int); +#endif + +/* Make memrchr available on systems that do not have it. */ +#if !defined (__GNU_LIBRARY__ ) && !defined (__linux__) && \ + !defined (HAVE_MEMRCHR) +extern void *memrchr(const void *, int, size_t); +#endif + /* Get the working directory. The result is cached, so don't call chdir() between calls to getpwd(). */ diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dfe3f05..7c1163d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -79,6 +79,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_CRC, /* LSE instructions. */ AARCH64_FEATURE_LSE, + /* LSFE instructions. */ + AARCH64_FEATURE_LSFE, /* PAN instructions. */ AARCH64_FEATURE_PAN, /* LOR instructions. */ @@ -135,8 +137,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_ID_PFR2, /* SSBS mechanism enabled. */ AARCH64_FEATURE_SSBS, + /* Compare and branch instructions. */ + AARCH64_FEATURE_CMPBR, /* Memory Tagging Extension. */ AARCH64_FEATURE_MEMTAG, + /* Outer Cacheable Cache Maintenance Operation. */ + AARCH64_FEATURE_OCCMO, /* Transactional Memory Extension. */ AARCH64_FEATURE_TME, /* XS memory attribute. */ @@ -210,7 +216,7 @@ enum aarch64_feature_bit { /* Instrumentation Extension. */ AARCH64_FEATURE_ITE, /* 128-bit page table descriptor, system registers - and isntructions. */ + and instructions. */ AARCH64_FEATURE_D128, /* Armv8.9-A/Armv9.4-A architecture Debug extension. */ AARCH64_FEATURE_DEBUGv8p9, @@ -230,6 +236,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME2p1, /* SVE2.1 instructions. */ AARCH64_FEATURE_SVE2p1, + /* SVE_F16F32MM instructions. */ + AARCH64_FEATURE_SVE_F16F32MM, + /* F8F32MM instructions. */ + AARCH64_FEATURE_F8F32MM, + /* F8F16MM instructions. */ + AARCH64_FEATURE_F8F16MM, /* RCPC3 instructions. */ AARCH64_FEATURE_RCPC3, /* Enhanced Software Step Extension. */ @@ -264,12 +276,26 @@ enum aarch64_feature_bit { AARCH64_FEATURE_SME_F8F16, /* Non-widening half-precision FP16 to FP16 arithmetic for SME2. */ AARCH64_FEATURE_SME_F16F16, + /* FEAT_SVE_BFSCALE. */ + AARCH64_FEATURE_SVE_BFSCALE, /* SVE Z-targeting non-widening BFloat16 instructions. */ AARCH64_FEATURE_SVE_B16B16, /* SME non-widening BFloat16 instructions. */ AARCH64_FEATURE_SME_B16B16, + /* Armv9.1-A processors. */ + AARCH64_FEATURE_V9_1A, + /* Armv9.2-A processors. */ + AARCH64_FEATURE_V9_2A, + /* Armv9.3-A processors. */ + AARCH64_FEATURE_V9_3A, + /* Armv9.4-A processors. */ + AARCH64_FEATURE_V9_4A, /* Armv9.5-A processors. */ AARCH64_FEATURE_V9_5A, + /* FPRCVT instructions. */ + AARCH64_FEATURE_FPRCVT, + /* Point of Physical Storage. */ + AARCH64_FEATURE_PoPS, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -281,6 +307,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FP8DOT2_SVE, /* +sme-f16f16 or +sme-f8f16 */ AARCH64_FEATURE_SME_F16F16_F8F16, + /* +sve2 or +sme2 */ + AARCH64_FEATURE_SVE2_SME2, /* +sve2p1 or +sme */ AARCH64_FEATURE_SVE2p1_SME, /* +sve2p1 or +sme2 */ @@ -290,13 +318,49 @@ enum aarch64_feature_bit { AARCH64_NUM_FEATURES }; +typedef uint64_t aarch64_feature_word; +#define AARCH64_BITS_PER_FEATURE_WORD 64 + +#define AA64_REPLICATE(SEP, BODY, ...) \ + BODY (0, __VA_ARGS__) SEP \ + BODY (1, __VA_ARGS__) SEP \ + BODY (2, __VA_ARGS__) + +/* Some useful SEP operators for use with replication. */ +#define REP_COMMA , +#define REP_SEMICOLON ; +#define REP_OR_OR || +#define REP_AND_AND && +#define REP_PLUS + + +/* Not currently needed, but if an empty SEP is required define: + #define REP_NO_SEP + Then use REP_NO_SEP in the SEP field. */ + +/* Used to generate one instance of VAL for each value of ELT (ELT is + not otherwise used). */ +#define AA64_REPVAL(ELT, VAL) VAL + +/* static_assert requires C11 (or C++11) or later. Support older + versions by disabling this check since compilers without this are + pretty uncommon these days. */ +#if ((defined __STDC_VERSION__ && __STDC_VERSION__ >= 201112L) \ + || (defined __cplusplus && __cplusplus >= 201103L)) +static_assert ((AA64_REPLICATE (REP_PLUS, AA64_REPVAL, + AARCH64_BITS_PER_FEATURE_WORD)) + >= AARCH64_NUM_FEATURES, + "Insufficient repetitions in AA64_REPLICATE()"); +#endif + /* These macros take an initial argument X that gives the index into an aarch64_feature_set. The macros then return the bitmask for that array index. */ /* A mask in which feature bit BIT is set and all other bits are clear. */ -#define AARCH64_UINT64_BIT(X, BIT) \ - ((X) == (BIT) / 64 ? 1ULL << (BIT) % 64 : 0) +#define AARCH64_UINT64_BIT(X, BIT) \ + ((X) == (BIT) / AARCH64_BITS_PER_FEATURE_WORD \ + ? 1ULL << (BIT) % AARCH64_BITS_PER_FEATURE_WORD \ + : 0) /* A mask that includes only AARCH64_FEATURE_<NAME>. */ #define AARCH64_FEATBIT(X, NAME) \ @@ -374,10 +438,14 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, F16) \ | AARCH64_FEATBIT (X, SVE) \ | AARCH64_FEATBIT (X, SVE2)) -#define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X) -#define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X) -#define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X) -#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \ +#define AARCH64_ARCH_V9_1A_FEATURES(X) (AARCH64_FEATBIT (X, V9_1A) \ + | AARCH64_ARCH_V8_6A_FEATURES (X)) +#define AARCH64_ARCH_V9_2A_FEATURES(X) (AARCH64_FEATBIT (X, V9_2A) \ + | AARCH64_ARCH_V8_7A_FEATURES (X)) +#define AARCH64_ARCH_V9_3A_FEATURES(X) (AARCH64_FEATBIT (X, V9_3A) \ + | AARCH64_ARCH_V8_8A_FEATURES (X)) +#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_FEATBIT (X, V9_4A) \ + | AARCH64_ARCH_V8_9A_FEATURES (X) \ | AARCH64_FEATBIT (X, SVE2p1)) #define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \ | AARCH64_FEATBIT (X, CPA) \ @@ -431,60 +499,74 @@ enum aarch64_feature_bit { /* CPU-specific features. */ typedef struct { - uint64_t flags[(AARCH64_NUM_FEATURES + 63) / 64]; + aarch64_feature_word flags[AA64_REPLICATE (REP_PLUS, AA64_REPVAL, 1)]; } aarch64_feature_set; -#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ - ((~(CPU).flags[0] & AARCH64_FEATBIT (0, FEAT)) == 0 \ - && (~(CPU).flags[1] & AARCH64_FEATBIT (1, FEAT)) == 0) +#define AARCH64_CPU_HAS_FEATURE_BODY(ELT, CPU, FEAT) \ + ((~(CPU).flags[ELT] & AARCH64_FEATBIT (ELT, FEAT)) == 0) +#define AARCH64_CPU_HAS_FEATURE(CPU, FEAT) \ + (AA64_REPLICATE (REP_AND_AND, AARCH64_CPU_HAS_FEATURE_BODY, CPU, FEAT)) -#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ - ((~(CPU).flags[0] & (FEAT).flags[0]) == 0 \ - && (~(CPU).flags[1] & (FEAT).flags[1]) == 0) +#define AARCH64_CPU_HAS_ALL_FEATURES_BODY(ELT, CPU, FEAT) \ + ((~(CPU).flags[ELT] & (FEAT).flags[ELT]) == 0) +#define AARCH64_CPU_HAS_ALL_FEATURES(CPU, FEAT) \ + (AA64_REPLICATE (REP_AND_AND, AARCH64_CPU_HAS_ALL_FEATURES_BODY, CPU, FEAT)) +#define AARCH64_CPU_HAS_ANY_FEATURES_BODY(ELT, CPU, FEAT) \ + (((CPU).flags[ELT] & (FEAT).flags[ELT]) != 0) #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ - (((CPU).flags[0] & (FEAT).flags[0]) != 0 \ - || ((CPU).flags[1] & (FEAT).flags[1]) != 0) + (AA64_REPLICATE (REP_OR_OR, AARCH64_CPU_HAS_ANY_FEATURES_BODY, CPU, FEAT)) +#define AARCH64_SET_FEATURE_BODY(ELT, DEST, FEAT) \ + (DEST).flags[ELT] = FEAT (ELT) #define AARCH64_SET_FEATURE(DEST, FEAT) \ - ((DEST).flags[0] = FEAT (0), \ - (DEST).flags[1] = FEAT (1)) + (AA64_REPLICATE (REP_COMMA, AARCH64_SET_FEATURE_BODY, DEST, FEAT)) +#define AARCH64_CLEAR_FEATURE_BODY(ELT, DEST, SRC, FEAT) \ + (DEST).flags[ELT] = ((SRC).flags[ELT] \ + & ~AARCH64_FEATBIT (ELT, FEAT)) #define AARCH64_CLEAR_FEATURE(DEST, SRC, FEAT) \ - ((DEST).flags[0] = (SRC).flags[0] & ~AARCH64_FEATBIT (0, FEAT), \ - (DEST).flags[1] = (SRC).flags[1] & ~AARCH64_FEATBIT (1, FEAT)) - -#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do \ - { \ - (TARG).flags[0] = (F1).flags[0] | (F2).flags[0]; \ - (TARG).flags[1] = (F1).flags[1] | (F2).flags[1]; \ - } \ + (AA64_REPLICATE (REP_COMMA, AARCH64_CLEAR_FEATURE_BODY, DEST, SRC, FEAT)) + +#define AARCH64_MERGE_FEATURE_SETS_BODY(ELT, TARG, F1, F2) \ + (TARG).flags[ELT] = (F1).flags[ELT] | (F2).flags[ELT]; +#define AARCH64_MERGE_FEATURE_SETS(TARG, F1, F2) \ + do \ + { \ + AA64_REPLICATE (REP_SEMICOLON, \ + AARCH64_MERGE_FEATURE_SETS_BODY, TARG, F1, F2); \ + } \ while (0) -#define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \ - do \ - { \ - (TARG).flags[0] = (F1).flags[0] &~ (F2).flags[0]; \ - (TARG).flags[1] = (F1).flags[1] &~ (F2).flags[1]; \ - } \ +#define AARCH64_CLEAR_FEATURES_BODY(ELT, TARG, F1, F2) \ + (TARG).flags[ELT] = (F1).flags[ELT] &~ (F2).flags[ELT]; +#define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \ + do \ + { \ + AA64_REPLICATE (REP_SEMICOLON, \ + AARCH64_CLEAR_FEATURES_BODY, TARG, F1, F2); \ + } \ while (0) /* aarch64_feature_set initializers for no features and all features, respectively. */ -#define AARCH64_NO_FEATURES { { 0, 0 } } -#define AARCH64_ALL_FEATURES { { -1, -1 } } +#define AARCH64_NO_FEATURES { { AA64_REPLICATE (REP_COMMA, AA64_REPVAL, 0) } } +#define AARCH64_ALL_FEATURES { { AA64_REPLICATE (REP_COMMA, AA64_REPVAL, -1) } } /* An aarch64_feature_set initializer for a single feature, AARCH64_FEATURE_<FEAT>. */ -#define AARCH64_FEATURE(FEAT) \ - { { AARCH64_FEATBIT (0, FEAT), AARCH64_FEATBIT (1, FEAT) } } +#define AARCH64_FEATURE_BODY(ELT, FEAT) \ + AARCH64_FEATBIT (ELT, FEAT) +#define AARCH64_FEATURE(FEAT) \ + { { AA64_REPLICATE (REP_COMMA, AARCH64_FEATURE_BODY, FEAT) } } /* An aarch64_feature_set initializer for a specific architecture version, including all the features that are enabled by default for that architecture version. */ -#define AARCH64_ARCH_FEATURES(ARCH) \ - { { AARCH64_ARCH_##ARCH (0), AARCH64_ARCH_##ARCH (1) } } +#define AARCH64_ARCH_FEATURES_BODY(ELT, ARCH) \ + AARCH64_ARCH_##ARCH (ELT) +#define AARCH64_ARCH_FEATURES(ARCH) \ + { { AA64_REPLICATE (REP_COMMA, AARCH64_ARCH_FEATURES_BODY, ARCH) } } /* Used by AARCH64_CPU_FEATURES. */ #define AARCH64_OR_FEATURES_1(X, ARCH, F1) \ @@ -508,9 +590,11 @@ typedef struct { /* An aarch64_feature_set initializer for a CPU that implements architecture version ARCH, and additionally provides the N features listed in "...". */ +#define AARCH64_CPU_FEATURES_BODY(ELT, ARCH, N, ...) \ + AARCH64_OR_FEATURES_##N (ELT, ARCH, __VA_ARGS__) #define AARCH64_CPU_FEATURES(ARCH, N, ...) \ - { { AARCH64_OR_FEATURES_##N (0, ARCH, __VA_ARGS__), \ - AARCH64_OR_FEATURES_##N (1, ARCH, __VA_ARGS__) } } + { { AA64_REPLICATE (REP_COMMA, AARCH64_CPU_FEATURES_BODY, \ + ARCH, N, __VA_ARGS__) } } /* An aarch64_feature_set initializer for the N features listed in "...". */ #define AARCH64_FEATURES(N, ...) \ @@ -618,6 +702,8 @@ enum aarch64_opnd AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ AARCH64_OPND_IMM, /* Immediate. */ AARCH64_OPND_IMM_2, /* Immediate. */ + AARCH64_OPND_IMMP1_2, /* Immediate plus 1. */ + AARCH64_OPND_IMMS1_2, /* Immediate minus 1. */ AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ @@ -645,6 +731,7 @@ enum aarch64_opnd AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ + AARCH64_OPND_ADDR_PCREL9, /* 9-bit PC-relative address for e.g. CB<cc>. */ AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ @@ -704,12 +791,16 @@ enum aarch64_opnd AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ - AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ - AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ - AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ + AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>{, <Xm|XZR>}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #1}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #2}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #3}]. */ + AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>{, <Xm|XZR>, LSL #4}]. */ + AARCH64_OPND_SVE_ADDR_RM, /* SVE [<Xn|SP>, <Xm|XZR>]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ + AARCH64_OPND_SVE_ADDR_RM_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ @@ -824,6 +915,7 @@ enum aarch64_opnd AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ + AARCH64_OPND_SME_Zm_17, /* SVE vector register list in [20:17]. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ @@ -1051,6 +1143,8 @@ enum aarch64_insn_class floatdp3, floatimm, floatsel, + fprcvtfloat2int, + fprcvtint2float, ldst_immpost, ldst_immpre, ldst_imm9, /* immpost or immpre */ @@ -1391,7 +1485,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_OPD_PAIR_OPT (1ULL << 32) /* This instruction does not allow the full range of values that the width of fields in the assembler instruction would theoretically - allow. This impacts the constraintts on assembly but yelds no + allow. This impacts the constraints on assembly but yields no impact on disassembly. */ #define F_OPD_NARROW (1ULL << 33) /* For the instruction with size[22:23] field. */ @@ -1421,7 +1515,10 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_DP_TAG_ONLY (1ULL << 37) #define F_SUBCLASS_OTHER (F_SUBCLASS) -/* Next bit is 41. */ + +/* For LSFE instructions with size[30:31] field. */ +#define F_LSFE_SZ (1ULL << 41) +/* Next bit is 42. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1505,7 +1602,7 @@ opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND - | F_OPD_SIZE | F_RCPC3_SIZE)) != 0; + | F_OPD_SIZE | F_RCPC3_SIZE | F_LSFE_SZ )) != 0; } struct aarch64_name_value_pair @@ -1757,7 +1854,7 @@ struct aarch64_inst /* Corresponding opcode entry. */ const aarch64_opcode *opcode; - /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ + /* Condition for a truly conditional-executed instruction, e.g. b.cond. */ const aarch64_cond *cond; /* Operands information. */ @@ -1857,7 +1954,7 @@ struct aarch64_inst yet still accept a wider range of registers. AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and - AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the + AARCH64_OPDE_FATAL_SYNTAX_ERROR are only detected by GAS while the AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as only libopcodes has the information about the valid variants of each instruction. diff --git a/include/opcode/kvx.h b/include/opcode/kvx.h index aa51903..9a3c39c 100644 --- a/include/opcode/kvx.h +++ b/include/opcode/kvx.h @@ -140,13 +140,13 @@ struct kvx_pseudo_relocs struct kvx_reloc *kreloc; }; -typedef struct symbol symbolS; +struct symbol; struct pseudo_func { const char *name; - symbolS *sym; + struct symbol *sym; struct kvx_pseudo_relocs pseudo_relocs; }; diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 71ad7ff..1c64962 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2311,6 +2311,9 @@ /* Smctr/Ssctr instruction. */ #define MATCH_SCTRCLR 0x10400073 #define MASK_SCTRCLR 0xffffffff +/* Smrnmi instruction. */ +#define MATCH_MNRET 0x70200073 +#define MASK_MNRET 0xffffffff /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3699,6 +3702,21 @@ #define MASK_TH_VFMVFS 0xfe0ff07f #define MATCH_TH_VFMVSF 0x36005057 #define MASK_TH_VFMVSF 0xfff0707f +/* Vendor-specific (T-Head) XTheadVdot instructions. */ +#define MATCH_TH_VMAQA_VV 0x8000600b +#define MASK_TH_VMAQA_VV 0xfc00707f +#define MATCH_TH_VMAQA_VX 0x8400600b +#define MASK_TH_VMAQA_VX 0xfc00707f +#define MATCH_TH_VMAQAU_VV 0x8800600b +#define MASK_TH_VMAQAU_VV 0xfc00707f +#define MATCH_TH_VMAQAU_VX 0x8c00600b +#define MASK_TH_VMAQAU_VX 0xfc00707f +#define MATCH_TH_VMAQASU_VV 0x9000600b +#define MASK_TH_VMAQASU_VV 0xfc00707f +#define MATCH_TH_VMAQASU_VX 0x9400600b +#define MASK_TH_VMAQASU_VX 0xfc00707f +#define MATCH_TH_VMAQAUS_VX 0x9c00600b +#define MASK_TH_VMAQAUS_VX 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f @@ -3786,6 +3804,25 @@ #define MASK_SFVFNRCLIPXUFQF 0xfe00707f #define MATCH_SFVFNRCLIPXFQF 0x8e00505b #define MASK_SFVFNRCLIPXFQF 0xfe00707f +/* MIPS custom instruction. */ +#define MATCH_MIPS_CCMOV 0x600300b +#define MASK_MIPS_CCMOV 0x600707f +#define MATCH_MIPS_LWP 0x0010400b +#define MASK_MIPS_LWP 0x0030707f +#define MATCH_MIPS_LDP 0x0000400b +#define MASK_MIPS_LDP 0x0070707f +#define MATCH_MIPS_SWP 0x0000508b +#define MASK_MIPS_SWP 0x000071ff +#define MATCH_MIPS_SDP 0x0000500b +#define MASK_MIPS_SDP 0x000073ff +#define MATCH_MIPS_EHB 0x00301013 +#define MASK_MIPS_EHB 0xffffffff +#define MATCH_MIPS_IHB 0x00101013 +#define MASK_MIPS_IHB 0xffffffff +#define MATCH_MIPS_PAUSE 0x00501013 +#define MASK_MIPS_PAUSE 0xffffffff +#define MATCH_MIPS_PREF 0x0000000b +#define MASK_MIPS_PREF 0xe000707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -3877,6 +3914,7 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -4067,6 +4105,7 @@ #define CSR_HIE 0x604 #define CSR_HCOUNTEREN 0x606 #define CSR_HGEIE 0x607 +#define CSR_HEDELEGH 0x612 #define CSR_HTVAL 0x643 #define CSR_HIP 0x644 #define CSR_HVIP 0x645 @@ -4168,6 +4207,8 @@ #define CSR_HVIPRIO2H 0x657 #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Ssccfg CSR address. */ +#define CSR_SCOUNTINHIBIT 0x120 /* Sscsrind extension */ #define CSR_SIREG2 0x152 #define CSR_SIREG3 0x153 @@ -4254,6 +4295,8 @@ #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 +/* Ssqosid CSR addresses. */ +#define CSR_SRMCFG 0x181 #endif /* RISCV_ENCODING_H */ #ifdef DECLARE_INSN DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) @@ -4791,6 +4834,8 @@ DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT) DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT) /* Smctr/Ssctr instruction. */ DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR) +/* Smrnmi instruction */ +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ @@ -4923,6 +4968,16 @@ DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) /* Zicfilp instructions. */ DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) +/* MIPS custom instructions. */ +DECLARE_INSN(mips_ccmov, MATCH_MIPS_CCMOV, MASK_MIPS_CCMOV) +DECLARE_INSN(mips_lwp, MATCH_MIPS_LWP, MASK_MIPS_LWP) +DECLARE_INSN(mips_ldp, MATCH_MIPS_LDP, MASK_MIPS_LDP) +DECLARE_INSN(mips_swp, MATCH_MIPS_SWP, MASK_MIPS_SWP) +DECLARE_INSN(mips_sdp, MATCH_MIPS_SDP, MASK_MIPS_SDP) +DECLARE_INSN(mips_ehb, MATCH_MIPS_EHB, MASK_MIPS_EHB) +DECLARE_INSN(mips_ihb, MATCH_MIPS_IHB, MASK_MIPS_IHB) +DECLARE_INSN(mips_pause, MATCH_MIPS_PAUSE, MASK_MIPS_PAUSE) +DECLARE_INSN(mips_pref, MATCH_MIPS_PREF, MASK_MIPS_PREF) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ @@ -5011,6 +5066,7 @@ DECLARE_CSR(mconfigptr, CSR_MCONFIGPTR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_ DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) +DECLARE_CSR(medelegh, CSR_MEDELEGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT) @@ -5202,6 +5258,7 @@ DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRI /* Privileged Hypervisor CSRs. */ DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +DECLARE_CSR(hedelegh, CSR_HEDELEGH, CSR_CLASS_H_32, PRIV_SPEC_CLASS_1P13, PRIV_SPEC_CLASS_DRAFT) DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_H, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) @@ -5296,6 +5353,8 @@ DECLARE_CSR(hviprio1h, CSR_HVIPRIO1H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_ DECLARE_CSR(hviprio2h, CSR_HVIPRIO2H, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsieh, CSR_VSIEH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsiph, CSR_VSIPH, CSR_CLASS_SSAIA_AND_H_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Ssccfg CSR. */ +DECLARE_CSR(scountinhibit, CSR_SCOUNTINHIBIT, CSR_CLASS_SSCCFG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Sscsrind extension */ DECLARE_CSR(sireg2, CSR_SIREG2, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(sireg3, CSR_SIREG3, CSR_CLASS_SSCSRIND, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) @@ -5393,6 +5452,8 @@ DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_N DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Ssqosid CSR. */ +DECLARE_CSR(srmcfg, CSR_SRMCFG, CSR_CLASS_SSQOSID, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) #endif /* DECLARE_CSR */ #ifdef DECLARE_CSR_ALIAS DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6bcea63..2b146af 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -132,6 +132,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1) | (RV_IMM_SIGN_N(x, 20, 5) << 5)) #define EXTRACT_CV_SIMD_UIMM6(x) \ ((RV_X(x, 25, 1)) | (RV_X(x, 20, 5) << 1)) +/* Vendor-specific (MIPS) extract macros. */ +#define EXTRACT_MIPS_LWP_IMM(x) \ + (RV_X(x, 22, 5) << 2) +#define EXTRACT_MIPS_LDP_IMM(x) \ + (RV_X(x, 23, 4) << 3) +#define EXTRACT_MIPS_SWP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2)) +#define EXTRACT_MIPS_SDP_IMM(x) \ + ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3)) #define ENCODE_ITYPE_IMM(x) \ (RV_X(x, 0, 12) << 20) @@ -200,6 +209,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) #define ENCODE_CV_SIMD_UIMM6(x) \ ((RV_X(x, 0, 1) << 25) | (RV_X(x, 1, 5) << 20)) +/* Vendor-specific (MIPS) encode macros. */ +#define ENCODE_MIPS_LWP_IMM(x) \ + (RV_X(x, 2, 5) << 22) +#define ENCODE_MIPS_LDP_IMM(x) \ + (RV_X(x, 3, 4) << 23) +#define ENCODE_MIPS_SWP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 2, 3) << 9)) +#define ENCODE_MIPS_SDP_IMM(x) \ + ((RV_X(x, 5, 2) << 25) | (RV_X(x, 3, 2) << 10)) #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) @@ -383,8 +401,27 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_XSO1 0x1 #define OP_SH_XSO1 26 +/* MIPS fields. */ +#define OP_MASK_MIPS_IMM9 0x1ff +#define OP_SH_MIPS_IMM9 20 +#define OP_MASK_MIPS_HINT 0x1f +#define OP_SH_MIPS_HINT 7 +#define OP_MASK_MIPS_LWP_OFFSET 0x1f +#define OP_SH_MIPS_LWP_OFFSET 22 +#define OP_MASK_MIPS_LDP_OFFSET 0xf +#define OP_SH_MIPS_LDP_OFFSET 23 +#define OP_MASK_MIPS_SWP_OFFSET9 0x7 +#define OP_SH_MIPS_SWP_OFFSET9 9 +#define OP_MASK_MIPS_SWP_OFFSET25 0x3 +#define OP_SH_MIPS_SWP_OFFSET25 25 +#define OP_MASK_MIPS_SDP_OFFSET10 0x3 +#define OP_SH_MIPS_SDP_OFFSET10 10 +#define OP_MASK_MIPS_SDP_OFFSET25 0x3 +#define OP_SH_MIPS_SDP_OFFSET25 25 + /* ABI names for selected x-registers. */ +#define X_ZERO 0 #define X_RA 1 #define X_SP 2 #define X_GP 3 @@ -526,6 +563,9 @@ enum riscv_insn_class INSN_CLASS_ZCMP, INSN_CLASS_ZCMT, INSN_CLASS_SMCTR_OR_SSCTR, + INSN_CLASS_ZILSD, + INSN_CLASS_ZCLSD, + INSN_CLASS_SMRNMI, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, @@ -554,6 +594,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, + INSN_CLASS_XTHEADVDOT, INSN_CLASS_XTHEADZVAMO, INSN_CLASS_XVENTANACONDOPS, INSN_CLASS_XSFVCP, @@ -561,6 +602,10 @@ enum riscv_insn_class INSN_CLASS_XSFVQMACCQOQ, INSN_CLASS_XSFVQMACCDOD, INSN_CLASS_XSFVFNRCLIPXFQF, + INSN_CLASS_XMIPSCBOP, + INSN_CLASS_XMIPSCMOV, + INSN_CLASS_XMIPSEXECTL, + INSN_CLASS_XMIPSLSP, }; /* This structure holds information for a particular instruction. */ |