diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9da1def..39d5067 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -240,6 +240,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_LUT, /* Branch Record Buffer Extension */ AARCH64_FEATURE_BRBE, + /* SME LUTv2 instructions. */ + AARCH64_FEATURE_SME_LUTv2, AARCH64_NUM_FEATURES }; @@ -760,10 +762,12 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zdnx4_STRIDED, /* SVE vector register list from [4:2]*4. */ AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ + AARCH64_OPND_SME_Znx2_BIT_INDEX, /* SVE vector register list encoding a bit index from [9:6]*2. */ AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ @@ -812,6 +816,7 @@ enum aarch64_opnd AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */ + AARCH64_OPND_SME_ZT0_INDEX2_12, /* ZT0[<imm>], bits [13:12]. */ AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ @@ -1003,6 +1008,7 @@ enum aarch64_insn_class sme_shift, sme_size_12_bhs, sme_size_12_hs, + sme_size_12_b, sme_size_22, sme_size_22_hsd, sme_sz_23, |