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| author | saurabh.jha@arm.com <saurabh.jha@arm.com> | 2024-06-21 16:30:59 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-06-24 15:00:40 +0100 |
| commit | adea87e275802fb7afe7acefae1477f692c48969 (patch) | |
| tree | 8b7ef7d13df4366cfb917425a09bb3e95cd14ce9 /include/opcode | |
| parent | c702f1ad8a6a51b9c74445c77e1f6e822ba9293b (diff) | |
| download | gdb-adea87e275802fb7afe7acefae1477f692c48969.zip gdb-adea87e275802fb7afe7acefae1477f692c48969.tar.gz gdb-adea87e275802fb7afe7acefae1477f692c48969.tar.bz2 | |
gas, aarch64: Add SME2 lutv2 extension
Introduces instructions for the SME2 lutv2 extension for AArch64. They
are documented in the following document:
* ARM DDI0602
For both luti4 instructions, we introduced an operand called
SME_Znx2_BIT_INDEX. We use the existing function parse_vector_reg_list
for parsing but modified that function so that it can accept operands
without qualifiers and rejects instructions that have operands with
qualifiers but are not supposed to have operands with qualifiers.
For disassembly, we modified print_register_list so that it could
accept register lists without qualifiers.
For one luti4 instruction, we introduced a SME_Zdnx4_STRIDED. It is
similar to SME_Ztx4_STRIDED and we could use existing code for parsing,
encoding, and disassembly.
For movt instruction, we introduced an operand called SME_ZT0_INDEX2_12.
This is a ZT0 register with a bit index encoded in [13:12]. It is
similar to SME_ZT0_INDEX.
We also introduced an iclass named sme_size_12_b so that we can encode
size bits [13:12] correctly when only 'b' is allowed as qualifier.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9da1def..39d5067 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -240,6 +240,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_LUT, /* Branch Record Buffer Extension */ AARCH64_FEATURE_BRBE, + /* SME LUTv2 instructions. */ + AARCH64_FEATURE_SME_LUTv2, AARCH64_NUM_FEATURES }; @@ -760,10 +762,12 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zdnx4_STRIDED, /* SVE vector register list from [4:2]*4. */ AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ + AARCH64_OPND_SME_Znx2_BIT_INDEX, /* SVE vector register list encoding a bit index from [9:6]*2. */ AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ @@ -812,6 +816,7 @@ enum aarch64_opnd AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */ + AARCH64_OPND_SME_ZT0_INDEX2_12, /* ZT0[<imm>], bits [13:12]. */ AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ @@ -1003,6 +1008,7 @@ enum aarch64_insn_class sme_shift, sme_size_12_bhs, sme_size_12_hs, + sme_size_12_b, sme_size_22, sme_size_22_hsd, sme_sz_23, |