diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/ChangeLog-2020 | 8 | ||||
| -rw-r--r-- | gas/ChangeLog-9295 | 2 | ||||
| -rw-r--r-- | gas/config/tc-i386.c | 2 | ||||
| -rw-r--r-- | gas/config/tc-riscv.c | 4 | ||||
| -rw-r--r-- | gas/config/tc-s390.c | 4 | ||||
| -rw-r--r-- | gas/doc/c-i386.texi | 2 | ||||
| -rw-r--r-- | gas/doc/c-s390.texi | 2 |
8 files changed, 20 insertions, 12 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 71bdd2d..155ec7e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2021-01-01 Nicolas Boulenguez <nicolas@debian.org> + + * config/tc-i386.c: Correct comment spelling. + * config/tc-riscv.c: Likewise. + * config/tc-s390.c: Correct comment grammar. + * doc/c-i386.texi: Correct spelling. + * doc/c-s390.texi: Correct grammar. + 2021-01-01 Alan Modra <amodra@gmail.com> Update year range in copyright notice of all files. diff --git a/gas/ChangeLog-2020 b/gas/ChangeLog-2020 index 8cdf93b..369cfee 100644 --- a/gas/ChangeLog-2020 +++ b/gas/ChangeLog-2020 @@ -3436,7 +3436,7 @@ gas/ChangeLog: prefix into i.rex for SSE2AVX templates. (set_rex_vrex): New helper. (build_modrm_byte): Use it. - * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict + * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explicit REX prefixes. * testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations. @@ -3462,7 +3462,7 @@ gas/ChangeLog: * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to explicit_priv_attr. It used to indicate CSR or priv instructions are - explictly used. + explicitly used. (riscv_is_priv_insn): Return True if it is a privileged instruction. (riscv_ip): Call riscv_is_priv_insn to check whether the instruction is privileged or not. If it is, then set explicit_priv_attr to TRUE. @@ -3665,7 +3665,7 @@ gas/ChangeLog: 2020-06-05 Nelson Chu <nelson.chu@sifive.com> * config/tc-riscv.c (explicit_csr): New static boolean. - Used to indicate CSR are explictly used. + Used to indicate CSR are explicitly used. (riscv_ip): Set explicit_csr to TRUE if any CSR is used. (riscv_write_out_attrs): If we already have set elf priv attributes, then generate them. Otherwise, don't generate @@ -4324,7 +4324,7 @@ gas/ChangeLog: (md_parse_option): Change -mlfence-before-ret=[none|not|or] to -mlfence-before-ret=[none/not/or/shl/yes]. Enable -mlfence-before-ret=shl when - -mlfence-beofre-indirect-branch=all and no explict -mlfence-before-ret option. + -mlfence-beofre-indirect-branch=all and no explicit -mlfence-before-ret option. (md_show_usage): Ditto. * doc/c-i386.texi: Ditto. * testsuite/gas/i386/i386.exp: Add new testcases. diff --git a/gas/ChangeLog-9295 b/gas/ChangeLog-9295 index c84475b..2ea3bb3 100644 --- a/gas/ChangeLog-9295 +++ b/gas/ChangeLog-9295 @@ -1931,7 +1931,7 @@ Tue Aug 1 17:35:26 1995 Ian Lance Taylor <ian@cygnus.com> Tue Aug 1 11:35:18 1995 steve chamberlain <sac@slash.cygnus.com> * config/tc-sh.c (md_convert_frag): Make some error messages - more explict. + more explicit. Mon Jul 31 21:40:47 1995 Ken Raeburn <raeburn@cygnus.com> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a04fb36..9a2dfc9 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7156,7 +7156,7 @@ process_suffix (void) break; case 0: - /* Select word/dword/qword operation with explict data sizing prefix + /* Select word/dword/qword operation with explicit data sizing prefix when there are no suitable register operands. */ if (i.tm.opcode_modifier.w && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a7a6aa3..e938a88 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -401,10 +401,10 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; /* Indicate we are already assemble any instructions or not. */ static bfd_boolean start_assemble = FALSE; -/* Indicate ELF attributes are explictly set. */ +/* Indicate ELF attributes are explicitly set. */ static bfd_boolean explicit_attr = FALSE; -/* Indicate CSR or priv instructions are explictly used. */ +/* Indicate CSR or priv instructions are explicitly used. */ static bfd_boolean explicit_priv_attr = FALSE; /* Macros for encoding relaxation state for RVC branches and far jumps. */ diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 0fcb45e..c6daef9 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -1900,7 +1900,7 @@ s390_literals (int ignore ATTRIBUTE_UNUSED) #define MAX_HISTORY 100 -/* The .machine pseudo op allows to switch to a different CPU level in +/* The .machine pseudo op allows one to switch to a different CPU level in the asm listing. The current CPU setting can be stored on a stack with .machine push and restored with .machine pop. */ @@ -1991,7 +1991,7 @@ s390_machine (int ignore ATTRIBUTE_UNUSED) demand_empty_rest_of_line (); } -/* The .machinemode pseudo op allows to switch to a different +/* The .machinemode pseudo op allows one to switch to a different architecture mode in the asm listing. The current architecture mode setting can be stored on a stack with .machinemode push and restored with .machinemode pop. */ diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 7bec686..cb996c8 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -513,7 +513,7 @@ before indirect near branch instructions. before indirect near branch via register and issue a warning before indirect near branch via memory. It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when -there's no explict @option{-mlfence-before-ret=}. +there's no explicit @option{-mlfence-before-ret=}. @option{-mlfence-before-indirect-branch=@var{register}} will generate lfence before indirect near branch via register. @option{-mlfence-before-indirect-branch=@var{memory}} will issue a diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi index d7553f1..c1b46a1 100644 --- a/gas/doc/c-s390.texi +++ b/gas/doc/c-s390.texi @@ -905,7 +905,7 @@ except instructions from the HTM facility. @cindex @code{.machinemode} directive, s390 @item .machinemode string -This directive allows to change the architecture mode for which code +This directive allows one to change the architecture mode for which code is being generated. @code{string} may be @code{esa}, @code{zarch}, @code{zarch_nohighgprs}, @code{push}, or @code{pop}. @code{.machinemode zarch_nohighgprs} can be used to prevent the |