diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/config/tc-arm.c | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vldr-bad-3.l | 34 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vldr-bad-3.s | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vstrldr-1.d | 17 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/mve-vstrldr-1.s | 13 |
5 files changed, 81 insertions, 6 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 7760d18..2f394ba 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -17282,6 +17282,7 @@ static void do_mve_vstr_vldr_RQ (int size, int elsize, int load) { unsigned os = inst.operands[1].imm >> 5; + unsigned type = inst.vectype.el[0].type; constraint (os != 0 && size == 8, _("can not shift offsets when accessing less than half-word")); constraint (os && os != neon_logbits (size), @@ -17312,15 +17313,14 @@ do_mve_vstr_vldr_RQ (int size, int elsize, int load) constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), _("destination register and offset register may not be" " the same")); - constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned, + constraint (size == elsize && type == NT_signed, BAD_EL_TYPE); + constraint (size != elsize && type != NT_unsigned && type != NT_signed, BAD_EL_TYPE); - constraint (inst.vectype.el[0].type != NT_unsigned - && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE); - inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28; + inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28; } else { - constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE); + constraint (type != NT_untyped, BAD_EL_TYPE); } inst.instruction |= 1 << 23; diff --git a/gas/testsuite/gas/arm/mve-vldr-bad-3.l b/gas/testsuite/gas/arm/mve-vldr-bad-3.l index 024822d..4b773b1 100644 --- a/gas/testsuite/gas/arm/mve-vldr-bad-3.l +++ b/gas/testsuite/gas/arm/mve-vldr-bad-3.l @@ -133,3 +133,37 @@ [^:]*:134: Error: syntax error -- `vldrweq.32 q0,\[r0\]' [^:]*:135: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.32 q0,\[r0\]' [^:]*:137: Error: instruction missing MVE vector predication code -- `vldrw.32 q0,\[r0\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.16 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.32 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.64 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.f16 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.f32 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.f64 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.p16 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.p32 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.p64 q0,\[r2,q3\]' +[^:]*:140: Error: bad element type for instruction -- `vldrb.s8 q0,\[r2,q3\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.8 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.32 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.64 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.f32 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.f64 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.p32 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.p64 q0,\[r2,q3,uxtw#1\]' +[^:]*:143: Error: bad element type for instruction -- `vldrh.s16 q0,\[r2,q3,uxtw#1\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.8 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.16 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.64 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.f16 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.f64 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.p16 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.p64 q0,\[r2,q3,uxtw#2\]' +[^:]*:146: Error: bad element type for instruction -- `vldrw.s32 q0,\[r2,q3,uxtw#2\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.8 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.16 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.32 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.f16 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.f32 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.p16 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.p32 q0,\[r2,q3,uxtw#3\]' +[^:]*:149: Error: bad element type for instruction -- `vldrd.s64 q0,\[r2,q3,uxtw#3\]' diff --git a/gas/testsuite/gas/arm/mve-vldr-bad-3.s b/gas/testsuite/gas/arm/mve-vldr-bad-3.s index 3b3fd61..3712cad 100644 --- a/gas/testsuite/gas/arm/mve-vldr-bad-3.s +++ b/gas/testsuite/gas/arm/mve-vldr-bad-3.s @@ -135,4 +135,15 @@ vldrweq.32 q0, [r0] vldrwt.32 q0, [r0] vpst vldrw.32 q0, [r0] - +.irp op1, 16, 32, 64, f16, f32, f64, p16, p32, p64, s8 +vldrb.\op1 q0, [r2, q3] +.endr +.irp op1, 8, 32, 64, f32, f64, p32, p64, s16 +vldrh.\op1 q0, [r2, q3, uxtw #1] +.endr +.irp op1, 8, 16, 64, f16, f64, p16, p64, s32 +vldrw.\op1 q0, [r2, q3, uxtw #2] +.endr +.irp op1, 8, 16, 32, f16, f32, p16, p32, s64 +vldrd.\op1 q0, [r2, q3, uxtw #3] +.endr diff --git a/gas/testsuite/gas/arm/mve-vstrldr-1.d b/gas/testsuite/gas/arm/mve-vstrldr-1.d index ca3d97c..0bffd2e 100644 --- a/gas/testsuite/gas/arm/mve-vstrldr-1.d +++ b/gas/testsuite/gas/arm/mve-vstrldr-1.d @@ -7561,3 +7561,20 @@ Disassembly of section .text: [^>]*> fe71 8f4d vpste [^>]*> fc93 6fdb vldrdt.u64 q3, \[r3, q5, uxtw #3\] [^>]*> fc97 efd9 vldrde.u64 q7, \[r7, q4, uxtw #3\] +[^>]*> fc92 0e06 vldrb.u8 q0, \[r2, q3\] +[^>]*> ec92 0e86 vldrb.s16 q0, \[r2, q3\] +[^>]*> fc92 0e06 vldrb.u8 q0, \[r2, q3\] +[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\] +[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\] +[^>]*> ec92 0f17 vldrh.s32 q0, \[r2, q3, uxtw #1\] +[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\] +[^>]*> fc92 0e97 vldrh.u16 q0, \[r2, q3, uxtw #1\] +[^>]*> fc92 0f17 vldrh.u32 q0, \[r2, q3, uxtw #1\] +[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\] +[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\] +[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\] +[^>]*> fc92 0f47 vldrw.u32 q0, \[r2, q3, uxtw #2\] +[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\] +[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\] +[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\] +[^>]*> fc92 0fd7 vldrd.u64 q0, \[r2, q3, uxtw #3\] diff --git a/gas/testsuite/gas/arm/mve-vstrldr-1.s b/gas/testsuite/gas/arm/mve-vstrldr-1.s index 3911216..d6d11cc 100644 --- a/gas/testsuite/gas/arm/mve-vstrldr-1.s +++ b/gas/testsuite/gas/arm/mve-vstrldr-1.s @@ -116,3 +116,16 @@ vldrde.u64 q2, [r0, q1] vpste vldrdt.u64 q3, [r3, q5, UXTW #3] vldrde.u64 q7, [r7, q4, UXTW #3] + +.irp dt, u8, s16, 8 +vldrb.\dt q0, [r2, q3] +.endr +.irp dt, 16, u16, s32, f16, p16, u32 +vldrh.\dt q0, [r2, q3, UXTW #1] +.endr +.irp dt, 32, u32, f32, p32 +vldrw.\dt q0, [r2, q3, UXTW #2] +.endr +.irp dt, 64, u64, f64, p64 +vldrd.\dt q0, [r2, q3, UXTW #3] +.endr |