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-rw-r--r--gas/ChangeLog10
-rw-r--r--gas/config/tc-arm.c30
-rw-r--r--gas/testsuite/gas/arm/cde-scalar.s8
-rw-r--r--gas/testsuite/gas/arm/cde-warnings.l18
-rw-r--r--gas/testsuite/gas/arm/cde-warnings.s30
5 files changed, 50 insertions, 46 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ddce181..601fb50 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2020-02-26 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * config/tc-arm.c (enum pred_instruction_type): Remove
+ NEUTRAL_IT_NO_VPT_INSN predication type.
+ (cxn_handle_predication): Modify to require condition suffixes.
+ (handle_pred_state): Remove NEUTRAL_IT_NO_VPT_INSN cases.
+ * testsuite/gas/arm/cde-scalar.s: Update test.
+ * testsuite/gas/arm/cde-warnings.l: Update test.
+ * testsuite/gas/arm/cde-warnings.s: Update test.
+
2020-02-26 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (reg_expected_msgs[REG_TYPE_RNB]): Don't use
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 30c69fb..59b1f6b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -506,8 +506,6 @@ enum pred_instruction_type
MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
a predication code. */
MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
- NEUTRAL_IT_NO_VPT_INSN, /* Instruction that can be either inside or outside
- an IT block, but must not be in a VPT block. */
};
/* The maximum number of operands we need. */
@@ -21674,15 +21672,13 @@ cde_handle_coproc (void)
static void
cxn_handle_predication (bfd_boolean is_accum)
{
- /* This function essentially checks for a suffix, not whether the instruction
- is inside an IT block or not.
- The CX* instructions should never have a conditional suffix -- this is not
- mentioned in the syntax. */
- if (conditional_insn ())
+ if (is_accum && conditional_insn ())
+ set_pred_insn_type (INSIDE_IT_INSN);
+ else if (conditional_insn ())
+ /* conditional_insn essentially checks for a suffix, not whether the
+ instruction is inside an IT block or not.
+ The non-accumulator versions should not have suffixes. */
inst.error = BAD_SYNTAX;
- /* Here we ensure that if the current element */
- else if (is_accum)
- set_pred_insn_type (NEUTRAL_IT_NO_VPT_INSN);
else
set_pred_insn_type (OUTSIDE_PRED_INSN);
}
@@ -22980,7 +22976,6 @@ handle_pred_state (void)
gas_assert (0);
case IF_INSIDE_IT_LAST_INSN:
case NEUTRAL_IT_INSN:
- case NEUTRAL_IT_NO_VPT_INSN:
break;
case VPT_INSN:
@@ -23044,12 +23039,6 @@ handle_pred_state (void)
close_automatic_it_block ();
break;
- case NEUTRAL_IT_NO_VPT_INSN:
- if (now_pred.type == VECTOR_PRED)
- {
- inst.error = BAD_NO_VPT;
- break;
- }
/* Fallthrough. */
case NEUTRAL_IT_INSN:
now_pred.block_length++;
@@ -23234,13 +23223,6 @@ handle_pred_state (void)
}
break;
- case NEUTRAL_IT_NO_VPT_INSN:
- if (now_pred.type == VECTOR_PRED)
- {
- inst.error = BAD_NO_VPT;
- break;
- }
- /* Fallthrough. */
case NEUTRAL_IT_INSN:
/* The BKPT instruction is unconditional even in a IT or VPT
block. */
diff --git a/gas/testsuite/gas/arm/cde-scalar.s b/gas/testsuite/gas/arm/cde-scalar.s
index ac188a3..43f6f72 100644
--- a/gas/testsuite/gas/arm/cde-scalar.s
+++ b/gas/testsuite/gas/arm/cde-scalar.s
@@ -37,7 +37,7 @@ cx1a p0, APSR_nzcv, #0
cx1a p0, r9, #0
it ne
-cx1a p0, r0, #0
+cx1ane p0, r0, #0
# cx1d{a} encoding of following form:
# 111a111000iiiiiidddd0pppi1iiiiii
@@ -65,7 +65,7 @@ cx1da p7, r0, r1, #0
cx1da p0, r10, r11, #0
it ne
-cx1da p0, r0, r1, #0
+cx1dane p0, r0, r1, #0
# cx2{a} Has arguments of the following form:
@@ -100,7 +100,7 @@ cx2a p0, r0, APSR_nzcv, #0
cx2a p0, r0, r9, #0
it ne
-cx2a p0, r0, r0, #0
+cx2ane p0, r0, r0, #0
# cx2d{a} encoding has following form:
# 111a111001iinnnndddd0pppi1iiiiii
@@ -168,7 +168,7 @@ cx3a p0, r0, r0, APSR_nzcv, #0
cx3a p0, r0, r0, r9, #0
it ne
-cx3a p0, r0, r0, r0, #0
+cx3ane p0, r0, r0, r0, #0
# cx3d{a} encoding has following form:
# 111a11101iiinnnnmmmm0pppi1iidddd
diff --git a/gas/testsuite/gas/arm/cde-warnings.l b/gas/testsuite/gas/arm/cde-warnings.l
index d0380d9..5c69850 100644
--- a/gas/testsuite/gas/arm/cde-warnings.l
+++ b/gas/testsuite/gas/arm/cde-warnings.l
@@ -11,7 +11,8 @@
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx1a p0,r13,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1 p0,r0,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx1ne p0,r0,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx1ane p0,r0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1a p0,r0,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx1aeq p0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1 p1,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1a p1,r0,#0'
[^ :]+:[0-9]+: Error: constant expression required -- `cx1 p0,r0,r0,#0'
@@ -35,8 +36,9 @@
[^ :]+:[0-9]+: Error: Register must be an even register between r0-r10\. -- `cx1d p0,r13,r14,#0'
[^ :]+:[0-9]+: Error: Register must be an even register between r0-r10\. -- `cx1da p0,r13,r14,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1d p0,r0,r1,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx1da p0,r0,r1,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx1dne p0,r0,r1,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx1dane p0,r0,r1,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx1daeq p0,r0,r1,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1d p1,r0,r1,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx1da p1,r0,r1,#0'
[^ :]+:[0-9]+: Error: cx1d requires consecutive destination registers\. -- `cx1d p0,r0,r2,#0'
@@ -60,8 +62,9 @@
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2 p0,r0,r13,#0'
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2a p0,r0,r13,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2 p0,r0,r0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2a p0,r0,r0,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx2ne p0,r0,r0,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx2ane p0,r0,r0,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx2aeq p0,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2 p1,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2a p1,r0,r0,#0'
[^ :]+:[0-9]+: Error: constant expression required -- `cx2 p0,r0,r0,r0,#0'
@@ -93,8 +96,9 @@
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2d p0,r0,r1,r15,#0'
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx2da p0,r0,r1,r15,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2d p0,r0,r1,r0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx2da p0,r0,r1,r0,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx2dne p0,r0,r1,r0,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx2dane p0,r0,r1,r0,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx2daeq p0,r0,r1,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2d p1,r0,r1,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx2da p1,r0,r1,r0,#0'
[^ :]+:[0-9]+: Error: cx2d requires consecutive destination registers\. -- `cx2d p0,r0,r2,r0,#0'
@@ -122,8 +126,9 @@
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3 p0,r0,r0,r13,#0'
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3a p0,r0,r0,r13,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3 p0,r0,r0,r0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3a p0,r0,r0,r0,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx3ne p0,r0,r0,r0,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx3ane p0,r0,r0,r0,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx3aeq p0,r0,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3 p1,r0,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3a p1,r0,r0,r0,#0'
[^ :]+:[0-9]+: Error: constant expression required -- `cx3 p0,r0,r0,r0,r0,#0'
@@ -163,8 +168,9 @@
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3d p0,r0,r1,r0,r15,#0'
[^ :]+:[0-9]+: Error: Register must be r0-r14 except r13, or APSR_nzcv\. -- `cx3da p0,r0,r1,r0,r15,#0'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3d p0,r0,r1,r0,r0,#0'
+[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `cx3da p0,r0,r1,r0,r0,#0'
[^ :]+:[0-9]+: Error: syntax error -- `cx3dne p0,r0,r1,r0,r0,#0'
-[^ :]+:[0-9]+: Error: syntax error -- `cx3dane p0,r0,r1,r0,r0,#0'
+[^ :]+:[0-9]+: Error: incorrect condition in IT block -- `cx3daeq p0,r0,r1,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3d p1,r0,r1,r0,r0,#0'
[^ :]+:[0-9]+: Error: coprocessor for insn is not enabled for cde -- `cx3da p1,r0,r1,r0,r0,#0'
[^ :]+:[0-9]+: Error: cx3d requires consecutive destination registers\. -- `cx3d p0,r0,r2,r0,r0,#0'
diff --git a/gas/testsuite/gas/arm/cde-warnings.s b/gas/testsuite/gas/arm/cde-warnings.s
index 34b923f..d1d9840 100644
--- a/gas/testsuite/gas/arm/cde-warnings.s
+++ b/gas/testsuite/gas/arm/cde-warnings.s
@@ -23,10 +23,11 @@ cx1a p0, r16, #0
cx1 p0, r13, #0
cx1a p0, r13, #0
-ittt ne
+itttt ne
cx1 p0, r0, #0
cx1ne p0, r0, #0
-cx1ane p0, r0, #0
+cx1a p0, r0, #0
+cx1aeq p0, r0, #0
cx1 p1, r0, #0
cx1a p1, r0, #0
@@ -73,10 +74,11 @@ cx1da p0, r9, r10, #0
cx1d p0, r13, r14, #0
cx1da p0, r13, r14, #0
-ittt ne
+itttt ne
cx1d p0, r0, r1, #0
+cx1da p0, r0, r1, #0
cx1dne p0, r0, r1, #0
-cx1dane p0, r0, r1, #0
+cx1daeq p0, r0, r1, #0
cx1d p1, r0, r1, #0
cx1da p1, r0, r1, #0
@@ -122,10 +124,11 @@ cx2a p0, r13, r0, #0
cx2 p0, r0, r13, #0
cx2a p0, r0, r13, #0
-ittt ne
+itttt ne
cx2 p0, r0, r0, #0
+cx2a p0, r0, r0, #0
cx2ne p0, r0, r0, #0
-cx2ane p0, r0, r0, #0
+cx2aeq p0, r0, r0, #0
cx2 p1, r0, r0, #0
cx2a p1, r0, r0, #0
@@ -184,10 +187,11 @@ cx2da p0, r0, r1, r13, #0
cx2d p0, r0, r1, r15, #0
cx2da p0, r0, r1, r15, #0
-ittt ne
+itttt ne
cx2d p0, r0, r1, r0, #0
+cx2da p0, r0, r1, r0, #0
cx2dne p0, r0, r1, r0, #0
-cx2dane p0, r0, r1, r0, #0
+cx2daeq p0, r0, r1, r0, #0
cx2d p1, r0, r1, r0, #0
cx2da p1, r0, r1, r0, #0
@@ -240,10 +244,11 @@ cx3a p0, r0, r13, r0, #0
cx3 p0, r0, r0, r13, #0
cx3a p0, r0, r0, r13, #0
-ittt ne
+itttt ne
cx3 p0, r0, r0, r0, #0
+cx3a p0, r0, r0, r0, #0
cx3ne p0, r0, r0, r0, #0
-cx3ane p0, r0, r0, r0, #0
+cx3aeq p0, r0, r0, r0, #0
cx3 p1, r0, r0, r0, #0
cx3a p1, r0, r0, r0, #0
@@ -317,10 +322,11 @@ cx3da p0, r0, r1, r15, r0, #0
cx3d p0, r0, r1, r0, r15, #0
cx3da p0, r0, r1, r0, r15, #0
-ittt ne
+itttt ne
cx3d p0, r0, r1, r0, r0, #0
+cx3da p0, r0, r1, r0, r0, #0
cx3dne p0, r0, r1, r0, r0, #0
-cx3dane p0, r0, r1, r0, r0, #0
+cx3daeq p0, r0, r1, r0, r0, #0
cx3d p1, r0, r1, r0, r0, #0
cx3da p1, r0, r1, r0, r0, #0
generated by cgit v1.1 at 2024-11-26 03:41:50 +0000