diff options
Diffstat (limited to 'gas')
19 files changed, 4293 insertions, 14 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 8985edf..0b11bb3 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -61,10 +61,11 @@ enum riscv_csr_class CSR_CLASS_NONE, CSR_CLASS_I, - CSR_CLASS_I_32, /* rv32 only */ - CSR_CLASS_F, /* f-ext only */ - CSR_CLASS_ZKR, /* zkr only */ - CSR_CLASS_DEBUG /* debug CSR */ + CSR_CLASS_I_32, /* rv32 only */ + CSR_CLASS_F, /* f-ext only */ + CSR_CLASS_ZKR, /* zkr only */ + CSR_CLASS_V, /* rvv only */ + CSR_CLASS_DEBUG /* debug CSR */ }; /* This structure holds all restricted conditions for a CSR. */ @@ -773,6 +774,8 @@ enum reg_class { RCLASS_GPR, RCLASS_FPR, + RCLASS_VECR, + RCLASS_VECM, RCLASS_MAX, RCLASS_CSR @@ -880,6 +883,10 @@ riscv_csr_address (const char *csr_name, result = riscv_subset_supports (&riscv_rps_as, "zkr"); need_check_version = false; break; + case CSR_CLASS_V: + result = riscv_subset_supports (&riscv_rps_as, "v"); + need_check_version = false; + break; case CSR_CLASS_DEBUG: need_check_version = false; break; @@ -1068,18 +1075,42 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'F': /* Compressed funct for .insn directive. */ switch (*++oparg) { - case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; - case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; - case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; - case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; - default: - goto unknown_validate_operand; + case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; + case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; + case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; + case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; + default: + goto unknown_validate_operand; } break; default: goto unknown_validate_operand; } break; + case 'V': /* RVV */ + switch (*++oparg) + { + case 'd': + case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break; + case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break; + case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break; + case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; + case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1); + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; + case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD); + USE_BITS (OP_MASK_VS1, OP_SH_VS1); + USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; + case '0': break; + case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break; + case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break; + case 'i': + case 'j': + case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; + case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; + default: + goto unknown_validate_operand; + } + break; case ',': break; case '(': break; case ')': break; @@ -1221,6 +1252,8 @@ md_begin (void) hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); + hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR); + hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM); /* Add "fp" as an alias for "s0". */ hash_reg_name (RCLASS_GPR, "fp", 8); @@ -1360,6 +1393,39 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) fmtStart = fmt; switch (*fmt) { + case 'V': /* RVV */ + switch (*++fmt) + { + case 'd': + INSERT_OPERAND (VD, insn, va_arg (args, int)); + continue; + case 's': + INSERT_OPERAND (VS1, insn, va_arg (args, int)); + continue; + case 't': + INSERT_OPERAND (VS2, insn, va_arg (args, int)); + continue; + case 'm': + { + int reg = va_arg (args, int); + if (reg == -1) + { + INSERT_OPERAND (VMASK, insn, 1); + continue; + } + else if (reg == 0) + { + INSERT_OPERAND (VMASK, insn, 0); + continue; + } + else + goto unknown_macro_argument; + } + default: + goto unknown_macro_argument; + } + break; + case 'd': INSERT_OPERAND (RD, insn, va_arg (args, int)); continue; @@ -1382,6 +1448,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) case ',': continue; default: + unknown_macro_argument: as_fatal (_("internal: invalid macro argument `%s'"), fmtStart); } break; @@ -1570,6 +1637,95 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) } } +/* Expand RISC-V Vector macros into one or more instructions. */ + +static void +vector_macro (struct riscv_cl_insn *ip) +{ + int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD; + int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1; + int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2; + int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK; + int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6; + int mask = ip->insn_mo->mask; + + switch (mask) + { + case M_VMSGE: + if (vm) + { + /* Unmasked. */ + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1); + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); + break; + } + if (vtemp != 0) + { + /* Masked. Have vtemp to avoid overlap constraints. */ + if (vd == vm) + { + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); + } + else + { + /* Preserve the value of vd if not updating by vm. */ + macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); + } + } + else if (vd != vm) + { + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm); + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); + } + else + as_bad (_("must provide temp if destination overlaps mask")); + break; + + case M_VMSGEU: + if (vm) + { + /* Unmasked. */ + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1); + macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); + break; + } + if (vtemp != 0) + { + /* Masked. Have vtemp to avoid overlap constraints. */ + if (vd == vm) + { + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); + } + else + { + /* Preserve the value of vd if not updating by vm. */ + macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); + macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); + macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); + } + } + else if (vd != vm) + { + /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm); + macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); + } + else + as_bad (_("must provide temp if destination overlaps mask")); + break; + + default: + break; + } +} + /* Expand RISC-V assembly macros into one or more instructions. */ static void @@ -1708,6 +1864,11 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, riscv_ext (rd, rs1, xlen - 16, true); break; + case M_VMSGE: + case M_VMSGEU: + vector_macro (ip); + break; + default: as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); break; @@ -1879,6 +2040,66 @@ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, return my_getSmallExpression (ep, reloc, str, percent_op); } +/* Parse string STR as a vsetvli operand. Store the expression in *EP. + On exit, EXPR_END points to the first character after the expression. */ + +static void +my_getVsetvliExpression (expressionS *ep, char *str) +{ + unsigned int vsew_value = 0, vlmul_value = 0; + unsigned int vta_value = 0, vma_value = 0; + bfd_boolean vsew_found = FALSE, vlmul_found = FALSE; + bfd_boolean vta_found = FALSE, vma_found = FALSE; + + if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value)) + { + if (*str == ',') + ++str; + if (vsew_found) + as_bad (_("multiple vsew constants")); + vsew_found = TRUE; + } + if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value)) + { + if (*str == ',') + ++str; + if (vlmul_found) + as_bad (_("multiple vlmul constants")); + vlmul_found = TRUE; + } + if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value)) + { + if (*str == ',') + ++str; + if (vta_found) + as_bad (_("multiple vta constants")); + vta_found = TRUE; + } + if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value)) + { + if (*str == ',') + ++str; + if (vma_found) + as_bad (_("multiple vma constants")); + vma_found = TRUE; + } + + if (vsew_found || vlmul_found || vta_found || vma_found) + { + ep->X_op = O_constant; + ep->X_add_number = (vlmul_value << OP_SH_VLMUL) + | (vsew_value << OP_SH_VSEW) + | (vta_value << OP_SH_VTA) + | (vma_value << OP_SH_VMA); + expr_end = str; + } + else + { + my_getExpression (ep, str); + str = expr_end; + } +} + /* Detect and handle implicitly zero load-store offsets. For example, "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such an implicit offset was detected. */ @@ -2014,6 +2235,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) continue; + /* Reset error message of the previous round. */ + error = _("illegal operands"); create_insn (ip, insn); argnum = 1; @@ -2056,6 +2279,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, as_warn (_("read-only CSR is written `%s'"), str); insn_with_csr = false; } + + /* The (segmant) load and store with EEW 64 cannot be used + when zve32x is enabled. */ + if (ip->insn_mo->pinfo & INSN_V_EEW64 + && riscv_subset_supports (&riscv_rps_as, "zve32x") + && !riscv_subset_supports (&riscv_rps_as, "zve64x")) + { + error = _("illegal opcode for zve32x"); + break; + } } if (*asarg != '\0') break; @@ -2356,6 +2589,172 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'V': /* RVV */ + switch (*++oparg) + { + case 'd': /* VD */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + INSERT_OPERAND (VD, *ip, regno); + continue; + + case 'e': /* AMO VD */ + if (reg_lookup (&asarg, RCLASS_GPR, ®no) && regno == 0) + INSERT_OPERAND (VWD, *ip, 0); + else if (reg_lookup (&asarg, RCLASS_VECR, ®no)) + { + INSERT_OPERAND (VWD, *ip, 1); + INSERT_OPERAND (VD, *ip, regno); + } + else + break; + continue; + + case 'f': /* AMO VS3 */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + if (!EXTRACT_OPERAND (VWD, ip->insn_opcode)) + INSERT_OPERAND (VD, *ip, regno); + else + { + /* VS3 must match VD. */ + if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno) + break; + } + continue; + + case 's': /* VS1 */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + INSERT_OPERAND (VS1, *ip, regno); + continue; + + case 't': /* VS2 */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + INSERT_OPERAND (VS2, *ip, regno); + continue; + + case 'u': /* VS1 == VS2 */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + INSERT_OPERAND (VS1, *ip, regno); + INSERT_OPERAND (VS2, *ip, regno); + continue; + + case 'v': /* VD == VS1 == VS2 */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) + break; + INSERT_OPERAND (VD, *ip, regno); + INSERT_OPERAND (VS1, *ip, regno); + INSERT_OPERAND (VS2, *ip, regno); + continue; + + /* The `V0` is carry-in register for v[m]adc and v[m]sbc, + and is used to choose vs1/rs1/frs1/imm or vs2 for + v[f]merge. It use the same encoding as the vector mask + register. */ + case '0': + if (reg_lookup (&asarg, RCLASS_VECR, ®no) && regno == 0) + continue; + break; + + case 'b': /* vtypei for vsetivli */ + my_getVsetvliExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if (!VALID_RVV_VB_IMM (imm_expr->X_add_number)) + as_bad (_("bad value for vsetivli immediate field, " + "value must be 0..1023")); + ip->insn_opcode + |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'c': /* vtypei for vsetvli */ + my_getVsetvliExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if (!VALID_RVV_VC_IMM (imm_expr->X_add_number)) + as_bad (_("bad value for vsetvli immediate field, " + "value must be 0..2047")); + ip->insn_opcode + |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'i': /* vector arith signed immediate */ + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if (imm_expr->X_add_number > 15 + || imm_expr->X_add_number < -16) + as_bad (_("bad value for vector immediate field, " + "value must be -16...15")); + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'j': /* vector arith unsigned immediate */ + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if (imm_expr->X_add_number < 0 + || imm_expr->X_add_number >= 32) + as_bad (_("bad value for vector immediate field, " + "value must be 0...31")); + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'k': /* vector arith signed immediate, minus 1 */ + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + if (imm_expr->X_add_number > 16 + || imm_expr->X_add_number < -15) + as_bad (_("bad value for vector immediate field, " + "value must be -15...16")); + INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1); + imm_expr->X_op = O_absent; + asarg = expr_end; + continue; + + case 'm': /* optional vector mask */ + if (*asarg == '\0') + { + INSERT_OPERAND (VMASK, *ip, 1); + continue; + } + else if (*asarg == ',' && asarg++ + && reg_lookup (&asarg, RCLASS_VECM, ®no) + && regno == 0) + { + INSERT_OPERAND (VMASK, *ip, 0); + continue; + } + break; + + case 'M': /* required vector mask */ + if (reg_lookup (&asarg, RCLASS_VECM, ®no) && regno == 0) + { + INSERT_OPERAND (VMASK, *ip, 0); + continue; + } + break; + + case 'T': /* vector macro temporary register */ + if (!reg_lookup (&asarg, RCLASS_VECR, ®no) || regno == 0) + break; + /* Store it in the FUNCT6 field as we don't have anyplace + else to store it. */ + INSERT_OPERAND (VFUNCT6, *ip, regno); + continue; + + default: + goto unknown_riscv_ip_operand; + } + break; + case ',': ++argnum; if (*asarg++ == *oparg) @@ -2752,7 +3151,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, break; } asarg = asargStart; - error = _("illegal operands"); insn_with_csr = false; } diff --git a/gas/testsuite/gas/riscv/march-imply-v.d b/gas/testsuite/gas/riscv/march-imply-v.d new file mode 100644 index 0000000..e07eecf --- /dev/null +++ b/gas/testsuite/gas/riscv/march-imply-v.d @@ -0,0 +1,6 @@ +#as: -march=rv32iv -march-attr -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d index 68acc09..3e1836a 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d @@ -1,4 +1,4 @@ -#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.10 -march-attr +#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.10 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p10.l #readelf: -A diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d index 3aa611c..e1705e7 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d @@ -1,4 +1,4 @@ -#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.11 -march-attr +#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.11 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p11.l #readelf: -A diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d index e08381a..56ade59 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d @@ -1,4 +1,4 @@ -#as: -march=rv32if_zkr -mcsr-check -mpriv-spec=1.9.1 -march-attr +#as: -march=rv32ifv_zkr -mcsr-check -mpriv-spec=1.9.1 -march-attr #source: priv-reg.s #warning_output: priv-reg-fail-version-1p9p1.l #readelf: -A diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d index 78c683d..ee4f405 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p10.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p10.d @@ -266,3 +266,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d index 6c1cc70..185e84d 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p11.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p11.d @@ -266,3 +266,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d index 3d2ab74..0e0ba77 100644 --- a/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d @@ -266,3 +266,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3 [ ]+[0-9a-f]+:[ ]+01502573[ ]+csrr[ ]+a0,seed +[ ]+[0-9a-f]+:[ ]+00802573[ ]+csrr[ ]+a0,vstart +[ ]+[0-9a-f]+:[ ]+00902573[ ]+csrr[ ]+a0,vxsat +[ ]+[0-9a-f]+:[ ]+00a02573[ ]+csrr[ ]+a0,vxrm +[ ]+[0-9a-f]+:[ ]+00f02573[ ]+csrr[ ]+a0,vcsr +[ ]+[0-9a-f]+:[ ]+c2002573[ ]+csrr[ ]+a0,vl +[ ]+[0-9a-f]+:[ ]+c2102573[ ]+csrr[ ]+a0,vtype +[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s index 85ff2a6..5cf3ebc 100644 --- a/gas/testsuite/gas/riscv/priv-reg.s +++ b/gas/testsuite/gas/riscv/priv-reg.s @@ -285,3 +285,12 @@ # Scalar crypto csr seed # 0x015, Entropy Source + + # Vector + csr vstart + csr vxsat + csr vxrm + csr vcsr + csr vl + csr vtype + csr vlenb diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d new file mode 100644 index 0000000..f3ae39b --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zve32f +#source: vector-insns.s +#error_output: vector-insns-fail-zve32xf.l diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l new file mode 100644 index 0000000..d9ebc49 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l @@ -0,0 +1,225 @@ +.*Assembler messages: +.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vle64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vse64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlse64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vsse64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vle64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg2e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg2e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg3e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg3e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg4e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg4e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg5e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg5e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg6e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg6e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg7e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg7e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg8e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vsseg8e64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg2e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg3e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg4e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg5e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg6e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg7e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg8e64.v v4,0\(a0\),a1' +.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1,v0.t' +.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,0\(a0\),v12' +.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12,v0.t' +.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\),v0.t' +.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)' +.*Error: illegal opcode for zve32x `vl1re64.v v3,0\(a0\)' +.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)' +.*Error: illegal opcode for zve32x `vl2re64.v v2,0\(a0\)' +.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)' +.*Error: illegal opcode for zve32x `vl4re64.v v4,0\(a0\)' +.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)' +.*Error: illegal opcode for zve32x `vl8re64.v v8,0\(a0\)' diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvl.d b/gas/testsuite/gas/riscv/vector-insns-fail-zvl.d new file mode 100644 index 0000000..b8549a6 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvl.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zvl65536b +#source: empty.s +#error_output: vector-insns-fail-zvl.l diff --git a/gas/testsuite/gas/riscv/vector-insns-fail-zvl.l b/gas/testsuite/gas/riscv/vector-insns-fail-zvl.l new file mode 100644 index 0000000..d820ded --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zvl.l @@ -0,0 +1,2 @@ +.*Assembler messages: +.*Error: zvl\*b extensions need to enable either `v' or `zve' extension diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d new file mode 100644 index 0000000..dcc951a --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d @@ -0,0 +1,29 @@ +#as: -march=rv32iv +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+vmslt.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 +[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 +[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 +[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+vmsltu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 +[ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t +[ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 +[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 +[ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 +[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s new file mode 100644 index 0000000..afbb7cc --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.s @@ -0,0 +1,9 @@ + vmsge.vx v4, v8, a1 # unmasked va >= x + vmsge.vx v8, v12, a2, v0.t # masked va >= x, vd != v0 + vmsge.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0 + vmsge.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd + + vmsgeu.vx v4, v8, a1 # unmasked va >= x + vmsgeu.vx v8, v12, a2, v0.t # masked va >= x, vd != v0 + vmsgeu.vx v0, v8, a1, v0.t, v12 # masked va >= x, vd == v0 + vmsgeu.vx v4, v8, a1, v0.t, v12 # masked va >= x, any vd diff --git a/gas/testsuite/gas/riscv/vector-insns-zero-imm.d b/gas/testsuite/gas/riscv/vector-insns-zero-imm.d new file mode 100644 index 0000000..88a3cfd --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-zero-imm.d @@ -0,0 +1,17 @@ +#as: -march=rv32iv +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+768fb257[ ]+vmsle.vi[ ]+v4,v8,-1 +[ ]+[0-9a-f]+:[ ]+748fb257[ ]+vmsle.vi[ ]+v4,v8,-1,v0.t +[ ]+[0-9a-f]+:[ ]+66840257[ ]+vmsne.vv[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+64840257[ ]+vmsne.vv[ ]+v4,v8,v8,v0.t +[ ]+[0-9a-f]+:[ ]+7e8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1 +[ ]+[0-9a-f]+:[ ]+7c8fb257[ ]+vmsgt.vi[ ]+v4,v8,-1,v0.t +[ ]+[0-9a-f]+:[ ]+62840257[ ]+vmseq.vv[ ]+v4,v8,v8 +[ ]+[0-9a-f]+:[ ]+60840257[ ]+vmseq.vv[ ]+v4,v8,v8,v0.t diff --git a/gas/testsuite/gas/riscv/vector-insns-zero-imm.s b/gas/testsuite/gas/riscv/vector-insns-zero-imm.s new file mode 100644 index 0000000..98b7063 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-zero-imm.s @@ -0,0 +1,8 @@ + vmslt.vi v4, v8, 0 + vmslt.vi v4, v8, 0, v0.t + vmsltu.vi v4, v8, 0 + vmsltu.vi v4, v8, 0, v0.t + vmsge.vi v4, v8, 0 + vmsge.vi v4, v8, 0, v0.t + vmsgeu.vi v4, v8, 0 + vmsgeu.vi v4, v8, 0, v0.t diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d new file mode 100644 index 0000000..711f927 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns.d @@ -0,0 +1,1666 @@ +#as: -march=rv32ifv +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047 +[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu +[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu +[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu +[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu +[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma +[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma +[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma +[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu +[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma +[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu +[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu +[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu +[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu +[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu +[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma +[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma +[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma +[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu +[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) +[ 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]+a0,v12 +[ ]+[0-9a-f]+:[ ]+42c8a557[ ]+vfirst.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+5280a257[ ]+vmsbf.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5281a257[ ]+vmsif.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+52812257[ ]+vmsof.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+52882257[ ]+viota.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5208a257[ ]+vid.v[ ]+v4 +[ ]+[0-9a-f]+:[ ]+40c82557[ ]+vcpop.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+40c8a557[ ]+vfirst.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5080a257[ ]+vmsbf.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5081a257[ ]+vmsif.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+50812257[ ]+vmsof.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+50882257[ ]+viota.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5008a257[ ]+vid.v[ ]+v4,v0.t +[ ]+[0-9a-f]+:[ ]+42c02557[ ]+vmv.x.s[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+42056257[ ]+vmv.s.x[ ]+v4,a0 +[ ]+[0-9a-f]+:[ ]+42801557[ ]+vfmv.f.s[ ]+fa0,v8 +[ ]+[0-9a-f]+:[ ]+4205d257[ ]+vfmv.s.f[ ]+v4,fa1 +[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+vslideup.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3a803257[ ]+vslideup.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+vslideup.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+vslidedown.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e803257[ ]+vslidedown.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+vslidedown.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+vslideup.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+38803257[ ]+vslideup.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+vslideup.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+vslidedown.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+vslidedown.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+vslidedown.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+vslide1up.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+vslide1down.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+vslide1up.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+vslide1down.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3a85d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1 +[ ]+[0-9a-f]+:[ ]+3e85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1 +[ ]+[0-9a-f]+:[ ]+3885d257[ ]+vfslide1up.vf[ ]+v4,v8,fa1,v0.t +[ ]+[0-9a-f]+:[ ]+3c85d257[ ]+vfslide1down.vf[ ]+v4,v8,fa1,v0.t +[ ]+[0-9a-f]+:[ ]+32860257[ ]+vrgather.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+vrgather.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+32803257[ ]+vrgather.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+vrgather.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+30860257[ ]+vrgather.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+vrgather.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+30803257[ ]+vrgather.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+vrgather.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3a860257[ ]+vrgatherei16.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+38860257[ ]+vrgatherei16.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+vcompress.vm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9e2030d7[ ]+vmv1r.v[ ]+v1,v2 +[ ]+[0-9a-f]+:[ ]+9e40b157[ ]+vmv2r.v[ ]+v2,v4 +[ ]+[0-9a-f]+:[ ]+9e81b257[ ]+vmv4r.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+9e83b057[ ]+vmv8r.v[ ]+v0,v8 diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s new file mode 100644 index 0000000..37b6ba4 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns.s @@ -0,0 +1,1883 @@ + vsetvl a0, a1, a2 + vsetvli a0, a1, 0 + vsetvli a0, a1, 0x7ff + vsetvli a0, a1, e16, m2 + vsetvli a0, a1, e256, m8 + vsetvli a0, a1, e512, m8 + vsetvli a0, a1, e1024, m8 + vsetvli a0, a1, e1024, m1 + vsetvli a0, a1, e1024, mf2 + vsetvli a0, a1, e512, mf4 + vsetvli a0, a1, e256, mf8 + vsetvli a0, a1, e256, m2, ta + vsetvli a0, a1, e256, m2, ma + vsetvli a0, a1, e256, m2, tu + vsetvli a0, a1, e256, m2, mu + vsetvli a0, a1, e256, m2, ta, ma + vsetvli a0, a1, e256, m2, tu, ma + vsetvli a0, a1, e256, m2, ta, mu + vsetvli a0, a1, e256, m2, tu, mu + vsetivli a0, 0xb, 0 + vsetivli a0, 0xb, 0x3ff + vsetivli a0, 0xb, e16, m2 + vsetivli a0, 0xb, e256, m8 + vsetivli a0, 0xb, e512, m8 + vsetivli a0, 0xb, e1024, m8 + vsetivli a0, 0xb, e1024, m1 + vsetivli a0, 0xb, e1024, mf2 + vsetivli a0, 0xb, e512, mf4 + vsetivli a0, 0xb, e256, mf8 + vsetivli a0, 0xb, e256, m2, ta + vsetivli a0, 0xb, e256, m2, ma + vsetivli a0, 0xb, e256, m2, tu + vsetivli a0, 0xb, e256, m2, mu + vsetivli a0, 0xb, e256, m2, ta, ma + vsetivli a0, 0xb, e256, m2, tu, ma + vsetivli a0, 0xb, e256, m2, ta, mu + vsetivli a0, 0xb, e256, m2, tu, mu + + vlm.v v4, (a0) + vlm.v v4, 0(a0) + vle1.v v4, (a0) # Alias of vlm.v + vle1.v v4, 0(a0) + vsm.v v4, (a0) + vsm.v v4, 0(a0) + vse1.v v4, (a0) # Alias of vsm.v + vse1.v v4, 0(a0) + + vle8.v v4, (a0) + vle8.v v4, 0(a0) + vle8.v v4, (a0), v0.t + vse8.v v4, (a0) + vse8.v v4, 0(a0) + vse8.v v4, (a0), v0.t + + vle16.v v4, (a0) + vle16.v v4, 0(a0) + vle16.v v4, (a0), v0.t + vse16.v v4, (a0) + vse16.v v4, 0(a0) + vse16.v v4, (a0), v0.t + + vle32.v v4, (a0) + vle32.v v4, 0(a0) + vle32.v v4, (a0), v0.t + vse32.v v4, (a0) + vse32.v v4, 0(a0) + vse32.v v4, (a0), v0.t + + vle64.v v4, (a0) + vle64.v v4, 0(a0) + vle64.v v4, (a0), v0.t + vse64.v v4, (a0) + vse64.v v4, 0(a0) + vse64.v v4, (a0), v0.t + + vlse8.v v4, (a0), a1 + vlse8.v v4, 0(a0), a1 + vlse8.v v4, (a0), a1, v0.t + vsse8.v v4, (a0), a1 + vsse8.v v4, 0(a0), a1 + vsse8.v v4, (a0), a1, v0.t + + vlse16.v v4, (a0), a1 + vlse16.v v4, 0(a0), a1 + vlse16.v v4, (a0), a1, v0.t + vsse16.v v4, (a0), a1 + vsse16.v v4, 0(a0), a1 + vsse16.v v4, (a0), a1, v0.t + + vlse32.v v4, (a0), a1 + vlse32.v v4, 0(a0), a1 + vlse32.v v4, (a0), a1, v0.t + vsse32.v v4, (a0), a1 + vsse32.v v4, 0(a0), a1 + vsse32.v v4, (a0), a1, v0.t + + vlse64.v v4, (a0), a1 + vlse64.v v4, 0(a0), a1 + vlse64.v v4, (a0), a1, v0.t + vsse64.v v4, (a0), a1 + vsse64.v v4, 0(a0), a1 + vsse64.v v4, (a0), a1, v0.t + + vloxei8.v v4, (a0), v12 + vloxei8.v v4, 0(a0), v12 + vloxei8.v v4, (a0), v12, v0.t + vsoxei8.v v4, (a0), v12 + vsoxei8.v v4, 0(a0), v12 + vsoxei8.v v4, (a0), v12, v0.t + vluxei8.v v4, (a0), v12 + vluxei8.v v4, 0(a0), v12 + vluxei8.v v4, (a0), v12, v0.t + vsuxei8.v v4, (a0), v12 + vsuxei8.v v4, 0(a0), v12 + vsuxei8.v v4, (a0), v12, v0.t + + vloxei16.v v4, (a0), v12 + vloxei16.v v4, 0(a0), v12 + vloxei16.v v4, (a0), v12, v0.t + vsoxei16.v v4, (a0), v12 + vsoxei16.v v4, 0(a0), v12 + vsoxei16.v v4, (a0), v12, v0.t + vluxei16.v v4, (a0), v12 + vluxei16.v v4, 0(a0), v12 + vluxei16.v v4, (a0), v12, v0.t + vsuxei16.v v4, (a0), v12 + vsuxei16.v v4, 0(a0), v12 + vsuxei16.v v4, (a0), v12, v0.t + + vloxei32.v v4, (a0), v12 + vloxei32.v v4, 0(a0), v12 + vloxei32.v v4, (a0), v12, v0.t + vsoxei32.v v4, (a0), v12 + vsoxei32.v v4, 0(a0), v12 + vsoxei32.v v4, (a0), v12, v0.t + vluxei32.v v4, (a0), v12 + vluxei32.v v4, 0(a0), v12 + vluxei32.v v4, (a0), v12, v0.t + vsuxei32.v v4, (a0), v12 + vsuxei32.v v4, 0(a0), v12 + vsuxei32.v v4, (a0), v12, v0.t + + vloxei64.v v4, (a0), v12 + vloxei64.v v4, 0(a0), v12 + vloxei64.v v4, (a0), v12, v0.t + vsoxei64.v v4, (a0), v12 + vsoxei64.v v4, 0(a0), v12 + vsoxei64.v v4, (a0), v12, v0.t + vluxei64.v v4, (a0), v12 + vluxei64.v v4, 0(a0), v12 + vluxei64.v v4, (a0), v12, v0.t + vsuxei64.v v4, (a0), v12 + vsuxei64.v v4, 0(a0), v12 + vsuxei64.v v4, (a0), v12, v0.t + + vle8ff.v v4, (a0) + vle8ff.v v4, 0(a0) + vle8ff.v v4, (a0), v0.t + + vle16ff.v v4, (a0) + vle16ff.v v4, 0(a0) + vle16ff.v v4, (a0), v0.t + + vle32ff.v v4, (a0) + vle32ff.v v4, 0(a0) + vle32ff.v v4, (a0), v0.t + + vle64ff.v v4, (a0) + vle64ff.v v4, 0(a0) + vle64ff.v v4, (a0), v0.t + + vlseg2e8.v v4, (a0) + vlseg2e8.v v4, 0(a0) + vlseg2e8.v v4, (a0), v0.t + vsseg2e8.v v4, (a0) + vsseg2e8.v v4, 0(a0) + vsseg2e8.v v4, (a0), v0.t + + vlseg3e8.v v4, (a0) + vlseg3e8.v v4, 0(a0) + vlseg3e8.v v4, (a0), v0.t + vsseg3e8.v v4, (a0) + vsseg3e8.v v4, 0(a0) + vsseg3e8.v v4, (a0), v0.t + + vlseg4e8.v v4, (a0) + vlseg4e8.v v4, 0(a0) + vlseg4e8.v v4, (a0), v0.t + vsseg4e8.v v4, (a0) + vsseg4e8.v v4, 0(a0) + vsseg4e8.v v4, (a0), v0.t + + vlseg5e8.v v4, (a0) + vlseg5e8.v v4, 0(a0) + vlseg5e8.v v4, (a0), v0.t + vsseg5e8.v v4, (a0) + vsseg5e8.v v4, 0(a0) + vsseg5e8.v v4, (a0), v0.t + + vlseg6e8.v v4, (a0) + vlseg6e8.v v4, 0(a0) + vlseg6e8.v v4, (a0), v0.t + vsseg6e8.v v4, (a0) + vsseg6e8.v v4, 0(a0) + vsseg6e8.v v4, (a0), v0.t + + vlseg7e8.v v4, (a0) + vlseg7e8.v v4, 0(a0) + vlseg7e8.v v4, (a0), v0.t + vsseg7e8.v v4, (a0) + vsseg7e8.v v4, 0(a0) + vsseg7e8.v v4, (a0), v0.t + + vlseg8e8.v v4, (a0) + vlseg8e8.v v4, 0(a0) + vlseg8e8.v v4, (a0), v0.t + vsseg8e8.v v4, (a0) + vsseg8e8.v v4, 0(a0) + vsseg8e8.v v4, (a0), v0.t + + vlseg2e16.v v4, (a0) + vlseg2e16.v v4, 0(a0) + vlseg2e16.v v4, (a0), v0.t + vsseg2e16.v v4, (a0) + vsseg2e16.v v4, 0(a0) + vsseg2e16.v v4, (a0), v0.t + + vlseg3e16.v v4, (a0) + vlseg3e16.v v4, 0(a0) + vlseg3e16.v v4, (a0), v0.t + vsseg3e16.v v4, (a0) + vsseg3e16.v v4, 0(a0) + vsseg3e16.v v4, (a0), v0.t + + vlseg4e16.v v4, (a0) + vlseg4e16.v v4, 0(a0) + vlseg4e16.v v4, (a0), v0.t + vsseg4e16.v v4, (a0) + vsseg4e16.v v4, 0(a0) + vsseg4e16.v v4, (a0), v0.t + + vlseg5e16.v v4, (a0) + vlseg5e16.v v4, 0(a0) + vlseg5e16.v v4, (a0), v0.t + vsseg5e16.v v4, (a0) + vsseg5e16.v v4, 0(a0) + vsseg5e16.v v4, (a0), v0.t + + vlseg6e16.v v4, (a0) + vlseg6e16.v v4, 0(a0) + vlseg6e16.v v4, (a0), v0.t + vsseg6e16.v v4, (a0) + vsseg6e16.v v4, 0(a0) + vsseg6e16.v v4, (a0), v0.t + + vlseg7e16.v v4, (a0) + vlseg7e16.v v4, 0(a0) + vlseg7e16.v v4, (a0), v0.t + vsseg7e16.v v4, (a0) + vsseg7e16.v v4, 0(a0) + vsseg7e16.v v4, (a0), v0.t + + vlseg8e16.v v4, (a0) + vlseg8e16.v v4, 0(a0) + vlseg8e16.v v4, (a0), v0.t + vsseg8e16.v v4, (a0) + vsseg8e16.v v4, 0(a0) + vsseg8e16.v v4, (a0), v0.t + + vlseg2e32.v v4, (a0) + vlseg2e32.v v4, 0(a0) + vlseg2e32.v v4, (a0), v0.t + vsseg2e32.v v4, (a0) + vsseg2e32.v v4, 0(a0) + vsseg2e32.v v4, (a0), v0.t + + vlseg3e32.v v4, (a0) + vlseg3e32.v v4, 0(a0) + vlseg3e32.v v4, (a0), v0.t + vsseg3e32.v v4, (a0) + vsseg3e32.v v4, 0(a0) + vsseg3e32.v v4, (a0), v0.t + + vlseg4e32.v v4, (a0) + vlseg4e32.v v4, 0(a0) + vlseg4e32.v v4, (a0), v0.t + vsseg4e32.v v4, (a0) + vsseg4e32.v v4, 0(a0) + vsseg4e32.v v4, (a0), v0.t + + vlseg5e32.v v4, (a0) + vlseg5e32.v v4, 0(a0) + vlseg5e32.v v4, (a0), v0.t + vsseg5e32.v v4, (a0) + vsseg5e32.v v4, 0(a0) + vsseg5e32.v v4, (a0), v0.t + + vlseg6e32.v v4, (a0) + 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vlseg3e8ff.v v4, 0(a0) + vlseg3e8ff.v v4, (a0), v0.t + + vlseg4e8ff.v v4, (a0) + vlseg4e8ff.v v4, 0(a0) + vlseg4e8ff.v v4, (a0), v0.t + + vlseg5e8ff.v v4, (a0) + vlseg5e8ff.v v4, 0(a0) + vlseg5e8ff.v v4, (a0), v0.t + + vlseg6e8ff.v v4, (a0) + vlseg6e8ff.v v4, 0(a0) + vlseg6e8ff.v v4, (a0), v0.t + + vlseg7e8ff.v v4, (a0) + vlseg7e8ff.v v4, 0(a0) + vlseg7e8ff.v v4, (a0), v0.t + + vlseg8e8ff.v v4, (a0) + vlseg8e8ff.v v4, 0(a0) + vlseg8e8ff.v v4, (a0), v0.t + + vlseg2e16ff.v v4, (a0) + vlseg2e16ff.v v4, 0(a0) + vlseg2e16ff.v v4, (a0), v0.t + + vlseg3e16ff.v v4, (a0) + vlseg3e16ff.v v4, 0(a0) + vlseg3e16ff.v v4, (a0), v0.t + + vlseg4e16ff.v v4, (a0) + vlseg4e16ff.v v4, 0(a0) + vlseg4e16ff.v v4, (a0), v0.t + + vlseg5e16ff.v v4, (a0) + vlseg5e16ff.v v4, 0(a0) + vlseg5e16ff.v v4, (a0), v0.t + + vlseg6e16ff.v v4, (a0) + vlseg6e16ff.v v4, 0(a0) + vlseg6e16ff.v v4, (a0), v0.t + + vlseg7e16ff.v v4, (a0) + vlseg7e16ff.v v4, 0(a0) + vlseg7e16ff.v v4, (a0), v0.t + + vlseg8e16ff.v v4, (a0) + vlseg8e16ff.v v4, 0(a0) + vlseg8e16ff.v v4, (a0), v0.t + + vlseg2e32ff.v v4, (a0) + vlseg2e32ff.v v4, 0(a0) + vlseg2e32ff.v v4, (a0), v0.t + + vlseg3e32ff.v v4, (a0) + vlseg3e32ff.v v4, 0(a0) + vlseg3e32ff.v v4, (a0), v0.t + + vlseg4e32ff.v v4, (a0) + vlseg4e32ff.v v4, 0(a0) + vlseg4e32ff.v v4, (a0), v0.t + + vlseg5e32ff.v v4, (a0) + vlseg5e32ff.v v4, 0(a0) + vlseg5e32ff.v v4, (a0), v0.t + + vlseg6e32ff.v v4, (a0) + vlseg6e32ff.v v4, 0(a0) + vlseg6e32ff.v v4, (a0), v0.t + + vlseg7e32ff.v v4, (a0) + vlseg7e32ff.v v4, 0(a0) + vlseg7e32ff.v v4, (a0), v0.t + + vlseg8e32ff.v v4, (a0) + vlseg8e32ff.v v4, 0(a0) + vlseg8e32ff.v v4, (a0), v0.t + + vlseg2e64ff.v v4, (a0) + vlseg2e64ff.v v4, 0(a0) + vlseg2e64ff.v v4, (a0), v0.t + + vlseg3e64ff.v v4, (a0) + vlseg3e64ff.v v4, 0(a0) + vlseg3e64ff.v v4, (a0), v0.t + + vlseg4e64ff.v v4, (a0) + vlseg4e64ff.v v4, 0(a0) + vlseg4e64ff.v v4, (a0), v0.t + + vlseg5e64ff.v v4, (a0) + vlseg5e64ff.v v4, 0(a0) + vlseg5e64ff.v v4, (a0), v0.t + + vlseg6e64ff.v v4, (a0) + vlseg6e64ff.v v4, 0(a0) + vlseg6e64ff.v v4, (a0), v0.t + + vlseg7e64ff.v v4, (a0) + vlseg7e64ff.v v4, 0(a0) + vlseg7e64ff.v v4, (a0), v0.t + + vlseg8e64ff.v v4, (a0) + vlseg8e64ff.v v4, 0(a0) + vlseg8e64ff.v v4, (a0), v0.t + + vl1r.v v3, (a0) + vl1r.v v3, 0(a0) + vl1re8.v v3, (a0) + vl1re8.v v3, 0(a0) + vl1re16.v v3, (a0) + vl1re16.v v3, 0(a0) + vl1re32.v v3, (a0) + vl1re32.v v3, 0(a0) + vl1re64.v v3, (a0) + vl1re64.v v3, 0(a0) + + vl2r.v v2, (a0) + vl2r.v v2, 0(a0) + vl2re8.v v2, (a0) + vl2re8.v v2, 0(a0) + vl2re16.v v2, (a0) + vl2re16.v v2, 0(a0) + vl2re32.v v2, (a0) + vl2re32.v v2, 0(a0) + vl2re64.v v2, (a0) + vl2re64.v v2, 0(a0) + + vl4r.v v4, (a0) + vl4r.v v4, 0(a0) + vl4re8.v v4, (a0) + vl4re8.v v4, 0(a0) + vl4re16.v v4, (a0) + vl4re16.v v4, 0(a0) + vl4re32.v v4, (a0) + vl4re32.v v4, 0(a0) + vl4re64.v v4, (a0) + vl4re64.v v4, 0(a0) + + vl8r.v v8, (a0) + vl8r.v v8, 0(a0) + vl8re8.v v8, (a0) + vl8re8.v v8, 0(a0) + vl8re16.v v8, (a0) + vl8re16.v v8, 0(a0) + vl8re32.v v8, (a0) + vl8re32.v v8, 0(a0) + vl8re64.v v8, (a0) + vl8re64.v v8, 0(a0) + + vs1r.v v3, (a1) + vs1r.v v3, 0(a1) + vs2r.v v2, (a1) + vs2r.v v2, 0(a1) + vs4r.v v4, (a1) + vs4r.v v4, 0(a1) + vs8r.v v8, (a1) + vs8r.v v8, 0(a1) + + vneg.v v4, v8 + vneg.v v4, v8, v0.t + + vadd.vv v4, v8, v12 + vadd.vx v4, v8, a1 + vadd.vi v4, v8, 15 + vadd.vi v4, v8, -16 + vadd.vv v4, v8, v12, v0.t + vadd.vx v4, v8, a1, v0.t + vadd.vi v4, v8, 15, v0.t + vadd.vi v4, v8, -16, v0.t + vsub.vv v4, v8, v12 + vsub.vx v4, v8, a1 + vrsub.vx v4, v8, a1 + vrsub.vi v4, v8, 15 + vrsub.vi v4, v8, -16 + vsub.vv v4, v8, v12, v0.t + vsub.vx v4, v8, a1, v0.t + vrsub.vx v4, v8, a1, v0.t + vrsub.vi v4, v8, 15, v0.t + vrsub.vi v4, v8, -16, v0.t + + # Aliases + vwcvt.x.x.v v4, v8 + vwcvtu.x.x.v v4, v8 + vwcvt.x.x.v v4, v8, v0.t + vwcvtu.x.x.v v4, v8, v0.t + + vwaddu.vv v4, v8, v12 + vwaddu.vx v4, v8, a1 + vwaddu.vv v4, v8, v12, v0.t + vwaddu.vx v4, v8, a1, v0.t + vwsubu.vv v4, v8, v12 + vwsubu.vx v4, v8, a1 + vwsubu.vv v4, v8, v12, v0.t + vwsubu.vx v4, v8, a1, v0.t + vwadd.vv v4, v8, v12 + vwadd.vx v4, v8, a1 + vwadd.vv v4, v8, v12, v0.t + vwadd.vx v4, v8, a1, v0.t + vwsub.vv v4, v8, v12 + vwsub.vx v4, v8, a1 + vwsub.vv v4, v8, v12, v0.t + vwsub.vx v4, v8, a1, v0.t + vwaddu.wv v4, v8, v12 + vwaddu.wx v4, v8, a1 + vwaddu.wv v4, v8, v12, v0.t + vwaddu.wx v4, v8, a1, v0.t + vwsubu.wv v4, v8, v12 + vwsubu.wx v4, v8, a1 + vwsubu.wv v4, v8, v12, v0.t + vwsubu.wx v4, v8, a1, v0.t + vwadd.wv v4, v8, v12 + vwadd.wx v4, v8, a1 + vwadd.wv v4, v8, v12, v0.t + vwadd.wx v4, v8, a1, v0.t + vwsub.wv v4, v8, v12 + vwsub.wx v4, v8, a1 + vwsub.wv v4, v8, v12, v0.t + vwsub.wx v4, v8, a1, v0.t + + vzext.vf2 v4, v8 + vzext.vf2 v4, v8, v0.t + vsext.vf2 v4, v8 + vsext.vf2 v4, v8, v0.t + vzext.vf4 v4, v8 + vzext.vf4 v4, v8, v0.t + vsext.vf4 v4, v8 + vsext.vf4 v4, v8, v0.t + vzext.vf8 v4, v8 + vzext.vf8 v4, v8, v0.t + vsext.vf8 v4, v8 + vsext.vf8 v4, v8, v0.t + + vadc.vvm v4, v8, v12, v0 + vadc.vxm v4, v8, a1, v0 + vadc.vim v4, v8, 15, v0 + vadc.vim v4, v8, -16, v0 + vmadc.vvm v4, v8, v12, v0 + vmadc.vxm v4, v8, a1, v0 + vmadc.vim v4, v8, 15, v0 + vmadc.vim v4, v8, -16, v0 + vmadc.vv v4, v8, v12 + vmadc.vx v4, v8, a1 + vmadc.vi v4, v8, 15 + vmadc.vi v4, v8, -16 + vsbc.vvm v4, v8, v12, v0 + vsbc.vxm v4, v8, a1, v0 + vmsbc.vvm v4, v8, v12, v0 + vmsbc.vxm v4, v8, a1, v0 + vmsbc.vv v4, v8, v12 + vmsbc.vx v4, v8, a1 + + # Aliases + vnot.v v4, v8 + vnot.v v4, v8, v0.t + + vand.vv v4, v8, v12 + vand.vx v4, v8, a1 + vand.vi v4, v8, 15 + vand.vi v4, v8, -16 + vand.vv v4, v8, v12, v0.t + vand.vx v4, v8, a1, v0.t + vand.vi v4, v8, 15, v0.t + vand.vi v4, v8, -16, v0.t + vor.vv v4, v8, v12 + vor.vx v4, v8, a1 + vor.vi v4, v8, 15 + vor.vi v4, v8, -16 + vor.vv v4, v8, v12, v0.t + vor.vx v4, v8, a1, v0.t + vor.vi v4, v8, 15, v0.t + vor.vi v4, v8, -16, v0.t + vxor.vv v4, v8, v12 + vxor.vx v4, v8, a1 + vxor.vi v4, v8, 15 + vxor.vi v4, v8, -16 + vxor.vv v4, v8, v12, v0.t + vxor.vx v4, v8, a1, v0.t + vxor.vi v4, v8, 15, v0.t + vxor.vi v4, v8, -16, v0.t + + vsll.vv v4, v8, v12 + vsll.vx v4, v8, a1 + vsll.vi v4, v8, 1 + vsll.vi v4, v8, 31 + vsll.vv v4, v8, v12, v0.t + vsll.vx v4, v8, a1, v0.t + vsll.vi v4, v8, 1, v0.t + vsll.vi v4, v8, 31, v0.t + vsrl.vv v4, v8, v12 + vsrl.vx v4, v8, a1 + vsrl.vi v4, v8, 1 + vsrl.vi v4, v8, 31 + vsrl.vv v4, v8, v12, v0.t + vsrl.vx v4, v8, a1, v0.t + vsrl.vi v4, v8, 1, v0.t + vsrl.vi v4, v8, 31, v0.t + vsra.vv v4, v8, v12 + vsra.vx v4, v8, a1 + vsra.vi v4, v8, 1 + vsra.vi v4, v8, 31 + vsra.vv v4, v8, v12, v0.t + vsra.vx v4, v8, a1, v0.t + vsra.vi v4, v8, 1, v0.t + vsra.vi v4, v8, 31, v0.t + + # Aliases + vncvt.x.x.w v4, v8 + vncvt.x.x.w v4, v8, v0.t + + vnsrl.wv v4, v8, v12 + vnsrl.wx v4, v8, a1 + vnsrl.wi v4, v8, 1 + vnsrl.wi v4, v8, 31 + vnsrl.wv v4, v8, v12, v0.t + vnsrl.wx v4, v8, a1, v0.t + vnsrl.wi v4, v8, 1, v0.t + vnsrl.wi v4, v8, 31, v0.t + vnsra.wv v4, v8, v12 + vnsra.wx v4, v8, a1 + vnsra.wi v4, v8, 1 + vnsra.wi v4, v8, 31 + vnsra.wv v4, v8, v12, v0.t + vnsra.wx v4, v8, a1, v0.t + vnsra.wi v4, v8, 1, v0.t + vnsra.wi v4, v8, 31, v0.t + + # Aliases + vmsgt.vv v4, v8, v12 + vmsgtu.vv v4, v8, v12 + vmsge.vv v4, v8, v12 + vmsgeu.vv v4, v8, v12 + vmsgt.vv v4, v8, v12, v0.t + vmsgtu.vv v4, v8, v12, v0.t + vmsge.vv v4, v8, v12, v0.t + vmsgeu.vv v4, v8, v12, v0.t + vmslt.vi v4, v8, 16 + vmslt.vi v4, v8, -15 + vmsltu.vi v4, v8, 16 + vmsltu.vi v4, v8, -15 + vmsge.vi v4, v8, 16 + vmsge.vi v4, v8, -15 + vmsgeu.vi v4, v8, 16 + vmsgeu.vi v4, v8, -15 + vmslt.vi v4, v8, 16, v0.t + vmslt.vi v4, v8, -15, v0.t + vmsltu.vi v4, v8, 16, v0.t + vmsltu.vi v4, v8, -15, v0.t + vmsge.vi v4, v8, 16, v0.t + vmsge.vi v4, v8, -15, v0.t + vmsgeu.vi v4, v8, 16, v0.t + vmsgeu.vi v4, v8, -15, v0.t + + vmseq.vv v4, v8, v12 + vmseq.vx v4, v8, a1 + vmseq.vi v4, v8, 15 + vmseq.vi v4, v8, -16 + vmseq.vv v4, v8, v12, v0.t + vmseq.vx v4, v8, a1, v0.t + vmseq.vi v4, v8, 15, v0.t + vmseq.vi v4, v8, -16, v0.t + vmsne.vv v4, v8, v12 + vmsne.vx v4, v8, a1 + vmsne.vi v4, v8, 15 + vmsne.vi v4, v8, -16 + vmsne.vv v4, v8, v12, v0.t + vmsne.vx v4, v8, a1, v0.t + vmsne.vi v4, v8, 15, v0.t + vmsne.vi v4, v8, -16, v0.t + vmsltu.vv v4, v8, v12 + vmsltu.vx v4, v8, a1 + vmsltu.vv v4, v8, v12, v0.t + vmsltu.vx v4, v8, a1, v0.t + vmslt.vv v4, v8, v12 + vmslt.vx v4, v8, a1 + vmslt.vv v4, v8, v12, v0.t + vmslt.vx v4, v8, a1, v0.t + vmsleu.vv v4, v8, v12 + vmsleu.vx v4, v8, a1 + vmsleu.vi v4, v8, 15 + vmsleu.vi v4, v8, -16 + vmsleu.vv v4, v8, v12, v0.t + vmsleu.vx v4, v8, a1, v0.t + vmsleu.vi v4, v8, 15, v0.t + vmsleu.vi v4, v8, -16, v0.t + vmsle.vv v4, v8, v12 + vmsle.vx v4, v8, a1 + vmsle.vi v4, v8, 15 + vmsle.vi v4, v8, -16 + vmsle.vv v4, v8, v12, v0.t + vmsle.vx v4, v8, a1, v0.t + vmsle.vi v4, v8, 15, v0.t + vmsle.vi v4, v8, -16, v0.t + vmsgtu.vx v4, v8, a1 + vmsgtu.vi v4, v8, 15 + vmsgtu.vi v4, v8, -16 + vmsgtu.vx v4, v8, a1, v0.t + vmsgtu.vi v4, v8, 15, v0.t + vmsgtu.vi v4, v8, -16, v0.t + vmsgt.vx v4, v8, a1 + vmsgt.vi v4, v8, 15 + vmsgt.vi v4, v8, -16 + vmsgt.vx v4, v8, a1, v0.t + vmsgt.vi v4, v8, 15, v0.t + vmsgt.vi v4, v8, -16, v0.t + + vminu.vv v4, v8, v12 + vminu.vx v4, v8, a1 + vminu.vv v4, v8, v12, v0.t + vminu.vx v4, v8, a1, v0.t + vmin.vv v4, v8, v12 + vmin.vx v4, v8, a1 + vmin.vv v4, v8, v12, v0.t + vmin.vx v4, v8, a1, v0.t + vmaxu.vv v4, v8, v12 + vmaxu.vx v4, v8, a1 + vmaxu.vv v4, v8, v12, v0.t + vmaxu.vx v4, v8, a1, v0.t + vmax.vv v4, v8, v12 + vmax.vx v4, v8, a1 + vmax.vv v4, v8, v12, v0.t + vmax.vx v4, v8, a1, v0.t + + vmul.vv v4, v8, v12 + vmul.vx v4, v8, a1 + vmul.vv v4, v8, v12, v0.t + vmul.vx v4, v8, a1, v0.t + vmulh.vv v4, v8, v12 + vmulh.vx v4, v8, a1 + vmulh.vv v4, v8, v12, v0.t + vmulh.vx v4, v8, a1, v0.t + vmulhu.vv v4, v8, v12 + vmulhu.vx v4, v8, a1 + vmulhu.vv v4, v8, v12, v0.t + vmulhu.vx v4, v8, a1, v0.t + vmulhsu.vv v4, v8, v12 + vmulhsu.vx v4, v8, a1 + vmulhsu.vv v4, v8, v12, v0.t + vmulhsu.vx v4, v8, a1, v0.t + + vwmul.vv v4, v8, v12 + vwmul.vx v4, v8, a1 + vwmul.vv v4, v8, v12, v0.t + vwmul.vx v4, v8, a1, v0.t + vwmulu.vv v4, v8, v12 + vwmulu.vx v4, v8, a1 + vwmulu.vv v4, v8, v12, v0.t + vwmulu.vx v4, v8, a1, v0.t + vwmulsu.vv v4, v8, v12 + vwmulsu.vx v4, v8, a1 + vwmulsu.vv v4, v8, v12, v0.t + vwmulsu.vx v4, v8, a1, v0.t + + vmacc.vv v4, v12, v8 + vmacc.vx v4, a1, v8 + vmacc.vv v4, v12, v8, v0.t + vmacc.vx v4, a1, v8, v0.t + vnmsac.vv v4, v12, v8 + vnmsac.vx v4, a1, v8 + vnmsac.vv v4, v12, v8, v0.t + vnmsac.vx v4, a1, v8, v0.t + vmadd.vv v4, v12, v8 + vmadd.vx v4, a1, v8 + vmadd.vv v4, v12, v8, v0.t + vmadd.vx v4, a1, v8, v0.t + vnmsub.vv v4, v12, v8 + vnmsub.vx v4, a1, v8 + vnmsub.vv v4, v12, v8, v0.t + vnmsub.vx v4, a1, v8, v0.t + + vwmaccu.vv v4, v12, v8 + vwmaccu.vx v4, a1, v8 + vwmaccu.vv v4, v12, v8, v0.t + vwmaccu.vx v4, a1, v8, v0.t + vwmacc.vv v4, v12, v8 + vwmacc.vx v4, a1, v8 + vwmacc.vv v4, v12, v8, v0.t + vwmacc.vx v4, a1, v8, v0.t + vwmaccsu.vv v4, v12, v8 + vwmaccsu.vx v4, a1, v8 + vwmaccsu.vv v4, v12, v8, v0.t + vwmaccsu.vx v4, a1, v8, v0.t + vwmaccus.vx v4, a1, v8 + vwmaccus.vx v4, a1, v8, v0.t + + vdivu.vv v4, v8, v12 + vdivu.vx v4, v8, a1 + vdivu.vv v4, v8, v12, v0.t + vdivu.vx v4, v8, a1, v0.t + vdiv.vv v4, v8, v12 + vdiv.vx v4, v8, a1 + vdiv.vv v4, v8, v12, v0.t + vdiv.vx v4, v8, a1, v0.t + vremu.vv v4, v8, v12 + vremu.vx v4, v8, a1 + vremu.vv v4, v8, v12, v0.t + vremu.vx v4, v8, a1, v0.t + vrem.vv v4, v8, v12 + vrem.vx v4, v8, a1 + vrem.vv v4, v8, v12, v0.t + vrem.vx v4, v8, a1, v0.t + + vmerge.vvm v4, v8, v12, v0 + vmerge.vxm v4, v8, a1, v0 + vmerge.vim v4, v8, 15, v0 + vmerge.vim v4, v8, -16, v0 + + vmv.v.v v8, v12 + vmv.v.x v8, a1 + vmv.v.i v8, 15 + vmv.v.i v8, -16 + + vsaddu.vv v4, v8, v12 + vsaddu.vx v4, v8, a1 + vsaddu.vi v4, v8, 15 + vsaddu.vi v4, v8, -16 + vsaddu.vv v4, v8, v12, v0.t + vsaddu.vx v4, v8, a1, v0.t + vsaddu.vi v4, v8, 15, v0.t + vsaddu.vi v4, v8, -16, v0.t + vsadd.vv v4, v8, v12 + vsadd.vx v4, v8, a1 + vsadd.vi v4, v8, 15 + vsadd.vi v4, v8, -16 + vsadd.vv v4, v8, v12, v0.t + vsadd.vx v4, v8, a1, v0.t + vsadd.vi v4, v8, 15, v0.t + vsadd.vi v4, v8, -16, v0.t + vssubu.vv v4, v8, v12 + vssubu.vx v4, v8, a1 + vssubu.vv v4, v8, v12, v0.t + vssubu.vx v4, v8, a1, v0.t + vssub.vv v4, v8, v12 + vssub.vx v4, v8, a1 + vssub.vv v4, v8, v12, v0.t + vssub.vx v4, v8, a1, v0.t + + vaaddu.vv v4, v8, v12 + vaaddu.vx v4, v8, a1 + vaaddu.vv v4, v8, v12, v0.t + vaaddu.vx v4, v8, a1, v0.t + vaadd.vv v4, v8, v12 + vaadd.vx v4, v8, a1 + vaadd.vv v4, v8, v12, v0.t + vaadd.vx v4, v8, a1, v0.t + vasubu.vv v4, v8, v12 + vasubu.vx v4, v8, a1 + vasubu.vv v4, v8, v12, v0.t + vasubu.vx v4, v8, a1, v0.t + vasub.vv v4, v8, v12 + vasub.vx v4, v8, a1 + vasub.vv v4, v8, v12, v0.t + vasub.vx v4, v8, a1, v0.t + + vsmul.vv v4, v8, v12 + vsmul.vx v4, v8, a1 + vsmul.vv v4, v8, v12, v0.t + vsmul.vx v4, v8, a1, v0.t + + vssrl.vv v4, v8, v12 + vssrl.vx v4, v8, a1 + vssrl.vi v4, v8, 1 + vssrl.vi v4, v8, 31 + vssrl.vv v4, v8, v12, v0.t + vssrl.vx v4, v8, a1, v0.t + vssrl.vi v4, v8, 1, v0.t + vssrl.vi v4, v8, 31, v0.t + vssra.vv v4, v8, v12 + vssra.vx v4, v8, a1 + vssra.vi v4, v8, 1 + vssra.vi v4, v8, 31 + vssra.vv v4, v8, v12, v0.t + vssra.vx v4, v8, a1, v0.t + vssra.vi v4, v8, 1, v0.t + vssra.vi v4, v8, 31, v0.t + + vnclipu.wv v4, v8, v12 + vnclipu.wx v4, v8, a1 + vnclipu.wi v4, v8, 1 + vnclipu.wi v4, v8, 31 + vnclipu.wv v4, v8, v12, v0.t + vnclipu.wx v4, v8, a1, v0.t + vnclipu.wi v4, v8, 1, v0.t + vnclipu.wi v4, v8, 31, v0.t + vnclip.wv v4, v8, v12 + vnclip.wx v4, v8, a1 + vnclip.wi v4, v8, 1 + vnclip.wi v4, v8, 31 + vnclip.wv v4, v8, v12, v0.t + vnclip.wx v4, v8, a1, v0.t + vnclip.wi v4, v8, 1, v0.t + vnclip.wi v4, v8, 31, v0.t + + vfadd.vv v4, v8, v12 + vfadd.vf v4, v8, fa2 + vfadd.vv v4, v8, v12, v0.t + vfadd.vf v4, v8, fa2, v0.t + vfsub.vv v4, v8, v12 + vfsub.vf v4, v8, fa2 + vfsub.vv v4, v8, v12, v0.t + vfsub.vf v4, v8, fa2, v0.t + vfrsub.vf v4, v8, fa2 + vfrsub.vf v4, v8, fa2, v0.t + + vfwadd.vv v4, v8, v12 + vfwadd.vf v4, v8, fa2 + vfwadd.vv v4, v8, v12, v0.t + vfwadd.vf v4, v8, fa2, v0.t + vfwsub.vv v4, v8, v12 + vfwsub.vf v4, v8, fa2 + vfwsub.vv v4, v8, v12, v0.t + vfwsub.vf v4, v8, fa2, v0.t + vfwadd.wv v4, v8, v12 + vfwadd.wf v4, v8, fa2 + vfwadd.wv v4, v8, v12, v0.t + vfwadd.wf v4, v8, fa2, v0.t + vfwsub.wv v4, v8, v12 + vfwsub.wf v4, v8, fa2 + vfwsub.wv v4, v8, v12, v0.t + vfwsub.wf v4, v8, fa2, v0.t + + vfmul.vv v4, v8, v12 + vfmul.vf v4, v8, fa2 + vfmul.vv v4, v8, v12, v0.t + vfmul.vf v4, v8, fa2, v0.t + vfdiv.vv v4, v8, v12 + vfdiv.vf v4, v8, fa2 + vfdiv.vv v4, v8, v12, v0.t + vfdiv.vf v4, v8, fa2, v0.t + vfrdiv.vf v4, v8, fa2 + vfrdiv.vf v4, v8, fa2, v0.t + + vfwmul.vv v4, v8, v12 + vfwmul.vf v4, v8, fa2 + vfwmul.vv v4, v8, v12, v0.t + vfwmul.vf v4, v8, fa2, v0.t + + vfmadd.vv v4, v12, v8 + vfmadd.vf v4, fa2, v8 + vfnmadd.vv v4, v12, v8 + vfnmadd.vf v4, fa2, v8 + vfmsub.vv v4, v12, v8 + vfmsub.vf v4, fa2, v8 + vfnmsub.vv v4, v12, v8 + vfnmsub.vf v4, fa2, v8 + vfmadd.vv v4, v12, v8, v0.t + vfmadd.vf v4, fa2, v8, v0.t + vfnmadd.vv v4, v12, v8, v0.t + vfnmadd.vf v4, fa2, v8, v0.t + vfmsub.vv v4, v12, v8, v0.t + vfmsub.vf v4, fa2, v8, v0.t + vfnmsub.vv v4, v12, v8, v0.t + vfnmsub.vf v4, fa2, v8, v0.t + vfmacc.vv v4, v12, v8 + vfmacc.vf v4, fa2, v8 + vfnmacc.vv v4, v12, v8 + vfnmacc.vf v4, fa2, v8 + vfmsac.vv v4, v12, v8 + vfmsac.vf v4, fa2, v8 + vfnmsac.vv v4, v12, v8 + vfnmsac.vf v4, fa2, v8 + vfmacc.vv v4, v12, v8, v0.t + vfmacc.vf v4, fa2, v8, v0.t + vfnmacc.vv v4, v12, v8, v0.t + vfnmacc.vf v4, fa2, v8, v0.t + vfmsac.vv v4, v12, v8, v0.t + vfmsac.vf v4, fa2, v8, v0.t + vfnmsac.vv v4, v12, v8, v0.t + vfnmsac.vf v4, fa2, v8, v0.t + + vfwmacc.vv v4, v12, v8 + vfwmacc.vf v4, fa2, v8 + vfwnmacc.vv v4, v12, v8 + vfwnmacc.vf v4, fa2, v8 + vfwmsac.vv v4, v12, v8 + vfwmsac.vf v4, fa2, v8 + vfwnmsac.vv v4, v12, v8 + vfwnmsac.vf v4, fa2, v8 + vfwmacc.vv v4, v12, v8, v0.t + vfwmacc.vf v4, fa2, v8, v0.t + vfwnmacc.vv v4, v12, v8, v0.t + vfwnmacc.vf v4, fa2, v8, v0.t + vfwmsac.vv v4, v12, v8, v0.t + vfwmsac.vf v4, fa2, v8, v0.t + vfwnmsac.vv v4, v12, v8, v0.t + vfwnmsac.vf v4, fa2, v8, v0.t + + vfsqrt.v v4, v8 + vfsqrt.v v4, v8, v0.t + vfrsqrte7.v v4, v8 + vfrsqrte7.v v4, v8, v0.t + vfrsqrt7.v v4, v8 + vfrsqrt7.v v4, v8, v0.t + vfrece7.v v4, v8 + vfrece7.v v4, v8, v0.t + vfrec7.v v4, v8 + vfrec7.v v4, v8, v0.t + vfclass.v v4, v8 + vfclass.v v4, v8, v0.t + + vfmin.vv v4, v8, v12 + vfmin.vf v4, v8, fa2 + vfmax.vv v4, v8, v12 + vfmax.vf v4, v8, fa2 + vfmin.vv v4, v8, v12, v0.t + vfmin.vf v4, v8, fa2, v0.t + vfmax.vv v4, v8, v12, v0.t + vfmax.vf v4, v8, fa2, v0.t + + vfneg.v v4, v8 + vfneg.v v4, v8, v0.t + vfabs.v v4, v8 + vfabs.v v4, v8, v0.t + + vfsgnj.vv v4, v8, v12 + vfsgnj.vf v4, v8, fa2 + vfsgnjn.vv v4, v8, v12 + vfsgnjn.vf v4, v8, fa2 + vfsgnjx.vv v4, v8, v12 + vfsgnjx.vf v4, v8, fa2 + vfsgnj.vv v4, v8, v12, v0.t + vfsgnj.vf v4, v8, fa2, v0.t + vfsgnjn.vv v4, v8, v12, v0.t + vfsgnjn.vf v4, v8, fa2, v0.t + vfsgnjx.vv v4, v8, v12, v0.t + vfsgnjx.vf v4, v8, fa2, v0.t + + # Aliases + vmfgt.vv v4, v8, v12 + vmfge.vv v4, v8, v12 + vmfgt.vv v4, v8, v12, v0.t + vmfge.vv v4, v8, v12, v0.t + + vmfeq.vv v4, v8, v12 + vmfeq.vf v4, v8, fa2 + vmfne.vv v4, v8, v12 + vmfne.vf v4, v8, fa2 + vmflt.vv v4, v8, v12 + vmflt.vf v4, v8, fa2 + vmfle.vv v4, v8, v12 + vmfle.vf v4, v8, fa2 + vmfgt.vf v4, v8, fa2 + vmfge.vf v4, v8, fa2 + vmfeq.vv v4, v8, v12, v0.t + vmfeq.vf v4, v8, fa2, v0.t + vmfne.vv v4, v8, v12, v0.t + vmfne.vf v4, v8, fa2, v0.t + vmflt.vv v4, v8, v12, v0.t + vmflt.vf v4, v8, fa2, v0.t + vmfle.vv v4, v8, v12, v0.t + vmfle.vf v4, v8, fa2, v0.t + vmfgt.vf v4, v8, fa2, v0.t + vmfge.vf v4, v8, fa2, v0.t + + vfmerge.vfm v4, v8, fa2, v0 + vfmv.v.f v4, fa1 + + vfcvt.xu.f.v v4, v8 + vfcvt.x.f.v v4, v8 + vfcvt.rtz.xu.f.v v4, v8 + vfcvt.rtz.x.f.v v4, v8 + vfcvt.f.xu.v v4, v8 + vfcvt.f.x.v v4, v8 + vfcvt.xu.f.v v4, v8, v0.t + vfcvt.x.f.v v4, v8, v0.t + vfcvt.rtz.xu.f.v v4, v8, v0.t + vfcvt.rtz.x.f.v v4, v8, v0.t + vfcvt.f.xu.v v4, v8, v0.t + vfcvt.f.x.v v4, v8, v0.t + + vfwcvt.xu.f.v v4, v8 + vfwcvt.x.f.v v4, v8 + vfwcvt.rtz.xu.f.v v4, v8 + vfwcvt.rtz.x.f.v v4, v8 + vfwcvt.f.xu.v v4, v8 + vfwcvt.f.x.v v4, v8 + vfwcvt.f.f.v v4, v8 + vfwcvt.xu.f.v v4, v8, v0.t + vfwcvt.x.f.v v4, v8, v0.t + vfwcvt.rtz.xu.f.v v4, v8, v0.t + vfwcvt.rtz.x.f.v v4, v8, v0.t + vfwcvt.f.xu.v v4, v8, v0.t + vfwcvt.f.x.v v4, v8, v0.t + vfwcvt.f.f.v v4, v8, v0.t + + vfncvt.xu.f.w v4, v8 + vfncvt.x.f.w v4, v8 + vfncvt.rtz.xu.f.w v4, v8 + vfncvt.rtz.x.f.w v4, v8 + vfncvt.f.xu.w v4, v8 + vfncvt.f.x.w v4, v8 + vfncvt.f.f.w v4, v8 + vfncvt.rod.f.f.w v4, v8 + vfncvt.xu.f.w v4, v8, v0.t + vfncvt.x.f.w v4, v8, v0.t + vfncvt.rtz.xu.f.w v4, v8, v0.t + vfncvt.rtz.x.f.w v4, v8, v0.t + vfncvt.f.xu.w v4, v8, v0.t + vfncvt.f.x.w v4, v8, v0.t + vfncvt.f.f.w v4, v8, v0.t + vfncvt.rod.f.f.w v4, v8, v0.t + + vredsum.vs v4, v8, v12 + vredmaxu.vs v4, v8, v8 + vredmax.vs v4, v8, v8 + vredminu.vs v4, v8, v8 + vredmin.vs v4, v8, v8 + vredand.vs v4, v8, v12 + vredor.vs v4, v8, v12 + vredxor.vs v4, v8, v12 + vredsum.vs v4, v8, v12, v0.t + vredmaxu.vs v4, v8, v8, v0.t + vredmax.vs v4, v8, v8, v0.t + vredminu.vs v4, v8, v8, v0.t + vredmin.vs v4, v8, v8, v0.t + vredand.vs v4, v8, v12, v0.t + vredor.vs v4, v8, v12, v0.t + vredxor.vs v4, v8, v12, v0.t + + vwredsumu.vs v4, v8, v12 + vwredsum.vs v4, v8, v12 + vwredsumu.vs v4, v8, v12, v0.t + vwredsum.vs v4, v8, v12, v0.t + + vfredosum.vs v4, v8, v12 + vfredusum.vs v4, v8, v12 + vfredsum.vs v4, v8, v12 # Alias of vfredusum.vs. + vfredmax.vs v4, v8, v12 + vfredmin.vs v4, v8, v12 + vfredosum.vs v4, v8, v12, v0.t + vfredusum.vs v4, v8, v12, v0.t + vfredsum.vs v4, v8, v12, v0.t # Alias of vfredusum.vs. + vfredmax.vs v4, v8, v12, v0.t + vfredmin.vs v4, v8, v12, v0.t + + vfwredosum.vs v4, v8, v12 + vfwredusum.vs v4, v8, v12 + vfwredsum.vs v4, v8, v12 # Alias of vfwredusum.vs. + vfwredosum.vs v4, v8, v12, v0.t + vfwredusum.vs v4, v8, v12, v0.t + vfwredsum.vs v4, v8, v12, v0.t # Alias of vfwredusum.vs. + + # Aliases + vmcpy.m v4, v8 + vmmv.m v4, v8 + vmclr.m v4 + vmset.m v4 + vmnot.m v4, v8 + + vmand.mm v4, v8, v12 + vmnand.mm v4, v8, v12 + vmandn.mm v4, v8, v12 + vmandnot.mm v4, v8, v12 # Alias of vmandn.mm. + vmxor.mm v4, v8, v12 + vmor.mm v4, v8, v12 + vmnor.mm v4, v8, v12 + vmorn.mm v4, v8, v12 + vmornot.mm v4, v8, v12 # Alias of vmorn.mm. + vmxnor.mm v4, v8, v12 + + vcpop.m a0, v12 + vfirst.m a0, v12 + vmsbf.m v4, v8 + vmsif.m v4, v8 + vmsof.m v4, v8 + viota.m v4, v8 + vid.v v4 + vcpop.m a0, v12, v0.t + vfirst.m a0, v12, v0.t + vmsbf.m v4, v8, v0.t + vmsif.m v4, v8, v0.t + vmsof.m v4, v8, v0.t + viota.m v4, v8, v0.t + vid.v v4, v0.t + + vmv.x.s a0, v12 + vmv.s.x v4, a0 + + vfmv.f.s fa0, v8 + vfmv.s.f v4, fa1 + + vslideup.vx v4, v8, a1 + vslideup.vi v4, v8, 0 + vslideup.vi v4, v8, 31 + vslidedown.vx v4, v8, a1 + vslidedown.vi v4, v8, 0 + vslidedown.vi v4, v8, 31 + vslideup.vx v4, v8, a1, v0.t + vslideup.vi v4, v8, 0, v0.t + vslideup.vi v4, v8, 31, v0.t + vslidedown.vx v4, v8, a1, v0.t + vslidedown.vi v4, v8, 0, v0.t + vslidedown.vi v4, v8, 31, v0.t + + vslide1up.vx v4, v8, a1 + vslide1down.vx v4, v8, a1 + vslide1up.vx v4, v8, a1, v0.t + vslide1down.vx v4, v8, a1, v0.t + + vfslide1up.vf v4, v8, fa1 + vfslide1down.vf v4, v8, fa1 + vfslide1up.vf v4, v8, fa1, v0.t + vfslide1down.vf v4, v8, fa1, v0.t + + vrgather.vv v4, v8, v12 + vrgather.vx v4, v8, a1 + vrgather.vi v4, v8, 0 + vrgather.vi v4, v8, 31 + vrgather.vv v4, v8, v12, v0.t + vrgather.vx v4, v8, a1, v0.t + vrgather.vi v4, v8, 0, v0.t + vrgather.vi v4, v8, 31, v0.t + + vrgatherei16.vv v4, v8, v12 + vrgatherei16.vv v4, v8, v12, v0.t + + vcompress.vm v4, v8, v12 + + vmv1r.v v1, v2 + vmv2r.v v2, v4 + vmv4r.v v4, v8 + vmv8r.v v0, v8 |