diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.d | 40 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s | 55 |
3 files changed, 101 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index d5fc14b..be2607c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2019-02-07 Tamar Christina <tamar.christina@arm.com> + + PR binutils/23212 + * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. + * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. + 2019-02-07 Eric Botcazou <ebotcazou@adacore.com> * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on diff --git a/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.d b/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.d new file mode 100644 index 0000000..41afa67 --- /dev/null +++ b/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.d @@ -0,0 +1,40 @@ +#as: -march=armv8.4-a +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+:\s+5f909000 fmul s0, s0, v16.s\[0\] +[^:]+:\s+5ff09000 .inst 0x5ff09000 ; undefined +[^:]+:\s+5f901000 fmla s0, s0, v16.s\[0\] +[^:]+:\s+5ff01000 .inst 0x5ff01000 ; undefined +[^:]+:\s+5f905000 fmls s0, s0, v16.s\[0\] +[^:]+:\s+5ff05000 .inst 0x5ff05000 ; undefined +[^:]+:\s+7f909000 fmulx s0, s0, v16.s\[0\] +[^:]+:\s+7ff09000 .inst 0x7ff09000 ; undefined +[^:]+:\s+5fd09000 fmul d0, d0, v16.d\[0\] +[^:]+:\s+5ff09000 .inst 0x5ff09000 ; undefined +[^:]+:\s+5fd01000 fmla d0, d0, v16.d\[0\] +[^:]+:\s+5ff01000 .inst 0x5ff01000 ; undefined +[^:]+:\s+5fd05000 fmls d0, d0, v16.d\[0\] +[^:]+:\s+5ff05000 .inst 0x5ff05000 ; undefined +[^:]+:\s+7fd09000 fmulx d0, d0, v16.d\[0\] +[^:]+:\s+7ff09000 .inst 0x7ff09000 ; undefined +[^:]+:\s+4f909000 fmul v0.4s, v0.4s, v16.s\[0\] +[^:]+:\s+4ff09000 .inst 0x4ff09000 ; undefined +[^:]+:\s+4f901000 fmla v0.4s, v0.4s, v16.s\[0\] +[^:]+:\s+4ff01000 .inst 0x4ff01000 ; undefined +[^:]+:\s+4f905000 fmls v0.4s, v0.4s, v16.s\[0\] +[^:]+:\s+4ff05000 .inst 0x4ff05000 ; undefined +[^:]+:\s+6f909000 fmulx v0.4s, v0.4s, v16.s\[0\] +[^:]+:\s+6ff09000 .inst 0x6ff09000 ; undefined +[^:]+:\s+4fd09000 fmul v0.2d, v0.2d, v16.d\[0\] +[^:]+:\s+4ff09000 .inst 0x4ff09000 ; undefined +[^:]+:\s+4fd01000 fmla v0.2d, v0.2d, v16.d\[0\] +[^:]+:\s+4ff01000 .inst 0x4ff01000 ; undefined +[^:]+:\s+4fd05000 fmls v0.2d, v0.2d, v16.d\[0\] +[^:]+:\s+4ff05000 .inst 0x4ff05000 ; undefined +[^:]+:\s+6fd09000 fmulx v0.2d, v0.2d, v16.d\[0\] +[^:]+:\s+6ff09000 .inst 0x6ff09000 ; undefined diff --git a/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s b/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s new file mode 100644 index 0000000..19e93b0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s @@ -0,0 +1,55 @@ +# Generates tests to see if setting bit 22 (sz) and 21 (L) together correctly +# marks the instruction as undefined. This pattern can't be created by the +# assembler so instead manually encode it. +.macro gen_insns opc + .inst \opc + .inst (\opc | 0x600000) +.endm + +# fmul s0, s0, v16.s[0] +gen_insns 0x5f909000 + +# fmla s0, s0, v16.s[0] +gen_insns 0x5f901000 + +# fmls s0, s0, v16.s[0] +gen_insns 0x5f905000 + +# fmulx s0, s0, v16.s[0] +gen_insns 0x7f909000 + +# fmul d0, d0, v16.d[0] +gen_insns 0x5fd09000 + +# fmla d0, d0, v16.d[0] +gen_insns 0x5fd01000 + +# fmls d0, d0, v16.d[0] +gen_insns 0x5fd05000 + +# fmulx d0, d0, v16.d[0] +gen_insns 0x7fd09000 + +# fmul v0.4s, v0.4s, v16.s[0] +gen_insns 0x4f909000 + +# fmla v0.4s, v0.4s, v16.s[0] +gen_insns 0x4f901000 + +# fmls v0.4s, v0.4s, v16.s[0] +gen_insns 0x4f905000 + +# fmulx v0.4s, v0.4s, v16.s[0] +gen_insns 0x6f909000 + +# fmul v0.2d, v0.2d, v16.d[0] +gen_insns 0x4fd09000 + +# fmla v0.2d, v0.2d, v16.d[0] +gen_insns 0x4fd01000 + +# fmls v0.2d, v0.2d, v16.d[0] +gen_insns 0x4fd05000 + +# fmulx v0.2d, v0.2d, v16.d[0] +gen_insns 0x6fd09000 |