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-rw-r--r--gas/NEWS2
-rw-r--r--gas/config/tc-riscv.c68
-rw-r--r--gas/doc/c-riscv.texi7
-rw-r--r--gas/testsuite/gas/riscv/sifive-insns.d37
-rw-r--r--gas/testsuite/gas/riscv/sifive-insns.s33
5 files changed, 147 insertions, 0 deletions
diff --git a/gas/NEWS b/gas/NEWS
index 143d9c8..53113d7 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -37,6 +37,8 @@
* Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg
and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual.
+* Add support for RISC-V SiFive VCIX extension (XSfVcp) with version 1.0.
+
* The BPF assembler now uses semi-colon (;) to separate statements, and
therefore they cannot longer be used to begin line comments. This matches the
behavior of the clang/LLVM BPF assembler.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 04738d5..9365b87 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1499,6 +1499,24 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
goto unknown_validate_operand;
}
break;
+ case 's': /* Vendor-specific (SiFive) operands. */
+ switch (*++oparg)
+ {
+ case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
+ case 'O':
+ switch (*++oparg)
+ {
+ case '2': USE_BITS (OP_MASK_XSO2, OP_SH_XSO2); break;
+ case '1': USE_BITS (OP_MASK_XSO1, OP_SH_XSO1); break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
+ default:
+ goto unknown_validate_operand;
+ }
+ break;
default:
goto unknown_validate_operand;
}
@@ -3616,6 +3634,56 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
break;
+ case 's': /* Vendor-specific (SiFive) operands. */
+#define UIMM_BITFIELD_VAL(S, E) (1 << ((E) - (S) + 1))
+#define ENCODE_UIMM_BIT_FIELD(NAME, IP, EXPR, RELOC, ASARG, \
+ START, END) \
+ do \
+ { \
+ if (my_getOpcodeExpression (EXPR, RELOC, ASARG) \
+ || EXPR->X_op != O_constant \
+ || EXPR->X_add_number < 0 \
+ || EXPR->X_add_number >= UIMM_BITFIELD_VAL (START, END)) \
+ { \
+ as_bad (_("bad value for <bit-%s-%s> " \
+ "field, value must be 0...%d"), \
+ #START, #END, UIMM_BITFIELD_VAL (START, END)); \
+ break; \
+ } \
+ INSERT_OPERAND (NAME, *IP, EXPR->X_add_number); \
+ EXPR->X_op = O_absent; \
+ ASARG = expr_parse_end; \
+ } \
+ while (0);
+ switch (*++oparg)
+ {
+ case 'd': /* Xsd */
+ ENCODE_UIMM_BIT_FIELD
+ (RD, ip, imm_expr, imm_reloc, asarg, 7, 11);
+ continue;
+ case 't': /* Xst */
+ ENCODE_UIMM_BIT_FIELD
+ (RS2, ip, imm_expr, imm_reloc, asarg, 20, 24)
+ continue;
+ case 'O':
+ switch (*++oparg)
+ {
+ case '2': /* XsO2 */
+ ENCODE_UIMM_BIT_FIELD
+ (XSO2, ip, imm_expr, imm_reloc, asarg, 26, 27);
+ continue;
+ case '1': /* XsO1 */
+ ENCODE_UIMM_BIT_FIELD
+ (XSO1, ip, imm_expr, imm_reloc, asarg, 26, 26);
+ continue;
+ }
+ default:
+ goto unknown_riscv_ip_operand;
+ }
+#undef UIMM_BITFIELD_VAL
+#undef ENCODE_UIMM_BIT_FIELD
+ break;
+
default:
goto unknown_riscv_ip_operand;
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 763e89c..f15526e 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -832,4 +832,11 @@ bitwise-logic, and conditional select operations.
It is documented in @url{https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf}.
+@item XSfVcp
+The XSfVcp (VCIX) extension provides flexible instructions for extending
+vector coprocessor. To accelerate performance, system designers may use
+VCIX as a low-latency, high-throughput interface to a coprocessor.
+
+It is documented in @url{https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf}.
+
@end table
diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
new file mode 100644
index 0000000..f7d63d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/sifive-insns.d
@@ -0,0 +1,37 @@
+#as:
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+0ef5cfdb[ ]+sf.vc.x[ ]+0x3,0xf,0x1f,a1
+[ ]+[0-9a-f]+:[ ]+0ef7bfdb[ ]+sf.vc.i[ ]+0x3,0xf,0x1f,15
+[ ]+[0-9a-f]+:[ ]+2e208fdb[ ]+sf.vc.vv[ ]+0x3,0x1f,v2,v1
+[ ]+[0-9a-f]+:[ ]+2e25cfdb[ ]+sf.vc.xv[ ]+0x3,0x1f,v2,a1
+[ ]+[0-9a-f]+:[ ]+2e27bfdb[ ]+sf.vc.iv[ ]+0x3,0x1f,v2,15
+[ ]+[0-9a-f]+:[ ]+2e25dfdb[ ]+sf.vc.fv[ ]+0x1,0x1f,v2,fa1
+[ ]+[0-9a-f]+:[ ]+ae20805b[ ]+sf.vc.vvv[ ]+0x3,v0,v2,v1
+[ ]+[0-9a-f]+:[ ]+ae25c05b[ ]+sf.vc.xvv[ ]+0x3,v0,v2,a1
+[ ]+[0-9a-f]+:[ ]+ae27b05b[ ]+sf.vc.ivv[ ]+0x3,v0,v2,15
+[ ]+[0-9a-f]+:[ ]+ae25d05b[ ]+sf.vc.fvv[ ]+0x1,v0,v2,fa1
+[ ]+[0-9a-f]+:[ ]+fe20805b[ ]+sf.vc.vvw[ ]+0x3,v0,v2,v1
+[ ]+[0-9a-f]+:[ ]+fe25c05b[ ]+sf.vc.xvw[ ]+0x3,v0,v2,a1
+[ ]+[0-9a-f]+:[ ]+fe27b05b[ ]+sf.vc.ivw[ ]+0x3,v0,v2,15
+[ ]+[0-9a-f]+:[ ]+fe25d05b[ ]+sf.vc.fvw[ ]+0x1,v0,v2,fa1
+[ ]+[0-9a-f]+:[ ]+0cf5c05b[ ]+sf.vc.v.x[ ]+0x3,0xf,v0,a1
+[ ]+[0-9a-f]+:[ ]+0cf7b05b[ ]+sf.vc.v.i[ ]+0x3,0xf,v0,15
+[ ]+[0-9a-f]+:[ ]+2c20805b[ ]+sf.vc.v.vv[ ]+0x3,v0,v2,v1
+[ ]+[0-9a-f]+:[ ]+2c25c05b[ ]+sf.vc.v.xv[ ]+0x3,v0,v2,a1
+[ ]+[0-9a-f]+:[ ]+2c27b05b[ ]+sf.vc.v.iv[ ]+0x3,v0,v2,15
+[ ]+[0-9a-f]+:[ ]+2c25d05b[ ]+sf.vc.v.fv[ ]+0x1,v0,v2,fa1
+[ ]+[0-9a-f]+:[ ]+ac20805b[ ]+sf.vc.v.vvv[ ]+0x3,v0,v2,v1
+[ ]+[0-9a-f]+:[ ]+ac25c05b[ ]+sf.vc.v.xvv[ ]+0x3,v0,v2,a1
+[ ]+[0-9a-f]+:[ ]+ac27b05b[ ]+sf.vc.v.ivv[ ]+0x3,v0,v2,15
+[ ]+[0-9a-f]+:[ ]+ac25d05b[ ]+sf.vc.v.fvv[ ]+0x1,v0,v2,fa1
+[ ]+[0-9a-f]+:[ ]+fc20805b[ ]+sf.vc.v.vvw[ ]+0x3,v0,v2,v1
+[ ]+[0-9a-f]+:[ ]+fc25c05b[ ]+sf.vc.v.xvw[ ]+0x3,v0,v2,a1
+[ ]+[0-9a-f]+:[ ]+fc27b05b[ ]+sf.vc.v.ivw[ ]+0x3,v0,v2,15
+[ ]+[0-9a-f]+:[ ]+fc25d05b[ ]+sf.vc.v.fvw[ ]+0x1,v0,v2,fa1
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
new file mode 100644
index 0000000..d593692
--- /dev/null
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -0,0 +1,33 @@
+ .attribute arch, "rv32iv"
+ # xsfvcp
+ .option push
+ .option arch, +xsfvcp
+ sf.vc.x 0x3, 0xf, 0x1f, a1
+ sf.vc.i 0x3, 0xf, 0x1f, 15
+ sf.vc.vv 0x3, 0x1f, v2, v1
+ sf.vc.xv 0x3, 0x1f, v2, a1
+ sf.vc.iv 0x3, 0x1f, v2, 15
+ sf.vc.fv 0x1, 0x1f, v2, fa1
+ sf.vc.vvv 0x3, v0, v2, v1
+ sf.vc.xvv 0x3, v0, v2, a1
+ sf.vc.ivv 0x3, v0, v2, 15
+ sf.vc.fvv 0x1, v0, v2, fa1
+ sf.vc.vvw 0x3, v0, v2, v1
+ sf.vc.xvw 0x3, v0, v2, a1
+ sf.vc.ivw 0x3, v0, v2, 15
+ sf.vc.fvw 0x1, v0, v2, fa1
+ sf.vc.v.x 0x3, 0xf, v0, a1
+ sf.vc.v.i 0x3, 0xf, v0, 15
+ sf.vc.v.vv 0x3, v0, v2, v1
+ sf.vc.v.xv 0x3, v0, v2, a1
+ sf.vc.v.iv 0x3, v0, v2, 15
+ sf.vc.v.fv 0x1, v0, v2, fa1
+ sf.vc.v.vvv 0x3, v0, v2, v1
+ sf.vc.v.xvv 0x3, v0, v2, a1
+ sf.vc.v.ivv 0x3, v0, v2, 15
+ sf.vc.v.fvv 0x1, v0, v2, fa1
+ sf.vc.v.vvw 0x3, v0, v2, v1
+ sf.vc.v.xvw 0x3, v0, v2, a1
+ sf.vc.v.ivw 0x3, v0, v2, 15
+ sf.vc.v.fvw 0x1, v0, v2, fa1
+ .option pop
generated by cgit v1.1 at 2025-02-20 16:15:53 +0000