From 7eb1f99adaa3515463b6082e4a911d8b334e852f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 1 Jul 2021 01:04:48 -0400 Subject: sim: unify reserved instruction bits settings Move these options up to the common dir so we only test & export them once across all ports. The setting only affects igen based ports, and they were turning this on by default, so keep the default in place. --- sim/riscv/ChangeLog | 4 ++++ sim/riscv/configure | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'sim/riscv') diff --git a/sim/riscv/ChangeLog b/sim/riscv/ChangeLog index ee7246a..e9aa744 100644 --- a/sim/riscv/ChangeLog +++ b/sim/riscv/ChangeLog @@ -1,3 +1,7 @@ +2021-07-01 Mike Frysinger + + * configure: Regenerate. + 2021-06-30 Mike Frysinger * configure: Regenerate. diff --git a/sim/riscv/configure b/sim/riscv/configure index e366d09..577d4cd 100755 --- a/sim/riscv/configure +++ b/sim/riscv/configure @@ -586,7 +586,6 @@ ac_subst_vars='LTLIBOBJS LIBOBJS SIM_COMMON_BUILD_FALSE SIM_COMMON_BUILD_TRUE -sim_reserved_bits sim_float cgen_breaks target_alias @@ -1760,7 +1759,6 @@ ac_config_commands="$ac_config_commands stamp-h" - SIM_COMMON_BUILD_TRUE='#' SIM_COMMON_BUILD_FALSE= -- cgit v1.1