This commit was manufactured by cvs2svn to create branch 'cr-0x5f1'.cr-0x5f1

Sprout from master 2006-07-25 08:39:57 UTC Paolo Bonzini <bonzini@gnu.org> 'Sync from GCC'
Cherrypick from cygnus 2000-02-22 15:59:20 UTC Ian Lance Taylor <ian@airs.com> 'import libiberty from egcs':
    README
    config/mh-armpic
    config/mh-elfalphapic
    config/mh-m68kpic
    config/mh-papic
    config/mh-ppcpic
    config/mh-x86pic
    config/mt-d30v
    config/mt-netware
    config/mt-ospace
    etc/add-log.el
    etc/add-log.vi
    etc/configbuild.ein
    etc/configbuild.fig
    etc/configbuild.jin
    etc/configbuild.tin
    etc/configdev.ein
    etc/configdev.fig
    etc/configdev.jin
    etc/configdev.tin
    include/aout/hppa.h
    include/coff/sym.h
    include/fopen-bin.h
    include/fopen-same.h
    include/fopen-vms.h
    include/opcode/tahoe.h
    libiberty/config.h-vms
    libiberty/config/mh-aix
    libiberty/config/mh-cxux7
    libiberty/config/mh-fbsd21
    libiberty/config/mh-windows
    libiberty/makefile.vms
    libiberty/msdos.c
    libiberty/vmsbuild.com
    makefile.vms
Delete:
    bfd/COPYING
    bfd/ChangeLog
    bfd/ChangeLog-0001
    bfd/ChangeLog-0203
    bfd/ChangeLog-2004
    bfd/ChangeLog-2005
    bfd/ChangeLog-9193
    bfd/ChangeLog-9495
    bfd/ChangeLog-9697
    bfd/ChangeLog-9899
    bfd/MAINTAINERS
    bfd/Makefile.am
    bfd/Makefile.in
    bfd/PORTING
    bfd/README
    bfd/TODO
    bfd/acinclude.m4
    bfd/aclocal.m4
    bfd/aix386-core.c
    bfd/aix5ppc-core.c
    bfd/aout-adobe.c
    bfd/aout-arm.c
    bfd/aout-cris.c
    bfd/aout-ns32k.c
    bfd/aout-sparcle.c
    bfd/aout-target.h
    bfd/aout-tic30.c
    bfd/aout0.c
    bfd/aout32.c
    bfd/aout64.c
    bfd/aoutf1.h
    bfd/aoutx.h
    bfd/archive.c
    bfd/archive64.c
    bfd/archures.c
    bfd/armnetbsd.c
    bfd/bfd-in.h
    bfd/bfd-in2.h
    bfd/bfd.c
    bfd/bfd.m4
    bfd/bfdio.c
    bfd/bfdwin.c
    bfd/binary.c
    bfd/bout.c
    bfd/cache.c
    bfd/cf-i386lynx.c
    bfd/cf-sparclynx.c
    bfd/cisco-core.c
    bfd/coff-alpha.c
    bfd/coff-apollo.c
    bfd/coff-arm.c
    bfd/coff-aux.c
    bfd/coff-go32.c
    bfd/coff-h8300.c
    bfd/coff-h8500.c
    bfd/coff-i386.c
    bfd/coff-i860.c
    bfd/coff-i960.c
    bfd/coff-ia64.c
    bfd/coff-m68k.c
    bfd/coff-m88k.c
    bfd/coff-maxq.c
    bfd/coff-mcore.c
    bfd/coff-mips.c
    bfd/coff-or32.c
    bfd/coff-pmac.c
    bfd/coff-ppc.c
    bfd/coff-rs6000.c
    bfd/coff-sh.c
    bfd/coff-sparc.c
    bfd/coff-stgo32.c
    bfd/coff-svm68k.c
    bfd/coff-tic30.c
    bfd/coff-tic4x.c
    bfd/coff-tic54x.c
    bfd/coff-tic80.c
    bfd/coff-u68k.c
    bfd/coff-w65.c
    bfd/coff-we32k.c
    bfd/coff-z80.c
    bfd/coff-z8k.c
    bfd/coff64-rs6000.c
    bfd/coffcode.h
    bfd/coffgen.c
    bfd/cofflink.c
    bfd/coffswap.h
    bfd/config.bfd
    bfd/config.in
    bfd/configure
    bfd/configure.com
    bfd/configure.host
    bfd/configure.in
    bfd/corefile.c
    bfd/cpu-alpha.c
    bfd/cpu-arc.c
    bfd/cpu-arm.c
    bfd/cpu-avr.c
    bfd/cpu-bfin.c
    bfd/cpu-cr16c.c
    bfd/cpu-cris.c
    bfd/cpu-crx.c
    bfd/cpu-d10v.c
    bfd/cpu-d30v.c
    bfd/cpu-dlx.c
    bfd/cpu-fr30.c
    bfd/cpu-frv.c
    bfd/cpu-h8300.c
    bfd/cpu-h8500.c
    bfd/cpu-hppa.c
    bfd/cpu-i370.c
    bfd/cpu-i386.c
    bfd/cpu-i860.c
    bfd/cpu-i960.c
    bfd/cpu-ia64-opc.c
    bfd/cpu-ia64.c
    bfd/cpu-ip2k.c
    bfd/cpu-iq2000.c
    bfd/cpu-m10200.c
    bfd/cpu-m10300.c
    bfd/cpu-m32c.c
    bfd/cpu-m32r.c
    bfd/cpu-m68hc11.c
    bfd/cpu-m68hc12.c
    bfd/cpu-m68k.c
    bfd/cpu-m88k.c
    bfd/cpu-maxq.c
    bfd/cpu-mcore.c
    bfd/cpu-mips.c
    bfd/cpu-mmix.c
    bfd/cpu-msp430.c
    bfd/cpu-mt.c
    bfd/cpu-ns32k.c
    bfd/cpu-openrisc.c
    bfd/cpu-or32.c
    bfd/cpu-pdp11.c
    bfd/cpu-pj.c
    bfd/cpu-powerpc.c
    bfd/cpu-rs6000.c
    bfd/cpu-s390.c
    bfd/cpu-sh.c
    bfd/cpu-sparc.c
    bfd/cpu-tic30.c
    bfd/cpu-tic4x.c
    bfd/cpu-tic54x.c
    bfd/cpu-tic80.c
    bfd/cpu-v850.c
    bfd/cpu-vax.c
    bfd/cpu-w65.c
    bfd/cpu-we32k.c
    bfd/cpu-xc16x.c
    bfd/cpu-xstormy16.c
    bfd/cpu-xtensa.c
    bfd/cpu-z80.c
    bfd/cpu-z8k.c
    bfd/demo64.c
    bfd/dep-in.sed
    bfd/doc/ChangeLog
    bfd/doc/ChangeLog-9103
    bfd/doc/Makefile.am
    bfd/doc/Makefile.in
    bfd/doc/bfd.texinfo
    bfd/doc/bfdint.texi
    bfd/doc/bfdsumm.texi
    bfd/doc/chew.c
    bfd/doc/doc.str
    bfd/doc/fdl.texi
    bfd/doc/header.sed
    bfd/doc/makefile.vms
    bfd/doc/proto.str
    bfd/dwarf1.c
    bfd/dwarf2.c
    bfd/ecoff.c
    bfd/ecofflink.c
    bfd/ecoffswap.h
    bfd/efi-app-ia32.c
    bfd/efi-app-ia64.c
    bfd/elf-bfd.h
    bfd/elf-eh-frame.c
    bfd/elf-hppa.h
    bfd/elf-m10200.c
    bfd/elf-m10300.c
    bfd/elf-strtab.c
    bfd/elf-vxworks.c
    bfd/elf-vxworks.h
    bfd/elf.c
    bfd/elf32-am33lin.c
    bfd/elf32-arc.c
    bfd/elf32-arm.c
    bfd/elf32-avr.c
    bfd/elf32-avr.h
    bfd/elf32-bfin.c
    bfd/elf32-cr16c.c
    bfd/elf32-cris.c
    bfd/elf32-crx.c
    bfd/elf32-d10v.c
    bfd/elf32-d30v.c
    bfd/elf32-dlx.c
    bfd/elf32-fr30.c
    bfd/elf32-frv.c
    bfd/elf32-gen.c
    bfd/elf32-h8300.c
    bfd/elf32-hppa.c
    bfd/elf32-hppa.h
    bfd/elf32-i370.c
    bfd/elf32-i386.c
    bfd/elf32-i860.c
    bfd/elf32-i960.c
    bfd/elf32-ip2k.c
    bfd/elf32-iq2000.c
    bfd/elf32-m32c.c
    bfd/elf32-m32r.c
    bfd/elf32-m68hc11.c
    bfd/elf32-m68hc12.c
    bfd/elf32-m68hc1x.c
    bfd/elf32-m68hc1x.h
    bfd/elf32-m68k.c
    bfd/elf32-m88k.c
    bfd/elf32-mcore.c
    bfd/elf32-mips.c
    bfd/elf32-msp430.c
    bfd/elf32-mt.c
    bfd/elf32-openrisc.c
    bfd/elf32-or32.c
    bfd/elf32-pj.c
    bfd/elf32-ppc.c
    bfd/elf32-ppc.h
    bfd/elf32-s390.c
    bfd/elf32-sh-symbian.c
    bfd/elf32-sh.c
    bfd/elf32-sh64-com.c
    bfd/elf32-sh64.c
    bfd/elf32-sh64.h
    bfd/elf32-sparc.c
    bfd/elf32-v850.c
    bfd/elf32-vax.c
    bfd/elf32-xc16x.c
    bfd/elf32-xstormy16.c
    bfd/elf32-xtensa.c
    bfd/elf32.c
    bfd/elf64-alpha.c
    bfd/elf64-gen.c
    bfd/elf64-hppa.c
    bfd/elf64-hppa.h
    bfd/elf64-mips.c
    bfd/elf64-mmix.c
    bfd/elf64-ppc.c
    bfd/elf64-ppc.h
    bfd/elf64-s390.c
    bfd/elf64-sh64.c
    bfd/elf64-sparc.c
    bfd/elf64-x86-64.c
    bfd/elf64.c
    bfd/elfcode.h
    bfd/elfcore.h
    bfd/elflink.c
    bfd/elfn32-mips.c
    bfd/elfxx-ia64.c
    bfd/elfxx-mips.c
    bfd/elfxx-mips.h
    bfd/elfxx-sparc.c
    bfd/elfxx-sparc.h
    bfd/elfxx-target.h
    bfd/epoc-pe-arm.c
    bfd/epoc-pei-arm.c
    bfd/format.c
    bfd/freebsd.h
    bfd/gen-aout.c
    bfd/genlink.h
    bfd/go32stub.h
    bfd/hash.c
    bfd/host-aout.c
    bfd/hosts/alphalinux.h
    bfd/hosts/alphavms.h
    bfd/hosts/decstation.h
    bfd/hosts/delta68.h
    bfd/hosts/dpx2.h
    bfd/hosts/hp300bsd.h
    bfd/hosts/i386bsd.h
    bfd/hosts/i386linux.h
    bfd/hosts/i386mach3.h
    bfd/hosts/i386sco.h
    bfd/hosts/i860mach3.h
    bfd/hosts/m68kaux.h
    bfd/hosts/m68klinux.h
    bfd/hosts/m88kmach3.h
    bfd/hosts/mipsbsd.h
    bfd/hosts/mipsmach3.h
    bfd/hosts/news-mips.h
    bfd/hosts/news.h
    bfd/hosts/pc532mach.h
    bfd/hosts/riscos.h
    bfd/hosts/symmetry.h
    bfd/hosts/tahoe.h
    bfd/hosts/vaxbsd.h
    bfd/hosts/vaxlinux.h
    bfd/hosts/vaxult.h
    bfd/hosts/vaxult2.h
    bfd/hp300bsd.c
    bfd/hp300hpux.c
    bfd/hppabsd-core.c
    bfd/hpux-core.c
    bfd/i386aout.c
    bfd/i386bsd.c
    bfd/i386dynix.c
    bfd/i386freebsd.c
    bfd/i386linux.c
    bfd/i386lynx.c
    bfd/i386mach3.c
    bfd/i386msdos.c
    bfd/i386netbsd.c
    bfd/i386os9k.c
    bfd/ieee.c
    bfd/ihex.c
    bfd/init.c
    bfd/irix-core.c
    bfd/libaout.h
    bfd/libbfd-in.h
    bfd/libbfd.c
    bfd/libbfd.h
    bfd/libcoff-in.h
    bfd/libcoff.h
    bfd/libecoff.h
    bfd/libhppa.h
    bfd/libieee.h
    bfd/libnlm.h
    bfd/liboasys.h
    bfd/libpei.h
    bfd/libxcoff.h
    bfd/linker.c
    bfd/lynx-core.c
    bfd/m68k4knetbsd.c
    bfd/m68klinux.c
    bfd/m68knetbsd.c
    bfd/m88kmach3.c
    bfd/m88kopenbsd.c
    bfd/mach-o-target.c
    bfd/mach-o.c
    bfd/mach-o.h
    bfd/makefile.vms
    bfd/merge.c
    bfd/mipsbsd.c
    bfd/mmo.c
    bfd/netbsd-core.c
    bfd/netbsd.h
    bfd/newsos3.c
    bfd/nlm-target.h
    bfd/nlm.c
    bfd/nlm32-alpha.c
    bfd/nlm32-i386.c
    bfd/nlm32-ppc.c
    bfd/nlm32-sparc.c
    bfd/nlm32.c
    bfd/nlm64.c
    bfd/nlmcode.h
    bfd/nlmswap.h
    bfd/ns32k.h
    bfd/ns32knetbsd.c
    bfd/oasys.c
    bfd/opncls.c
    bfd/osf-core.c
    bfd/pc532-mach.c
    bfd/pdp11.c
    bfd/pe-arm.c
    bfd/pe-i386.c
    bfd/pe-mcore.c
    bfd/pe-mips.c
    bfd/pe-ppc.c
    bfd/pe-sh.c
    bfd/peXXigen.c
    bfd/pef-traceback.h
    bfd/pef.c
    bfd/pef.h
    bfd/pei-arm.c
    bfd/pei-i386.c
    bfd/pei-mcore.c
    bfd/pei-mips.c
    bfd/pei-ppc.c
    bfd/pei-sh.c
    bfd/peicode.h
    bfd/po/.cvsignore
    bfd/po/BLD-POTFILES.in
    bfd/po/Make-in
    bfd/po/SRC-POTFILES.in
    bfd/po/bfd.pot
    bfd/po/da.po
    bfd/po/es.po
    bfd/po/fr.po
    bfd/po/ja.po
    bfd/po/ro.po
    bfd/po/rw.po
    bfd/po/sv.po
    bfd/po/tr.po
    bfd/po/vi.po
    bfd/po/zh_CN.po
    bfd/ppcboot.c
    bfd/ptrace-core.c
    bfd/reloc.c
    bfd/reloc16.c
    bfd/riscix.c
    bfd/rs6000-core.c
    bfd/sco5-core.c
    bfd/section.c
    bfd/simple.c
    bfd/som.c
    bfd/som.h
    bfd/sparclinux.c
    bfd/sparclynx.c
    bfd/sparcnetbsd.c
    bfd/srec.c
    bfd/stab-syms.c
    bfd/stabs.c
    bfd/stamp-h.in
    bfd/sunos.c
    bfd/syms.c
    bfd/sysdep.h
    bfd/targets.c
    bfd/targmatch.sed
    bfd/tekhex.c
    bfd/ticoff.h
    bfd/trad-core.c
    bfd/vax1knetbsd.c
    bfd/vaxbsd.c
    bfd/vaxnetbsd.c
    bfd/versados.c
    bfd/version.h
    bfd/vms-gsd.c
    bfd/vms-hdr.c
    bfd/vms-misc.c
    bfd/vms-tir.c
    bfd/vms.c
    bfd/vms.h
    bfd/warning.m4
    bfd/xcoff-target.h
    bfd/xcofflink.c
    bfd/xsym.c
    bfd/xsym.h
    bfd/xtensa-isa.c
    bfd/xtensa-modules.c
    binutils/BRANCHES
    binutils/ChangeLog
    binutils/ChangeLog-0001
    binutils/ChangeLog-0203
    binutils/ChangeLog-2004
    binutils/ChangeLog-2005
    binutils/ChangeLog-9197
    binutils/ChangeLog-9899
    binutils/MAINTAINERS
    binutils/Makefile.am
    binutils/Makefile.in
    binutils/NEWS
    binutils/README
    binutils/acinclude.m4
    binutils/aclocal.m4
    binutils/addr2line.c
    binutils/ar.c
    binutils/arlex.l
    binutils/arparse.y
    binutils/arsup.c
    binutils/arsup.h
    binutils/binemul.c
    binutils/binemul.h
    binutils/bucomm.c
    binutils/bucomm.h
    binutils/budbg.h
    binutils/budemang.c
    binutils/budemang.h
    binutils/coffdump.c
    binutils/coffgrok.c
    binutils/coffgrok.h
    binutils/config.in
    binutils/configure
    binutils/configure.com
    binutils/configure.in
    binutils/configure.tgt
    binutils/cxxfilt.c
    binutils/debug.c
    binutils/debug.h
    binutils/deflex.l
    binutils/defparse.y
    binutils/dep-in.sed
    binutils/dlltool.c
    binutils/dlltool.h
    binutils/dllwrap.c
    binutils/doc/Makefile.am
    binutils/doc/Makefile.in
    binutils/doc/binutils.texi
    binutils/doc/fdl.texi
    binutils/dwarf.c
    binutils/dwarf.h
    binutils/emul_aix.c
    binutils/emul_vanilla.c
    binutils/filemode.c
    binutils/ieee.c
    binutils/is-ranlib.c
    binutils/is-strip.c
    binutils/makefile.vms-in
    binutils/maybe-ranlib.c
    binutils/maybe-strip.c
    binutils/nlmconv.c
    binutils/nlmconv.h
    binutils/nlmheader.y
    binutils/nm.c
    binutils/not-ranlib.c
    binutils/not-strip.c
    binutils/objcopy.c
    binutils/objdump.c
    binutils/po/.cvsignore
    binutils/po/Make-in
    binutils/po/POTFILES.in
    binutils/po/binutils.pot
    binutils/po/da.po
    binutils/po/es.po
    binutils/po/fi.po
    binutils/po/fr.po
    binutils/po/ja.po
    binutils/po/ro.po
    binutils/po/ru.po
    binutils/po/rw.po
    binutils/po/sv.po
    binutils/po/tr.po
    binutils/po/vi.po
    binutils/po/zh_CN.po
    binutils/po/zh_TW.po
    binutils/prdbg.c
    binutils/ranlib.sh
    binutils/rclex.l
    binutils/rcparse.y
    binutils/rdcoff.c
    binutils/rddbg.c
    binutils/readelf.c
    binutils/rename.c
    binutils/resbin.c
    binutils/rescoff.c
    binutils/resrc.c
    binutils/resres.c
    binutils/sanity.sh
    binutils/size.c
    binutils/srconv.c
    binutils/stabs.c
    binutils/stamp-h.in
    binutils/strings.c
    binutils/sysdump.c
    binutils/sysinfo.y
    binutils/syslex.l
    binutils/sysroff.info
    binutils/testsuite/ChangeLog
    binutils/testsuite/ChangeLog-9303
    binutils/testsuite/binutils-all/alias.def
    binutils/testsuite/binutils-all/ar.exp
    binutils/testsuite/binutils-all/arm/objdump.exp
    binutils/testsuite/binutils-all/arm/thumb2-cond.s
    binutils/testsuite/binutils-all/bintest.s
    binutils/testsuite/binutils-all/copy-1.d
    binutils/testsuite/binutils-all/copy-1.s
    binutils/testsuite/binutils-all/copy-2.d
    binutils/testsuite/binutils-all/copy-3.d
    binutils/testsuite/binutils-all/copytest.s
    binutils/testsuite/binutils-all/dlltool.exp
    binutils/testsuite/binutils-all/fastcall.def
    binutils/testsuite/binutils-all/group.s
    binutils/testsuite/binutils-all/hppa/addendbug.s
    binutils/testsuite/binutils-all/hppa/freg.s
    binutils/testsuite/binutils-all/hppa/objdump.exp
    binutils/testsuite/binutils-all/link-order.s
    binutils/testsuite/binutils-all/localize-hidden-1.d
    binutils/testsuite/binutils-all/localize-hidden-1.s
    binutils/testsuite/binutils-all/localize-hidden-2.d
    binutils/testsuite/binutils-all/localize-hidden-2.s
    binutils/testsuite/binutils-all/m68k/movem.s
    binutils/testsuite/binutils-all/m68k/objdump.exp
    binutils/testsuite/binutils-all/nm.exp
    binutils/testsuite/binutils-all/objcopy.exp
    binutils/testsuite/binutils-all/objdump.exp
    binutils/testsuite/binutils-all/readelf.exp
    binutils/testsuite/binutils-all/readelf.h
    binutils/testsuite/binutils-all/readelf.r
    binutils/testsuite/binutils-all/readelf.r-64
    binutils/testsuite/binutils-all/readelf.s
    binutils/testsuite/binutils-all/readelf.s-64
    binutils/testsuite/binutils-all/readelf.ss
    binutils/testsuite/binutils-all/readelf.ss-64
    binutils/testsuite/binutils-all/readelf.ss-mips
    binutils/testsuite/binutils-all/readelf.ss-tmips
    binutils/testsuite/binutils-all/size.exp
    binutils/testsuite/binutils-all/testprog.c
    binutils/testsuite/binutils-all/unknown.s
    binutils/testsuite/binutils-all/vax/entrymask.s
    binutils/testsuite/binutils-all/vax/objdump.exp
    binutils/testsuite/binutils-all/windres/README
    binutils/testsuite/binutils-all/windres/bmp1.bmp
    binutils/testsuite/binutils-all/windres/bmpalign.rc
    binutils/testsuite/binutils-all/windres/bmpalign.rsd
    binutils/testsuite/binutils-all/windres/capstyle.rc
    binutils/testsuite/binutils-all/windres/capstyle.rsd
    binutils/testsuite/binutils-all/windres/checkbox.rc
    binutils/testsuite/binutils-all/windres/checkbox.rsd
    binutils/testsuite/binutils-all/windres/combobox.rc
    binutils/testsuite/binutils-all/windres/combobox.rsd
    binutils/testsuite/binutils-all/windres/deflang.rc
    binutils/testsuite/binutils-all/windres/deflang.rsd
    binutils/testsuite/binutils-all/windres/dialog0.rc
    binutils/testsuite/binutils-all/windres/dialog0.rsd
    binutils/testsuite/binutils-all/windres/dialog1.rc
    binutils/testsuite/binutils-all/windres/dialog1.rsd
    binutils/testsuite/binutils-all/windres/dialogid.rc
    binutils/testsuite/binutils-all/windres/dialogid.rsd
    binutils/testsuite/binutils-all/windres/dialogsignature.rc
    binutils/testsuite/binutils-all/windres/dialogsignature.rsd
    binutils/testsuite/binutils-all/windres/dlgfont.rc
    binutils/testsuite/binutils-all/windres/dlgfont.rsd
    binutils/testsuite/binutils-all/windres/edittext.rc
    binutils/testsuite/binutils-all/windres/edittext.rsd
    binutils/testsuite/binutils-all/windres/escapea.rc
    binutils/testsuite/binutils-all/windres/escapea.rsd
    binutils/testsuite/binutils-all/windres/escapex-2.rc
    binutils/testsuite/binutils-all/windres/escapex-2.rsd
    binutils/testsuite/binutils-all/windres/escapex.rc
    binutils/testsuite/binutils-all/windres/escapex.rsd
    binutils/testsuite/binutils-all/windres/lang.rc
    binutils/testsuite/binutils-all/windres/lang.rsd
    binutils/testsuite/binutils-all/windres/listbox.rc
    binutils/testsuite/binutils-all/windres/listbox.rsd
    binutils/testsuite/binutils-all/windres/msupdate
    binutils/testsuite/binutils-all/windres/nocaption.rc
    binutils/testsuite/binutils-all/windres/nocaption.rsd
    binutils/testsuite/binutils-all/windres/printstyle.rc
    binutils/testsuite/binutils-all/windres/printstyle.rsd
    binutils/testsuite/binutils-all/windres/quoteclass.rc
    binutils/testsuite/binutils-all/windres/scrollbar.rc
    binutils/testsuite/binutils-all/windres/scrollbar.rsd
    binutils/testsuite/binutils-all/windres/strtab1.rc
    binutils/testsuite/binutils-all/windres/strtab1.rsd
    binutils/testsuite/binutils-all/windres/sublang.rc
    binutils/testsuite/binutils-all/windres/sublang.rsd
    binutils/testsuite/binutils-all/windres/windres.exp
    binutils/testsuite/config/default.exp
    binutils/testsuite/config/hppa.sed
    binutils/testsuite/lib/utils-lib.exp
    binutils/unwind-ia64.c
    binutils/unwind-ia64.h
    binutils/version.c
    binutils/windres.c
    binutils/windres.h
    binutils/winduni.c
    binutils/winduni.h
    binutils/wrstabs.c
    compile
    config.rpath
    cpu/ChangeLog
    cpu/cris.cpu
    cpu/frv.cpu
    cpu/frv.opc
    cpu/iq10.cpu
    cpu/iq2000.cpu
    cpu/iq2000.opc
    cpu/iq2000m.cpu
    cpu/m32c.cpu
    cpu/m32c.opc
    cpu/m32r.cpu
    cpu/m32r.opc
    cpu/mt.cpu
    cpu/mt.opc
    cpu/sh.cpu
    cpu/sh.opc
    cpu/sh64-compact.cpu
    cpu/sh64-media.cpu
    cpu/simplify.inc
    cpu/xc16x.cpu
    cpu/xc16x.opc
    djunpack.bat
    gas/CONTRIBUTORS
    gas/COPYING
    gas/ChangeLog
    gas/ChangeLog-0001
    gas/ChangeLog-0203
    gas/ChangeLog-2004
    gas/ChangeLog-2005
    gas/ChangeLog-9295
    gas/ChangeLog-9697
    gas/ChangeLog-9899
    gas/MAINTAINERS
    gas/Makefile.am
    gas/Makefile.in
    gas/NEWS
    gas/README
    gas/acinclude.m4
    gas/aclocal.m4
    gas/app.c
    gas/as.c
    gas/as.h
    gas/asintl.h
    gas/atof-generic.c
    gas/bignum.h
    gas/bit_fix.h
    gas/cgen.c
    gas/cgen.h
    gas/cond.c
    gas/config.in
    gas/config/aout_gnu.h
    gas/config/atof-ieee.c
    gas/config/atof-vax.c
    gas/config/bfin-aux.h
    gas/config/bfin-defs.h
    gas/config/bfin-lex.l
    gas/config/bfin-parse.y
    gas/config/e-crisaout.c
    gas/config/e-criself.c
    gas/config/e-i386aout.c
    gas/config/e-i386coff.c
    gas/config/e-i386elf.c
    gas/config/e-mipsecoff.c
    gas/config/e-mipself.c
    gas/config/itbl-mips.h
    gas/config/m68k-parse.h
    gas/config/m68k-parse.y
    gas/config/obj-aout.c
    gas/config/obj-aout.h
    gas/config/obj-coff.c
    gas/config/obj-coff.h
    gas/config/obj-ecoff.c
    gas/config/obj-ecoff.h
    gas/config/obj-elf.c
    gas/config/obj-elf.h
    gas/config/obj-evax.c
    gas/config/obj-evax.h
    gas/config/obj-multi.c
    gas/config/obj-multi.h
    gas/config/obj-som.c
    gas/config/obj-som.h
    gas/config/tc-alpha.c
    gas/config/tc-alpha.h
    gas/config/tc-arc.c
    gas/config/tc-arc.h
    gas/config/tc-arm.c
    gas/config/tc-arm.h
    gas/config/tc-avr.c
    gas/config/tc-avr.h
    gas/config/tc-bfin.c
    gas/config/tc-bfin.h
    gas/config/tc-cris.c
    gas/config/tc-cris.h
    gas/config/tc-crx.c
    gas/config/tc-crx.h
    gas/config/tc-d10v.c
    gas/config/tc-d10v.h
    gas/config/tc-d30v.c
    gas/config/tc-d30v.h
    gas/config/tc-dlx.c
    gas/config/tc-dlx.h
    gas/config/tc-fr30.c
    gas/config/tc-fr30.h
    gas/config/tc-frv.c
    gas/config/tc-frv.h
    gas/config/tc-generic.c
    gas/config/tc-generic.h
    gas/config/tc-h8300.c
    gas/config/tc-h8300.h
    gas/config/tc-hppa.c
    gas/config/tc-hppa.h
    gas/config/tc-i370.c
    gas/config/tc-i370.h
    gas/config/tc-i386.c
    gas/config/tc-i386.h
    gas/config/tc-i860.c
    gas/config/tc-i860.h
    gas/config/tc-i960.c
    gas/config/tc-i960.h
    gas/config/tc-ia64.c
    gas/config/tc-ia64.h
    gas/config/tc-ip2k.c
    gas/config/tc-ip2k.h
    gas/config/tc-iq2000.c
    gas/config/tc-iq2000.h
    gas/config/tc-m32c.c
    gas/config/tc-m32c.h
    gas/config/tc-m32r.c
    gas/config/tc-m32r.h
    gas/config/tc-m68851.h
    gas/config/tc-m68hc11.c
    gas/config/tc-m68hc11.h
    gas/config/tc-m68k.c
    gas/config/tc-m68k.h
    gas/config/tc-maxq.c
    gas/config/tc-maxq.h
    gas/config/tc-mcore.c
    gas/config/tc-mcore.h
    gas/config/tc-mips.c
    gas/config/tc-mips.h
    gas/config/tc-mmix.c
    gas/config/tc-mmix.h
    gas/config/tc-mn10200.c
    gas/config/tc-mn10200.h
    gas/config/tc-mn10300.c
    gas/config/tc-mn10300.h
    gas/config/tc-msp430.c
    gas/config/tc-msp430.h
    gas/config/tc-mt.c
    gas/config/tc-mt.h
    gas/config/tc-ns32k.c
    gas/config/tc-ns32k.h
    gas/config/tc-openrisc.c
    gas/config/tc-openrisc.h
    gas/config/tc-or32.c
    gas/config/tc-or32.h
    gas/config/tc-pdp11.c
    gas/config/tc-pdp11.h
    gas/config/tc-pj.c
    gas/config/tc-pj.h
    gas/config/tc-ppc.c
    gas/config/tc-ppc.h
    gas/config/tc-s390.c
    gas/config/tc-s390.h
    gas/config/tc-sh.c
    gas/config/tc-sh.h
    gas/config/tc-sh64.c
    gas/config/tc-sh64.h
    gas/config/tc-sparc.c
    gas/config/tc-sparc.h
    gas/config/tc-tic30.c
    gas/config/tc-tic30.h
    gas/config/tc-tic4x.c
    gas/config/tc-tic4x.h
    gas/config/tc-tic54x.c
    gas/config/tc-tic54x.h
    gas/config/tc-v850.c
    gas/config/tc-v850.h
    gas/config/tc-vax.c
    gas/config/tc-vax.h
    gas/config/tc-xc16x.c
    gas/config/tc-xc16x.h
    gas/config/tc-xstormy16.c
    gas/config/tc-xstormy16.h
    gas/config/tc-xtensa.c
    gas/config/tc-xtensa.h
    gas/config/tc-z80.c
    gas/config/tc-z80.h
    gas/config/tc-z8k.c
    gas/config/tc-z8k.h
    gas/config/te-386bsd.h
    gas/config/te-aix5.h
    gas/config/te-armeabi.h
    gas/config/te-armlinuxeabi.h
    gas/config/te-dynix.h
    gas/config/te-epoc-pe.h
    gas/config/te-freebsd.h
    gas/config/te-generic.h
    gas/config/te-gnu.h
    gas/config/te-go32.h
    gas/config/te-hppa.h
    gas/config/te-hppa64.h
    gas/config/te-hppalinux64.h
    gas/config/te-hpux.h
    gas/config/te-i386aix.h
    gas/config/te-ia64aix.h
    gas/config/te-interix.h
    gas/config/te-irix.h
    gas/config/te-linux.h
    gas/config/te-lnews.h
    gas/config/te-lynx.h
    gas/config/te-mach.h
    gas/config/te-macos.h
    gas/config/te-nbsd.h
    gas/config/te-nbsd532.h
    gas/config/te-netware.h
    gas/config/te-pc532mach.h
    gas/config/te-pe.h
    gas/config/te-psos.h
    gas/config/te-riscix.h
    gas/config/te-sparcaout.h
    gas/config/te-sun3.h
    gas/config/te-svr4.h
    gas/config/te-symbian.h
    gas/config/te-tmips.h
    gas/config/te-vxworks.h
    gas/config/te-wince-pe.h
    gas/config/vax-inst.h
    gas/config/xtensa-istack.h
    gas/config/xtensa-relax.c
    gas/config/xtensa-relax.h
    gas/configure
    gas/configure.in
    gas/configure.tgt
    gas/debug.c
    gas/dep-in.sed
    gas/depend.c
    gas/doc/Makefile.am
    gas/doc/Makefile.in
    gas/doc/all.texi
    gas/doc/as.texinfo
    gas/doc/c-alpha.texi
    gas/doc/c-arc.texi
    gas/doc/c-arm.texi
    gas/doc/c-avr.texi
    gas/doc/c-bfin.texi
    gas/doc/c-cris.texi
    gas/doc/c-d10v.texi
    gas/doc/c-d30v.texi
    gas/doc/c-h8300.texi
    gas/doc/c-hppa.texi
    gas/doc/c-i370.texi
    gas/doc/c-i386.texi
    gas/doc/c-i860.texi
    gas/doc/c-i960.texi
    gas/doc/c-ia64.texi
    gas/doc/c-ip2k.texi
    gas/doc/c-m32c.texi
    gas/doc/c-m32r.texi
    gas/doc/c-m68hc11.texi
    gas/doc/c-m68k.texi
    gas/doc/c-mips.texi
    gas/doc/c-mmix.texi
    gas/doc/c-msp430.texi
    gas/doc/c-mt.texi
    gas/doc/c-ns32k.texi
    gas/doc/c-pdp11.texi
    gas/doc/c-pj.texi
    gas/doc/c-ppc.texi
    gas/doc/c-sh.texi
    gas/doc/c-sh64.texi
    gas/doc/c-sparc.texi
    gas/doc/c-tic54x.texi
    gas/doc/c-v850.texi
    gas/doc/c-vax.texi
    gas/doc/c-xc16x.texi
    gas/doc/c-xtensa.texi
    gas/doc/c-z80.texi
    gas/doc/c-z8k.texi
    gas/doc/fdl.texi
    gas/doc/h8.texi
    gas/doc/internals.texi
    gas/dw2gencfi.c
    gas/dw2gencfi.h
    gas/dwarf2dbg.c
    gas/dwarf2dbg.h
    gas/ecoff.c
    gas/ecoff.h
    gas/ehopt.c
    gas/emul-target.h
    gas/emul.h
    gas/expr.c
    gas/expr.h
    gas/flonum-copy.c
    gas/flonum-konst.c
    gas/flonum-mult.c
    gas/flonum.h
    gas/frags.c
    gas/frags.h
    gas/gdbinit.in
    gas/hash.c
    gas/hash.h
    gas/input-file.c
    gas/input-file.h
    gas/input-scrub.c
    gas/itbl-lex.h
    gas/itbl-lex.l
    gas/itbl-ops.c
    gas/itbl-ops.h
    gas/itbl-parse.y
    gas/listing.c
    gas/listing.h
    gas/literal.c
    gas/macro.c
    gas/macro.h
    gas/messages.c
    gas/obj.h
    gas/output-file.c
    gas/output-file.h
    gas/po/.cvsignore
    gas/po/Make-in
    gas/po/POTFILES.in
    gas/po/es.po
    gas/po/fr.po
    gas/po/gas.pot
    gas/po/rw.po
    gas/po/tr.po
    gas/read.c
    gas/read.h
    gas/sb.c
    gas/sb.h
    gas/stabs.c
    gas/stamp-h.in
    gas/struc-symbol.h
    gas/subsegs.c
    gas/subsegs.h
    gas/symbols.c
    gas/symbols.h
    gas/tc.h
    gas/testsuite/ChangeLog
    gas/testsuite/ChangeLog-2004
    gas/testsuite/ChangeLog-2005
    gas/testsuite/ChangeLog-9303
    gas/testsuite/config/default.exp
    gas/testsuite/gas/all/align.d
    gas/testsuite/gas/all/align.s
    gas/testsuite/gas/all/align2.d
    gas/testsuite/gas/all/align2.s
    gas/testsuite/gas/all/altmac2.d
    gas/testsuite/gas/all/altmac2.s
    gas/testsuite/gas/all/altmacro.d
    gas/testsuite/gas/all/altmacro.s
    gas/testsuite/gas/all/assign-bad.s
    gas/testsuite/gas/all/assign-ok.s
    gas/testsuite/gas/all/assign.d
    gas/testsuite/gas/all/assign.s
    gas/testsuite/gas/all/cofftag.d
    gas/testsuite/gas/all/cofftag.s
    gas/testsuite/gas/all/comment.s
    gas/testsuite/gas/all/cond.l
    gas/testsuite/gas/all/cond.s
    gas/testsuite/gas/all/diff1.s
    gas/testsuite/gas/all/equ-bad.s
    gas/testsuite/gas/all/equ-ok.s
    gas/testsuite/gas/all/equiv1.s
    gas/testsuite/gas/all/equiv2.s
    gas/testsuite/gas/all/eqv-bad.s
    gas/testsuite/gas/all/eqv-ok.s
    gas/testsuite/gas/all/err-1.s
    gas/testsuite/gas/all/eval.d
    gas/testsuite/gas/all/eval.s
    gas/testsuite/gas/all/excl.s
    gas/testsuite/gas/all/fastcall.s
    gas/testsuite/gas/all/float.s
    gas/testsuite/gas/all/forward.d
    gas/testsuite/gas/all/forward.s
    gas/testsuite/gas/all/gas.exp
    gas/testsuite/gas/all/incbin.d
    gas/testsuite/gas/all/incbin.dat
    gas/testsuite/gas/all/incbin.s
    gas/testsuite/gas/all/itbl
    gas/testsuite/gas/all/itbl-test.c
    gas/testsuite/gas/all/itbl.s
    gas/testsuite/gas/all/p1480.s
    gas/testsuite/gas/all/p2425.s
    gas/testsuite/gas/all/quad.d
    gas/testsuite/gas/all/quad.s
    gas/testsuite/gas/all/redef.d
    gas/testsuite/gas/all/redef.s
    gas/testsuite/gas/all/redef2.d
    gas/testsuite/gas/all/redef2.s
    gas/testsuite/gas/all/redef3.d
    gas/testsuite/gas/all/redef3.s
    gas/testsuite/gas/all/redef4.s
    gas/testsuite/gas/all/redef5.s
    gas/testsuite/gas/all/sleb128.d
    gas/testsuite/gas/all/sleb128.s
    gas/testsuite/gas/all/struct.d
    gas/testsuite/gas/all/struct.s
    gas/testsuite/gas/all/test-example.c
    gas/testsuite/gas/all/test-gen.c
    gas/testsuite/gas/all/warn-1.s
    gas/testsuite/gas/all/weakref1.d
    gas/testsuite/gas/all/weakref1.s
    gas/testsuite/gas/all/weakref1g.d
    gas/testsuite/gas/all/weakref1l.d
    gas/testsuite/gas/all/weakref1u.d
    gas/testsuite/gas/all/weakref1w.d
    gas/testsuite/gas/all/weakref2.s
    gas/testsuite/gas/all/weakref3.s
    gas/testsuite/gas/all/weakref4.s
    gas/testsuite/gas/all/x930509.s
    gas/testsuite/gas/alpha/alpha.exp
    gas/testsuite/gas/alpha/elf-reloc-1.d
    gas/testsuite/gas/alpha/elf-reloc-1.s
    gas/testsuite/gas/alpha/elf-reloc-2.l
    gas/testsuite/gas/alpha/elf-reloc-2.s
    gas/testsuite/gas/alpha/elf-reloc-3.l
    gas/testsuite/gas/alpha/elf-reloc-3.s
    gas/testsuite/gas/alpha/elf-reloc-4.d
    gas/testsuite/gas/alpha/elf-reloc-4.s
    gas/testsuite/gas/alpha/elf-reloc-5.d
    gas/testsuite/gas/alpha/elf-reloc-5.s
    gas/testsuite/gas/alpha/elf-reloc-6.l
    gas/testsuite/gas/alpha/elf-reloc-6.s
    gas/testsuite/gas/alpha/elf-reloc-7.d
    gas/testsuite/gas/alpha/elf-reloc-7.s
    gas/testsuite/gas/alpha/elf-reloc-8.d
    gas/testsuite/gas/alpha/elf-reloc-8.s
    gas/testsuite/gas/alpha/elf-tls-1.d
    gas/testsuite/gas/alpha/elf-tls-1.s
    gas/testsuite/gas/alpha/elf-tls-2.l
    gas/testsuite/gas/alpha/elf-tls-2.s
    gas/testsuite/gas/alpha/elf-tls-3.l
    gas/testsuite/gas/alpha/elf-tls-3.s
    gas/testsuite/gas/alpha/elf-usepv-1.d
    gas/testsuite/gas/alpha/elf-usepv-1.s
    gas/testsuite/gas/alpha/elf-usepv-2.l
    gas/testsuite/gas/alpha/elf-usepv-2.s
    gas/testsuite/gas/alpha/fp.d
    gas/testsuite/gas/alpha/fp.s
    gas/testsuite/gas/alpha/unop.d
    gas/testsuite/gas/alpha/unop.s
    gas/testsuite/gas/arc/adc.d
    gas/testsuite/gas/arc/adc.s
    gas/testsuite/gas/arc/add.d
    gas/testsuite/gas/arc/add.s
    gas/testsuite/gas/arc/alias.d
    gas/testsuite/gas/arc/alias.s
    gas/testsuite/gas/arc/and.d
    gas/testsuite/gas/arc/and.s
    gas/testsuite/gas/arc/arc.exp
    gas/testsuite/gas/arc/asl.d
    gas/testsuite/gas/arc/asl.s
    gas/testsuite/gas/arc/asr.d
    gas/testsuite/gas/arc/asr.s
    gas/testsuite/gas/arc/b.d
    gas/testsuite/gas/arc/b.s
    gas/testsuite/gas/arc/bic.d
    gas/testsuite/gas/arc/bic.s
    gas/testsuite/gas/arc/bl.d
    gas/testsuite/gas/arc/bl.s
    gas/testsuite/gas/arc/branch.d
    gas/testsuite/gas/arc/branch.s
    gas/testsuite/gas/arc/brk.d
    gas/testsuite/gas/arc/brk.s
    gas/testsuite/gas/arc/extb.d
    gas/testsuite/gas/arc/extb.s
    gas/testsuite/gas/arc/extensions.d
    gas/testsuite/gas/arc/extensions.s
    gas/testsuite/gas/arc/extw.d
    gas/testsuite/gas/arc/extw.s
    gas/testsuite/gas/arc/flag.d
    gas/testsuite/gas/arc/flag.s
    gas/testsuite/gas/arc/insn3.d
    gas/testsuite/gas/arc/insn3.s
    gas/testsuite/gas/arc/j.d
    gas/testsuite/gas/arc/j.s
    gas/testsuite/gas/arc/jl.d
    gas/testsuite/gas/arc/jl.s
    gas/testsuite/gas/arc/ld.d
    gas/testsuite/gas/arc/ld.s
    gas/testsuite/gas/arc/ld2.d
    gas/testsuite/gas/arc/ld2.s
    gas/testsuite/gas/arc/lp.d
    gas/testsuite/gas/arc/lp.s
    gas/testsuite/gas/arc/lsr.d
    gas/testsuite/gas/arc/lsr.s
    gas/testsuite/gas/arc/math.d
    gas/testsuite/gas/arc/math.s
    gas/testsuite/gas/arc/mov.d
    gas/testsuite/gas/arc/mov.s
    gas/testsuite/gas/arc/nop.d
    gas/testsuite/gas/arc/nop.s
    gas/testsuite/gas/arc/or.d
    gas/testsuite/gas/arc/or.s
    gas/testsuite/gas/arc/rlc.d
    gas/testsuite/gas/arc/rlc.s
    gas/testsuite/gas/arc/ror.d
    gas/testsuite/gas/arc/ror.s
    gas/testsuite/gas/arc/rrc.d
    gas/testsuite/gas/arc/rrc.s
    gas/testsuite/gas/arc/sbc.d
    gas/testsuite/gas/arc/sbc.s
    gas/testsuite/gas/arc/sexb.d
    gas/testsuite/gas/arc/sexb.s
    gas/testsuite/gas/arc/sexw.d
    gas/testsuite/gas/arc/sexw.s
    gas/testsuite/gas/arc/sleep.d
    gas/testsuite/gas/arc/sleep.s
    gas/testsuite/gas/arc/sshift.d
    gas/testsuite/gas/arc/sshift.s
    gas/testsuite/gas/arc/st.d
    gas/testsuite/gas/arc/st.s
    gas/testsuite/gas/arc/sub.d
    gas/testsuite/gas/arc/sub.s
    gas/testsuite/gas/arc/swi.d
    gas/testsuite/gas/arc/swi.s
    gas/testsuite/gas/arc/warn.exp
    gas/testsuite/gas/arc/warn.s
    gas/testsuite/gas/arc/xor.d
    gas/testsuite/gas/arc/xor.s
    gas/testsuite/gas/arm/abs12.d
    gas/testsuite/gas/arm/abs12.s
    gas/testsuite/gas/arm/adrl.d
    gas/testsuite/gas/arm/adrl.s
    gas/testsuite/gas/arm/arch4t.d
    gas/testsuite/gas/arm/arch4t.s
    gas/testsuite/gas/arm/arch5tej.d
    gas/testsuite/gas/arm/arch5tej.s
    gas/testsuite/gas/arm/arch6zk.d
    gas/testsuite/gas/arm/arch6zk.s
    gas/testsuite/gas/arm/arch7.d
    gas/testsuite/gas/arm/arch7.s
    gas/testsuite/gas/arm/arch7m-bad.d
    gas/testsuite/gas/arm/arch7m-bad.l
    gas/testsuite/gas/arm/arch7m-bad.s
    gas/testsuite/gas/arm/archv6.d
    gas/testsuite/gas/arm/archv6.s
    gas/testsuite/gas/arm/archv6t2-bad.d
    gas/testsuite/gas/arm/archv6t2-bad.l
    gas/testsuite/gas/arm/archv6t2-bad.s
    gas/testsuite/gas/arm/archv6t2.d
    gas/testsuite/gas/arm/archv6t2.s
    gas/testsuite/gas/arm/arm.exp
    gas/testsuite/gas/arm/arm3-bad.d
    gas/testsuite/gas/arm/arm3-bad.l
    gas/testsuite/gas/arm/arm3-bad.s
    gas/testsuite/gas/arm/arm3.d
    gas/testsuite/gas/arm/arm3.s
    gas/testsuite/gas/arm/arm6.d
    gas/testsuite/gas/arm/arm6.s
    gas/testsuite/gas/arm/arm7dm.d
    gas/testsuite/gas/arm/arm7dm.s
    gas/testsuite/gas/arm/arm7t.d
    gas/testsuite/gas/arm/arm7t.s
    gas/testsuite/gas/arm/armv1-bad.d
    gas/testsuite/gas/arm/armv1-bad.l
    gas/testsuite/gas/arm/armv1-bad.s
    gas/testsuite/gas/arm/armv1.d
    gas/testsuite/gas/arm/armv1.l
    gas/testsuite/gas/arm/armv1.s
    gas/testsuite/gas/arm/bignum1.d
    gas/testsuite/gas/arm/bignum1.s
    gas/testsuite/gas/arm/blx-local.d
    gas/testsuite/gas/arm/blx-local.s
    gas/testsuite/gas/arm/copro.d
    gas/testsuite/gas/arm/copro.s
    gas/testsuite/gas/arm/eabi_attr_1.d
    gas/testsuite/gas/arm/eabi_attr_1.s
    gas/testsuite/gas/arm/el_segundo.d
    gas/testsuite/gas/arm/el_segundo.s
    gas/testsuite/gas/arm/float.d
    gas/testsuite/gas/arm/float.s
    gas/testsuite/gas/arm/fpa-dyadic.d
    gas/testsuite/gas/arm/fpa-dyadic.s
    gas/testsuite/gas/arm/fpa-mem.d
    gas/testsuite/gas/arm/fpa-mem.s
    gas/testsuite/gas/arm/fpa-monadic.d
    gas/testsuite/gas/arm/fpa-monadic.s
    gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d
    gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l
    gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s
    gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d
    gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l
    gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s
    gas/testsuite/gas/arm/group-reloc-alu.d
    gas/testsuite/gas/arm/group-reloc-alu.s
    gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d
    gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
    gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
    gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d
    gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
    gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
    gas/testsuite/gas/arm/group-reloc-ldc.d
    gas/testsuite/gas/arm/group-reloc-ldc.s
    gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d
    gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l
    gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s
    gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d
    gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l
    gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s
    gas/testsuite/gas/arm/group-reloc-ldr.d
    gas/testsuite/gas/arm/group-reloc-ldr.s
    gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d
    gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l
    gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s
    gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d
    gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l
    gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s
    gas/testsuite/gas/arm/group-reloc-ldrs.d
    gas/testsuite/gas/arm/group-reloc-ldrs.s
    gas/testsuite/gas/arm/immed.d
    gas/testsuite/gas/arm/immed.s
    gas/testsuite/gas/arm/inst.d
    gas/testsuite/gas/arm/inst.s
    gas/testsuite/gas/arm/itblock.s
    gas/testsuite/gas/arm/iwmmxt-bad.d
    gas/testsuite/gas/arm/iwmmxt-bad.l
    gas/testsuite/gas/arm/iwmmxt-bad.s
    gas/testsuite/gas/arm/iwmmxt-bad2.d
    gas/testsuite/gas/arm/iwmmxt-bad2.l
    gas/testsuite/gas/arm/iwmmxt-bad2.s
    gas/testsuite/gas/arm/iwmmxt.d
    gas/testsuite/gas/arm/iwmmxt.s
    gas/testsuite/gas/arm/ldconst.d
    gas/testsuite/gas/arm/ldconst.s
    gas/testsuite/gas/arm/le-fpconst.d
    gas/testsuite/gas/arm/le-fpconst.s
    gas/testsuite/gas/arm/local_function.d
    gas/testsuite/gas/arm/local_function.s
    gas/testsuite/gas/arm/macro1.d
    gas/testsuite/gas/arm/macro1.s
    gas/testsuite/gas/arm/mapping.d
    gas/testsuite/gas/arm/mapping.s
    gas/testsuite/gas/arm/maverick.c
    gas/testsuite/gas/arm/maverick.d
    gas/testsuite/gas/arm/maverick.s
    gas/testsuite/gas/arm/neon-cond-bad-inc.s
    gas/testsuite/gas/arm/neon-cond-bad.d
    gas/testsuite/gas/arm/neon-cond-bad.l
    gas/testsuite/gas/arm/neon-cond-bad.s
    gas/testsuite/gas/arm/neon-cond-bad_t2.d
    gas/testsuite/gas/arm/neon-cond-bad_t2.s
    gas/testsuite/gas/arm/neon-cond.d
    gas/testsuite/gas/arm/neon-cond.s
    gas/testsuite/gas/arm/neon-const.d
    gas/testsuite/gas/arm/neon-const.s
    gas/testsuite/gas/arm/neon-cov.d
    gas/testsuite/gas/arm/neon-cov.s
    gas/testsuite/gas/arm/neon-ldst-es.d
    gas/testsuite/gas/arm/neon-ldst-es.s
    gas/testsuite/gas/arm/neon-ldst-rm.d
    gas/testsuite/gas/arm/neon-ldst-rm.s
    gas/testsuite/gas/arm/neon-omit.d
    gas/testsuite/gas/arm/neon-omit.s
    gas/testsuite/gas/arm/neon-psyn.d
    gas/testsuite/gas/arm/neon-psyn.s
    gas/testsuite/gas/arm/nomapping.d
    gas/testsuite/gas/arm/nomapping.s
    gas/testsuite/gas/arm/offset.d
    gas/testsuite/gas/arm/offset.s
    gas/testsuite/gas/arm/pic.d
    gas/testsuite/gas/arm/pic.s
    gas/testsuite/gas/arm/pic_vxworks.d
    gas/testsuite/gas/arm/r15-bad.d
    gas/testsuite/gas/arm/r15-bad.l
    gas/testsuite/gas/arm/r15-bad.s
    gas/testsuite/gas/arm/reg-alias.d
    gas/testsuite/gas/arm/reg-alias.s
    gas/testsuite/gas/arm/req.d
    gas/testsuite/gas/arm/req.l
    gas/testsuite/gas/arm/req.s
    gas/testsuite/gas/arm/svc.d
    gas/testsuite/gas/arm/svc.s
    gas/testsuite/gas/arm/t16-bad.d
    gas/testsuite/gas/arm/t16-bad.l
    gas/testsuite/gas/arm/t16-bad.s
    gas/testsuite/gas/arm/tcompat.d
    gas/testsuite/gas/arm/tcompat.s
    gas/testsuite/gas/arm/tcompat2.d
    gas/testsuite/gas/arm/tcompat2.s
    gas/testsuite/gas/arm/thumb.d
    gas/testsuite/gas/arm/thumb.s
    gas/testsuite/gas/arm/thumb2_add.d
    gas/testsuite/gas/arm/thumb2_add.s
    gas/testsuite/gas/arm/thumb2_bcond.d
    gas/testsuite/gas/arm/thumb2_bcond.s
    gas/testsuite/gas/arm/thumb2_invert.d
    gas/testsuite/gas/arm/thumb2_invert.s
    gas/testsuite/gas/arm/thumb2_it.d
    gas/testsuite/gas/arm/thumb2_it.s
    gas/testsuite/gas/arm/thumb2_it_bad.d
    gas/testsuite/gas/arm/thumb2_it_bad.l
    gas/testsuite/gas/arm/thumb2_it_bad.s
    gas/testsuite/gas/arm/thumb2_pool.d
    gas/testsuite/gas/arm/thumb2_pool.s
    gas/testsuite/gas/arm/thumb2_relax.d
    gas/testsuite/gas/arm/thumb2_relax.s
    gas/testsuite/gas/arm/thumb32.d
    gas/testsuite/gas/arm/thumb32.l
    gas/testsuite/gas/arm/thumb32.s
    gas/testsuite/gas/arm/thumbv6.d
    gas/testsuite/gas/arm/thumbv6.s
    gas/testsuite/gas/arm/thumbv6k.d
    gas/testsuite/gas/arm/thumbv6k.s
    gas/testsuite/gas/arm/tls.d
    gas/testsuite/gas/arm/tls.s
    gas/testsuite/gas/arm/tls_vxworks.d
    gas/testsuite/gas/arm/undefined.d
    gas/testsuite/gas/arm/undefined.l
    gas/testsuite/gas/arm/undefined.s
    gas/testsuite/gas/arm/undefined_coff.d
    gas/testsuite/gas/arm/undefined_coff.l
    gas/testsuite/gas/arm/undefined_coff.s
    gas/testsuite/gas/arm/unwind.d
    gas/testsuite/gas/arm/unwind.s
    gas/testsuite/gas/arm/unwind_vxworks.d
    gas/testsuite/gas/arm/vfp-bad.d
    gas/testsuite/gas/arm/vfp-bad.l
    gas/testsuite/gas/arm/vfp-bad.s
    gas/testsuite/gas/arm/vfp-bad_t2.d
    gas/testsuite/gas/arm/vfp-bad_t2.l
    gas/testsuite/gas/arm/vfp-bad_t2.s
    gas/testsuite/gas/arm/vfp-neon-overlap.d
    gas/testsuite/gas/arm/vfp-neon-overlap.s
    gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
    gas/testsuite/gas/arm/vfp-neon-syntax.d
    gas/testsuite/gas/arm/vfp-neon-syntax.s
    gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
    gas/testsuite/gas/arm/vfp-neon-syntax_t2.s
    gas/testsuite/gas/arm/vfp1.d
    gas/testsuite/gas/arm/vfp1.s
    gas/testsuite/gas/arm/vfp1_t2.d
    gas/testsuite/gas/arm/vfp1_t2.s
    gas/testsuite/gas/arm/vfp1xD.d
    gas/testsuite/gas/arm/vfp1xD.s
    gas/testsuite/gas/arm/vfp1xD_t2.d
    gas/testsuite/gas/arm/vfp1xD_t2.s
    gas/testsuite/gas/arm/vfp2.d
    gas/testsuite/gas/arm/vfp2.s
    gas/testsuite/gas/arm/vfp2_t2.d
    gas/testsuite/gas/arm/vfp2_t2.s
    gas/testsuite/gas/arm/vfpv3-32drs.d
    gas/testsuite/gas/arm/vfpv3-32drs.s
    gas/testsuite/gas/arm/vfpv3-const-conv.d
    gas/testsuite/gas/arm/vfpv3-const-conv.s
    gas/testsuite/gas/arm/wince_inst.d
    gas/testsuite/gas/arm/xscale.d
    gas/testsuite/gas/arm/xscale.s
    gas/testsuite/gas/bfin/arithmetic.d
    gas/testsuite/gas/bfin/arithmetic.s
    gas/testsuite/gas/bfin/bfin.exp
    gas/testsuite/gas/bfin/bit.d
    gas/testsuite/gas/bfin/bit.s
    gas/testsuite/gas/bfin/bit2.d
    gas/testsuite/gas/bfin/bit2.s
    gas/testsuite/gas/bfin/cache.d
    gas/testsuite/gas/bfin/cache.s
    gas/testsuite/gas/bfin/cache2.d
    gas/testsuite/gas/bfin/cache2.s
    gas/testsuite/gas/bfin/control_code.d
    gas/testsuite/gas/bfin/control_code.s
    gas/testsuite/gas/bfin/control_code2.d
    gas/testsuite/gas/bfin/control_code2.s
    gas/testsuite/gas/bfin/event.d
    gas/testsuite/gas/bfin/event.s
    gas/testsuite/gas/bfin/event2.d
    gas/testsuite/gas/bfin/event2.s
    gas/testsuite/gas/bfin/expected_errors.l
    gas/testsuite/gas/bfin/expected_errors.s
    gas/testsuite/gas/bfin/expected_move_errors.l
    gas/testsuite/gas/bfin/expected_move_errors.s
    gas/testsuite/gas/bfin/flow.d
    gas/testsuite/gas/bfin/flow.s
    gas/testsuite/gas/bfin/flow2.d
    gas/testsuite/gas/bfin/flow2.s
    gas/testsuite/gas/bfin/load.d
    gas/testsuite/gas/bfin/load.s
    gas/testsuite/gas/bfin/logical.d
    gas/testsuite/gas/bfin/logical.s
    gas/testsuite/gas/bfin/logical2.d
    gas/testsuite/gas/bfin/logical2.s
    gas/testsuite/gas/bfin/move.d
    gas/testsuite/gas/bfin/move.s
    gas/testsuite/gas/bfin/move2.d
    gas/testsuite/gas/bfin/move2.s
    gas/testsuite/gas/bfin/parallel.d
    gas/testsuite/gas/bfin/parallel.s
    gas/testsuite/gas/bfin/parallel2.d
    gas/testsuite/gas/bfin/parallel2.s
    gas/testsuite/gas/bfin/parallel3.d
    gas/testsuite/gas/bfin/parallel3.s
    gas/testsuite/gas/bfin/parallel4.d
    gas/testsuite/gas/bfin/parallel4.s
    gas/testsuite/gas/bfin/reloc.d
    gas/testsuite/gas/bfin/reloc.s
    gas/testsuite/gas/bfin/shift.d
    gas/testsuite/gas/bfin/shift.s
    gas/testsuite/gas/bfin/shift2.d
    gas/testsuite/gas/bfin/shift2.s
    gas/testsuite/gas/bfin/stack.d
    gas/testsuite/gas/bfin/stack.s
    gas/testsuite/gas/bfin/stack2.d
    gas/testsuite/gas/bfin/stack2.s
    gas/testsuite/gas/bfin/store.d
    gas/testsuite/gas/bfin/store.s
    gas/testsuite/gas/bfin/vector.d
    gas/testsuite/gas/bfin/vector.s
    gas/testsuite/gas/bfin/vector2.d
    gas/testsuite/gas/bfin/vector2.s
    gas/testsuite/gas/bfin/video.d
    gas/testsuite/gas/bfin/video.s
    gas/testsuite/gas/bfin/video2.d
    gas/testsuite/gas/bfin/video2.s
    gas/testsuite/gas/cfi/cfi-alpha-1.d
    gas/testsuite/gas/cfi/cfi-alpha-1.s
    gas/testsuite/gas/cfi/cfi-alpha-2.d
    gas/testsuite/gas/cfi/cfi-alpha-2.s
    gas/testsuite/gas/cfi/cfi-alpha-3.d
    gas/testsuite/gas/cfi/cfi-alpha-3.s
    gas/testsuite/gas/cfi/cfi-arm-1.d
    gas/testsuite/gas/cfi/cfi-arm-1.s
    gas/testsuite/gas/cfi/cfi-common-1.d
    gas/testsuite/gas/cfi/cfi-common-1.s
    gas/testsuite/gas/cfi/cfi-common-2.d
    gas/testsuite/gas/cfi/cfi-common-2.s
    gas/testsuite/gas/cfi/cfi-common-3.d
    gas/testsuite/gas/cfi/cfi-common-3.s
    gas/testsuite/gas/cfi/cfi-common-4.d
    gas/testsuite/gas/cfi/cfi-common-4.s
    gas/testsuite/gas/cfi/cfi-diag-1.l
    gas/testsuite/gas/cfi/cfi-diag-1.s
    gas/testsuite/gas/cfi/cfi-i386-2.d
    gas/testsuite/gas/cfi/cfi-i386-2.s
    gas/testsuite/gas/cfi/cfi-i386.d
    gas/testsuite/gas/cfi/cfi-i386.s
    gas/testsuite/gas/cfi/cfi-m68k.d
    gas/testsuite/gas/cfi/cfi-m68k.s
    gas/testsuite/gas/cfi/cfi-mips-1.d
    gas/testsuite/gas/cfi/cfi-mips-1.s
    gas/testsuite/gas/cfi/cfi-ppc-1.d
    gas/testsuite/gas/cfi/cfi-ppc-1.s
    gas/testsuite/gas/cfi/cfi-s390-1.d
    gas/testsuite/gas/cfi/cfi-s390-1.s
    gas/testsuite/gas/cfi/cfi-s390x-1.d
    gas/testsuite/gas/cfi/cfi-s390x-1.s
    gas/testsuite/gas/cfi/cfi-sh-1.d
    gas/testsuite/gas/cfi/cfi-sh-1.s
    gas/testsuite/gas/cfi/cfi-sparc-1.d
    gas/testsuite/gas/cfi/cfi-sparc-1.s
    gas/testsuite/gas/cfi/cfi-sparc64-1.d
    gas/testsuite/gas/cfi/cfi-sparc64-1.s
    gas/testsuite/gas/cfi/cfi-x86_64.d
    gas/testsuite/gas/cfi/cfi-x86_64.s
    gas/testsuite/gas/cfi/cfi.exp
    gas/testsuite/gas/cris/abs32-1.s
    gas/testsuite/gas/cris/addi.d
    gas/testsuite/gas/cris/addi.s
    gas/testsuite/gas/cris/arch-err-1.s
    gas/testsuite/gas/cris/arch-err-2.s
    gas/testsuite/gas/cris/arch-err-3.s
    gas/testsuite/gas/cris/arch-err-4.s
    gas/testsuite/gas/cris/arch-err-5.s
    gas/testsuite/gas/cris/binop-cmpmove.d
    gas/testsuite/gas/cris/binop-cmpmovx.d
    gas/testsuite/gas/cris/binop-extx.d
    gas/testsuite/gas/cris/binop-segref.s
    gas/testsuite/gas/cris/binop.d
    gas/testsuite/gas/cris/binop.s
    gas/testsuite/gas/cris/bork.d
    gas/testsuite/gas/cris/bork.s
    gas/testsuite/gas/cris/bound-err-1.s
    gas/testsuite/gas/cris/branch-warn-1.s
    gas/testsuite/gas/cris/branch-warn-2.s
    gas/testsuite/gas/cris/branch-warn-3.s
    gas/testsuite/gas/cris/branch.d
    gas/testsuite/gas/cris/branch.s
    gas/testsuite/gas/cris/break.d
    gas/testsuite/gas/cris/break.s
    gas/testsuite/gas/cris/brokw-1.d
    gas/testsuite/gas/cris/brokw-1.s
    gas/testsuite/gas/cris/brokw-2.d
    gas/testsuite/gas/cris/brokw-2.s
    gas/testsuite/gas/cris/brokw-3.d
    gas/testsuite/gas/cris/brokw-3.s
    gas/testsuite/gas/cris/brokw-3b.s
    gas/testsuite/gas/cris/bwtest-err-1.s
    gas/testsuite/gas/cris/ccr.d
    gas/testsuite/gas/cris/ccr.s
    gas/testsuite/gas/cris/clear.d
    gas/testsuite/gas/cris/continue.d
    gas/testsuite/gas/cris/continue.s
    gas/testsuite/gas/cris/cris.exp
    gas/testsuite/gas/cris/diffexp-ovwr.d
    gas/testsuite/gas/cris/diffexp-ovwr.s
    gas/testsuite/gas/cris/fragtest.d
    gas/testsuite/gas/cris/fragtest.s
    gas/testsuite/gas/cris/jump-type.d
    gas/testsuite/gas/cris/labfloat.d
    gas/testsuite/gas/cris/labfloat.s
    gas/testsuite/gas/cris/macroat.d
    gas/testsuite/gas/cris/macroat.s
    gas/testsuite/gas/cris/march-err-1.s
    gas/testsuite/gas/cris/march-err-2.s
    gas/testsuite/gas/cris/movem-to-reg.d
    gas/testsuite/gas/cris/mulbug-err-1.s
    gas/testsuite/gas/cris/nosep.d
    gas/testsuite/gas/cris/nosep.s
    gas/testsuite/gas/cris/oneop-type.d
    gas/testsuite/gas/cris/operand-err-1.s
    gas/testsuite/gas/cris/pic-err-1.s
    gas/testsuite/gas/cris/prefix.d
    gas/testsuite/gas/cris/prefix.s
    gas/testsuite/gas/cris/push-err-1.s
    gas/testsuite/gas/cris/push-err-2.s
    gas/testsuite/gas/cris/pushpop-byte-sreg.d
    gas/testsuite/gas/cris/pushpop-dcr1-sreg.d
    gas/testsuite/gas/cris/pushpop-dword-sreg.d
    gas/testsuite/gas/cris/pushpop-word-sreg.d
    gas/testsuite/gas/cris/pushpop.d
    gas/testsuite/gas/cris/pushpop.s
    gas/testsuite/gas/cris/pushpopv32.s
    gas/testsuite/gas/cris/quick-s6.d
    gas/testsuite/gas/cris/quick-u5.d
    gas/testsuite/gas/cris/quick-u6.d
    gas/testsuite/gas/cris/quick.s
    gas/testsuite/gas/cris/range-err-1.s
    gas/testsuite/gas/cris/range-err-2.s
    gas/testsuite/gas/cris/rd-abs32-1.d
    gas/testsuite/gas/cris/rd-abs32-2.d
    gas/testsuite/gas/cris/rd-arch-1.d
    gas/testsuite/gas/cris/rd-arch-2.d
    gas/testsuite/gas/cris/rd-arch-3.d
    gas/testsuite/gas/cris/rd-bcnst-pic.d
    gas/testsuite/gas/cris/rd-bcnst.d
    gas/testsuite/gas/cris/rd-bcnst.s
    gas/testsuite/gas/cris/rd-bkw1b.d
    gas/testsuite/gas/cris/rd-bkw2b.d
    gas/testsuite/gas/cris/rd-bkw3b.d
    gas/testsuite/gas/cris/rd-bound1.d
    gas/testsuite/gas/cris/rd-bound1.s
    gas/testsuite/gas/cris/rd-bound2.d
    gas/testsuite/gas/cris/rd-bound3.d
    gas/testsuite/gas/cris/rd-bound4.d
    gas/testsuite/gas/cris/rd-branch-pic.d
    gas/testsuite/gas/cris/rd-break32.d
    gas/testsuite/gas/cris/rd-brokw-pic-1.d
    gas/testsuite/gas/cris/rd-brokw-pic-2.d
    gas/testsuite/gas/cris/rd-brokw-pic-3.d
    gas/testsuite/gas/cris/rd-dw2-1.d
    gas/testsuite/gas/cris/rd-dw2-10.d
    gas/testsuite/gas/cris/rd-dw2-11.d
    gas/testsuite/gas/cris/rd-dw2-12.d
    gas/testsuite/gas/cris/rd-dw2-13.d
    gas/testsuite/gas/cris/rd-dw2-14.d
    gas/testsuite/gas/cris/rd-dw2-15.d
    gas/testsuite/gas/cris/rd-dw2-2.d
    gas/testsuite/gas/cris/rd-dw2-3.d
    gas/testsuite/gas/cris/rd-dw2-4.d
    gas/testsuite/gas/cris/rd-dw2-5.d
    gas/testsuite/gas/cris/rd-dw2-6.d
    gas/testsuite/gas/cris/rd-dw2-7.d
    gas/testsuite/gas/cris/rd-dw2-8.d
    gas/testsuite/gas/cris/rd-dw2-9.d
    gas/testsuite/gas/cris/rd-fragtest-pic.d
    gas/testsuite/gas/cris/rd-mulbug-1.d
    gas/testsuite/gas/cris/rd-pcplus.d
    gas/testsuite/gas/cris/rd-pcplus.s
    gas/testsuite/gas/cris/rd-pcrel1.d
    gas/testsuite/gas/cris/rd-pcrel1.s
    gas/testsuite/gas/cris/rd-pcrel2.d
    gas/testsuite/gas/cris/rd-pcrel2.s
    gas/testsuite/gas/cris/rd-pic-1.d
    gas/testsuite/gas/cris/rd-pic-1.s
    gas/testsuite/gas/cris/rd-pic-2.d
    gas/testsuite/gas/cris/rd-pic-2.s
    gas/testsuite/gas/cris/rd-ppv1032.d
    gas/testsuite/gas/cris/rd-ppv32.d
    gas/testsuite/gas/cris/rd-regprefix-1.d
    gas/testsuite/gas/cris/rd-regprefix-1.s
    gas/testsuite/gas/cris/rd-regprefix-1b.d
    gas/testsuite/gas/cris/rd-spr-1.d
    gas/testsuite/gas/cris/rd-spr-1.s
    gas/testsuite/gas/cris/rd-usp-1.d
    gas/testsuite/gas/cris/rd-usp-1b.d
    gas/testsuite/gas/cris/rd-v10_32o-1.d
    gas/testsuite/gas/cris/rd-v10_32o-2.d
    gas/testsuite/gas/cris/rd-v10_32o-2.s
    gas/testsuite/gas/cris/rd-v32-b1.d
    gas/testsuite/gas/cris/rd-v32-b1.s
    gas/testsuite/gas/cris/rd-v32-b2.d
    gas/testsuite/gas/cris/rd-v32-b2.s
    gas/testsuite/gas/cris/rd-v32-b3.d
    gas/testsuite/gas/cris/rd-v32-b3.s
    gas/testsuite/gas/cris/rd-v32-f1.d
    gas/testsuite/gas/cris/rd-v32-f1.s
    gas/testsuite/gas/cris/rd-v32-i1.d
    gas/testsuite/gas/cris/rd-v32-i1.s
    gas/testsuite/gas/cris/rd-v32-l1.d
    gas/testsuite/gas/cris/rd-v32-l1.s
    gas/testsuite/gas/cris/rd-v32-l3.d
    gas/testsuite/gas/cris/rd-v32-l3.s
    gas/testsuite/gas/cris/rd-v32-l4.d
    gas/testsuite/gas/cris/rd-v32-l4.s
    gas/testsuite/gas/cris/rd-v32o-1.d
    gas/testsuite/gas/cris/rd-v32s-1.d
    gas/testsuite/gas/cris/rd-v32s-2.d
    gas/testsuite/gas/cris/rd-v32s-2.s
    gas/testsuite/gas/cris/rd-v32s-3.d
    gas/testsuite/gas/cris/rd-v32s-3.s
    gas/testsuite/gas/cris/rd-v32s-4.d
    gas/testsuite/gas/cris/rd-v32s-4.s
    gas/testsuite/gas/cris/rd-vao-1.d
    gas/testsuite/gas/cris/reg-to-mem.d
    gas/testsuite/gas/cris/regprefix-err-1.s
    gas/testsuite/gas/cris/regreg.d
    gas/testsuite/gas/cris/regreg.s
    gas/testsuite/gas/cris/return.d
    gas/testsuite/gas/cris/return.s
    gas/testsuite/gas/cris/scc.d
    gas/testsuite/gas/cris/scc.s
    gas/testsuite/gas/cris/sep-err-1.s
    gas/testsuite/gas/cris/sep-err-2.s
    gas/testsuite/gas/cris/sep-err-3.s
    gas/testsuite/gas/cris/separator.d
    gas/testsuite/gas/cris/separator.s
    gas/testsuite/gas/cris/shexpr-1.d
    gas/testsuite/gas/cris/shexpr-1.s
    gas/testsuite/gas/cris/sreg-to-x.d
    gas/testsuite/gas/cris/string-1.d
    gas/testsuite/gas/cris/string-1.s
    gas/testsuite/gas/cris/string-2.d
    gas/testsuite/gas/cris/string-2.s
    gas/testsuite/gas/cris/test.d
    gas/testsuite/gas/cris/unimplemented.d
    gas/testsuite/gas/cris/unimplemented.s
    gas/testsuite/gas/cris/unop-mem.d
    gas/testsuite/gas/cris/unop.s
    gas/testsuite/gas/cris/us-err-1.s
    gas/testsuite/gas/cris/us-err-2.s
    gas/testsuite/gas/cris/us-err-3.s
    gas/testsuite/gas/cris/v32-err-1.s
    gas/testsuite/gas/cris/v32-err-10.s
    gas/testsuite/gas/cris/v32-err-11.s
    gas/testsuite/gas/cris/v32-err-2.s
    gas/testsuite/gas/cris/v32-err-3.s
    gas/testsuite/gas/cris/v32-err-4.s
    gas/testsuite/gas/cris/v32-err-5.s
    gas/testsuite/gas/cris/v32-err-6.s
    gas/testsuite/gas/cris/v32-err-7.s
    gas/testsuite/gas/cris/v32-err-8.s
    gas/testsuite/gas/cris/v32-err-9.s
    gas/testsuite/gas/cris/x-to-byte-sreg.d
    gas/testsuite/gas/cris/x-to-dcr1-sreg.d
    gas/testsuite/gas/cris/x-to-dword-sreg.d
    gas/testsuite/gas/cris/x-to-word-sreg.d
    gas/testsuite/gas/crx/allinsn.exp
    gas/testsuite/gas/crx/arith_insn.d
    gas/testsuite/gas/crx/arith_insn.s
    gas/testsuite/gas/crx/beq_insn.d
    gas/testsuite/gas/crx/beq_insn.s
    gas/testsuite/gas/crx/bit_insn.d
    gas/testsuite/gas/crx/bit_insn.s
    gas/testsuite/gas/crx/br_insn.d
    gas/testsuite/gas/crx/br_insn.s
    gas/testsuite/gas/crx/cmov_insn.d
    gas/testsuite/gas/crx/cmov_insn.s
    gas/testsuite/gas/crx/cmpbr_insn.d
    gas/testsuite/gas/crx/cmpbr_insn.s
    gas/testsuite/gas/crx/cop_insn.d
    gas/testsuite/gas/crx/cop_insn.s
    gas/testsuite/gas/crx/gas-segfault.d
    gas/testsuite/gas/crx/gas-segfault.s
    gas/testsuite/gas/crx/jscond_insn.d
    gas/testsuite/gas/crx/jscond_insn.s
    gas/testsuite/gas/crx/list_insn.d
    gas/testsuite/gas/crx/list_insn.s
    gas/testsuite/gas/crx/load_stor_insn.d
    gas/testsuite/gas/crx/load_stor_insn.s
    gas/testsuite/gas/crx/misc_insn.d
    gas/testsuite/gas/crx/misc_insn.s
    gas/testsuite/gas/crx/no_op_insn.d
    gas/testsuite/gas/crx/no_op_insn.s
    gas/testsuite/gas/crx/shift_insn.d
    gas/testsuite/gas/crx/shift_insn.s
    gas/testsuite/gas/d10v/address-001.d
    gas/testsuite/gas/d10v/address-001.s
    gas/testsuite/gas/d10v/address-002.l
    gas/testsuite/gas/d10v/address-002.s
    gas/testsuite/gas/d10v/address-003.l
    gas/testsuite/gas/d10v/address-003.s
    gas/testsuite/gas/d10v/address-004.l
    gas/testsuite/gas/d10v/address-004.s
    gas/testsuite/gas/d10v/address-005.l
    gas/testsuite/gas/d10v/address-005.s
    gas/testsuite/gas/d10v/address-006.l
    gas/testsuite/gas/d10v/address-006.s
    gas/testsuite/gas/d10v/address-007.l
    gas/testsuite/gas/d10v/address-007.s
    gas/testsuite/gas/d10v/address-008.l
    gas/testsuite/gas/d10v/address-008.s
    gas/testsuite/gas/d10v/address-009.l
    gas/testsuite/gas/d10v/address-009.s
    gas/testsuite/gas/d10v/address-010.l
    gas/testsuite/gas/d10v/address-010.s
    gas/testsuite/gas/d10v/address-011.l
    gas/testsuite/gas/d10v/address-011.s
    gas/testsuite/gas/d10v/address-012.l
    gas/testsuite/gas/d10v/address-012.s
    gas/testsuite/gas/d10v/address-013.l
    gas/testsuite/gas/d10v/address-013.s
    gas/testsuite/gas/d10v/address-014.l
    gas/testsuite/gas/d10v/address-014.s
    gas/testsuite/gas/d10v/address-015.l
    gas/testsuite/gas/d10v/address-015.s
    gas/testsuite/gas/d10v/address-016.l
    gas/testsuite/gas/d10v/address-016.s
    gas/testsuite/gas/d10v/address-017.l
    gas/testsuite/gas/d10v/address-017.s
    gas/testsuite/gas/d10v/address-018.l
    gas/testsuite/gas/d10v/address-018.s
    gas/testsuite/gas/d10v/address-019.l
    gas/testsuite/gas/d10v/address-019.s
    gas/testsuite/gas/d10v/address-020.l
    gas/testsuite/gas/d10v/address-020.s
    gas/testsuite/gas/d10v/address-021.l
    gas/testsuite/gas/d10v/address-021.s
    gas/testsuite/gas/d10v/address-022.l
    gas/testsuite/gas/d10v/address-022.s
    gas/testsuite/gas/d10v/address-023.l
    gas/testsuite/gas/d10v/address-023.s
    gas/testsuite/gas/d10v/address-024.l
    gas/testsuite/gas/d10v/address-024.s
    gas/testsuite/gas/d10v/address-025.l
    gas/testsuite/gas/d10v/address-025.s
    gas/testsuite/gas/d10v/address-026.l
    gas/testsuite/gas/d10v/address-026.s
    gas/testsuite/gas/d10v/address-027.l
    gas/testsuite/gas/d10v/address-027.s
    gas/testsuite/gas/d10v/address-028.l
    gas/testsuite/gas/d10v/address-028.s
    gas/testsuite/gas/d10v/address-029.l
    gas/testsuite/gas/d10v/address-029.s
    gas/testsuite/gas/d10v/address-030.l
    gas/testsuite/gas/d10v/address-030.s
    gas/testsuite/gas/d10v/address-031.l
    gas/testsuite/gas/d10v/address-031.s
    gas/testsuite/gas/d10v/address-032.l
    gas/testsuite/gas/d10v/address-032.s
    gas/testsuite/gas/d10v/address-033.l
    gas/testsuite/gas/d10v/address-033.s
    gas/testsuite/gas/d10v/address-034.l
    gas/testsuite/gas/d10v/address-034.s
    gas/testsuite/gas/d10v/address-035.l
    gas/testsuite/gas/d10v/address-035.s
    gas/testsuite/gas/d10v/address-036.l
    gas/testsuite/gas/d10v/address-036.s
    gas/testsuite/gas/d10v/address-037.l
    gas/testsuite/gas/d10v/address-037.s
    gas/testsuite/gas/d10v/address-038.l
    gas/testsuite/gas/d10v/address-038.s
    gas/testsuite/gas/d10v/address-039.l
    gas/testsuite/gas/d10v/address-039.s
    gas/testsuite/gas/d10v/address-040.l
    gas/testsuite/gas/d10v/address-040.s
    gas/testsuite/gas/d10v/address-041.l
    gas/testsuite/gas/d10v/address-041.s
    gas/testsuite/gas/d10v/control-001.d
    gas/testsuite/gas/d10v/control-001.s
    gas/testsuite/gas/d10v/d10v.exp
    gas/testsuite/gas/d10v/error-001.d
    gas/testsuite/gas/d10v/error-001.s
    gas/testsuite/gas/d10v/error-002.d
    gas/testsuite/gas/d10v/error-002.s
    gas/testsuite/gas/d10v/immediate-001.d
    gas/testsuite/gas/d10v/immediate-001.s
    gas/testsuite/gas/d10v/immediate-002.d
    gas/testsuite/gas/d10v/immediate-002.s
    gas/testsuite/gas/d10v/immediate-003.d
    gas/testsuite/gas/d10v/immediate-003.s
    gas/testsuite/gas/d10v/immediate-004.d
    gas/testsuite/gas/d10v/immediate-004.s
    gas/testsuite/gas/d10v/immediate-005.d
    gas/testsuite/gas/d10v/immediate-005.s
    gas/testsuite/gas/d10v/immediate-006.d
    gas/testsuite/gas/d10v/immediate-006.s
    gas/testsuite/gas/d10v/immediate-007.d
    gas/testsuite/gas/d10v/immediate-007.s
    gas/testsuite/gas/d10v/inst.d
    gas/testsuite/gas/d10v/inst.s
    gas/testsuite/gas/d10v/instruction_packing-001.d
    gas/testsuite/gas/d10v/instruction_packing-001.s
    gas/testsuite/gas/d10v/instruction_packing-002.d
    gas/testsuite/gas/d10v/instruction_packing-002.s
    gas/testsuite/gas/d10v/instruction_packing-003.d
    gas/testsuite/gas/d10v/instruction_packing-003.s
    gas/testsuite/gas/d10v/instruction_packing-004.d
    gas/testsuite/gas/d10v/instruction_packing-004.s
    gas/testsuite/gas/d10v/instruction_packing-005.d
    gas/testsuite/gas/d10v/instruction_packing-005.s
    gas/testsuite/gas/d10v/instruction_packing-006.d
    gas/testsuite/gas/d10v/instruction_packing-006.s
    gas/testsuite/gas/d10v/instruction_packing-007.d
    gas/testsuite/gas/d10v/instruction_packing-007.s
    gas/testsuite/gas/d10v/instruction_packing-008.d
    gas/testsuite/gas/d10v/instruction_packing-009.d
    gas/testsuite/gas/d10v/instruction_packing-010.d
    gas/testsuite/gas/d10v/instruction_packing.d
    gas/testsuite/gas/d10v/instruction_packing.s
    gas/testsuite/gas/d10v/label-001.d
    gas/testsuite/gas/d10v/label-001.s
    gas/testsuite/gas/d10v/warning-001.d
    gas/testsuite/gas/d10v/warning-001.s
    gas/testsuite/gas/d10v/warning-002.d
    gas/testsuite/gas/d10v/warning-002.s
    gas/testsuite/gas/d10v/warning-003.d
    gas/testsuite/gas/d10v/warning-003.s
    gas/testsuite/gas/d10v/warning-004.d
    gas/testsuite/gas/d10v/warning-004.s
    gas/testsuite/gas/d10v/warning-005.d
    gas/testsuite/gas/d10v/warning-005.s
    gas/testsuite/gas/d10v/warning-006.d
    gas/testsuite/gas/d10v/warning-006.s
    gas/testsuite/gas/d10v/warning-007.d
    gas/testsuite/gas/d10v/warning-007.s
    gas/testsuite/gas/d10v/warning-008.d
    gas/testsuite/gas/d10v/warning-008.s
    gas/testsuite/gas/d10v/warning-009.d
    gas/testsuite/gas/d10v/warning-009.s
    gas/testsuite/gas/d10v/warning-010.d
    gas/testsuite/gas/d10v/warning-010.s
    gas/testsuite/gas/d10v/warning-011.d
    gas/testsuite/gas/d10v/warning-011.s
    gas/testsuite/gas/d10v/warning-012.d
    gas/testsuite/gas/d10v/warning-012.s
    gas/testsuite/gas/d10v/warning-013.d
    gas/testsuite/gas/d10v/warning-013.s
    gas/testsuite/gas/d10v/warning-014.d
    gas/testsuite/gas/d10v/warning-014.s
    gas/testsuite/gas/d10v/warning-015.d
    gas/testsuite/gas/d10v/warning-016.d
    gas/testsuite/gas/d10v/warning-016.s
    gas/testsuite/gas/d10v/warning-017.d
    gas/testsuite/gas/d10v/warning-017.s
    gas/testsuite/gas/d10v/warning-018.d
    gas/testsuite/gas/d10v/warning-018.s
    gas/testsuite/gas/d10v/warning-019.d
    gas/testsuite/gas/d10v/warning-019.s
    gas/testsuite/gas/d30v/align.d
    gas/testsuite/gas/d30v/align.s
    gas/testsuite/gas/d30v/array.d
    gas/testsuite/gas/d30v/array.s
    gas/testsuite/gas/d30v/bittest.d
    gas/testsuite/gas/d30v/bittest.l
    gas/testsuite/gas/d30v/bittest.s
    gas/testsuite/gas/d30v/d30.exp
    gas/testsuite/gas/d30v/guard-debug.d
    gas/testsuite/gas/d30v/guard-debug.s
    gas/testsuite/gas/d30v/guard.d
    gas/testsuite/gas/d30v/guard.s
    gas/testsuite/gas/d30v/inst.d
    gas/testsuite/gas/d30v/inst.s
    gas/testsuite/gas/d30v/label-debug.d
    gas/testsuite/gas/d30v/label-debug.s
    gas/testsuite/gas/d30v/label.d
    gas/testsuite/gas/d30v/label.s
    gas/testsuite/gas/d30v/mul.d
    gas/testsuite/gas/d30v/mul.s
    gas/testsuite/gas/d30v/opt.d
    gas/testsuite/gas/d30v/opt.s
    gas/testsuite/gas/d30v/reloc.d
    gas/testsuite/gas/d30v/reloc.s
    gas/testsuite/gas/d30v/serial.l
    gas/testsuite/gas/d30v/serial.s
    gas/testsuite/gas/d30v/serial2.l
    gas/testsuite/gas/d30v/serial2.s
    gas/testsuite/gas/d30v/serial2O.l
    gas/testsuite/gas/d30v/serial2O.s
    gas/testsuite/gas/d30v/warn_oddreg.l
    gas/testsuite/gas/d30v/warn_oddreg.s
    gas/testsuite/gas/dlx/alltests.exp
    gas/testsuite/gas/dlx/branch.d
    gas/testsuite/gas/dlx/branch.s
    gas/testsuite/gas/dlx/itype.d
    gas/testsuite/gas/dlx/itype.s
    gas/testsuite/gas/dlx/lhi.d
    gas/testsuite/gas/dlx/lhi.s
    gas/testsuite/gas/dlx/load.d
    gas/testsuite/gas/dlx/load.s
    gas/testsuite/gas/dlx/lohi.d
    gas/testsuite/gas/dlx/lohi.s
    gas/testsuite/gas/dlx/rtype.d
    gas/testsuite/gas/dlx/rtype.s
    gas/testsuite/gas/dlx/store.d
    gas/testsuite/gas/dlx/store.s
    gas/testsuite/gas/elf/ehopt0.d
    gas/testsuite/gas/elf/ehopt0.s
    gas/testsuite/gas/elf/elf.exp
    gas/testsuite/gas/elf/group0.s
    gas/testsuite/gas/elf/group0a.d
    gas/testsuite/gas/elf/group0b.d
    gas/testsuite/gas/elf/group1.s
    gas/testsuite/gas/elf/group1a.d
    gas/testsuite/gas/elf/group1b.d
    gas/testsuite/gas/elf/redef.d
    gas/testsuite/gas/elf/redef.s
    gas/testsuite/gas/elf/section0.d
    gas/testsuite/gas/elf/section0.s
    gas/testsuite/gas/elf/section1.d
    gas/testsuite/gas/elf/section1.s
    gas/testsuite/gas/elf/section2.e
    gas/testsuite/gas/elf/section2.e-armeabi
    gas/testsuite/gas/elf/section2.e-m32r
    gas/testsuite/gas/elf/section2.e-mips
    gas/testsuite/gas/elf/section2.e-miwmmxt
    gas/testsuite/gas/elf/section2.l
    gas/testsuite/gas/elf/section2.s
    gas/testsuite/gas/elf/section3.d
    gas/testsuite/gas/elf/section3.s
    gas/testsuite/gas/elf/section4.d
    gas/testsuite/gas/elf/section4.s
    gas/testsuite/gas/elf/section5.e
    gas/testsuite/gas/elf/section5.l
    gas/testsuite/gas/elf/section5.s
    gas/testsuite/gas/elf/struct.d
    gas/testsuite/gas/elf/struct.s
    gas/testsuite/gas/elf/symver.d
    gas/testsuite/gas/elf/symver.s
    gas/testsuite/gas/elf/type.e
    gas/testsuite/gas/elf/type.s
    gas/testsuite/gas/fr30/allinsn.d
    gas/testsuite/gas/fr30/allinsn.exp
    gas/testsuite/gas/fr30/allinsn.s
    gas/testsuite/gas/fr30/fr30.exp
    gas/testsuite/gas/frv/allinsn.d
    gas/testsuite/gas/frv/allinsn.exp
    gas/testsuite/gas/frv/allinsn.s
    gas/testsuite/gas/frv/fdpic.d
    gas/testsuite/gas/frv/fdpic.s
    gas/testsuite/gas/frv/fr405-insn.d
    gas/testsuite/gas/frv/fr405-insn.l
    gas/testsuite/gas/frv/fr405-insn.s
    gas/testsuite/gas/frv/fr450-insn.d
    gas/testsuite/gas/frv/fr450-insn.l
    gas/testsuite/gas/frv/fr450-insn.s
    gas/testsuite/gas/frv/fr450-media-issue.l
    gas/testsuite/gas/frv/fr450-media-issue.s
    gas/testsuite/gas/frv/fr450-spr.d
    gas/testsuite/gas/frv/fr450-spr.s
    gas/testsuite/gas/frv/fr550-pack1.d
    gas/testsuite/gas/frv/fr550-pack1.s
    gas/testsuite/gas/frv/reloc1.d
    gas/testsuite/gas/frv/reloc1.s
    gas/testsuite/gas/h8300/addsub.s
    gas/testsuite/gas/h8300/addsubh.s
    gas/testsuite/gas/h8300/addsubrxcheck.s
    gas/testsuite/gas/h8300/addsubs.s
    gas/testsuite/gas/h8300/bitops1.s
    gas/testsuite/gas/h8300/bitops1h.s
    gas/testsuite/gas/h8300/bitops1s.s
    gas/testsuite/gas/h8300/bitops2.s
    gas/testsuite/gas/h8300/bitops2h.s
    gas/testsuite/gas/h8300/bitops2s.s
    gas/testsuite/gas/h8300/bitops3.s
    gas/testsuite/gas/h8300/bitops3h.s
    gas/testsuite/gas/h8300/bitops3s.s
    gas/testsuite/gas/h8300/bitops4.s
    gas/testsuite/gas/h8300/bitops4h.s
    gas/testsuite/gas/h8300/bitops4s.s
    gas/testsuite/gas/h8300/branch-coff.s
    gas/testsuite/gas/h8300/branch-elf.s
    gas/testsuite/gas/h8300/branchh-coff.s
    gas/testsuite/gas/h8300/branchh-elf.s
    gas/testsuite/gas/h8300/branchs-coff.s
    gas/testsuite/gas/h8300/branchs-elf.s
    gas/testsuite/gas/h8300/cbranch.s
    gas/testsuite/gas/h8300/cbranchh.s
    gas/testsuite/gas/h8300/cbranchs.s
    gas/testsuite/gas/h8300/cmpsi2.s
    gas/testsuite/gas/h8300/compare.s
    gas/testsuite/gas/h8300/compareh.s
    gas/testsuite/gas/h8300/compares.s
    gas/testsuite/gas/h8300/decimal.s
    gas/testsuite/gas/h8300/decimalh.s
    gas/testsuite/gas/h8300/decimals.s
    gas/testsuite/gas/h8300/divmul.s
    gas/testsuite/gas/h8300/divmulh.s
    gas/testsuite/gas/h8300/divmuls.s
    gas/testsuite/gas/h8300/extendh.s
    gas/testsuite/gas/h8300/extends.s
    gas/testsuite/gas/h8300/ffxx1-coff.d
    gas/testsuite/gas/h8300/ffxx1-coff.s
    gas/testsuite/gas/h8300/ffxx1-elf.d
    gas/testsuite/gas/h8300/ffxx1-elf.s
    gas/testsuite/gas/h8300/h8300-coff.exp
    gas/testsuite/gas/h8300/h8300-elf.exp
    gas/testsuite/gas/h8300/h8300.exp
    gas/testsuite/gas/h8300/h8sx_disp2.d
    gas/testsuite/gas/h8300/h8sx_disp2.s
    gas/testsuite/gas/h8300/h8sx_mov_imm.d
    gas/testsuite/gas/h8300/h8sx_mov_imm.s
    gas/testsuite/gas/h8300/h8sx_rtsl.d
    gas/testsuite/gas/h8300/h8sx_rtsl.s
    gas/testsuite/gas/h8300/incdec.s
    gas/testsuite/gas/h8300/incdech.s
    gas/testsuite/gas/h8300/incdecs.s
    gas/testsuite/gas/h8300/logical.s
    gas/testsuite/gas/h8300/logicalh.s
    gas/testsuite/gas/h8300/logicals.s
    gas/testsuite/gas/h8300/macs.s
    gas/testsuite/gas/h8300/misc.s
    gas/testsuite/gas/h8300/misch.s
    gas/testsuite/gas/h8300/miscs.s
    gas/testsuite/gas/h8300/mov32bug.s
    gas/testsuite/gas/h8300/movb.s
    gas/testsuite/gas/h8300/movbh.s
    gas/testsuite/gas/h8300/movbs.s
    gas/testsuite/gas/h8300/movlh.s
    gas/testsuite/gas/h8300/movls.s
    gas/testsuite/gas/h8300/movw.s
    gas/testsuite/gas/h8300/movwh.s
    gas/testsuite/gas/h8300/movws.s
    gas/testsuite/gas/h8300/multiples.s
    gas/testsuite/gas/h8300/pushpop.s
    gas/testsuite/gas/h8300/pushpoph.s
    gas/testsuite/gas/h8300/pushpops.s
    gas/testsuite/gas/h8300/rotsh.s
    gas/testsuite/gas/h8300/rotshh.s
    gas/testsuite/gas/h8300/rotshs.s
    gas/testsuite/gas/h8300/symaddgen.s
    gas/testsuite/gas/h8300/t01_mov.exp
    gas/testsuite/gas/h8300/t01_mov.s
    gas/testsuite/gas/h8300/t02_mova.exp
    gas/testsuite/gas/h8300/t02_mova.s
    gas/testsuite/gas/h8300/t03_add.exp
    gas/testsuite/gas/h8300/t03_add.s
    gas/testsuite/gas/h8300/t04_sub.exp
    gas/testsuite/gas/h8300/t04_sub.s
    gas/testsuite/gas/h8300/t05_cmp.exp
    gas/testsuite/gas/h8300/t05_cmp.s
    gas/testsuite/gas/h8300/t06_ari2.exp
    gas/testsuite/gas/h8300/t06_ari2.s
    gas/testsuite/gas/h8300/t07_ari3.exp
    gas/testsuite/gas/h8300/t07_ari3.s
    gas/testsuite/gas/h8300/t08_or.exp
    gas/testsuite/gas/h8300/t08_or.s
    gas/testsuite/gas/h8300/t09_xor.exp
    gas/testsuite/gas/h8300/t09_xor.s
    gas/testsuite/gas/h8300/t10_and.exp
    gas/testsuite/gas/h8300/t10_and.s
    gas/testsuite/gas/h8300/t11_logs.exp
    gas/testsuite/gas/h8300/t11_logs.s
    gas/testsuite/gas/h8300/t12_bit.exp
    gas/testsuite/gas/h8300/t12_bit.s
    gas/testsuite/gas/h8300/t13_otr.exp
    gas/testsuite/gas/h8300/t13_otr.s
    gas/testsuite/gas/hppa/README
    gas/testsuite/gas/hppa/basic/add.s
    gas/testsuite/gas/hppa/basic/add2.s
    gas/testsuite/gas/hppa/basic/addi.s
    gas/testsuite/gas/hppa/basic/basic.exp
    gas/testsuite/gas/hppa/basic/branch.s
    gas/testsuite/gas/hppa/basic/branch2.s
    gas/testsuite/gas/hppa/basic/comclr.s
    gas/testsuite/gas/hppa/basic/copr.s
    gas/testsuite/gas/hppa/basic/coprmem.s
    gas/testsuite/gas/hppa/basic/dcor.s
    gas/testsuite/gas/hppa/basic/dcor2.s
    gas/testsuite/gas/hppa/basic/deposit.s
    gas/testsuite/gas/hppa/basic/deposit2.s
    gas/testsuite/gas/hppa/basic/deposit3.s
    gas/testsuite/gas/hppa/basic/ds.s
    gas/testsuite/gas/hppa/basic/extract.s
    gas/testsuite/gas/hppa/basic/extract2.s
    gas/testsuite/gas/hppa/basic/extract3.s
    gas/testsuite/gas/hppa/basic/fmem.s
    gas/testsuite/gas/hppa/basic/fmemLRbug.s
    gas/testsuite/gas/hppa/basic/fp_comp.s
    gas/testsuite/gas/hppa/basic/fp_comp2.s
    gas/testsuite/gas/hppa/basic/fp_conv.s
    gas/testsuite/gas/hppa/basic/fp_fcmp.s
    gas/testsuite/gas/hppa/basic/fp_misc.s
    gas/testsuite/gas/hppa/basic/imem.s
    gas/testsuite/gas/hppa/basic/immed.s
    gas/testsuite/gas/hppa/basic/logical.s
    gas/testsuite/gas/hppa/basic/media.s
    gas/testsuite/gas/hppa/basic/perf.s
    gas/testsuite/gas/hppa/basic/purge.s
    gas/testsuite/gas/hppa/basic/purge2.s
    gas/testsuite/gas/hppa/basic/sh1add.s
    gas/testsuite/gas/hppa/basic/sh2add.s
    gas/testsuite/gas/hppa/basic/sh3add.s
    gas/testsuite/gas/hppa/basic/shift.s
    gas/testsuite/gas/hppa/basic/shift2.s
    gas/testsuite/gas/hppa/basic/shift3.s
    gas/testsuite/gas/hppa/basic/shladd.s
    gas/testsuite/gas/hppa/basic/shladd2.s
    gas/testsuite/gas/hppa/basic/special.s
    gas/testsuite/gas/hppa/basic/spop.s
    gas/testsuite/gas/hppa/basic/sub.s
    gas/testsuite/gas/hppa/basic/sub2.s
    gas/testsuite/gas/hppa/basic/subi.s
    gas/testsuite/gas/hppa/basic/system.s
    gas/testsuite/gas/hppa/basic/system2.s
    gas/testsuite/gas/hppa/basic/unit.s
    gas/testsuite/gas/hppa/basic/unit2.s
    gas/testsuite/gas/hppa/basic/weird.s
    gas/testsuite/gas/hppa/parse/align1.s
    gas/testsuite/gas/hppa/parse/align2.s
    gas/testsuite/gas/hppa/parse/appbug.s
    gas/testsuite/gas/hppa/parse/badfmpyadd.s
    gas/testsuite/gas/hppa/parse/block1.s
    gas/testsuite/gas/hppa/parse/block2.s
    gas/testsuite/gas/hppa/parse/calldatabug.s
    gas/testsuite/gas/hppa/parse/callinfobug.s
    gas/testsuite/gas/hppa/parse/defbug.s
    gas/testsuite/gas/hppa/parse/entrybug.s
    gas/testsuite/gas/hppa/parse/exportbug.s
    gas/testsuite/gas/hppa/parse/exprbug.s
    gas/testsuite/gas/hppa/parse/fixup7bug.s
    gas/testsuite/gas/hppa/parse/global.s
    gas/testsuite/gas/hppa/parse/labelbug.s
    gas/testsuite/gas/hppa/parse/linesepbug.s
    gas/testsuite/gas/hppa/parse/lselbug.s
    gas/testsuite/gas/hppa/parse/nosubspace.s
    gas/testsuite/gas/hppa/parse/parse.exp
    gas/testsuite/gas/hppa/parse/procbug.s
    gas/testsuite/gas/hppa/parse/regpopbug.s
    gas/testsuite/gas/hppa/parse/space.s
    gas/testsuite/gas/hppa/parse/spacebug.s
    gas/testsuite/gas/hppa/parse/ssbug.s
    gas/testsuite/gas/hppa/parse/stdreg.s
    gas/testsuite/gas/hppa/parse/stringer.s
    gas/testsuite/gas/hppa/parse/undefbug.s
    gas/testsuite/gas/hppa/parse/versionbug.s
    gas/testsuite/gas/hppa/parse/xmpyubug.s
    gas/testsuite/gas/hppa/reloc/applybug.s
    gas/testsuite/gas/hppa/reloc/blebug.s
    gas/testsuite/gas/hppa/reloc/blebug2.s
    gas/testsuite/gas/hppa/reloc/blebug3.s
    gas/testsuite/gas/hppa/reloc/exitbug.s
    gas/testsuite/gas/hppa/reloc/fixupbug.s
    gas/testsuite/gas/hppa/reloc/funcrelocbug.s
    gas/testsuite/gas/hppa/reloc/labelopbug.s
    gas/testsuite/gas/hppa/reloc/longcall.s
    gas/testsuite/gas/hppa/reloc/picreloc.s
    gas/testsuite/gas/hppa/reloc/plabelbug.s
    gas/testsuite/gas/hppa/reloc/r_no_reloc.s
    gas/testsuite/gas/hppa/reloc/reduce.s
    gas/testsuite/gas/hppa/reloc/reduce2.s
    gas/testsuite/gas/hppa/reloc/reduce3.s
    gas/testsuite/gas/hppa/reloc/reloc.exp
    gas/testsuite/gas/hppa/reloc/roundmode.s
    gas/testsuite/gas/hppa/reloc/selectorbug.s
    gas/testsuite/gas/hppa/unsorted/align3.s
    gas/testsuite/gas/hppa/unsorted/align4.s
    gas/testsuite/gas/hppa/unsorted/brlenbug.s
    gas/testsuite/gas/hppa/unsorted/common.s
    gas/testsuite/gas/hppa/unsorted/fragbug.s
    gas/testsuite/gas/hppa/unsorted/globalbug.s
    gas/testsuite/gas/hppa/unsorted/importbug.s
    gas/testsuite/gas/hppa/unsorted/labeldiffs.s
    gas/testsuite/gas/hppa/unsorted/locallabel.s
    gas/testsuite/gas/hppa/unsorted/ss_align.s
    gas/testsuite/gas/hppa/unsorted/unsorted.exp
    gas/testsuite/gas/i386/absrel.d
    gas/testsuite/gas/i386/absrel.s
    gas/testsuite/gas/i386/amd.d
    gas/testsuite/gas/i386/amd.s
    gas/testsuite/gas/i386/amdfam10.d
    gas/testsuite/gas/i386/amdfam10.s
    gas/testsuite/gas/i386/bss.d
    gas/testsuite/gas/i386/bss.s
    gas/testsuite/gas/i386/cr-err.l
    gas/testsuite/gas/i386/cr-err.s
    gas/testsuite/gas/i386/crx.d
    gas/testsuite/gas/i386/crx.s
    gas/testsuite/gas/i386/divide.d
    gas/testsuite/gas/i386/divide.s
    gas/testsuite/gas/i386/equ.d
    gas/testsuite/gas/i386/equ.e
    gas/testsuite/gas/i386/equ.s
    gas/testsuite/gas/i386/float.l
    gas/testsuite/gas/i386/float.s
    gas/testsuite/gas/i386/fp.d
    gas/testsuite/gas/i386/fp.s
    gas/testsuite/gas/i386/general.l
    gas/testsuite/gas/i386/general.s
    gas/testsuite/gas/i386/gotpc.d
    gas/testsuite/gas/i386/gotpc.s
    gas/testsuite/gas/i386/i386.exp
    gas/testsuite/gas/i386/immed32.d
    gas/testsuite/gas/i386/immed32.s
    gas/testsuite/gas/i386/immed64.d
    gas/testsuite/gas/i386/immed64.s
    gas/testsuite/gas/i386/intel.d
    gas/testsuite/gas/i386/intel.e
    gas/testsuite/gas/i386/intel.s
    gas/testsuite/gas/i386/intel16.d
    gas/testsuite/gas/i386/intel16.e
    gas/testsuite/gas/i386/intel16.s
    gas/testsuite/gas/i386/intelbad.l
    gas/testsuite/gas/i386/intelbad.s
    gas/testsuite/gas/i386/intelok.d
    gas/testsuite/gas/i386/intelok.e
    gas/testsuite/gas/i386/intelok.s
    gas/testsuite/gas/i386/intelpic.d
    gas/testsuite/gas/i386/intelpic.s
    gas/testsuite/gas/i386/inval-seg.l
    gas/testsuite/gas/i386/inval-seg.s
    gas/testsuite/gas/i386/inval.l
    gas/testsuite/gas/i386/inval.s
    gas/testsuite/gas/i386/jump.d
    gas/testsuite/gas/i386/jump.s
    gas/testsuite/gas/i386/jump16.d
    gas/testsuite/gas/i386/jump16.s
    gas/testsuite/gas/i386/katmai.d
    gas/testsuite/gas/i386/katmai.s
    gas/testsuite/gas/i386/merom.d
    gas/testsuite/gas/i386/merom.s
    gas/testsuite/gas/i386/mixed-mode-reloc.s
    gas/testsuite/gas/i386/mixed-mode-reloc32.d
    gas/testsuite/gas/i386/mixed-mode-reloc64.d
    gas/testsuite/gas/i386/modrm.l
    gas/testsuite/gas/i386/modrm.s
    gas/testsuite/gas/i386/naked.d
    gas/testsuite/gas/i386/naked.s
    gas/testsuite/gas/i386/nops-1-i386.d
    gas/testsuite/gas/i386/nops-1-i686.d
    gas/testsuite/gas/i386/nops-1-merom.d
    gas/testsuite/gas/i386/nops-1.d
    gas/testsuite/gas/i386/nops-1.s
    gas/testsuite/gas/i386/nops-2-i386.d
    gas/testsuite/gas/i386/nops-2-merom.d
    gas/testsuite/gas/i386/nops-2.d
    gas/testsuite/gas/i386/nops-2.s
    gas/testsuite/gas/i386/nops.d
    gas/testsuite/gas/i386/nops.s
    gas/testsuite/gas/i386/opcode.d
    gas/testsuite/gas/i386/opcode.s
    gas/testsuite/gas/i386/padlock.d
    gas/testsuite/gas/i386/padlock.s
    gas/testsuite/gas/i386/pcrel.d
    gas/testsuite/gas/i386/pcrel.s
    gas/testsuite/gas/i386/prefix.d
    gas/testsuite/gas/i386/prefix.s
    gas/testsuite/gas/i386/prescott.d
    gas/testsuite/gas/i386/prescott.s
    gas/testsuite/gas/i386/relax.d
    gas/testsuite/gas/i386/relax.s
    gas/testsuite/gas/i386/reloc.d
    gas/testsuite/gas/i386/reloc.s
    gas/testsuite/gas/i386/reloc32.d
    gas/testsuite/gas/i386/reloc32.l
    gas/testsuite/gas/i386/reloc32.s
    gas/testsuite/gas/i386/reloc64.d
    gas/testsuite/gas/i386/reloc64.l
    gas/testsuite/gas/i386/reloc64.s
    gas/testsuite/gas/i386/rep-suffix.d
    gas/testsuite/gas/i386/rep-suffix.s
    gas/testsuite/gas/i386/rep.d
    gas/testsuite/gas/i386/rep.s
    gas/testsuite/gas/i386/rex.d
    gas/testsuite/gas/i386/rex.s
    gas/testsuite/gas/i386/secrel.d
    gas/testsuite/gas/i386/secrel.s
    gas/testsuite/gas/i386/segment.l
    gas/testsuite/gas/i386/segment.s
    gas/testsuite/gas/i386/sib.d
    gas/testsuite/gas/i386/sib.s
    gas/testsuite/gas/i386/sse2.d
    gas/testsuite/gas/i386/sse2.s
    gas/testsuite/gas/i386/ssemmx2.d
    gas/testsuite/gas/i386/ssemmx2.s
    gas/testsuite/gas/i386/sub.d
    gas/testsuite/gas/i386/sub.s
    gas/testsuite/gas/i386/suffix.d
    gas/testsuite/gas/i386/suffix.s
    gas/testsuite/gas/i386/svme.d
    gas/testsuite/gas/i386/svme.s
    gas/testsuite/gas/i386/svme64.d
    gas/testsuite/gas/i386/tlsd.d
    gas/testsuite/gas/i386/tlsd.s
    gas/testsuite/gas/i386/tlsnopic.d
    gas/testsuite/gas/i386/tlsnopic.s
    gas/testsuite/gas/i386/tlspic.d
    gas/testsuite/gas/i386/tlspic.s
    gas/testsuite/gas/i386/vmx.d
    gas/testsuite/gas/i386/vmx.s
    gas/testsuite/gas/i386/white.l
    gas/testsuite/gas/i386/white.s
    gas/testsuite/gas/i386/x86-64-addr32.d
    gas/testsuite/gas/i386/x86-64-addr32.s
    gas/testsuite/gas/i386/x86-64-amdfam10.d
    gas/testsuite/gas/i386/x86-64-amdfam10.s
    gas/testsuite/gas/i386/x86-64-branch.d
    gas/testsuite/gas/i386/x86-64-branch.s
    gas/testsuite/gas/i386/x86-64-crx-suffix.d
    gas/testsuite/gas/i386/x86-64-crx.d
    gas/testsuite/gas/i386/x86-64-crx.s
    gas/testsuite/gas/i386/x86-64-drx-suffix.d
    gas/testsuite/gas/i386/x86-64-drx.d
    gas/testsuite/gas/i386/x86-64-drx.s
    gas/testsuite/gas/i386/x86-64-gidt.d
    gas/testsuite/gas/i386/x86-64-gidt.s
    gas/testsuite/gas/i386/x86-64-inval-seg.l
    gas/testsuite/gas/i386/x86-64-inval-seg.s
    gas/testsuite/gas/i386/x86-64-inval.l
    gas/testsuite/gas/i386/x86-64-inval.s
    gas/testsuite/gas/i386/x86-64-merom.d
    gas/testsuite/gas/i386/x86-64-merom.s
    gas/testsuite/gas/i386/x86-64-nops-1-k8.d
    gas/testsuite/gas/i386/x86-64-nops-1-merom.d
    gas/testsuite/gas/i386/x86-64-nops-1-nocona.d
    gas/testsuite/gas/i386/x86-64-nops-1.d
    gas/testsuite/gas/i386/x86-64-nops-1.s
    gas/testsuite/gas/i386/x86-64-nops.d
    gas/testsuite/gas/i386/x86-64-nops.s
    gas/testsuite/gas/i386/x86-64-opcode.d
    gas/testsuite/gas/i386/x86-64-opcode.s
    gas/testsuite/gas/i386/x86-64-pcrel.d
    gas/testsuite/gas/i386/x86-64-pcrel.s
    gas/testsuite/gas/i386/x86-64-prescott.d
    gas/testsuite/gas/i386/x86-64-prescott.s
    gas/testsuite/gas/i386/x86-64-rep-suffix.d
    gas/testsuite/gas/i386/x86-64-rep-suffix.s
    gas/testsuite/gas/i386/x86-64-rep.d
    gas/testsuite/gas/i386/x86-64-rep.s
    gas/testsuite/gas/i386/x86-64-rip.d
    gas/testsuite/gas/i386/x86-64-rip.s
    gas/testsuite/gas/i386/x86-64-segment.l
    gas/testsuite/gas/i386/x86-64-segment.s
    gas/testsuite/gas/i386/x86-64-stack-intel.d
    gas/testsuite/gas/i386/x86-64-stack-suffix.d
    gas/testsuite/gas/i386/x86-64-stack.d
    gas/testsuite/gas/i386/x86-64-stack.s
    gas/testsuite/gas/i386/x86-64-unwind.d
    gas/testsuite/gas/i386/x86-64-unwind.s
    gas/testsuite/gas/i386/x86-64-vmx.d
    gas/testsuite/gas/i386/x86-64-vmx.s
    gas/testsuite/gas/i386/x86_64.d
    gas/testsuite/gas/i386/x86_64.e
    gas/testsuite/gas/i386/x86_64.s
    gas/testsuite/gas/i860/README.i860
    gas/testsuite/gas/i860/bitwise.d
    gas/testsuite/gas/i860/bitwise.s
    gas/testsuite/gas/i860/branch.d
    gas/testsuite/gas/i860/branch.s
    gas/testsuite/gas/i860/bte.d
    gas/testsuite/gas/i860/bte.s
    gas/testsuite/gas/i860/dir-align01.d
    gas/testsuite/gas/i860/dir-align01.s
    gas/testsuite/gas/i860/dir-intel01.d
    gas/testsuite/gas/i860/dir-intel01.s
    gas/testsuite/gas/i860/dir-intel02.d
    gas/testsuite/gas/i860/dir-intel02.s
    gas/testsuite/gas/i860/dir-intel03-err.l
    gas/testsuite/gas/i860/dir-intel03-err.s
    gas/testsuite/gas/i860/dual01.d
    gas/testsuite/gas/i860/dual01.s
    gas/testsuite/gas/i860/dual02-err.l
    gas/testsuite/gas/i860/dual02-err.s
    gas/testsuite/gas/i860/dual03.d
    gas/testsuite/gas/i860/dual03.s
    gas/testsuite/gas/i860/fldst01.d
    gas/testsuite/gas/i860/fldst01.s
    gas/testsuite/gas/i860/fldst02.d
    gas/testsuite/gas/i860/fldst02.s
    gas/testsuite/gas/i860/fldst03.d
    gas/testsuite/gas/i860/fldst03.s
    gas/testsuite/gas/i860/fldst04.d
    gas/testsuite/gas/i860/fldst04.s
    gas/testsuite/gas/i860/fldst05.d
    gas/testsuite/gas/i860/fldst05.s
    gas/testsuite/gas/i860/fldst06.d
    gas/testsuite/gas/i860/fldst06.s
    gas/testsuite/gas/i860/fldst07.d
    gas/testsuite/gas/i860/fldst07.s
    gas/testsuite/gas/i860/fldst08.d
    gas/testsuite/gas/i860/fldst08.s
    gas/testsuite/gas/i860/float01.d
    gas/testsuite/gas/i860/float01.s
    gas/testsuite/gas/i860/float02.d
    gas/testsuite/gas/i860/float02.s
    gas/testsuite/gas/i860/float03.d
    gas/testsuite/gas/i860/float03.s
    gas/testsuite/gas/i860/float04.d
    gas/testsuite/gas/i860/float04.s
    gas/testsuite/gas/i860/form.d
    gas/testsuite/gas/i860/form.s
    gas/testsuite/gas/i860/i860.exp
    gas/testsuite/gas/i860/iarith.d
    gas/testsuite/gas/i860/iarith.s
    gas/testsuite/gas/i860/ldst01.d
    gas/testsuite/gas/i860/ldst01.s
    gas/testsuite/gas/i860/ldst02.d
    gas/testsuite/gas/i860/ldst02.s
    gas/testsuite/gas/i860/ldst03.d
    gas/testsuite/gas/i860/ldst03.s
    gas/testsuite/gas/i860/ldst04.d
    gas/testsuite/gas/i860/ldst04.s
    gas/testsuite/gas/i860/ldst05.d
    gas/testsuite/gas/i860/ldst05.s
    gas/testsuite/gas/i860/ldst06.d
    gas/testsuite/gas/i860/ldst06.s
    gas/testsuite/gas/i860/pfam.d
    gas/testsuite/gas/i860/pfam.s
    gas/testsuite/gas/i860/pfmam.d
    gas/testsuite/gas/i860/pfmam.s
    gas/testsuite/gas/i860/pfmsm.d
    gas/testsuite/gas/i860/pfmsm.s
    gas/testsuite/gas/i860/pfsm.d
    gas/testsuite/gas/i860/pfsm.s
    gas/testsuite/gas/i860/pseudo-ops01.d
    gas/testsuite/gas/i860/pseudo-ops01.s
    gas/testsuite/gas/i860/regress01.d
    gas/testsuite/gas/i860/regress01.s
    gas/testsuite/gas/i860/shift.d
    gas/testsuite/gas/i860/shift.s
    gas/testsuite/gas/i860/simd.d
    gas/testsuite/gas/i860/simd.s
    gas/testsuite/gas/i860/system.d
    gas/testsuite/gas/i860/system.s
    gas/testsuite/gas/i860/xp.d
    gas/testsuite/gas/i860/xp.s
    gas/testsuite/gas/ia64/alias-ilp32.d
    gas/testsuite/gas/ia64/alias.d
    gas/testsuite/gas/ia64/alias.s
    gas/testsuite/gas/ia64/align.d
    gas/testsuite/gas/ia64/align.s
    gas/testsuite/gas/ia64/alloc.l
    gas/testsuite/gas/ia64/alloc.s
    gas/testsuite/gas/ia64/bundling.d
    gas/testsuite/gas/ia64/bundling.s
    gas/testsuite/gas/ia64/dependency-1.d
    gas/testsuite/gas/ia64/dependency-1.s
    gas/testsuite/gas/ia64/dv-branch.d
    gas/testsuite/gas/ia64/dv-branch.s
    gas/testsuite/gas/ia64/dv-entry-err.l
    gas/testsuite/gas/ia64/dv-entry-err.s
    gas/testsuite/gas/ia64/dv-imply.d
    gas/testsuite/gas/ia64/dv-imply.s
    gas/testsuite/gas/ia64/dv-mutex-err.l
    gas/testsuite/gas/ia64/dv-mutex-err.s
    gas/testsuite/gas/ia64/dv-mutex.d
    gas/testsuite/gas/ia64/dv-mutex.s
    gas/testsuite/gas/ia64/dv-raw-err.l
    gas/testsuite/gas/ia64/dv-raw-err.s
    gas/testsuite/gas/ia64/dv-safe.d
    gas/testsuite/gas/ia64/dv-safe.s
    gas/testsuite/gas/ia64/dv-srlz.d
    gas/testsuite/gas/ia64/dv-srlz.s
    gas/testsuite/gas/ia64/dv-war-err.l
    gas/testsuite/gas/ia64/dv-war-err.s
    gas/testsuite/gas/ia64/dv-waw-err.l
    gas/testsuite/gas/ia64/dv-waw-err.s
    gas/testsuite/gas/ia64/fixup-dump.pl
    gas/testsuite/gas/ia64/forward.d
    gas/testsuite/gas/ia64/forward.s
    gas/testsuite/gas/ia64/global.d
    gas/testsuite/gas/ia64/global.s
    gas/testsuite/gas/ia64/group-1.d
    gas/testsuite/gas/ia64/group-1.s
    gas/testsuite/gas/ia64/group-2.d
    gas/testsuite/gas/ia64/group-2.s
    gas/testsuite/gas/ia64/hint.b-err.l
    gas/testsuite/gas/ia64/hint.b-err.s
    gas/testsuite/gas/ia64/hint.b-warn.l
    gas/testsuite/gas/ia64/hint.b-warn.s
    gas/testsuite/gas/ia64/ia64.exp
    gas/testsuite/gas/ia64/index.l
    gas/testsuite/gas/ia64/index.s
    gas/testsuite/gas/ia64/invalid-ar.l
    gas/testsuite/gas/ia64/invalid-ar.s
    gas/testsuite/gas/ia64/label.l
    gas/testsuite/gas/ia64/label.s
    gas/testsuite/gas/ia64/last.l
    gas/testsuite/gas/ia64/last.s
    gas/testsuite/gas/ia64/ldxmov-1.d
    gas/testsuite/gas/ia64/ldxmov-1.s
    gas/testsuite/gas/ia64/ldxmov-2.l
    gas/testsuite/gas/ia64/ldxmov-2.s
    gas/testsuite/gas/ia64/ltoff22x-1.d
    gas/testsuite/gas/ia64/ltoff22x-1.s
    gas/testsuite/gas/ia64/ltoff22x-2.d
    gas/testsuite/gas/ia64/ltoff22x-2.s
    gas/testsuite/gas/ia64/ltoff22x-3.d
    gas/testsuite/gas/ia64/ltoff22x-3.s
    gas/testsuite/gas/ia64/ltoff22x-4.d
    gas/testsuite/gas/ia64/ltoff22x-4.s
    gas/testsuite/gas/ia64/ltoff22x-5.d
    gas/testsuite/gas/ia64/ltoff22x-5.s
    gas/testsuite/gas/ia64/mov-ar.d
    gas/testsuite/gas/ia64/mov-ar.s
    gas/testsuite/gas/ia64/no-fit.l
    gas/testsuite/gas/ia64/no-fit.s
    gas/testsuite/gas/ia64/nop_x.d
    gas/testsuite/gas/ia64/nop_x.s
    gas/testsuite/gas/ia64/nostkreg.d
    gas/testsuite/gas/ia64/nostkreg.s
    gas/testsuite/gas/ia64/opc-a-err.l
    gas/testsuite/gas/ia64/opc-a-err.s
    gas/testsuite/gas/ia64/opc-a.d
    gas/testsuite/gas/ia64/opc-a.pl
    gas/testsuite/gas/ia64/opc-a.s
    gas/testsuite/gas/ia64/opc-b.d
    gas/testsuite/gas/ia64/opc-b.pl
    gas/testsuite/gas/ia64/opc-b.s
    gas/testsuite/gas/ia64/opc-f.d
    gas/testsuite/gas/ia64/opc-f.pl
    gas/testsuite/gas/ia64/opc-f.s
    gas/testsuite/gas/ia64/opc-i.d
    gas/testsuite/gas/ia64/opc-i.pl
    gas/testsuite/gas/ia64/opc-i.s
    gas/testsuite/gas/ia64/opc-m.d
    gas/testsuite/gas/ia64/opc-m.pl
    gas/testsuite/gas/ia64/opc-m.s
    gas/testsuite/gas/ia64/opc-x.d
    gas/testsuite/gas/ia64/opc-x.s
    gas/testsuite/gas/ia64/operand-or.d
    gas/testsuite/gas/ia64/operand-or.s
    gas/testsuite/gas/ia64/operands.l
    gas/testsuite/gas/ia64/operands.s
    gas/testsuite/gas/ia64/order.d
    gas/testsuite/gas/ia64/order.s
    gas/testsuite/gas/ia64/pcrel.d
    gas/testsuite/gas/ia64/pcrel.s
    gas/testsuite/gas/ia64/pound.l
    gas/testsuite/gas/ia64/pound.s
    gas/testsuite/gas/ia64/pred-rel.s
    gas/testsuite/gas/ia64/proc.l
    gas/testsuite/gas/ia64/proc.s
    gas/testsuite/gas/ia64/pseudo.d
    gas/testsuite/gas/ia64/pseudo.s
    gas/testsuite/gas/ia64/radix.l
    gas/testsuite/gas/ia64/radix.s
    gas/testsuite/gas/ia64/real.d
    gas/testsuite/gas/ia64/real.s
    gas/testsuite/gas/ia64/reg-err.l
    gas/testsuite/gas/ia64/reg-err.s
    gas/testsuite/gas/ia64/regs.d
    gas/testsuite/gas/ia64/regs.pl
    gas/testsuite/gas/ia64/regs.s
    gas/testsuite/gas/ia64/regval.l
    gas/testsuite/gas/ia64/regval.s
    gas/testsuite/gas/ia64/reloc-bad.l
    gas/testsuite/gas/ia64/reloc-bad.s
    gas/testsuite/gas/ia64/reloc-uw-ilp32.d
    gas/testsuite/gas/ia64/reloc-uw.d
    gas/testsuite/gas/ia64/reloc-uw.s
    gas/testsuite/gas/ia64/reloc.d
    gas/testsuite/gas/ia64/reloc.s
    gas/testsuite/gas/ia64/rotX.l
    gas/testsuite/gas/ia64/rotX.s
    gas/testsuite/gas/ia64/secname-ilp32.d
    gas/testsuite/gas/ia64/secname.d
    gas/testsuite/gas/ia64/secname.s
    gas/testsuite/gas/ia64/slot2.l
    gas/testsuite/gas/ia64/slot2.s
    gas/testsuite/gas/ia64/strange.d
    gas/testsuite/gas/ia64/strange.s
    gas/testsuite/gas/ia64/tls.d
    gas/testsuite/gas/ia64/tls.s
    gas/testsuite/gas/ia64/unwind-bad.l
    gas/testsuite/gas/ia64/unwind-bad.s
    gas/testsuite/gas/ia64/unwind-err.l
    gas/testsuite/gas/ia64/unwind-err.s
    gas/testsuite/gas/ia64/unwind-ilp32.d
    gas/testsuite/gas/ia64/unwind-ok.d
    gas/testsuite/gas/ia64/unwind-ok.s
    gas/testsuite/gas/ia64/unwind.d
    gas/testsuite/gas/ia64/unwind.s
    gas/testsuite/gas/ia64/xdata-ilp32.d
    gas/testsuite/gas/ia64/xdata.d
    gas/testsuite/gas/ia64/xdata.s
    gas/testsuite/gas/ieee-fp/x930509a.exp
    gas/testsuite/gas/ieee-fp/x930509a.s
    gas/testsuite/gas/iq2000/allinsn.d
    gas/testsuite/gas/iq2000/allinsn.exp
    gas/testsuite/gas/iq2000/allinsn.s
    gas/testsuite/gas/iq2000/hazard0.s
    gas/testsuite/gas/iq2000/hazard1.s
    gas/testsuite/gas/iq2000/hazard2.s
    gas/testsuite/gas/iq2000/hazard3.s
    gas/testsuite/gas/iq2000/hazard4.s
    gas/testsuite/gas/iq2000/hazard5.s
    gas/testsuite/gas/iq2000/load-hazards.exp
    gas/testsuite/gas/iq2000/nohazard.s
    gas/testsuite/gas/iq2000/noyield.s
    gas/testsuite/gas/iq2000/odd-ldw.exp
    gas/testsuite/gas/iq2000/odd-sdw.exp
    gas/testsuite/gas/iq2000/oddldw.s
    gas/testsuite/gas/iq2000/oddsdw.s
    gas/testsuite/gas/iq2000/yield.exp
    gas/testsuite/gas/iq2000/yield0.s
    gas/testsuite/gas/iq2000/yield1.s
    gas/testsuite/gas/iq2000/yield2.s
    gas/testsuite/gas/lns/lns-common-1.d
    gas/testsuite/gas/lns/lns-common-1.s
    gas/testsuite/gas/lns/lns-diag-1.l
    gas/testsuite/gas/lns/lns-diag-1.s
    gas/testsuite/gas/lns/lns.exp
    gas/testsuite/gas/m32r/allinsn.d
    gas/testsuite/gas/m32r/allinsn.exp
    gas/testsuite/gas/m32r/allinsn.s
    gas/testsuite/gas/m32r/error.exp
    gas/testsuite/gas/m32r/fslot.d
    gas/testsuite/gas/m32r/fslot.s
    gas/testsuite/gas/m32r/fslotx.d
    gas/testsuite/gas/m32r/fslotx.s
    gas/testsuite/gas/m32r/high-1.d
    gas/testsuite/gas/m32r/high-1.s
    gas/testsuite/gas/m32r/interfere.s
    gas/testsuite/gas/m32r/m32r.exp
    gas/testsuite/gas/m32r/m32r2.d
    gas/testsuite/gas/m32r/m32r2.exp
    gas/testsuite/gas/m32r/m32r2.s
    gas/testsuite/gas/m32r/m32rx.d
    gas/testsuite/gas/m32r/m32rx.exp
    gas/testsuite/gas/m32r/m32rx.s
    gas/testsuite/gas/m32r/outofrange.s
    gas/testsuite/gas/m32r/parallel-2.d
    gas/testsuite/gas/m32r/parallel-2.s
    gas/testsuite/gas/m32r/parallel.s
    gas/testsuite/gas/m32r/pic.d
    gas/testsuite/gas/m32r/pic.exp
    gas/testsuite/gas/m32r/pic.s
    gas/testsuite/gas/m32r/pic2.d
    gas/testsuite/gas/m32r/pic2.s
    gas/testsuite/gas/m32r/rel32-err.s
    gas/testsuite/gas/m32r/rel32-pic.d
    gas/testsuite/gas/m32r/rel32-pic.s
    gas/testsuite/gas/m32r/rel32.d
    gas/testsuite/gas/m32r/rel32.exp
    gas/testsuite/gas/m32r/rel32.s
    gas/testsuite/gas/m32r/rela-1.d
    gas/testsuite/gas/m32r/rela-1.s
    gas/testsuite/gas/m32r/relax-1.d
    gas/testsuite/gas/m32r/relax-1.s
    gas/testsuite/gas/m32r/relax-2.d
    gas/testsuite/gas/m32r/relax-2.s
    gas/testsuite/gas/m32r/seth.d
    gas/testsuite/gas/m32r/seth.s
    gas/testsuite/gas/m32r/signed-relocs.d
    gas/testsuite/gas/m32r/signed-relocs.s
    gas/testsuite/gas/m32r/uppercase.d
    gas/testsuite/gas/m32r/uppercase.s
    gas/testsuite/gas/m32r/wrongsize.s
    gas/testsuite/gas/m68hc11/abi-m68hc11-16-32.d
    gas/testsuite/gas/m68hc11/abi-m68hc11-16-64.d
    gas/testsuite/gas/m68hc11/abi-m68hc11-32-32.d
    gas/testsuite/gas/m68hc11/abi-m68hc11-32-64.d
    gas/testsuite/gas/m68hc11/abi.s
    gas/testsuite/gas/m68hc11/all_insns.d
    gas/testsuite/gas/m68hc11/all_insns.s
    gas/testsuite/gas/m68hc11/branchs12.d
    gas/testsuite/gas/m68hc11/branchs12.s
    gas/testsuite/gas/m68hc11/bug-1825.d
    gas/testsuite/gas/m68hc11/bug-1825.s
    gas/testsuite/gas/m68hc11/indexed12.d
    gas/testsuite/gas/m68hc11/indexed12.s
    gas/testsuite/gas/m68hc11/insns-dwarf2.d
    gas/testsuite/gas/m68hc11/insns.d
    gas/testsuite/gas/m68hc11/insns.s
    gas/testsuite/gas/m68hc11/insns12.d
    gas/testsuite/gas/m68hc11/insns12.s
    gas/testsuite/gas/m68hc11/lbranch-dwarf2.d
    gas/testsuite/gas/m68hc11/lbranch.d
    gas/testsuite/gas/m68hc11/lbranch.s
    gas/testsuite/gas/m68hc11/m68hc11.exp
    gas/testsuite/gas/m68hc11/malis-include.s
    gas/testsuite/gas/m68hc11/malis.d
    gas/testsuite/gas/m68hc11/malis.s
    gas/testsuite/gas/m68hc11/movb.d
    gas/testsuite/gas/m68hc11/movb.s
    gas/testsuite/gas/m68hc11/opers12-dwarf2.d
    gas/testsuite/gas/m68hc11/opers12.d
    gas/testsuite/gas/m68hc11/opers12.s
    gas/testsuite/gas/m68k-coff/gas.exp
    gas/testsuite/gas/m68k-coff/p2389.s
    gas/testsuite/gas/m68k-coff/p2389a.s
    gas/testsuite/gas/m68k-coff/p2430.s
    gas/testsuite/gas/m68k-coff/p2430a.s
    gas/testsuite/gas/m68k-coff/t1.s
    gas/testsuite/gas/m68k/all.exp
    gas/testsuite/gas/m68k/arch-cpu-1.d
    gas/testsuite/gas/m68k/arch-cpu-1.s
    gas/testsuite/gas/m68k/bitfield.d
    gas/testsuite/gas/m68k/bitfield.s
    gas/testsuite/gas/m68k/cas.d
    gas/testsuite/gas/m68k/cas.s
    gas/testsuite/gas/m68k/disperr.s
    gas/testsuite/gas/m68k/fmoveml.d
    gas/testsuite/gas/m68k/fmoveml.s
    gas/testsuite/gas/m68k/link.d
    gas/testsuite/gas/m68k/link.s
    gas/testsuite/gas/m68k/mcf-emac.d
    gas/testsuite/gas/m68k/mcf-emac.s
    gas/testsuite/gas/m68k/mcf-fpu.d
    gas/testsuite/gas/m68k/mcf-fpu.s
    gas/testsuite/gas/m68k/mcf-mac.d
    gas/testsuite/gas/m68k/mcf-mac.s
    gas/testsuite/gas/m68k/mcf-mov3q.d
    gas/testsuite/gas/m68k/mcf-mov3q.s
    gas/testsuite/gas/m68k/mode5.d
    gas/testsuite/gas/m68k/mode5.s
    gas/testsuite/gas/m68k/op68000.d
    gas/testsuite/gas/m68k/operands.d
    gas/testsuite/gas/m68k/operands.s
    gas/testsuite/gas/m68k/p2410.s
    gas/testsuite/gas/m68k/p2663.s
    gas/testsuite/gas/m68k/pcrel.d
    gas/testsuite/gas/m68k/pcrel.s
    gas/testsuite/gas/m68k/pic1.s
    gas/testsuite/gas/m68k/t2.d
    gas/testsuite/gas/m68k/t2.s
    gas/testsuite/gas/macros/and.s
    gas/testsuite/gas/macros/app1.d
    gas/testsuite/gas/macros/app1.s
    gas/testsuite/gas/macros/app2.d
    gas/testsuite/gas/macros/app2.s
    gas/testsuite/gas/macros/app3.d
    gas/testsuite/gas/macros/app3.s
    gas/testsuite/gas/macros/app4.d
    gas/testsuite/gas/macros/app4.s
    gas/testsuite/gas/macros/app4b.s
    gas/testsuite/gas/macros/badarg.l
    gas/testsuite/gas/macros/badarg.s
    gas/testsuite/gas/macros/dot.l
    gas/testsuite/gas/macros/dot.s
    gas/testsuite/gas/macros/end.l
    gas/testsuite/gas/macros/end.s
    gas/testsuite/gas/macros/err.s
    gas/testsuite/gas/macros/irp.d
    gas/testsuite/gas/macros/irp.s
    gas/testsuite/gas/macros/macros.exp
    gas/testsuite/gas/macros/paren.d
    gas/testsuite/gas/macros/paren.s
    gas/testsuite/gas/macros/purge.l
    gas/testsuite/gas/macros/purge.s
    gas/testsuite/gas/macros/redef.l
    gas/testsuite/gas/macros/redef.s
    gas/testsuite/gas/macros/repeat.d
    gas/testsuite/gas/macros/repeat.s
    gas/testsuite/gas/macros/rept.d
    gas/testsuite/gas/macros/rept.s
    gas/testsuite/gas/macros/semi.d
    gas/testsuite/gas/macros/semi.s
    gas/testsuite/gas/macros/strings.d
    gas/testsuite/gas/macros/strings.s
    gas/testsuite/gas/macros/test1.d
    gas/testsuite/gas/macros/test1.s
    gas/testsuite/gas/macros/test2.d
    gas/testsuite/gas/macros/test2.s
    gas/testsuite/gas/macros/test3.d
    gas/testsuite/gas/macros/test3.s
    gas/testsuite/gas/macros/vararg.d
    gas/testsuite/gas/macros/vararg.s
    gas/testsuite/gas/maxq10/bits.d
    gas/testsuite/gas/maxq10/bits.s
    gas/testsuite/gas/maxq10/call.d
    gas/testsuite/gas/maxq10/call.s
    gas/testsuite/gas/maxq10/data.s
    gas/testsuite/gas/maxq10/data2.d
    gas/testsuite/gas/maxq10/data2.s
    gas/testsuite/gas/maxq10/data3.d
    gas/testsuite/gas/maxq10/data3.s
    gas/testsuite/gas/maxq10/err.s
    gas/testsuite/gas/maxq10/jump.d
    gas/testsuite/gas/maxq10/jump.s
    gas/testsuite/gas/maxq10/logical.d
    gas/testsuite/gas/maxq10/logical.s
    gas/testsuite/gas/maxq10/math.d
    gas/testsuite/gas/maxq10/math.s
    gas/testsuite/gas/maxq10/maxq10.exp
    gas/testsuite/gas/maxq10/pmtest.d
    gas/testsuite/gas/maxq10/pmtest.s
    gas/testsuite/gas/maxq10/range.d
    gas/testsuite/gas/maxq10/range.s
    gas/testsuite/gas/maxq20/bits.d
    gas/testsuite/gas/maxq20/bits.s
    gas/testsuite/gas/maxq20/call.d
    gas/testsuite/gas/maxq20/call.s
    gas/testsuite/gas/maxq20/data1.d
    gas/testsuite/gas/maxq20/data1.s
    gas/testsuite/gas/maxq20/data2.d
    gas/testsuite/gas/maxq20/data2.s
    gas/testsuite/gas/maxq20/data3.d
    gas/testsuite/gas/maxq20/data3.s
    gas/testsuite/gas/maxq20/jump.d
    gas/testsuite/gas/maxq20/jump.s
    gas/testsuite/gas/maxq20/jzimm.d
    gas/testsuite/gas/maxq20/jzimm.s
    gas/testsuite/gas/maxq20/logical.d
    gas/testsuite/gas/maxq20/logical.s
    gas/testsuite/gas/maxq20/math.d
    gas/testsuite/gas/maxq20/math.s
    gas/testsuite/gas/maxq20/maxq20.exp
    gas/testsuite/gas/maxq20/pfx2.s
    gas/testsuite/gas/maxq20/pmtest.d
    gas/testsuite/gas/maxq20/pmtest.s
    gas/testsuite/gas/maxq20/pxf0.s
    gas/testsuite/gas/maxq20/range.d
    gas/testsuite/gas/maxq20/range.s
    gas/testsuite/gas/mcore/allinsn.d
    gas/testsuite/gas/mcore/allinsn.exp
    gas/testsuite/gas/mcore/allinsn.s
    gas/testsuite/gas/mips/abs.d
    gas/testsuite/gas/mips/abs.s
    gas/testsuite/gas/mips/add.d
    gas/testsuite/gas/mips/add.s
    gas/testsuite/gas/mips/and.d
    gas/testsuite/gas/mips/and.s
    gas/testsuite/gas/mips/baddata1.l
    gas/testsuite/gas/mips/baddata1.s
    gas/testsuite/gas/mips/beq.d
    gas/testsuite/gas/mips/beq.s
    gas/testsuite/gas/mips/bge.d
    gas/testsuite/gas/mips/bge.s
    gas/testsuite/gas/mips/bgeu.d
    gas/testsuite/gas/mips/bgeu.s
    gas/testsuite/gas/mips/blt.d
    gas/testsuite/gas/mips/blt.s
    gas/testsuite/gas/mips/bltu.d
    gas/testsuite/gas/mips/bltu.s
    gas/testsuite/gas/mips/branch-misc-1.d
    gas/testsuite/gas/mips/branch-misc-1.s
    gas/testsuite/gas/mips/branch-misc-2-64.d
    gas/testsuite/gas/mips/branch-misc-2.d
    gas/testsuite/gas/mips/branch-misc-2.s
    gas/testsuite/gas/mips/branch-misc-2pic-64.d
    gas/testsuite/gas/mips/branch-misc-2pic.d
    gas/testsuite/gas/mips/branch-misc-3.d
    gas/testsuite/gas/mips/branch-misc-3.s
    gas/testsuite/gas/mips/branch-swap.d
    gas/testsuite/gas/mips/branch-swap.s
    gas/testsuite/gas/mips/break20.d
    gas/testsuite/gas/mips/break20.s
    gas/testsuite/gas/mips/cp0-names-mips32.d
    gas/testsuite/gas/mips/cp0-names-mips32r2.d
    gas/testsuite/gas/mips/cp0-names-mips64.d
    gas/testsuite/gas/mips/cp0-names-mips64r2.d
    gas/testsuite/gas/mips/cp0-names-numeric.d
    gas/testsuite/gas/mips/cp0-names-sb1.d
    gas/testsuite/gas/mips/cp0-names.s
    gas/testsuite/gas/mips/cp0sel-names-mips32.d
    gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
    gas/testsuite/gas/mips/cp0sel-names-mips64.d
    gas/testsuite/gas/mips/cp0sel-names-mips64r2.d
    gas/testsuite/gas/mips/cp0sel-names-numeric.d
    gas/testsuite/gas/mips/cp0sel-names-sb1.d
    gas/testsuite/gas/mips/cp0sel-names.s
    gas/testsuite/gas/mips/delay.d
    gas/testsuite/gas/mips/delay.s
    gas/testsuite/gas/mips/div-ilocks.d
    gas/testsuite/gas/mips/div.d
    gas/testsuite/gas/mips/div.s
    gas/testsuite/gas/mips/dli.d
    gas/testsuite/gas/mips/dli.s
    gas/testsuite/gas/mips/e32-rel2.d
    gas/testsuite/gas/mips/e32-rel4.d
    gas/testsuite/gas/mips/e32el-rel2.d
    gas/testsuite/gas/mips/elf-consthilo.d
    gas/testsuite/gas/mips/elf-consthilo.s
    gas/testsuite/gas/mips/elf-jal.d
    gas/testsuite/gas/mips/elf-rel-got-n32.d
    gas/testsuite/gas/mips/elf-rel-got-n32.s
    gas/testsuite/gas/mips/elf-rel-got-n64.d
    gas/testsuite/gas/mips/elf-rel-got-n64.s
    gas/testsuite/gas/mips/elf-rel-xgot-n32.d
    gas/testsuite/gas/mips/elf-rel-xgot-n64.d
    gas/testsuite/gas/mips/elf-rel.d
    gas/testsuite/gas/mips/elf-rel.s
    gas/testsuite/gas/mips/elf-rel10.d
    gas/testsuite/gas/mips/elf-rel10.s
    gas/testsuite/gas/mips/elf-rel11.d
    gas/testsuite/gas/mips/elf-rel11.s
    gas/testsuite/gas/mips/elf-rel12.d
    gas/testsuite/gas/mips/elf-rel12.s
    gas/testsuite/gas/mips/elf-rel13.d
    gas/testsuite/gas/mips/elf-rel13.s
    gas/testsuite/gas/mips/elf-rel14.d
    gas/testsuite/gas/mips/elf-rel14.s
    gas/testsuite/gas/mips/elf-rel15.d
    gas/testsuite/gas/mips/elf-rel15.s
    gas/testsuite/gas/mips/elf-rel16.d
    gas/testsuite/gas/mips/elf-rel16.s
    gas/testsuite/gas/mips/elf-rel17.d
    gas/testsuite/gas/mips/elf-rel17.s
    gas/testsuite/gas/mips/elf-rel18.d
    gas/testsuite/gas/mips/elf-rel18.s
    gas/testsuite/gas/mips/elf-rel19.d
    gas/testsuite/gas/mips/elf-rel19.s
    gas/testsuite/gas/mips/elf-rel2.d
    gas/testsuite/gas/mips/elf-rel2.s
    gas/testsuite/gas/mips/elf-rel20.d
    gas/testsuite/gas/mips/elf-rel20.s
    gas/testsuite/gas/mips/elf-rel21.d
    gas/testsuite/gas/mips/elf-rel21.s
    gas/testsuite/gas/mips/elf-rel22.d
    gas/testsuite/gas/mips/elf-rel22.s
    gas/testsuite/gas/mips/elf-rel23.d
    gas/testsuite/gas/mips/elf-rel23.s
    gas/testsuite/gas/mips/elf-rel23a.d
    gas/testsuite/gas/mips/elf-rel23b.d
    gas/testsuite/gas/mips/elf-rel24.d
    gas/testsuite/gas/mips/elf-rel24.s
    gas/testsuite/gas/mips/elf-rel25.d
    gas/testsuite/gas/mips/elf-rel25.s
    gas/testsuite/gas/mips/elf-rel25a.d
    gas/testsuite/gas/mips/elf-rel3.d
    gas/testsuite/gas/mips/elf-rel3.s
    gas/testsuite/gas/mips/elf-rel4.d
    gas/testsuite/gas/mips/elf-rel4.s
    gas/testsuite/gas/mips/elf-rel5.d
    gas/testsuite/gas/mips/elf-rel5.s
    gas/testsuite/gas/mips/elf-rel6-n32.d
    gas/testsuite/gas/mips/elf-rel6-n64.d
    gas/testsuite/gas/mips/elf-rel6.d
    gas/testsuite/gas/mips/elf-rel6.s
    gas/testsuite/gas/mips/elf-rel7.d
    gas/testsuite/gas/mips/elf-rel7.s
    gas/testsuite/gas/mips/elf-rel8.d
    gas/testsuite/gas/mips/elf-rel8.s
    gas/testsuite/gas/mips/elf-rel9.d
    gas/testsuite/gas/mips/elf-rel9.s
    gas/testsuite/gas/mips/elf_arch_mips1.d
    gas/testsuite/gas/mips/elf_arch_mips2.d
    gas/testsuite/gas/mips/elf_arch_mips3.d
    gas/testsuite/gas/mips/elf_arch_mips32.d
    gas/testsuite/gas/mips/elf_arch_mips32r2.d
    gas/testsuite/gas/mips/elf_arch_mips4.d
    gas/testsuite/gas/mips/elf_arch_mips5.d
    gas/testsuite/gas/mips/elf_arch_mips64.d
    gas/testsuite/gas/mips/elf_arch_mips64r2.d
    gas/testsuite/gas/mips/elf_ase_mips16.d
    gas/testsuite/gas/mips/elf_e_flags.c
    gas/testsuite/gas/mips/elf_e_flags.s
    gas/testsuite/gas/mips/elf_e_flags1.d
    gas/testsuite/gas/mips/elf_e_flags2.d
    gas/testsuite/gas/mips/elf_e_flags3.d
    gas/testsuite/gas/mips/elf_e_flags4.d
    gas/testsuite/gas/mips/elfel-rel.d
    gas/testsuite/gas/mips/elfel-rel2.d
    gas/testsuite/gas/mips/elfel-rel3.d
    gas/testsuite/gas/mips/empty.s
    gas/testsuite/gas/mips/expr1.d
    gas/testsuite/gas/mips/expr1.s
    gas/testsuite/gas/mips/fpr-names-32.d
    gas/testsuite/gas/mips/fpr-names-64.d
    gas/testsuite/gas/mips/fpr-names-n32.d
    gas/testsuite/gas/mips/fpr-names-numeric.d
    gas/testsuite/gas/mips/fpr-names.s
    gas/testsuite/gas/mips/gpr-names-32.d
    gas/testsuite/gas/mips/gpr-names-64.d
    gas/testsuite/gas/mips/gpr-names-n32.d
    gas/testsuite/gas/mips/gpr-names-numeric.d
    gas/testsuite/gas/mips/gpr-names.s
    gas/testsuite/gas/mips/hwr-names-mips32r2.d
    gas/testsuite/gas/mips/hwr-names-mips64r2.d
    gas/testsuite/gas/mips/hwr-names-numeric.d
    gas/testsuite/gas/mips/hwr-names.s
    gas/testsuite/gas/mips/illegal.l
    gas/testsuite/gas/mips/illegal.s
    gas/testsuite/gas/mips/itbl
    gas/testsuite/gas/mips/itbl.s
    gas/testsuite/gas/mips/jal-newabi.d
    gas/testsuite/gas/mips/jal-newabi.s
    gas/testsuite/gas/mips/jal-range.l
    gas/testsuite/gas/mips/jal-range.s
    gas/testsuite/gas/mips/jal-svr4pic.d
    gas/testsuite/gas/mips/jal-svr4pic.s
    gas/testsuite/gas/mips/jal-xgot.d
    gas/testsuite/gas/mips/jal.d
    gas/testsuite/gas/mips/jal.s
    gas/testsuite/gas/mips/la-svr4pic.d
    gas/testsuite/gas/mips/la-xgot.d
    gas/testsuite/gas/mips/la.d
    gas/testsuite/gas/mips/la.s
    gas/testsuite/gas/mips/lb-pic.s
    gas/testsuite/gas/mips/lb-svr4pic-ilocks.d
    gas/testsuite/gas/mips/lb-svr4pic.d
    gas/testsuite/gas/mips/lb-xgot-ilocks.d
    gas/testsuite/gas/mips/lb-xgot.d
    gas/testsuite/gas/mips/lb.d
    gas/testsuite/gas/mips/lb.s
    gas/testsuite/gas/mips/lca-svr4pic.d
    gas/testsuite/gas/mips/lca-xgot.d
    gas/testsuite/gas/mips/lca.s
    gas/testsuite/gas/mips/ld-ilocks-addr32.d
    gas/testsuite/gas/mips/ld-ilocks.d
    gas/testsuite/gas/mips/ld-pic.s
    gas/testsuite/gas/mips/ld-svr4pic.d
    gas/testsuite/gas/mips/ld-xgot.d
    gas/testsuite/gas/mips/ld.d
    gas/testsuite/gas/mips/ld.s
    gas/testsuite/gas/mips/ldstla-32-1.l
    gas/testsuite/gas/mips/ldstla-32-1.s
    gas/testsuite/gas/mips/ldstla-32-mips3-1.l
    gas/testsuite/gas/mips/ldstla-32-mips3-1.s
    gas/testsuite/gas/mips/ldstla-32-mips3-shared.d
    gas/testsuite/gas/mips/ldstla-32-mips3.d
    gas/testsuite/gas/mips/ldstla-32-mips3.s
    gas/testsuite/gas/mips/ldstla-32-shared.d
    gas/testsuite/gas/mips/ldstla-32.d
    gas/testsuite/gas/mips/ldstla-32.s
    gas/testsuite/gas/mips/ldstla-eabi64.d
    gas/testsuite/gas/mips/ldstla-n64-shared.d
    gas/testsuite/gas/mips/ldstla-n64-sym32.d
    gas/testsuite/gas/mips/ldstla-n64.d
    gas/testsuite/gas/mips/ldstla-n64.s
    gas/testsuite/gas/mips/ldstla-sym32.s
    gas/testsuite/gas/mips/li.d
    gas/testsuite/gas/mips/li.s
    gas/testsuite/gas/mips/lif-svr4pic.d
    gas/testsuite/gas/mips/lif-xgot.d
    gas/testsuite/gas/mips/lifloat.d
    gas/testsuite/gas/mips/lifloat.s
    gas/testsuite/gas/mips/lineno.d
    gas/testsuite/gas/mips/lineno.s
    gas/testsuite/gas/mips/macro-warn-1-n32.d
    gas/testsuite/gas/mips/macro-warn-1-n32.l
    gas/testsuite/gas/mips/macro-warn-1.d
    gas/testsuite/gas/mips/macro-warn-1.l
    gas/testsuite/gas/mips/macro-warn-1.s
    gas/testsuite/gas/mips/macro-warn-2-n32.d
    gas/testsuite/gas/mips/macro-warn-2.d
    gas/testsuite/gas/mips/macro-warn-2.l
    gas/testsuite/gas/mips/macro-warn-2.s
    gas/testsuite/gas/mips/macro-warn-3.d
    gas/testsuite/gas/mips/macro-warn-3.l
    gas/testsuite/gas/mips/macro-warn-3.s
    gas/testsuite/gas/mips/macro-warn-4.d
    gas/testsuite/gas/mips/macro-warn-4.l
    gas/testsuite/gas/mips/macro-warn-4.s
    gas/testsuite/gas/mips/mips-abi32-pic.d
    gas/testsuite/gas/mips/mips-abi32-pic.s
    gas/testsuite/gas/mips/mips-abi32-pic2.d
    gas/testsuite/gas/mips/mips-abi32-pic2.s
    gas/testsuite/gas/mips/mips-abi32.d
    gas/testsuite/gas/mips/mips-abi32.s
    gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
    gas/testsuite/gas/mips/mips-gp32-fp32-pic.s
    gas/testsuite/gas/mips/mips-gp32-fp32.d
    gas/testsuite/gas/mips/mips-gp32-fp32.s
    gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
    gas/testsuite/gas/mips/mips-gp32-fp64-pic.s
    gas/testsuite/gas/mips/mips-gp32-fp64.d
    gas/testsuite/gas/mips/mips-gp32-fp64.l
    gas/testsuite/gas/mips/mips-gp32-fp64.s
    gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
    gas/testsuite/gas/mips/mips-gp64-fp32-pic.l
    gas/testsuite/gas/mips/mips-gp64-fp32-pic.s
    gas/testsuite/gas/mips/mips-gp64-fp32.d
    gas/testsuite/gas/mips/mips-gp64-fp32.l
    gas/testsuite/gas/mips/mips-gp64-fp32.s
    gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
    gas/testsuite/gas/mips/mips-gp64-fp64-pic.s
    gas/testsuite/gas/mips/mips-gp64-fp64.d
    gas/testsuite/gas/mips/mips-gp64-fp64.l
    gas/testsuite/gas/mips/mips-gp64-fp64.s
    gas/testsuite/gas/mips/mips-jalx.d
    gas/testsuite/gas/mips/mips-jalx.s
    gas/testsuite/gas/mips/mips-no-jalx.l
    gas/testsuite/gas/mips/mips-no-jalx.s
    gas/testsuite/gas/mips/mips.exp
    gas/testsuite/gas/mips/mips16-64.d
    gas/testsuite/gas/mips/mips16-dwarf2-n32.d
    gas/testsuite/gas/mips/mips16-dwarf2.d
    gas/testsuite/gas/mips/mips16-dwarf2.s
    gas/testsuite/gas/mips/mips16-e.d
    gas/testsuite/gas/mips/mips16-e.s
    gas/testsuite/gas/mips/mips16-f.d
    gas/testsuite/gas/mips/mips16-f.s
    gas/testsuite/gas/mips/mips16-hilo-n32.d
    gas/testsuite/gas/mips/mips16-hilo.d
    gas/testsuite/gas/mips/mips16-hilo.s
    gas/testsuite/gas/mips/mips16-jalx.d
    gas/testsuite/gas/mips/mips16-jalx.s
    gas/testsuite/gas/mips/mips16.d
    gas/testsuite/gas/mips/mips16.s
    gas/testsuite/gas/mips/mips16e-64.d
    gas/testsuite/gas/mips/mips16e-64.l
    gas/testsuite/gas/mips/mips16e-64.s
    gas/testsuite/gas/mips/mips16e-jrc.d
    gas/testsuite/gas/mips/mips16e-jrc.s
    gas/testsuite/gas/mips/mips16e-save.d
    gas/testsuite/gas/mips/mips16e-save.s
    gas/testsuite/gas/mips/mips16e.d
    gas/testsuite/gas/mips/mips16e.s
    gas/testsuite/gas/mips/mips32-dsp.d
    gas/testsuite/gas/mips/mips32-dsp.s
    gas/testsuite/gas/mips/mips32-mt.d
    gas/testsuite/gas/mips/mips32-mt.s
    gas/testsuite/gas/mips/mips32-sf32.d
    gas/testsuite/gas/mips/mips32-sf32.s
    gas/testsuite/gas/mips/mips32.d
    gas/testsuite/gas/mips/mips32.s
    gas/testsuite/gas/mips/mips32r2-ill-fp64.l
    gas/testsuite/gas/mips/mips32r2-ill-fp64.s
    gas/testsuite/gas/mips/mips32r2-ill.l
    gas/testsuite/gas/mips/mips32r2-ill.s
    gas/testsuite/gas/mips/mips32r2.d
    gas/testsuite/gas/mips/mips32r2.s
    gas/testsuite/gas/mips/mips4.d
    gas/testsuite/gas/mips/mips4.s
    gas/testsuite/gas/mips/mips4010.d
    gas/testsuite/gas/mips/mips4010.s
    gas/testsuite/gas/mips/mips4100.d
    gas/testsuite/gas/mips/mips4100.s
    gas/testsuite/gas/mips/mips4650.d
    gas/testsuite/gas/mips/mips4650.s
    gas/testsuite/gas/mips/mips5.d
    gas/testsuite/gas/mips/mips5.l
    gas/testsuite/gas/mips/mips5.s
    gas/testsuite/gas/mips/mips64-dsp.d
    gas/testsuite/gas/mips/mips64-dsp.s
    gas/testsuite/gas/mips/mips64-mdmx.d
    gas/testsuite/gas/mips/mips64-mdmx.s
    gas/testsuite/gas/mips/mips64-mips3d-incl.d
    gas/testsuite/gas/mips/mips64-mips3d.d
    gas/testsuite/gas/mips/mips64-mips3d.l
    gas/testsuite/gas/mips/mips64-mips3d.s
    gas/testsuite/gas/mips/mips64.d
    gas/testsuite/gas/mips/mips64.s
    gas/testsuite/gas/mips/mips64r2-ill.l
    gas/testsuite/gas/mips/mips64r2-ill.s
    gas/testsuite/gas/mips/mips64r2.d
    gas/testsuite/gas/mips/mips64r2.s
    gas/testsuite/gas/mips/mipsel16-e.d
    gas/testsuite/gas/mips/mipsel16-f.d
    gas/testsuite/gas/mips/mul-ilocks.d
    gas/testsuite/gas/mips/mul.d
    gas/testsuite/gas/mips/mul.s
    gas/testsuite/gas/mips/n32-consec.d
    gas/testsuite/gas/mips/n32-consec.s
    gas/testsuite/gas/mips/noat-1.d
    gas/testsuite/gas/mips/noat-1.s
    gas/testsuite/gas/mips/noat-2.l
    gas/testsuite/gas/mips/noat-2.s
    gas/testsuite/gas/mips/noat-3.l
    gas/testsuite/gas/mips/noat-3.s
    gas/testsuite/gas/mips/noat-4.l
    gas/testsuite/gas/mips/noat-4.s
    gas/testsuite/gas/mips/noat-5.l
    gas/testsuite/gas/mips/noat-5.s
    gas/testsuite/gas/mips/noat-6.l
    gas/testsuite/gas/mips/noat-6.s
    gas/testsuite/gas/mips/noat-7.l
    gas/testsuite/gas/mips/noat-7.s
    gas/testsuite/gas/mips/nodelay.d
    gas/testsuite/gas/mips/noreorder.d
    gas/testsuite/gas/mips/noreorder.s
    gas/testsuite/gas/mips/perfcount.d
    gas/testsuite/gas/mips/perfcount.s
    gas/testsuite/gas/mips/relax-swap1-mips1.d
    gas/testsuite/gas/mips/relax-swap1-mips2.d
    gas/testsuite/gas/mips/relax-swap1.l
    gas/testsuite/gas/mips/relax-swap1.s
    gas/testsuite/gas/mips/relax-swap2.d
    gas/testsuite/gas/mips/relax-swap2.l
    gas/testsuite/gas/mips/relax-swap2.s
    gas/testsuite/gas/mips/relax.d
    gas/testsuite/gas/mips/relax.l
    gas/testsuite/gas/mips/relax.s
    gas/testsuite/gas/mips/rm7000.d
    gas/testsuite/gas/mips/rm7000.s
    gas/testsuite/gas/mips/rol-hw.d
    gas/testsuite/gas/mips/rol.d
    gas/testsuite/gas/mips/rol.s
    gas/testsuite/gas/mips/rol64-hw.d
    gas/testsuite/gas/mips/rol64.d
    gas/testsuite/gas/mips/rol64.s
    gas/testsuite/gas/mips/sb.d
    gas/testsuite/gas/mips/sb.s
    gas/testsuite/gas/mips/sb1-ext-mdmx.d
    gas/testsuite/gas/mips/sb1-ext-mdmx.s
    gas/testsuite/gas/mips/sb1-ext-ps.d
    gas/testsuite/gas/mips/sb1-ext-ps.s
    gas/testsuite/gas/mips/set-arch.d
    gas/testsuite/gas/mips/set-arch.l
    gas/testsuite/gas/mips/set-arch.s
    gas/testsuite/gas/mips/smartmips.d
    gas/testsuite/gas/mips/smartmips.s
    gas/testsuite/gas/mips/sync.d
    gas/testsuite/gas/mips/sync.s
    gas/testsuite/gas/mips/tls-ill.l
    gas/testsuite/gas/mips/tls-ill.s
    gas/testsuite/gas/mips/tls-o32.d
    gas/testsuite/gas/mips/tls-o32.s
    gas/testsuite/gas/mips/tmips16-e.d
    gas/testsuite/gas/mips/tmips16-f.d
    gas/testsuite/gas/mips/tmipsel16-e.d
    gas/testsuite/gas/mips/tmipsel16-f.d
    gas/testsuite/gas/mips/trap20.d
    gas/testsuite/gas/mips/trap20.s
    gas/testsuite/gas/mips/trunc.d
    gas/testsuite/gas/mips/trunc.s
    gas/testsuite/gas/mips/uld.d
    gas/testsuite/gas/mips/uld.s
    gas/testsuite/gas/mips/uld2-eb.d
    gas/testsuite/gas/mips/uld2-el.d
    gas/testsuite/gas/mips/uld2.s
    gas/testsuite/gas/mips/ulh-pic.s
    gas/testsuite/gas/mips/ulh-svr4pic.d
    gas/testsuite/gas/mips/ulh-xgot.d
    gas/testsuite/gas/mips/ulh.d
    gas/testsuite/gas/mips/ulh.s
    gas/testsuite/gas/mips/ulh2-eb.d
    gas/testsuite/gas/mips/ulh2-el.d
    gas/testsuite/gas/mips/ulh2.s
    gas/testsuite/gas/mips/ulw.d
    gas/testsuite/gas/mips/ulw.s
    gas/testsuite/gas/mips/ulw2-eb-ilocks.d
    gas/testsuite/gas/mips/ulw2-eb.d
    gas/testsuite/gas/mips/ulw2-el-ilocks.d
    gas/testsuite/gas/mips/ulw2-el.d
    gas/testsuite/gas/mips/ulw2.s
    gas/testsuite/gas/mips/usd.d
    gas/testsuite/gas/mips/usd.s
    gas/testsuite/gas/mips/ush.d
    gas/testsuite/gas/mips/ush.s
    gas/testsuite/gas/mips/usw.d
    gas/testsuite/gas/mips/usw.s
    gas/testsuite/gas/mips/vr4111.d
    gas/testsuite/gas/mips/vr4111.s
    gas/testsuite/gas/mips/vr4120-2.d
    gas/testsuite/gas/mips/vr4120-2.s
    gas/testsuite/gas/mips/vr4120.d
    gas/testsuite/gas/mips/vr4120.s
    gas/testsuite/gas/mips/vr4130.d
    gas/testsuite/gas/mips/vr4130.s
    gas/testsuite/gas/mips/vr5400.d
    gas/testsuite/gas/mips/vr5400.s
    gas/testsuite/gas/mips/vr5500.d
    gas/testsuite/gas/mips/vr5500.s
    gas/testsuite/gas/mips/vxworks1-el.d
    gas/testsuite/gas/mips/vxworks1-xgot-el.d
    gas/testsuite/gas/mips/vxworks1-xgot.d
    gas/testsuite/gas/mips/vxworks1.d
    gas/testsuite/gas/mips/vxworks1.s
    gas/testsuite/gas/mmix/1cjmp1b-n.d
    gas/testsuite/gas/mmix/1cjmp1b-r.d
    gas/testsuite/gas/mmix/1cjmp1b.d
    gas/testsuite/gas/mmix/1cjmp1b.l
    gas/testsuite/gas/mmix/1cjmp1b.s
    gas/testsuite/gas/mmix/1cjmp1brn.d
    gas/testsuite/gas/mmix/1hjmp1b.d
    gas/testsuite/gas/mmix/1hjmp1b.l
    gas/testsuite/gas/mmix/1hjmp1b.s
    gas/testsuite/gas/mmix/align-1.d
    gas/testsuite/gas/mmix/align-1.s
    gas/testsuite/gas/mmix/basep-1.d
    gas/testsuite/gas/mmix/basep-1.s
    gas/testsuite/gas/mmix/basep-10.d
    gas/testsuite/gas/mmix/basep-10.s
    gas/testsuite/gas/mmix/basep-11.d
    gas/testsuite/gas/mmix/basep-11.s
    gas/testsuite/gas/mmix/basep-1b.d
    gas/testsuite/gas/mmix/basep-2.d
    gas/testsuite/gas/mmix/basep-2.s
    gas/testsuite/gas/mmix/basep-2b.d
    gas/testsuite/gas/mmix/basep-3.d
    gas/testsuite/gas/mmix/basep-3.s
    gas/testsuite/gas/mmix/basep-3b.d
    gas/testsuite/gas/mmix/basep-4.d
    gas/testsuite/gas/mmix/basep-5.d
    gas/testsuite/gas/mmix/basep-6.d
    gas/testsuite/gas/mmix/basep-7.d
    gas/testsuite/gas/mmix/basep-8.d
    gas/testsuite/gas/mmix/basep-8.s
    gas/testsuite/gas/mmix/basep-9.d
    gas/testsuite/gas/mmix/basep-9.s
    gas/testsuite/gas/mmix/bspec-1.d
    gas/testsuite/gas/mmix/bspec-1.s
    gas/testsuite/gas/mmix/bspec-2.d
    gas/testsuite/gas/mmix/bspec-2.s
    gas/testsuite/gas/mmix/builtin1.d
    gas/testsuite/gas/mmix/builtin1.s
    gas/testsuite/gas/mmix/builtin2.d
    gas/testsuite/gas/mmix/builtin3.d
    gas/testsuite/gas/mmix/byte-1.d
    gas/testsuite/gas/mmix/byte-1.s
    gas/testsuite/gas/mmix/bz-c.d
    gas/testsuite/gas/mmix/bz-c.s
    gas/testsuite/gas/mmix/comment-1.d
    gas/testsuite/gas/mmix/comment-1.s
    gas/testsuite/gas/mmix/comment-2.d
    gas/testsuite/gas/mmix/comment-2.s
    gas/testsuite/gas/mmix/comment-3.d
    gas/testsuite/gas/mmix/comment-3.s
    gas/testsuite/gas/mmix/cons-1.d
    gas/testsuite/gas/mmix/cons-1.s
    gas/testsuite/gas/mmix/cons-2.d
    gas/testsuite/gas/mmix/cons-2.s
    gas/testsuite/gas/mmix/err-bpo1.s
    gas/testsuite/gas/mmix/err-bpo2.s
    gas/testsuite/gas/mmix/err-bpo3.s
    gas/testsuite/gas/mmix/err-bpo4.s
    gas/testsuite/gas/mmix/err-bpo5.s
    gas/testsuite/gas/mmix/err-bpo6.s
    gas/testsuite/gas/mmix/err-bspec-1.s
    gas/testsuite/gas/mmix/err-bspec-2.s
    gas/testsuite/gas/mmix/err-bspec-3.s
    gas/testsuite/gas/mmix/err-bspec-4.s
    gas/testsuite/gas/mmix/err-bspec-5.s
    gas/testsuite/gas/mmix/err-builtin.s
    gas/testsuite/gas/mmix/err-byte1.s
    gas/testsuite/gas/mmix/err-byte2.s
    gas/testsuite/gas/mmix/err-case.s
    gas/testsuite/gas/mmix/err-fb-1.s
    gas/testsuite/gas/mmix/err-greg1.s
    gas/testsuite/gas/mmix/err-insn.s
    gas/testsuite/gas/mmix/err-is-1.s
    gas/testsuite/gas/mmix/err-loc-1.s
    gas/testsuite/gas/mmix/err-loc-2.s
    gas/testsuite/gas/mmix/err-loc-3.s
    gas/testsuite/gas/mmix/err-loc-4.s
    gas/testsuite/gas/mmix/err-loc-5.s
    gas/testsuite/gas/mmix/err-loc-6.s
    gas/testsuite/gas/mmix/err-loc-7.s
    gas/testsuite/gas/mmix/err-loc-8.s
    gas/testsuite/gas/mmix/err-local1.s
    gas/testsuite/gas/mmix/err-local2.s
    gas/testsuite/gas/mmix/err-ser-1.s
    gas/testsuite/gas/mmix/err-set.s
    gas/testsuite/gas/mmix/expr-1.d
    gas/testsuite/gas/mmix/expr-1.s
    gas/testsuite/gas/mmix/fb-1.d
    gas/testsuite/gas/mmix/fb-1.s
    gas/testsuite/gas/mmix/fb-2.d
    gas/testsuite/gas/mmix/fb-2.s
    gas/testsuite/gas/mmix/get-op-r.d
    gas/testsuite/gas/mmix/get-op.d
    gas/testsuite/gas/mmix/get-op.l
    gas/testsuite/gas/mmix/get-op.s
    gas/testsuite/gas/mmix/geta-c.d
    gas/testsuite/gas/mmix/geta-c.s
    gas/testsuite/gas/mmix/geta-op-r.d
    gas/testsuite/gas/mmix/geta-op.d
    gas/testsuite/gas/mmix/geta-op.l
    gas/testsuite/gas/mmix/geta-op.s
    gas/testsuite/gas/mmix/geta-opn.d
    gas/testsuite/gas/mmix/geta-oprn.d
    gas/testsuite/gas/mmix/greg1.d
    gas/testsuite/gas/mmix/greg1.s
    gas/testsuite/gas/mmix/greg1a.d
    gas/testsuite/gas/mmix/greg2.d
    gas/testsuite/gas/mmix/greg2.s
    gas/testsuite/gas/mmix/greg2a.d
    gas/testsuite/gas/mmix/greg3.d
    gas/testsuite/gas/mmix/greg3.s
    gas/testsuite/gas/mmix/greg4.d
    gas/testsuite/gas/mmix/greg4.s
    gas/testsuite/gas/mmix/greg5.d
    gas/testsuite/gas/mmix/greg5.s
    gas/testsuite/gas/mmix/greg6.d
    gas/testsuite/gas/mmix/greg6.s
    gas/testsuite/gas/mmix/greg7.d
    gas/testsuite/gas/mmix/greg7.s
    gas/testsuite/gas/mmix/greg8.d
    gas/testsuite/gas/mmix/greg8.s
    gas/testsuite/gas/mmix/greg9.d
    gas/testsuite/gas/mmix/greg9.s
    gas/testsuite/gas/mmix/hex-r.d
    gas/testsuite/gas/mmix/hex.d
    gas/testsuite/gas/mmix/hex.l
    gas/testsuite/gas/mmix/hex.s
    gas/testsuite/gas/mmix/hex2.d
    gas/testsuite/gas/mmix/hex2.s
    gas/testsuite/gas/mmix/is-1.d
    gas/testsuite/gas/mmix/is-1.s
    gas/testsuite/gas/mmix/jmp-op-n.d
    gas/testsuite/gas/mmix/jmp-op-r.d
    gas/testsuite/gas/mmix/jmp-op.d
    gas/testsuite/gas/mmix/jmp-op.l
    gas/testsuite/gas/mmix/jmp-op.s
    gas/testsuite/gas/mmix/jmp-oprn.d
    gas/testsuite/gas/mmix/jump-c.d
    gas/testsuite/gas/mmix/jump-c.s
    gas/testsuite/gas/mmix/list-in-n.d
    gas/testsuite/gas/mmix/list-in-r.d
    gas/testsuite/gas/mmix/list-in-rn.d
    gas/testsuite/gas/mmix/list-insns.d
    gas/testsuite/gas/mmix/list-insns.l
    gas/testsuite/gas/mmix/list-insns.s
    gas/testsuite/gas/mmix/list-pseudoints.l
    gas/testsuite/gas/mmix/list-pseudoints.s
    gas/testsuite/gas/mmix/list-textfirst
    gas/testsuite/gas/mmix/list-textfirst.l
    gas/testsuite/gas/mmix/list-textfirst.s
    gas/testsuite/gas/mmix/loc-1.d
    gas/testsuite/gas/mmix/loc-1.s
    gas/testsuite/gas/mmix/loc-2.d
    gas/testsuite/gas/mmix/loc-2.s
    gas/testsuite/gas/mmix/loc-3.d
    gas/testsuite/gas/mmix/loc-3.s
    gas/testsuite/gas/mmix/loc-4.d
    gas/testsuite/gas/mmix/loc-4.s
    gas/testsuite/gas/mmix/loc-5.d
    gas/testsuite/gas/mmix/loc-5.s
    gas/testsuite/gas/mmix/local-1.d
    gas/testsuite/gas/mmix/local-1.s
    gas/testsuite/gas/mmix/locall1.d
    gas/testsuite/gas/mmix/locall1.s
    gas/testsuite/gas/mmix/mmix-err.exp
    gas/testsuite/gas/mmix/mmix-list.exp
    gas/testsuite/gas/mmix/mmix.exp
    gas/testsuite/gas/mmix/odd-1.d
    gas/testsuite/gas/mmix/odd-1.s
    gas/testsuite/gas/mmix/op-0-1.d
    gas/testsuite/gas/mmix/op-0-1.s
    gas/testsuite/gas/mmix/op-0-1s.d
    gas/testsuite/gas/mmix/op-0-2.d
    gas/testsuite/gas/mmix/pop-op-r.d
    gas/testsuite/gas/mmix/pop-op.d
    gas/testsuite/gas/mmix/pop-op.l
    gas/testsuite/gas/mmix/pop-op.s
    gas/testsuite/gas/mmix/prefix1.d
    gas/testsuite/gas/mmix/prefix1.s
    gas/testsuite/gas/mmix/prefix2.d
    gas/testsuite/gas/mmix/prefix2.s
    gas/testsuite/gas/mmix/prefix3.d
    gas/testsuite/gas/mmix/prefix3.s
    gas/testsuite/gas/mmix/pseudo-1.d
    gas/testsuite/gas/mmix/pseudo-1.s
    gas/testsuite/gas/mmix/pushgo-op-r.d
    gas/testsuite/gas/mmix/pushgo-op.d
    gas/testsuite/gas/mmix/pushgo-op.l
    gas/testsuite/gas/mmix/pushgo-op.s
    gas/testsuite/gas/mmix/pushj-c.d
    gas/testsuite/gas/mmix/pushj-c.s
    gas/testsuite/gas/mmix/pushj-cs.d
    gas/testsuite/gas/mmix/put-op-r.d
    gas/testsuite/gas/mmix/put-op.d
    gas/testsuite/gas/mmix/put-op.l
    gas/testsuite/gas/mmix/put-op.s
    gas/testsuite/gas/mmix/reg-op-r.d
    gas/testsuite/gas/mmix/reg-op.d
    gas/testsuite/gas/mmix/reg-op.l
    gas/testsuite/gas/mmix/reg-op.s
    gas/testsuite/gas/mmix/reg3-op-r.d
    gas/testsuite/gas/mmix/reg3-op.d
    gas/testsuite/gas/mmix/reg3-op.l
    gas/testsuite/gas/mmix/reg3-op.s
    gas/testsuite/gas/mmix/regt-op-r.d
    gas/testsuite/gas/mmix/regt-op.d
    gas/testsuite/gas/mmix/regt-op.l
    gas/testsuite/gas/mmix/regt-op.s
    gas/testsuite/gas/mmix/regx-op-r.d
    gas/testsuite/gas/mmix/regx-op.d
    gas/testsuite/gas/mmix/regx-op.l
    gas/testsuite/gas/mmix/regx-op.s
    gas/testsuite/gas/mmix/regy-op-r.d
    gas/testsuite/gas/mmix/regy-op.d
    gas/testsuite/gas/mmix/regy-op.l
    gas/testsuite/gas/mmix/regy-op.s
    gas/testsuite/gas/mmix/relax1-n.d
    gas/testsuite/gas/mmix/relax1-r.d
    gas/testsuite/gas/mmix/relax1-rn.d
    gas/testsuite/gas/mmix/relax1.d
    gas/testsuite/gas/mmix/relax1.l
    gas/testsuite/gas/mmix/relax1.s
    gas/testsuite/gas/mmix/relax2.d
    gas/testsuite/gas/mmix/relax2.s
    gas/testsuite/gas/mmix/reloc16-n.d
    gas/testsuite/gas/mmix/reloc16-r.d
    gas/testsuite/gas/mmix/reloc16.d
    gas/testsuite/gas/mmix/reloc16.l
    gas/testsuite/gas/mmix/reloc16.s
    gas/testsuite/gas/mmix/reloc8-r.d
    gas/testsuite/gas/mmix/reloc8.d
    gas/testsuite/gas/mmix/reloc8.l
    gas/testsuite/gas/mmix/reloc8.s
    gas/testsuite/gas/mmix/relocl-n.d
    gas/testsuite/gas/mmix/reloclab-r.d
    gas/testsuite/gas/mmix/reloclab-rs.d
    gas/testsuite/gas/mmix/reloclab-s.d
    gas/testsuite/gas/mmix/reloclab.d
    gas/testsuite/gas/mmix/reloclab.l
    gas/testsuite/gas/mmix/reloclab.s
    gas/testsuite/gas/mmix/reloclrn.d
    gas/testsuite/gas/mmix/relocxrn.d
    gas/testsuite/gas/mmix/resume-op-r.d
    gas/testsuite/gas/mmix/resume-op.d
    gas/testsuite/gas/mmix/resume-op.l
    gas/testsuite/gas/mmix/resume-op.s
    gas/testsuite/gas/mmix/round2-op-r.d
    gas/testsuite/gas/mmix/round2-op.d
    gas/testsuite/gas/mmix/round2-op.l
    gas/testsuite/gas/mmix/round2-op.s
    gas/testsuite/gas/mmix/roundi-op-r.d
    gas/testsuite/gas/mmix/roundi-op.d
    gas/testsuite/gas/mmix/roundi-op.l
    gas/testsuite/gas/mmix/roundi-op.s
    gas/testsuite/gas/mmix/roundr-op-r.d
    gas/testsuite/gas/mmix/roundr-op.d
    gas/testsuite/gas/mmix/roundr-op.l
    gas/testsuite/gas/mmix/roundr-op.s
    gas/testsuite/gas/mmix/save-op-r.d
    gas/testsuite/gas/mmix/save-op.d
    gas/testsuite/gas/mmix/save-op.l
    gas/testsuite/gas/mmix/save-op.s
    gas/testsuite/gas/mmix/set-r.d
    gas/testsuite/gas/mmix/set.d
    gas/testsuite/gas/mmix/set.l
    gas/testsuite/gas/mmix/set.s
    gas/testsuite/gas/mmix/swym-op-r.d
    gas/testsuite/gas/mmix/swym-op.d
    gas/testsuite/gas/mmix/swym-op.l
    gas/testsuite/gas/mmix/swym-op.s
    gas/testsuite/gas/mmix/sym-1.d
    gas/testsuite/gas/mmix/sym-1.s
    gas/testsuite/gas/mmix/sync-op-r.d
    gas/testsuite/gas/mmix/sync-op.d
    gas/testsuite/gas/mmix/sync-op.l
    gas/testsuite/gas/mmix/sync-op.s
    gas/testsuite/gas/mmix/two-op-r.d
    gas/testsuite/gas/mmix/two-op.d
    gas/testsuite/gas/mmix/two-op.l
    gas/testsuite/gas/mmix/two-op.s
    gas/testsuite/gas/mmix/unsave-op-r.d
    gas/testsuite/gas/mmix/unsave-op.d
    gas/testsuite/gas/mmix/unsave-op.l
    gas/testsuite/gas/mmix/unsave-op.s
    gas/testsuite/gas/mmix/weak1-s.d
    gas/testsuite/gas/mmix/weak1.d
    gas/testsuite/gas/mmix/weak1.s
    gas/testsuite/gas/mmix/zerop-1.d
    gas/testsuite/gas/mmix/zerop-1.s
    gas/testsuite/gas/mn10200/add.s
    gas/testsuite/gas/mn10200/basic.exp
    gas/testsuite/gas/mn10200/bcc.s
    gas/testsuite/gas/mn10200/bccx.s
    gas/testsuite/gas/mn10200/bit.s
    gas/testsuite/gas/mn10200/cmp.s
    gas/testsuite/gas/mn10200/ext.s
    gas/testsuite/gas/mn10200/logical.s
    gas/testsuite/gas/mn10200/mov1.s
    gas/testsuite/gas/mn10200/mov2.s
    gas/testsuite/gas/mn10200/mov3.s
    gas/testsuite/gas/mn10200/mov4.s
    gas/testsuite/gas/mn10200/movb.s
    gas/testsuite/gas/mn10200/movbu.s
    gas/testsuite/gas/mn10200/movx.s
    gas/testsuite/gas/mn10200/muldiv.s
    gas/testsuite/gas/mn10200/other.s
    gas/testsuite/gas/mn10200/shift.s
    gas/testsuite/gas/mn10200/sub.s
    gas/testsuite/gas/mn10300/add.s
    gas/testsuite/gas/mn10300/am33-2.c
    gas/testsuite/gas/mn10300/am33-2.d
    gas/testsuite/gas/mn10300/am33-2.s
    gas/testsuite/gas/mn10300/am33.s
    gas/testsuite/gas/mn10300/am33_2.s
    gas/testsuite/gas/mn10300/am33_3.s
    gas/testsuite/gas/mn10300/am33_4.s
    gas/testsuite/gas/mn10300/am33_5.s
    gas/testsuite/gas/mn10300/am33_6.s
    gas/testsuite/gas/mn10300/am33_7.s
    gas/testsuite/gas/mn10300/am33_8.s
    gas/testsuite/gas/mn10300/basic.exp
    gas/testsuite/gas/mn10300/bcc.s
    gas/testsuite/gas/mn10300/bit.s
    gas/testsuite/gas/mn10300/cmp.s
    gas/testsuite/gas/mn10300/ext.s
    gas/testsuite/gas/mn10300/extend.s
    gas/testsuite/gas/mn10300/logical.s
    gas/testsuite/gas/mn10300/loop.s
    gas/testsuite/gas/mn10300/mov1.s
    gas/testsuite/gas/mn10300/mov2.s
    gas/testsuite/gas/mn10300/mov3.s
    gas/testsuite/gas/mn10300/mov4.s
    gas/testsuite/gas/mn10300/mov5.s
    gas/testsuite/gas/mn10300/movbu.s
    gas/testsuite/gas/mn10300/movhu.s
    gas/testsuite/gas/mn10300/movm.s
    gas/testsuite/gas/mn10300/movpc.l
    gas/testsuite/gas/mn10300/movpc.s
    gas/testsuite/gas/mn10300/muldiv.s
    gas/testsuite/gas/mn10300/other.s
    gas/testsuite/gas/mn10300/relax.d
    gas/testsuite/gas/mn10300/relax.s
    gas/testsuite/gas/mn10300/shift.s
    gas/testsuite/gas/mn10300/sub.s
    gas/testsuite/gas/mn10300/udf.s
    gas/testsuite/gas/mri/char.d
    gas/testsuite/gas/mri/char.s
    gas/testsuite/gas/mri/comment.d
    gas/testsuite/gas/mri/comment.s
    gas/testsuite/gas/mri/common.d
    gas/testsuite/gas/mri/common.s
    gas/testsuite/gas/mri/constants.d
    gas/testsuite/gas/mri/constants.s
    gas/testsuite/gas/mri/empty.s
    gas/testsuite/gas/mri/equ.d
    gas/testsuite/gas/mri/equ.s
    gas/testsuite/gas/mri/expr.d
    gas/testsuite/gas/mri/expr.s
    gas/testsuite/gas/mri/float.d
    gas/testsuite/gas/mri/float.s
    gas/testsuite/gas/mri/for.d
    gas/testsuite/gas/mri/for.s
    gas/testsuite/gas/mri/if.d
    gas/testsuite/gas/mri/if.s
    gas/testsuite/gas/mri/immconst.d
    gas/testsuite/gas/mri/label.d
    gas/testsuite/gas/mri/label.s
    gas/testsuite/gas/mri/moveml.d
    gas/testsuite/gas/mri/moveml.s
    gas/testsuite/gas/mri/mri.exp
    gas/testsuite/gas/mri/repeat.d
    gas/testsuite/gas/mri/repeat.s
    gas/testsuite/gas/mri/semi.d
    gas/testsuite/gas/mri/semi.s
    gas/testsuite/gas/mri/while.d
    gas/testsuite/gas/mri/while.s
    gas/testsuite/gas/msp430/msp430.exp
    gas/testsuite/gas/msp430/opcode.d
    gas/testsuite/gas/msp430/opcode.s
    gas/testsuite/gas/mt/allinsn.d
    gas/testsuite/gas/mt/allinsn.s
    gas/testsuite/gas/mt/badinsn.s
    gas/testsuite/gas/mt/badinsn1.s
    gas/testsuite/gas/mt/badoffsethigh.s
    gas/testsuite/gas/mt/badoffsetlow.s
    gas/testsuite/gas/mt/badorder.s
    gas/testsuite/gas/mt/badreg.s
    gas/testsuite/gas/mt/badsignedimmhigh.s
    gas/testsuite/gas/mt/badsignedimmlow.s
    gas/testsuite/gas/mt/badsyntax.s
    gas/testsuite/gas/mt/badsyntax1.s
    gas/testsuite/gas/mt/badunsignedimmhigh.s
    gas/testsuite/gas/mt/badunsignedimmlow.s
    gas/testsuite/gas/mt/errors.exp
    gas/testsuite/gas/mt/ldst.s
    gas/testsuite/gas/mt/misc.d
    gas/testsuite/gas/mt/misc.s
    gas/testsuite/gas/mt/ms1-16-003.d
    gas/testsuite/gas/mt/ms1-16-003.s
    gas/testsuite/gas/mt/ms2.d
    gas/testsuite/gas/mt/ms2.s
    gas/testsuite/gas/mt/msys.d
    gas/testsuite/gas/mt/msys.s
    gas/testsuite/gas/mt/mt.exp
    gas/testsuite/gas/mt/relocs.d
    gas/testsuite/gas/mt/relocs.exp
    gas/testsuite/gas/mt/relocs1.s
    gas/testsuite/gas/mt/relocs2.s
    gas/testsuite/gas/openrisc/addi.d
    gas/testsuite/gas/openrisc/addi.s
    gas/testsuite/gas/openrisc/allinsn.d
    gas/testsuite/gas/openrisc/allinsn.exp
    gas/testsuite/gas/openrisc/allinsn.s
    gas/testsuite/gas/openrisc/lohi.d
    gas/testsuite/gas/openrisc/lohi.s
    gas/testsuite/gas/openrisc/store.d
    gas/testsuite/gas/openrisc/store.s
    gas/testsuite/gas/pdp11/opcode.d
    gas/testsuite/gas/pdp11/opcode.s
    gas/testsuite/gas/pdp11/pdp11.exp
    gas/testsuite/gas/pj/ops.d
    gas/testsuite/gas/pj/ops.s
    gas/testsuite/gas/pj/pj.exp
    gas/testsuite/gas/ppc/aix.exp
    gas/testsuite/gas/ppc/align.s
    gas/testsuite/gas/ppc/altivec.d
    gas/testsuite/gas/ppc/altivec.s
    gas/testsuite/gas/ppc/altivec_xcoff.d
    gas/testsuite/gas/ppc/altivec_xcoff.s
    gas/testsuite/gas/ppc/altivec_xcoff64.d
    gas/testsuite/gas/ppc/altivec_xcoff64.s
    gas/testsuite/gas/ppc/astest.d
    gas/testsuite/gas/ppc/astest.s
    gas/testsuite/gas/ppc/astest2.d
    gas/testsuite/gas/ppc/astest2.s
    gas/testsuite/gas/ppc/astest2_64.d
    gas/testsuite/gas/ppc/astest2_64.s
    gas/testsuite/gas/ppc/astest64.d
    gas/testsuite/gas/ppc/astest64.s
    gas/testsuite/gas/ppc/booke.d
    gas/testsuite/gas/ppc/booke.s
    gas/testsuite/gas/ppc/booke_xcoff.d
    gas/testsuite/gas/ppc/booke_xcoff.s
    gas/testsuite/gas/ppc/booke_xcoff64.d
    gas/testsuite/gas/ppc/booke_xcoff64.s
    gas/testsuite/gas/ppc/e500.d
    gas/testsuite/gas/ppc/e500.s
    gas/testsuite/gas/ppc/generate.sh
    gas/testsuite/gas/ppc/machine.d
    gas/testsuite/gas/ppc/machine.s
    gas/testsuite/gas/ppc/power4.d
    gas/testsuite/gas/ppc/power4.s
    gas/testsuite/gas/ppc/ppc.exp
    gas/testsuite/gas/ppc/simpshft.d
    gas/testsuite/gas/ppc/simpshft.s
    gas/testsuite/gas/ppc/test1elf.asm
    gas/testsuite/gas/ppc/test1elf32.d
    gas/testsuite/gas/ppc/test1elf32.s
    gas/testsuite/gas/ppc/test1elf64.d
    gas/testsuite/gas/ppc/test1elf64.s
    gas/testsuite/gas/ppc/test1xcoff.asm
    gas/testsuite/gas/ppc/test1xcoff32.d
    gas/testsuite/gas/ppc/test1xcoff32.s
    gas/testsuite/gas/ppc/textalign-xcoff-001.d
    gas/testsuite/gas/ppc/textalign-xcoff-001.s
    gas/testsuite/gas/ppc/textalign-xcoff-002.d
    gas/testsuite/gas/s390/esa-g5.d
    gas/testsuite/gas/s390/esa-g5.s
    gas/testsuite/gas/s390/esa-operands.d
    gas/testsuite/gas/s390/esa-operands.s
    gas/testsuite/gas/s390/esa-reloc.d
    gas/testsuite/gas/s390/esa-reloc.s
    gas/testsuite/gas/s390/esa-z9-109.d
    gas/testsuite/gas/s390/esa-z9-109.s
    gas/testsuite/gas/s390/esa-z900.d
    gas/testsuite/gas/s390/esa-z900.s
    gas/testsuite/gas/s390/esa-z990.d
    gas/testsuite/gas/s390/esa-z990.s
    gas/testsuite/gas/s390/operands.d
    gas/testsuite/gas/s390/operands.s
    gas/testsuite/gas/s390/operands64.d
    gas/testsuite/gas/s390/operands64.s
    gas/testsuite/gas/s390/s390.exp
    gas/testsuite/gas/s390/zarch-operands.d
    gas/testsuite/gas/s390/zarch-operands.s
    gas/testsuite/gas/s390/zarch-reloc.d
    gas/testsuite/gas/s390/zarch-reloc.s
    gas/testsuite/gas/s390/zarch-z9-109.d
    gas/testsuite/gas/s390/zarch-z9-109.s
    gas/testsuite/gas/s390/zarch-z900.d
    gas/testsuite/gas/s390/zarch-z900.s
    gas/testsuite/gas/s390/zarch-z990.d
    gas/testsuite/gas/s390/zarch-z990.s
    gas/testsuite/gas/sh/arch/arch.exp
    gas/testsuite/gas/sh/arch/arch_expected.txt
    gas/testsuite/gas/sh/arch/sh-dsp.s
    gas/testsuite/gas/sh/arch/sh.s
    gas/testsuite/gas/sh/arch/sh2.s
    gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
    gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    gas/testsuite/gas/sh/arch/sh2a-nofpu.s
    gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
    gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
    gas/testsuite/gas/sh/arch/sh2a.s
    gas/testsuite/gas/sh/arch/sh2e.s
    gas/testsuite/gas/sh/arch/sh3-dsp.s
    gas/testsuite/gas/sh/arch/sh3-nommu.s
    gas/testsuite/gas/sh/arch/sh3.s
    gas/testsuite/gas/sh/arch/sh3e.s
    gas/testsuite/gas/sh/arch/sh4-nofpu.s
    gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
    gas/testsuite/gas/sh/arch/sh4.s
    gas/testsuite/gas/sh/arch/sh4a-nofpu.s
    gas/testsuite/gas/sh/arch/sh4a.s
    gas/testsuite/gas/sh/arch/sh4al-dsp.s
    gas/testsuite/gas/sh/basic.exp
    gas/testsuite/gas/sh/dsp.d
    gas/testsuite/gas/sh/dsp.s
    gas/testsuite/gas/sh/err-1.s
    gas/testsuite/gas/sh/err-at.s
    gas/testsuite/gas/sh/err-be.s
    gas/testsuite/gas/sh/err-le.s
    gas/testsuite/gas/sh/err-sh4a-fp.s
    gas/testsuite/gas/sh/err-sh4a.s
    gas/testsuite/gas/sh/err-sh4al-dsp.s
    gas/testsuite/gas/sh/err.exp
    gas/testsuite/gas/sh/fp.s
    gas/testsuite/gas/sh/pcrel-coff.d
    gas/testsuite/gas/sh/pcrel-coff.s
    gas/testsuite/gas/sh/pcrel-hms.d
    gas/testsuite/gas/sh/pcrel.d
    gas/testsuite/gas/sh/pcrel.l
    gas/testsuite/gas/sh/pcrel.s
    gas/testsuite/gas/sh/pcrel2.d
    gas/testsuite/gas/sh/pcrel2.s
    gas/testsuite/gas/sh/pic.d
    gas/testsuite/gas/sh/pic.s
    gas/testsuite/gas/sh/reg-prefix.d
    gas/testsuite/gas/sh/reg-prefix.s
    gas/testsuite/gas/sh/renesas-1.d
    gas/testsuite/gas/sh/renesas-1.s
    gas/testsuite/gas/sh/sh2a.d
    gas/testsuite/gas/sh/sh2a.s
    gas/testsuite/gas/sh/sh4a-dsp.d
    gas/testsuite/gas/sh/sh4a-dsp.s
    gas/testsuite/gas/sh/sh4a-fp.d
    gas/testsuite/gas/sh/sh4a-fp.s
    gas/testsuite/gas/sh/sh4a.d
    gas/testsuite/gas/sh/sh4a.s
    gas/testsuite/gas/sh/sh4al-dsp.d
    gas/testsuite/gas/sh/sh4al-dsp.s
    gas/testsuite/gas/sh/sh64/abi-32.d
    gas/testsuite/gas/sh/sh64/abi-32.s
    gas/testsuite/gas/sh/sh64/abi-64.d
    gas/testsuite/gas/sh/sh64/abi-64.s
    gas/testsuite/gas/sh/sh64/basic-1.d
    gas/testsuite/gas/sh/sh64/basic-1.s
    gas/testsuite/gas/sh/sh64/case-1.d
    gas/testsuite/gas/sh/sh64/case-1.s
    gas/testsuite/gas/sh/sh64/case-noexp-1.d
    gas/testsuite/gas/sh/sh64/crange1-1.d
    gas/testsuite/gas/sh/sh64/crange1-2.d
    gas/testsuite/gas/sh/sh64/crange1.s
    gas/testsuite/gas/sh/sh64/crange2-1.d
    gas/testsuite/gas/sh/sh64/crange2-2.d
    gas/testsuite/gas/sh/sh64/crange2-noexp-1.d
    gas/testsuite/gas/sh/sh64/crange2.s
    gas/testsuite/gas/sh/sh64/crange3-1.d
    gas/testsuite/gas/sh/sh64/crange3.s
    gas/testsuite/gas/sh/sh64/crange4-1.d
    gas/testsuite/gas/sh/sh64/crange4.s
    gas/testsuite/gas/sh/sh64/crange5-1.d
    gas/testsuite/gas/sh/sh64/crange5.s
    gas/testsuite/gas/sh/sh64/creg-1.d
    gas/testsuite/gas/sh/sh64/creg-1.s
    gas/testsuite/gas/sh/sh64/creg-2.d
    gas/testsuite/gas/sh/sh64/creg-2.s
    gas/testsuite/gas/sh/sh64/datal-1.s
    gas/testsuite/gas/sh/sh64/datal-2.d
    gas/testsuite/gas/sh/sh64/datal-2.s
    gas/testsuite/gas/sh/sh64/datal-3.s
    gas/testsuite/gas/sh/sh64/datal32-1.d
    gas/testsuite/gas/sh/sh64/datal32-3.d
    gas/testsuite/gas/sh/sh64/datal64-1.d
    gas/testsuite/gas/sh/sh64/datal64-3.d
    gas/testsuite/gas/sh/sh64/endian-1.d
    gas/testsuite/gas/sh/sh64/endian-1.s
    gas/testsuite/gas/sh/sh64/endian-2.d
    gas/testsuite/gas/sh/sh64/endian-2.s
    gas/testsuite/gas/sh/sh64/err-1.s
    gas/testsuite/gas/sh/sh64/err-2.s
    gas/testsuite/gas/sh/sh64/err-3.s
    gas/testsuite/gas/sh/sh64/err-4.s
    gas/testsuite/gas/sh/sh64/err-abi-32.s
    gas/testsuite/gas/sh/sh64/err-abi-64.s
    gas/testsuite/gas/sh/sh64/err-dsp.s
    gas/testsuite/gas/sh/sh64/err-movi-noexp-1.s
    gas/testsuite/gas/sh/sh64/err-noexp-cmd1.s
    gas/testsuite/gas/sh/sh64/err-pt-1.s
    gas/testsuite/gas/sh/sh64/err-pt32-cmd1.s
    gas/testsuite/gas/sh/sh64/err-pt32-cmd2.s
    gas/testsuite/gas/sh/sh64/err-pt32-cmd3.s
    gas/testsuite/gas/sh/sh64/err-ptb-1.s
    gas/testsuite/gas/sh/sh64/err-ptb-2.s
    gas/testsuite/gas/sh/sh64/err.exp
    gas/testsuite/gas/sh/sh64/immexpr1.s
    gas/testsuite/gas/sh/sh64/immexpr2.s
    gas/testsuite/gas/sh/sh64/immexpr32-1.d
    gas/testsuite/gas/sh/sh64/immexpr32-2.d
    gas/testsuite/gas/sh/sh64/immexpr64-1.d
    gas/testsuite/gas/sh/sh64/immexpr64-2.d
    gas/testsuite/gas/sh/sh64/lineno.d
    gas/testsuite/gas/sh/sh64/lineno.s
    gas/testsuite/gas/sh/sh64/localcom-1.d
    gas/testsuite/gas/sh/sh64/localcom-1.s
    gas/testsuite/gas/sh/sh64/mix-1.d
    gas/testsuite/gas/sh/sh64/mix-1.s
    gas/testsuite/gas/sh/sh64/mix-noexp-1.d
    gas/testsuite/gas/sh/sh64/movi-1.s
    gas/testsuite/gas/sh/sh64/movi-2.s
    gas/testsuite/gas/sh/sh64/movi-3.d
    gas/testsuite/gas/sh/sh64/movi-3.s
    gas/testsuite/gas/sh/sh64/movi32-1.d
    gas/testsuite/gas/sh/sh64/movi32-2.d
    gas/testsuite/gas/sh/sh64/movi32-noexp-2.d
    gas/testsuite/gas/sh/sh64/movi64-1.d
    gas/testsuite/gas/sh/sh64/movi64-2.d
    gas/testsuite/gas/sh/sh64/movi64-2.s
    gas/testsuite/gas/sh/sh64/movi64-3.d
    gas/testsuite/gas/sh/sh64/movi64-noexp-2.d
    gas/testsuite/gas/sh/sh64/pt-1.d
    gas/testsuite/gas/sh/sh64/pt-1.s
    gas/testsuite/gas/sh/sh64/pt-2.s
    gas/testsuite/gas/sh/sh64/pt-noexp-1.d
    gas/testsuite/gas/sh/sh64/pt32-1.d
    gas/testsuite/gas/sh/sh64/pt32-noexp-2.d
    gas/testsuite/gas/sh/sh64/pt64-1.d
    gas/testsuite/gas/sh/sh64/pt64-32-1.d
    gas/testsuite/gas/sh/sh64/pt64-32-2.d
    gas/testsuite/gas/sh/sh64/pt64-noexp-2.d
    gas/testsuite/gas/sh/sh64/ptc-1.s
    gas/testsuite/gas/sh/sh64/ptc32-1.d
    gas/testsuite/gas/sh/sh64/ptc32-noexp-1.d
    gas/testsuite/gas/sh/sh64/ptc64-1.d
    gas/testsuite/gas/sh/sh64/ptc64-32-1.d
    gas/testsuite/gas/sh/sh64/ptc64-noexp-1.d
    gas/testsuite/gas/sh/sh64/ptext-1.s
    gas/testsuite/gas/sh/sh64/ptext32-1.d
    gas/testsuite/gas/sh/sh64/ptext32-noexp-1.d
    gas/testsuite/gas/sh/sh64/ptext64-1.d
    gas/testsuite/gas/sh/sh64/ptext64-32-1.d
    gas/testsuite/gas/sh/sh64/ptext64-noexp-1.d
    gas/testsuite/gas/sh/sh64/rel-1.s
    gas/testsuite/gas/sh/sh64/rel-2.s
    gas/testsuite/gas/sh/sh64/rel-3.s
    gas/testsuite/gas/sh/sh64/rel-4.s
    gas/testsuite/gas/sh/sh64/rel-5.s
    gas/testsuite/gas/sh/sh64/rel32-1.d
    gas/testsuite/gas/sh/sh64/rel32-2.d
    gas/testsuite/gas/sh/sh64/rel32-3.d
    gas/testsuite/gas/sh/sh64/rel32-4.d
    gas/testsuite/gas/sh/sh64/rel32-5.d
    gas/testsuite/gas/sh/sh64/rel64-1.d
    gas/testsuite/gas/sh/sh64/rel64-2.d
    gas/testsuite/gas/sh/sh64/rel64-3.d
    gas/testsuite/gas/sh/sh64/rel64-4.d
    gas/testsuite/gas/sh/sh64/rel64-5.d
    gas/testsuite/gas/sh/sh64/relax-1.d
    gas/testsuite/gas/sh/sh64/relax-1.s
    gas/testsuite/gas/sh/sh64/relax-2.d
    gas/testsuite/gas/sh/sh64/relax-2.s
    gas/testsuite/gas/sh/sh64/relax-3.d
    gas/testsuite/gas/sh/sh64/relax-3.s
    gas/testsuite/gas/sh/sh64/sh64.exp
    gas/testsuite/gas/sh/sh64/shift-1.s
    gas/testsuite/gas/sh/sh64/shift-2.s
    gas/testsuite/gas/sh/sh64/shift-3.s
    gas/testsuite/gas/sh/sh64/shift32-1.d
    gas/testsuite/gas/sh/sh64/shift32-3.d
    gas/testsuite/gas/sh/sh64/shift32-noexp-3.d
    gas/testsuite/gas/sh/sh64/shift64-1.d
    gas/testsuite/gas/sh/sh64/shift64-2.d
    gas/testsuite/gas/sh/sh64/shift64-3.d
    gas/testsuite/gas/sh/sh64/shift64-noexp-3.d
    gas/testsuite/gas/sh/sh64/syntax-1.d
    gas/testsuite/gas/sh/sh64/syntax-1.s
    gas/testsuite/gas/sh/sh64/syntax-2.d
    gas/testsuite/gas/sh/sh64/syntax-2.s
    gas/testsuite/gas/sh/sh64/ua-1.s
    gas/testsuite/gas/sh/sh64/ua32-1.d
    gas/testsuite/gas/sh/sh64/ua64-1.d
    gas/testsuite/gas/sh/tlsd.d
    gas/testsuite/gas/sh/tlsd.s
    gas/testsuite/gas/sh/tlsnopic.d
    gas/testsuite/gas/sh/tlsnopic.s
    gas/testsuite/gas/sh/tlspic.d
    gas/testsuite/gas/sh/tlspic.s
    gas/testsuite/gas/sh/too_large.d
    gas/testsuite/gas/sh/too_large.s
    gas/testsuite/gas/sparc-solaris/addend.exp
    gas/testsuite/gas/sparc-solaris/addend.s
    gas/testsuite/gas/sparc-solaris/gas.exp
    gas/testsuite/gas/sparc-solaris/sol-cc.s
    gas/testsuite/gas/sparc-solaris/sol-gcc.s
    gas/testsuite/gas/sparc/asi.d
    gas/testsuite/gas/sparc/asi.s
    gas/testsuite/gas/sparc/membar.d
    gas/testsuite/gas/sparc/membar.s
    gas/testsuite/gas/sparc/mism-1.s
    gas/testsuite/gas/sparc/mismatch.exp
    gas/testsuite/gas/sparc/pcrel.d
    gas/testsuite/gas/sparc/pcrel.s
    gas/testsuite/gas/sparc/pcrel64.d
    gas/testsuite/gas/sparc/pcrel64.s
    gas/testsuite/gas/sparc/plt.d
    gas/testsuite/gas/sparc/plt.s
    gas/testsuite/gas/sparc/plt64.d
    gas/testsuite/gas/sparc/plt64.s
    gas/testsuite/gas/sparc/prefetch.d
    gas/testsuite/gas/sparc/prefetch.s
    gas/testsuite/gas/sparc/rdhpr.d
    gas/testsuite/gas/sparc/rdhpr.s
    gas/testsuite/gas/sparc/rdpr.d
    gas/testsuite/gas/sparc/rdpr.s
    gas/testsuite/gas/sparc/reloc64.d
    gas/testsuite/gas/sparc/reloc64.s
    gas/testsuite/gas/sparc/set64.d
    gas/testsuite/gas/sparc/set64.s
    gas/testsuite/gas/sparc/sparc.exp
    gas/testsuite/gas/sparc/splet-2.d
    gas/testsuite/gas/sparc/splet-2.s
    gas/testsuite/gas/sparc/splet.d
    gas/testsuite/gas/sparc/splet.s
    gas/testsuite/gas/sparc/synth.d
    gas/testsuite/gas/sparc/synth.s
    gas/testsuite/gas/sparc/synth64.d
    gas/testsuite/gas/sparc/synth64.s
    gas/testsuite/gas/sparc/unalign.d
    gas/testsuite/gas/sparc/unalign.s
    gas/testsuite/gas/sparc/vxworks-pic.d
    gas/testsuite/gas/sparc/vxworks-pic.s
    gas/testsuite/gas/sparc/window.d
    gas/testsuite/gas/sparc/window.s
    gas/testsuite/gas/sparc/wrhpr.d
    gas/testsuite/gas/sparc/wrhpr.s
    gas/testsuite/gas/sparc/wrpr.d
    gas/testsuite/gas/sparc/wrpr.s
    gas/testsuite/gas/sun4/addend.d
    gas/testsuite/gas/sun4/addend.exp
    gas/testsuite/gas/sun4/addend.s
    gas/testsuite/gas/symver/symver.exp
    gas/testsuite/gas/symver/symver0.d
    gas/testsuite/gas/symver/symver0.s
    gas/testsuite/gas/symver/symver1.d
    gas/testsuite/gas/symver/symver1.s
    gas/testsuite/gas/symver/symver2.l
    gas/testsuite/gas/symver/symver2.s
    gas/testsuite/gas/symver/symver3.l
    gas/testsuite/gas/symver/symver3.s
    gas/testsuite/gas/symver/symver4.l
    gas/testsuite/gas/symver/symver4.s
    gas/testsuite/gas/symver/symver5.l
    gas/testsuite/gas/symver/symver5.s
    gas/testsuite/gas/symver/symver6.l
    gas/testsuite/gas/symver/symver6.s
    gas/testsuite/gas/template
    gas/testsuite/gas/tic4x/addressing.s
    gas/testsuite/gas/tic4x/addressing_c3x.d
    gas/testsuite/gas/tic4x/addressing_c4x.d
    gas/testsuite/gas/tic4x/allopcodes.S
    gas/testsuite/gas/tic4x/data.d
    gas/testsuite/gas/tic4x/data.s
    gas/testsuite/gas/tic4x/float.d
    gas/testsuite/gas/tic4x/float.s
    gas/testsuite/gas/tic4x/opclasses.h
    gas/testsuite/gas/tic4x/opcodes.s
    gas/testsuite/gas/tic4x/opcodes_c3x.d
    gas/testsuite/gas/tic4x/opcodes_c4x.d
    gas/testsuite/gas/tic4x/opcodes_new.d
    gas/testsuite/gas/tic4x/rebuild.sh
    gas/testsuite/gas/tic4x/registers.s
    gas/testsuite/gas/tic4x/registers_c3x.d
    gas/testsuite/gas/tic4x/registers_c4x.d
    gas/testsuite/gas/tic4x/tic4x.exp
    gas/testsuite/gas/tic4x/zeros.d
    gas/testsuite/gas/tic4x/zeros.s
    gas/testsuite/gas/tic54x/address.d
    gas/testsuite/gas/tic54x/address.s
    gas/testsuite/gas/tic54x/addrfar.d
    gas/testsuite/gas/tic54x/align.d
    gas/testsuite/gas/tic54x/align.s
    gas/testsuite/gas/tic54x/all-opcodes.d
    gas/testsuite/gas/tic54x/all-opcodes.s
    gas/testsuite/gas/tic54x/asg.d
    gas/testsuite/gas/tic54x/asg.s
    gas/testsuite/gas/tic54x/cons.d
    gas/testsuite/gas/tic54x/cons.s
    gas/testsuite/gas/tic54x/consfar.d
    gas/testsuite/gas/tic54x/extaddr.d
    gas/testsuite/gas/tic54x/extaddr.s
    gas/testsuite/gas/tic54x/field.d
    gas/testsuite/gas/tic54x/field.s
    gas/testsuite/gas/tic54x/in_mlib.asm
    gas/testsuite/gas/tic54x/labels.d
    gas/testsuite/gas/tic54x/labels.inc
    gas/testsuite/gas/tic54x/labels.s
    gas/testsuite/gas/tic54x/loop.d
    gas/testsuite/gas/tic54x/loop.s
    gas/testsuite/gas/tic54x/lp.d
    gas/testsuite/gas/tic54x/lp.s
    gas/testsuite/gas/tic54x/macro.d
    gas/testsuite/gas/tic54x/macro.s
    gas/testsuite/gas/tic54x/macro1.s
    gas/testsuite/gas/tic54x/macros.lib
    gas/testsuite/gas/tic54x/math.d
    gas/testsuite/gas/tic54x/math.s
    gas/testsuite/gas/tic54x/opcodes.d
    gas/testsuite/gas/tic54x/opcodes.s
    gas/testsuite/gas/tic54x/sections.d
    gas/testsuite/gas/tic54x/sections.s
    gas/testsuite/gas/tic54x/set.d
    gas/testsuite/gas/tic54x/set.s
    gas/testsuite/gas/tic54x/struct.d
    gas/testsuite/gas/tic54x/struct.s
    gas/testsuite/gas/tic54x/subsym.d
    gas/testsuite/gas/tic54x/subsym.s
    gas/testsuite/gas/tic54x/subsym1.s
    gas/testsuite/gas/tic54x/tic54x.exp
    gas/testsuite/gas/v850/arith.s
    gas/testsuite/gas/v850/basic.exp
    gas/testsuite/gas/v850/bit.s
    gas/testsuite/gas/v850/branch.s
    gas/testsuite/gas/v850/compare.s
    gas/testsuite/gas/v850/fepsw.s
    gas/testsuite/gas/v850/hilo.s
    gas/testsuite/gas/v850/hilo2.s
    gas/testsuite/gas/v850/jumps.s
    gas/testsuite/gas/v850/logical.s
    gas/testsuite/gas/v850/mem.s
    gas/testsuite/gas/v850/misc.s
    gas/testsuite/gas/v850/move.s
    gas/testsuite/gas/v850/range.s
    gas/testsuite/gas/v850/reloc.s
    gas/testsuite/gas/v850/split-lo16.d
    gas/testsuite/gas/v850/split-lo16.s
    gas/testsuite/gas/v850/v850e1.d
    gas/testsuite/gas/v850/v850e1.s
    gas/testsuite/gas/vax/elf-rel.d
    gas/testsuite/gas/vax/elf-rel.s
    gas/testsuite/gas/vax/flonum.d
    gas/testsuite/gas/vax/flonum.s
    gas/testsuite/gas/vax/quad.s
    gas/testsuite/gas/vax/quad_elf.s
    gas/testsuite/gas/vax/vax.exp
    gas/testsuite/gas/xc16x/add.s
    gas/testsuite/gas/xc16x/add_test.s
    gas/testsuite/gas/xc16x/addb.s
    gas/testsuite/gas/xc16x/addc.s
    gas/testsuite/gas/xc16x/addcb.s
    gas/testsuite/gas/xc16x/and.s
    gas/testsuite/gas/xc16x/andb.s
    gas/testsuite/gas/xc16x/bfldl.s
    gas/testsuite/gas/xc16x/bit.s
    gas/testsuite/gas/xc16x/calla.s
    gas/testsuite/gas/xc16x/calli.s
    gas/testsuite/gas/xc16x/cmp.s
    gas/testsuite/gas/xc16x/cmp_test.s
    gas/testsuite/gas/xc16x/cmpb.s
    gas/testsuite/gas/xc16x/cmpi.s
    gas/testsuite/gas/xc16x/cpl.s
    gas/testsuite/gas/xc16x/div.s
    gas/testsuite/gas/xc16x/jmpa.s
    gas/testsuite/gas/xc16x/jmpi.s
    gas/testsuite/gas/xc16x/jmpr.s
    gas/testsuite/gas/xc16x/mov.s
    gas/testsuite/gas/xc16x/mov_test.s
    gas/testsuite/gas/xc16x/movb.s
    gas/testsuite/gas/xc16x/movbs.s
    gas/testsuite/gas/xc16x/movbz.s
    gas/testsuite/gas/xc16x/mul.s
    gas/testsuite/gas/xc16x/neg.s
    gas/testsuite/gas/xc16x/nop.s
    gas/testsuite/gas/xc16x/or.s
    gas/testsuite/gas/xc16x/orb.s
    gas/testsuite/gas/xc16x/prior.s
    gas/testsuite/gas/xc16x/pushpop.s
    gas/testsuite/gas/xc16x/ret.s
    gas/testsuite/gas/xc16x/scxt.s
    gas/testsuite/gas/xc16x/shlrol.s
    gas/testsuite/gas/xc16x/sub.s
    gas/testsuite/gas/xc16x/sub_test.s
    gas/testsuite/gas/xc16x/subb.s
    gas/testsuite/gas/xc16x/subc.s
    gas/testsuite/gas/xc16x/subcb.s
    gas/testsuite/gas/xc16x/syscontrol1.s
    gas/testsuite/gas/xc16x/syscontrol2.s
    gas/testsuite/gas/xc16x/trap.s
    gas/testsuite/gas/xc16x/xc16x.exp
    gas/testsuite/gas/xc16x/xor.s
    gas/testsuite/gas/xc16x/xorb.s
    gas/testsuite/gas/xstormy16/allinsn.d
    gas/testsuite/gas/xstormy16/allinsn.exp
    gas/testsuite/gas/xstormy16/allinsn.s
    gas/testsuite/gas/xstormy16/allinsn.sh
    gas/testsuite/gas/xstormy16/gcc.d
    gas/testsuite/gas/xstormy16/gcc.s
    gas/testsuite/gas/xstormy16/gcc.sh
    gas/testsuite/gas/xstormy16/reloc-1.d
    gas/testsuite/gas/xstormy16/reloc-1.s
    gas/testsuite/gas/xstormy16/reloc-2.d
    gas/testsuite/gas/xstormy16/reloc-2.s
    gas/testsuite/gas/xtensa/all.exp
    gas/testsuite/gas/xtensa/entry_align.s
    gas/testsuite/gas/xtensa/entry_misalign.s
    gas/testsuite/gas/xtensa/entry_misalign2.s
    gas/testsuite/gas/xtensa/j_too_far.s
    gas/testsuite/gas/xtensa/loop_align.s
    gas/testsuite/gas/xtensa/loop_misalign.s
    gas/testsuite/gas/xtensa/short_branch_offset.d
    gas/testsuite/gas/xtensa/short_branch_offset.s
    gas/testsuite/gas/z80/offset.d
    gas/testsuite/gas/z80/offset.s
    gas/testsuite/gas/z80/quotes.d
    gas/testsuite/gas/z80/quotes.s
    gas/testsuite/gas/z80/redef.d
    gas/testsuite/gas/z80/redef.s
    gas/testsuite/gas/z80/suffix.d
    gas/testsuite/gas/z80/suffix.s
    gas/testsuite/gas/z80/z80.exp
    gas/testsuite/gas/z8k/calr-backf.s
    gas/testsuite/gas/z8k/calr-forwf.s
    gas/testsuite/gas/z8k/calr.d
    gas/testsuite/gas/z8k/calr.s
    gas/testsuite/gas/z8k/ctrl-names.d
    gas/testsuite/gas/z8k/ctrl-names.s
    gas/testsuite/gas/z8k/dec.s
    gas/testsuite/gas/z8k/decbf.s
    gas/testsuite/gas/z8k/decf.s
    gas/testsuite/gas/z8k/djnz-backf.s
    gas/testsuite/gas/z8k/djnz-backf2.s
    gas/testsuite/gas/z8k/djnz.d
    gas/testsuite/gas/z8k/djnz.s
    gas/testsuite/gas/z8k/eidi.s
    gas/testsuite/gas/z8k/eidif.s
    gas/testsuite/gas/z8k/inc.s
    gas/testsuite/gas/z8k/incbf.s
    gas/testsuite/gas/z8k/incf.s
    gas/testsuite/gas/z8k/inout.d
    gas/testsuite/gas/z8k/inout.s
    gas/testsuite/gas/z8k/jmp-cc.d
    gas/testsuite/gas/z8k/jmp-cc.s
    gas/testsuite/gas/z8k/jr-back.d
    gas/testsuite/gas/z8k/jr-back.s
    gas/testsuite/gas/z8k/jr-backf.s
    gas/testsuite/gas/z8k/jr-forw.d
    gas/testsuite/gas/z8k/jr-forw.s
    gas/testsuite/gas/z8k/jr-forwf.s
    gas/testsuite/gas/z8k/ldk.s
    gas/testsuite/gas/z8k/ldkf.s
    gas/testsuite/gas/z8k/ret-cc.d
    gas/testsuite/gas/z8k/ret-cc.s
    gas/testsuite/gas/z8k/z8k.exp
    gas/testsuite/lib/doboth
    gas/testsuite/lib/doobjcmp
    gas/testsuite/lib/dostriptest
    gas/testsuite/lib/dotest
    gas/testsuite/lib/dounsreloc
    gas/testsuite/lib/dounssym
    gas/testsuite/lib/gas-defs.exp
    gas/testsuite/lib/gas-dg.exp
    gas/testsuite/lib/run
    gas/write.c
    gas/write.h
    gdb/CONTRIBUTE
    gdb/COPYING
    gdb/ChangeLog
    gdb/ChangeLog-1990
    gdb/ChangeLog-1991
    gdb/ChangeLog-1992
    gdb/ChangeLog-1993
    gdb/ChangeLog-1994
    gdb/ChangeLog-1995
    gdb/ChangeLog-1996
    gdb/ChangeLog-1997
    gdb/ChangeLog-1998
    gdb/ChangeLog-1999
    gdb/ChangeLog-2000
    gdb/ChangeLog-2001
    gdb/ChangeLog-2002
    gdb/ChangeLog-2003
    gdb/ChangeLog-2004
    gdb/ChangeLog-2005
    gdb/ChangeLog-3.x
    gdb/MAINTAINERS
    gdb/Makefile.in
    gdb/NEWS
    gdb/PROBLEMS
    gdb/README
    gdb/abug-rom.c
    gdb/acinclude.m4
    gdb/aclocal.m4
    gdb/ada-exp.y
    gdb/ada-lang.c
    gdb/ada-lang.h
    gdb/ada-lex.l
    gdb/ada-typeprint.c
    gdb/ada-valprint.c
    gdb/aix-thread.c
    gdb/alpha-linux-nat.c
    gdb/alpha-linux-tdep.c
    gdb/alpha-mdebug-tdep.c
    gdb/alpha-nat.c
    gdb/alpha-osf1-tdep.c
    gdb/alpha-tdep.c
    gdb/alpha-tdep.h
    gdb/alphabsd-nat.c
    gdb/alphabsd-tdep.c
    gdb/alphabsd-tdep.h
    gdb/alphafbsd-tdep.c
    gdb/alphanbsd-tdep.c
    gdb/alphaobsd-tdep.c
    gdb/amd64-linux-nat.c
    gdb/amd64-linux-tdep.c
    gdb/amd64-nat.c
    gdb/amd64-nat.h
    gdb/amd64-sol2-tdep.c
    gdb/amd64-tdep.c
    gdb/amd64-tdep.h
    gdb/amd64bsd-nat.c
    gdb/amd64fbsd-nat.c
    gdb/amd64fbsd-tdep.c
    gdb/amd64nbsd-nat.c
    gdb/amd64nbsd-tdep.c
    gdb/amd64obsd-nat.c
    gdb/amd64obsd-tdep.c
    gdb/annotate.c
    gdb/annotate.h
    gdb/arch-utils.c
    gdb/arch-utils.h
    gdb/arm-linux-nat.c
    gdb/arm-linux-tdep.c
    gdb/arm-linux-tdep.h
    gdb/arm-tdep.c
    gdb/arm-tdep.h
    gdb/armnbsd-nat.c
    gdb/armnbsd-tdep.c
    gdb/armobsd-tdep.c
    gdb/auxv.c
    gdb/auxv.h
    gdb/avr-tdep.c
    gdb/ax-gdb.c
    gdb/ax-gdb.h
    gdb/ax-general.c
    gdb/ax.h
    gdb/bcache.c
    gdb/bcache.h
    gdb/bfd-target.c
    gdb/bfd-target.h
    gdb/block.c
    gdb/block.h
    gdb/blockframe.c
    gdb/breakpoint.c
    gdb/breakpoint.h
    gdb/bsd-kvm.c
    gdb/bsd-kvm.h
    gdb/bsd-uthread.c
    gdb/bsd-uthread.h
    gdb/buildsym.c
    gdb/buildsym.h
    gdb/c-exp.y
    gdb/c-lang.c
    gdb/c-lang.h
    gdb/c-typeprint.c
    gdb/c-valprint.c
    gdb/call-cmds.h
    gdb/charset.c
    gdb/charset.h
    gdb/cli-out.c
    gdb/cli-out.h
    gdb/cli/cli-cmds.c
    gdb/cli/cli-cmds.h
    gdb/cli/cli-decode.c
    gdb/cli/cli-decode.h
    gdb/cli/cli-dump.c
    gdb/cli/cli-dump.h
    gdb/cli/cli-interp.c
    gdb/cli/cli-logging.c
    gdb/cli/cli-script.c
    gdb/cli/cli-script.h
    gdb/cli/cli-setshow.c
    gdb/cli/cli-setshow.h
    gdb/cli/cli-utils.c
    gdb/cli/cli-utils.h
    gdb/coff-pe-read.c
    gdb/coff-pe-read.h
    gdb/coff-solib.c
    gdb/coff-solib.h
    gdb/coffread.c
    gdb/command.h
    gdb/complaints.c
    gdb/complaints.h
    gdb/completer.c
    gdb/completer.h
    gdb/config.in
    gdb/config/alpha/alpha-linux.mh
    gdb/config/alpha/alpha-linux.mt
    gdb/config/alpha/alpha-osf1.mh
    gdb/config/alpha/alpha-osf1.mt
    gdb/config/alpha/alpha-osf2.mh
    gdb/config/alpha/alpha-osf3.mh
    gdb/config/alpha/alpha.mt
    gdb/config/alpha/fbsd.mh
    gdb/config/alpha/fbsd.mt
    gdb/config/alpha/nbsd.mh
    gdb/config/alpha/nbsd.mt
    gdb/config/alpha/nm-linux.h
    gdb/config/alpha/nm-osf.h
    gdb/config/alpha/nm-osf2.h
    gdb/config/alpha/nm-osf3.h
    gdb/config/alpha/obsd.mt
    gdb/config/alpha/tm-alpha.h
    gdb/config/alpha/tm-alphalinux.h
    gdb/config/arm/embed.mt
    gdb/config/arm/linux.mh
    gdb/config/arm/linux.mt
    gdb/config/arm/nbsd.mt
    gdb/config/arm/nbsdaout.mh
    gdb/config/arm/nbsdelf.mh
    gdb/config/arm/nm-linux.h
    gdb/config/arm/nm-nbsdaout.h
    gdb/config/arm/obsd.mt
    gdb/config/arm/tm-arm.h
    gdb/config/arm/tm-embed.h
    gdb/config/arm/tm-linux.h
    gdb/config/arm/tm-wince.h
    gdb/config/arm/wince.mt
    gdb/config/avr/avr.mt
    gdb/config/cris/cris.mt
    gdb/config/d10v/d10v.mt
    gdb/config/djgpp/README
    gdb/config/djgpp/config.sed
    gdb/config/djgpp/djcheck.sh
    gdb/config/djgpp/djconfig.sh
    gdb/config/djgpp/fnchange.lst
    gdb/config/frv/frv.mt
    gdb/config/frv/tm-frv.h
    gdb/config/h8300/h8300.mt
    gdb/config/i386/cygwin.mh
    gdb/config/i386/cygwin.mt
    gdb/config/i386/fbsd.mh
    gdb/config/i386/fbsd.mt
    gdb/config/i386/fbsd64.mh
    gdb/config/i386/fbsd64.mt
    gdb/config/i386/go32.mh
    gdb/config/i386/i386.mt
    gdb/config/i386/i386gnu.mh
    gdb/config/i386/i386gnu.mt
    gdb/config/i386/i386sco.mh
    gdb/config/i386/i386sco4.mh
    gdb/config/i386/i386sco5.mh
    gdb/config/i386/i386sol2.mh
    gdb/config/i386/i386sol2.mt
    gdb/config/i386/i386v.mh
    gdb/config/i386/i386v4.mh
    gdb/config/i386/i386v42mp.mh
    gdb/config/i386/linux.mh
    gdb/config/i386/linux.mt
    gdb/config/i386/linux64.mh
    gdb/config/i386/linux64.mt
    gdb/config/i386/nbsd.mt
    gdb/config/i386/nbsd64.mh
    gdb/config/i386/nbsd64.mt
    gdb/config/i386/nbsdaout.mh
    gdb/config/i386/nbsdelf.mh
    gdb/config/i386/ncr3000.mh
    gdb/config/i386/ncr3000.mt
    gdb/config/i386/nm-cygwin.h
    gdb/config/i386/nm-fbsd.h
    gdb/config/i386/nm-go32.h
    gdb/config/i386/nm-i386.h
    gdb/config/i386/nm-i386gnu.h
    gdb/config/i386/nm-i386sco.h
    gdb/config/i386/nm-i386sco4.h
    gdb/config/i386/nm-i386sco5.h
    gdb/config/i386/nm-i386sol2.h
    gdb/config/i386/nm-i386v.h
    gdb/config/i386/nm-i386v4.h
    gdb/config/i386/nm-i386v42mp.h
    gdb/config/i386/nm-linux.h
    gdb/config/i386/nm-linux64.h
    gdb/config/i386/nto.mh
    gdb/config/i386/nto.mt
    gdb/config/i386/obsd.mh
    gdb/config/i386/obsd.mt
    gdb/config/i386/obsd64.mh
    gdb/config/i386/obsd64.mt
    gdb/config/i386/obsdaout.mh
    gdb/config/i386/sol2-64.mh
    gdb/config/i386/sol2-64.mt
    gdb/config/i386/tm-i386sol2.h
    gdb/config/i386/tm-linux.h
    gdb/config/i386/tm-nto.h
    gdb/config/ia64/ia64.mt
    gdb/config/ia64/linux.mh
    gdb/config/ia64/linux.mt
    gdb/config/ia64/nm-linux.h
    gdb/config/ia64/tm-linux.h
    gdb/config/iq2000/iq2000.mt
    gdb/config/m32c/m32c.mt
    gdb/config/m32r/linux.mh
    gdb/config/m32r/linux.mt
    gdb/config/m32r/m32r.mt
    gdb/config/m32r/nm-linux.h
    gdb/config/m68hc11/m68hc11.mt
    gdb/config/m68k/cisco.mt
    gdb/config/m68k/linux.mh
    gdb/config/m68k/linux.mt
    gdb/config/m68k/monitor.mt
    gdb/config/m68k/nbsd.mt
    gdb/config/m68k/nbsdaout.mh
    gdb/config/m68k/nbsdelf.mh
    gdb/config/m68k/nm-linux.h
    gdb/config/m68k/obsd.mh
    gdb/config/m68k/obsd.mt
    gdb/config/m68k/os68k.mt
    gdb/config/m68k/st2000.mt
    gdb/config/m68k/tm-cisco.h
    gdb/config/m68k/tm-monitor.h
    gdb/config/m68k/tm-os68k.h
    gdb/config/m88k/obsd.mh
    gdb/config/m88k/obsd.mt
    gdb/config/mips/embed.mt
    gdb/config/mips/irix5.mh
    gdb/config/mips/irix5.mt
    gdb/config/mips/irix6.mh
    gdb/config/mips/irix6.mt
    gdb/config/mips/linux.mh
    gdb/config/mips/linux.mt
    gdb/config/mips/nbsd.mh
    gdb/config/mips/nbsd.mt
    gdb/config/mips/nm-irix5.h
    gdb/config/mips/nm-linux.h
    gdb/config/mips/obsd64.mh
    gdb/config/mips/obsd64.mt
    gdb/config/mips/tm-linux.h
    gdb/config/mips/tm-nbsd.h
    gdb/config/mips/tm-wince.h
    gdb/config/mips/wince.mt
    gdb/config/mn10300/linux.mt
    gdb/config/mn10300/mn10300.mt
    gdb/config/mt/mt.mt
    gdb/config/nm-linux.h
    gdb/config/nm-lynx.h
    gdb/config/nm-nbsd.h
    gdb/config/nm-nbsdaout.h
    gdb/config/pa/hppa.mt
    gdb/config/pa/hppa64.mt
    gdb/config/pa/hppahpux.mt
    gdb/config/pa/hpux.mh
    gdb/config/pa/linux.mh
    gdb/config/pa/linux.mt
    gdb/config/pa/nm-linux.h
    gdb/config/pa/obsd.mh
    gdb/config/pa/obsd.mt
    gdb/config/pa/tm-hppa.h
    gdb/config/pa/tm-hppah.h
    gdb/config/pa/tm-linux.h
    gdb/config/powerpc/aix.mh
    gdb/config/powerpc/aix.mt
    gdb/config/powerpc/linux.mh
    gdb/config/powerpc/linux.mt
    gdb/config/powerpc/nbsd.mh
    gdb/config/powerpc/nbsd.mt
    gdb/config/powerpc/nm-aix.h
    gdb/config/powerpc/nm-linux.h
    gdb/config/powerpc/nm-ppc64-linux.h
    gdb/config/powerpc/obsd.mh
    gdb/config/powerpc/obsd.mt
    gdb/config/powerpc/ppc-eabi.mt
    gdb/config/powerpc/ppc-sim.mt
    gdb/config/powerpc/ppc64-linux.mh
    gdb/config/powerpc/tm-linux.h
    gdb/config/powerpc/tm-ppc-eabi.h
    gdb/config/rs6000/aix4.mh
    gdb/config/rs6000/aix4.mt
    gdb/config/rs6000/nm-rs6000.h
    gdb/config/rs6000/rs6000.mh
    gdb/config/rs6000/rs6000.mt
    gdb/config/rs6000/rs6000lynx.mh
    gdb/config/rs6000/rs6000lynx.mt
    gdb/config/rs6000/tm-rs6000.h
    gdb/config/rs6000/tm-rs6000ly.h
    gdb/config/s390/nm-linux.h
    gdb/config/s390/s390.mh
    gdb/config/s390/s390.mt
    gdb/config/sh/embed.mt
    gdb/config/sh/linux.mt
    gdb/config/sh/nbsd.mh
    gdb/config/sh/nbsd.mt
    gdb/config/sh/sh64.mt
    gdb/config/sh/tm-linux.h
    gdb/config/sh/tm-nbsd.h
    gdb/config/sh/tm-sh.h
    gdb/config/sh/tm-wince.h
    gdb/config/sh/wince.mt
    gdb/config/sparc/fbsd.mh
    gdb/config/sparc/fbsd.mt
    gdb/config/sparc/linux.mh
    gdb/config/sparc/linux.mt
    gdb/config/sparc/linux64.mh
    gdb/config/sparc/linux64.mt
    gdb/config/sparc/nbsd.mt
    gdb/config/sparc/nbsd64.mh
    gdb/config/sparc/nbsd64.mt
    gdb/config/sparc/nbsdaout.mh
    gdb/config/sparc/nbsdelf.mh
    gdb/config/sparc/nm-linux.h
    gdb/config/sparc/nm-sol2.h
    gdb/config/sparc/obsd.mt
    gdb/config/sparc/obsd64.mt
    gdb/config/sparc/sol2-64.mt
    gdb/config/sparc/sol2.mh
    gdb/config/sparc/sol2.mt
    gdb/config/sparc/sparc.mt
    gdb/config/sparc/sparc64.mt
    gdb/config/sparc/tm-sol2.h
    gdb/config/tm-linux.h
    gdb/config/tm-nto.h
    gdb/config/v850/v850.mt
    gdb/config/vax/nbsd.mt
    gdb/config/vax/nbsdaout.mh
    gdb/config/vax/nbsdelf.mh
    gdb/config/vax/nm-vax.h
    gdb/config/vax/obsd.mh
    gdb/config/vax/obsd.mt
    gdb/config/vax/vax.mh
    gdb/config/vax/vax.mt
    gdb/config/xstormy16/xstormy16.mt
    gdb/configure
    gdb/configure.ac
    gdb/configure.host
    gdb/configure.tgt
    gdb/copying.awk
    gdb/copying.c
    gdb/core-aout.c
    gdb/core-regset.c
    gdb/corefile.c
    gdb/corelow.c
    gdb/cp-abi.c
    gdb/cp-abi.h
    gdb/cp-name-parser.y
    gdb/cp-namespace.c
    gdb/cp-support.c
    gdb/cp-support.h
    gdb/cp-valprint.c
    gdb/cpu32bug-rom.c
    gdb/cris-tdep.c
    gdb/d10v-tdep.c
    gdb/dbug-rom.c
    gdb/dbxread.c
    gdb/dcache.c
    gdb/dcache.h
    gdb/defs.h
    gdb/demangle.c
    gdb/dictionary.c
    gdb/dictionary.h
    gdb/dink32-rom.c
    gdb/disasm.c
    gdb/disasm.h
    gdb/doc/ChangeLog
    gdb/doc/LRS
    gdb/doc/Makefile.in
    gdb/doc/a4rc.sed
    gdb/doc/agentexpr.texi
    gdb/doc/all-cfg.texi
    gdb/doc/annotate.texinfo
    gdb/doc/configure
    gdb/doc/configure.ac
    gdb/doc/fdl.texi
    gdb/doc/gdb.texinfo
    gdb/doc/gdbint.texinfo
    gdb/doc/gpl.texi
    gdb/doc/lpsrc.sed
    gdb/doc/observer.texi
    gdb/doc/psrc.sed
    gdb/doc/refcard.tex
    gdb/doc/stabs.texinfo
    gdb/doublest.c
    gdb/doublest.h
    gdb/dsrec.c
    gdb/dummy-frame.c
    gdb/dummy-frame.h
    gdb/dve3900-rom.c
    gdb/dwarf2-frame.c
    gdb/dwarf2-frame.h
    gdb/dwarf2expr.c
    gdb/dwarf2expr.h
    gdb/dwarf2loc.c
    gdb/dwarf2loc.h
    gdb/dwarf2read.c
    gdb/dwarfread.c
    gdb/elfread.c
    gdb/environ.c
    gdb/environ.h
    gdb/eval.c
    gdb/event-loop.c
    gdb/event-loop.h
    gdb/event-top.c
    gdb/event-top.h
    gdb/exc_request.defs
    gdb/exceptions.c
    gdb/exceptions.h
    gdb/exec.c
    gdb/exec.h
    gdb/expprint.c
    gdb/expression.h
    gdb/f-exp.y
    gdb/f-lang.c
    gdb/f-lang.h
    gdb/f-typeprint.c
    gdb/f-valprint.c
    gdb/fbsd-nat.c
    gdb/fbsd-nat.h
    gdb/findvar.c
    gdb/fork-child.c
    gdb/frame-base.c
    gdb/frame-base.h
    gdb/frame-unwind.c
    gdb/frame-unwind.h
    gdb/frame.c
    gdb/frame.h
    gdb/frv-linux-tdep.c
    gdb/frv-tdep.c
    gdb/frv-tdep.h
    gdb/gcore.c
    gdb/gdb-events.c
    gdb/gdb-events.h
    gdb/gdb-events.sh
    gdb/gdb-stabs.h
    gdb/gdb.1
    gdb/gdb.c
    gdb/gdb.gdb
    gdb/gdb.h
    gdb/gdb_assert.h
    gdb/gdb_curses.h
    gdb/gdb_dirent.h
    gdb/gdb_gcore.sh
    gdb/gdb_indent.sh
    gdb/gdb_locale.h
    gdb/gdb_mbuild.sh
    gdb/gdb_obstack.h
    gdb/gdb_proc_service.h
    gdb/gdb_ptrace.h
    gdb/gdb_regex.h
    gdb/gdb_select.h
    gdb/gdb_stat.h
    gdb/gdb_string.h
    gdb/gdb_thread_db.h
    gdb/gdb_vfork.h
    gdb/gdb_wait.h
    gdb/gdbarch.c
    gdb/gdbarch.h
    gdb/gdbarch.sh
    gdb/gdbcmd.h
    gdb/gdbcore.h
    gdb/gdbinit.in
    gdb/gdbserver/ChangeLog
    gdb/gdbserver/Makefile.in
    gdb/gdbserver/README
    gdb/gdbserver/acinclude.m4
    gdb/gdbserver/aclocal.m4
    gdb/gdbserver/config.in
    gdb/gdbserver/configure
    gdb/gdbserver/configure.ac
    gdb/gdbserver/configure.srv
    gdb/gdbserver/gdb_proc_service.h
    gdb/gdbserver/gdbreplay.c
    gdb/gdbserver/gdbserver.1
    gdb/gdbserver/i387-fp.c
    gdb/gdbserver/i387-fp.h
    gdb/gdbserver/inferiors.c
    gdb/gdbserver/linux-arm-low.c
    gdb/gdbserver/linux-cris-low.c
    gdb/gdbserver/linux-crisv32-low.c
    gdb/gdbserver/linux-i386-low.c
    gdb/gdbserver/linux-ia64-low.c
    gdb/gdbserver/linux-low.c
    gdb/gdbserver/linux-low.h
    gdb/gdbserver/linux-m32r-low.c
    gdb/gdbserver/linux-m68k-low.c
    gdb/gdbserver/linux-mips-low.c
    gdb/gdbserver/linux-ppc-low.c
    gdb/gdbserver/linux-ppc64-low.c
    gdb/gdbserver/linux-s390-low.c
    gdb/gdbserver/linux-sh-low.c
    gdb/gdbserver/linux-x86-64-low.c
    gdb/gdbserver/mem-break.c
    gdb/gdbserver/mem-break.h
    gdb/gdbserver/proc-service.c
    gdb/gdbserver/regcache.c
    gdb/gdbserver/regcache.h
    gdb/gdbserver/remote-utils.c
    gdb/gdbserver/server.c
    gdb/gdbserver/server.h
    gdb/gdbserver/target.c
    gdb/gdbserver/target.h
    gdb/gdbserver/terminal.h
    gdb/gdbserver/thread-db.c
    gdb/gdbserver/utils.c
    gdb/gdbserver/win32-i386-low.c
    gdb/gdbthread.h
    gdb/gdbtypes.c
    gdb/gdbtypes.h
    gdb/glibc-tdep.c
    gdb/glibc-tdep.h
    gdb/gnu-nat.c
    gdb/gnu-nat.h
    gdb/gnu-v2-abi.c
    gdb/gnu-v2-abi.h
    gdb/gnu-v3-abi.c
    gdb/go32-nat.c
    gdb/gregset.h
    gdb/h8300-tdep.c
    gdb/hpacc-abi.c
    gdb/hppa-hpux-nat.c
    gdb/hppa-hpux-tdep.c
    gdb/hppa-linux-nat.c
    gdb/hppa-linux-tdep.c
    gdb/hppa-tdep.c
    gdb/hppa-tdep.h
    gdb/hppabsd-nat.c
    gdb/hppabsd-tdep.c
    gdb/hpread.c
    gdb/hpux-thread.c
    gdb/i386-cygwin-tdep.c
    gdb/i386-linux-nat.c
    gdb/i386-linux-tdep.c
    gdb/i386-linux-tdep.h
    gdb/i386-nat.c
    gdb/i386-nto-tdep.c
    gdb/i386-sol2-nat.c
    gdb/i386-sol2-tdep.c
    gdb/i386-stub.c
    gdb/i386-tdep.c
    gdb/i386-tdep.h
    gdb/i386bsd-nat.c
    gdb/i386bsd-nat.h
    gdb/i386bsd-tdep.c
    gdb/i386fbsd-nat.c
    gdb/i386fbsd-tdep.c
    gdb/i386gnu-nat.c
    gdb/i386gnu-tdep.c
    gdb/i386nbsd-nat.c
    gdb/i386nbsd-tdep.c
    gdb/i386obsd-nat.c
    gdb/i386obsd-tdep.c
    gdb/i386v-nat.c
    gdb/i386v4-nat.c
    gdb/i387-tdep.c
    gdb/i387-tdep.h
    gdb/ia64-linux-nat.c
    gdb/ia64-linux-tdep.c
    gdb/ia64-tdep.c
    gdb/ia64-tdep.h
    gdb/inf-child.c
    gdb/inf-child.h
    gdb/inf-loop.c
    gdb/inf-loop.h
    gdb/inf-ptrace.c
    gdb/inf-ptrace.h
    gdb/inf-ttrace.c
    gdb/inf-ttrace.h
    gdb/infcall.c
    gdb/infcall.h
    gdb/infcmd.c
    gdb/inferior.h
    gdb/inflow.c
    gdb/inflow.h
    gdb/infptrace.c
    gdb/infrun.c
    gdb/inftarg.c
    gdb/interps.c
    gdb/interps.h
    gdb/iq2000-tdep.c
    gdb/irix5-nat.c
    gdb/jv-exp.y
    gdb/jv-lang.c
    gdb/jv-lang.h
    gdb/jv-typeprint.c
    gdb/jv-valprint.c
    gdb/language.c
    gdb/language.h
    gdb/libunwind-frame.c
    gdb/libunwind-frame.h
    gdb/linespec.c
    gdb/linespec.h
    gdb/linux-fork.c
    gdb/linux-fork.h
    gdb/linux-nat.c
    gdb/linux-nat.h
    gdb/linux-thread-db.c
    gdb/lynx-nat.c
    gdb/m2-exp.y
    gdb/m2-lang.c
    gdb/m2-lang.h
    gdb/m2-typeprint.c
    gdb/m2-valprint.c
    gdb/m32c-tdep.c
    gdb/m32r-linux-nat.c
    gdb/m32r-linux-tdep.c
    gdb/m32r-rom.c
    gdb/m32r-stub.c
    gdb/m32r-tdep.c
    gdb/m32r-tdep.h
    gdb/m68hc11-tdep.c
    gdb/m68k-stub.c
    gdb/m68k-tdep.c
    gdb/m68k-tdep.h
    gdb/m68kbsd-nat.c
    gdb/m68kbsd-tdep.c
    gdb/m68klinux-nat.c
    gdb/m68klinux-tdep.c
    gdb/m88k-tdep.c
    gdb/m88k-tdep.h
    gdb/m88kbsd-nat.c
    gdb/macrocmd.c
    gdb/macroexp.c
    gdb/macroexp.h
    gdb/macroscope.c
    gdb/macroscope.h
    gdb/macrotab.c
    gdb/macrotab.h
    gdb/main.c
    gdb/main.h
    gdb/maint.c
    gdb/mdebugread.c
    gdb/mdebugread.h
    gdb/mem-break.c
    gdb/memattr.c
    gdb/memattr.h
    gdb/mi/ChangeLog-1999-2003
    gdb/mi/gdb-mi.el
    gdb/mi/mi-cmd-break.c
    gdb/mi/mi-cmd-disas.c
    gdb/mi/mi-cmd-env.c
    gdb/mi/mi-cmd-file.c
    gdb/mi/mi-cmd-stack.c
    gdb/mi/mi-cmd-var.c
    gdb/mi/mi-cmds.c
    gdb/mi/mi-cmds.h
    gdb/mi/mi-common.c
    gdb/mi/mi-common.h
    gdb/mi/mi-console.c
    gdb/mi/mi-console.h
    gdb/mi/mi-getopt.c
    gdb/mi/mi-getopt.h
    gdb/mi/mi-interp.c
    gdb/mi/mi-main.c
    gdb/mi/mi-main.h
    gdb/mi/mi-out.c
    gdb/mi/mi-out.h
    gdb/mi/mi-parse.c
    gdb/mi/mi-parse.h
    gdb/mi/mi-symbol-cmds.c
    gdb/mingw-hdep.c
    gdb/minsyms.c
    gdb/mips-irix-tdep.c
    gdb/mips-linux-nat.c
    gdb/mips-linux-tdep.c
    gdb/mips-linux-tdep.h
    gdb/mips-mdebug-tdep.c
    gdb/mips-mdebug-tdep.h
    gdb/mips-tdep.c
    gdb/mips-tdep.h
    gdb/mips64obsd-nat.c
    gdb/mips64obsd-tdep.c
    gdb/mipsnbsd-nat.c
    gdb/mipsnbsd-tdep.c
    gdb/mipsnbsd-tdep.h
    gdb/mipsread.c
    gdb/mipsv4-nat.c
    gdb/mn10300-linux-tdep.c
    gdb/mn10300-tdep.c
    gdb/mn10300-tdep.h
    gdb/monitor.c
    gdb/monitor.h
    gdb/msg.defs
    gdb/msg_reply.defs
    gdb/mt-tdep.c
    gdb/nbsd-tdep.c
    gdb/nbsd-tdep.h
    gdb/nlmread.c
    gdb/notify.defs
    gdb/nto-procfs.c
    gdb/nto-tdep.c
    gdb/nto-tdep.h
    gdb/objc-exp.y
    gdb/objc-lang.c
    gdb/objc-lang.h
    gdb/objfiles.c
    gdb/objfiles.h
    gdb/obsd-tdep.c
    gdb/obsd-tdep.h
    gdb/observer.c
    gdb/observer.sh
    gdb/ocd.c
    gdb/ocd.h
    gdb/osabi.c
    gdb/osabi.h
    gdb/osf-share/AT386/cma_thread_io.h
    gdb/osf-share/HP800/cma_thread_io.h
    gdb/osf-share/README
    gdb/osf-share/RIOS/cma_thread_io.h
    gdb/osf-share/cma_attr.h
    gdb/osf-share/cma_deb_core.h
    gdb/osf-share/cma_debug_client.h
    gdb/osf-share/cma_errors.h
    gdb/osf-share/cma_handle.h
    gdb/osf-share/cma_init.h
    gdb/osf-share/cma_list.h
    gdb/osf-share/cma_mutex.h
    gdb/osf-share/cma_sched.h
    gdb/osf-share/cma_semaphore_defs.h
    gdb/osf-share/cma_sequence.h
    gdb/osf-share/cma_stack.h
    gdb/osf-share/cma_stack_int.h
    gdb/osf-share/cma_tcb_defs.h
    gdb/osf-share/cma_util.h
    gdb/p-exp.y
    gdb/p-lang.c
    gdb/p-lang.h
    gdb/p-typeprint.c
    gdb/p-valprint.c
    gdb/parse.c
    gdb/parser-defs.h
    gdb/po/gdbtext
    gdb/posix-hdep.c
    gdb/ppc-bdm.c
    gdb/ppc-linux-nat.c
    gdb/ppc-linux-tdep.c
    gdb/ppc-sysv-tdep.c
    gdb/ppc-tdep.h
    gdb/ppcbug-rom.c
    gdb/ppcnbsd-nat.c
    gdb/ppcnbsd-tdep.c
    gdb/ppcnbsd-tdep.h
    gdb/ppcobsd-nat.c
    gdb/ppcobsd-tdep.c
    gdb/ppcobsd-tdep.h
    gdb/printcmd.c
    gdb/proc-api.c
    gdb/proc-events.c
    gdb/proc-flags.c
    gdb/proc-service.c
    gdb/proc-utils.h
    gdb/proc-why.c
    gdb/process_reply.defs
    gdb/procfs.c
    gdb/prologue-value.c
    gdb/prologue-value.h
    gdb/regcache.c
    gdb/regcache.h
    gdb/regformats/reg-arm.dat
    gdb/regformats/reg-cris.dat
    gdb/regformats/reg-crisv32.dat
    gdb/regformats/reg-i386-linux.dat
    gdb/regformats/reg-i386.dat
    gdb/regformats/reg-ia64.dat
    gdb/regformats/reg-m32r.dat
    gdb/regformats/reg-m68k.dat
    gdb/regformats/reg-mips.dat
    gdb/regformats/reg-ppc.dat
    gdb/regformats/reg-ppc64.dat
    gdb/regformats/reg-s390.dat
    gdb/regformats/reg-s390x.dat
    gdb/regformats/reg-sh.dat
    gdb/regformats/reg-x86-64.dat
    gdb/regformats/regdat.sh
    gdb/regformats/regdef.h
    gdb/reggroups.c
    gdb/reggroups.h
    gdb/regset.c
    gdb/regset.h
    gdb/remote-e7000.c
    gdb/remote-est.c
    gdb/remote-fileio.c
    gdb/remote-fileio.h
    gdb/remote-hms.c
    gdb/remote-m32r-sdi.c
    gdb/remote-mips.c
    gdb/remote-sds.c
    gdb/remote-sim.c
    gdb/remote-st.c
    gdb/remote-utils.c
    gdb/remote-utils.h
    gdb/remote.c
    gdb/remote.h
    gdb/reply_mig_hack.awk
    gdb/rom68k-rom.c
    gdb/rs6000-aix-tdep.c
    gdb/rs6000-nat.c
    gdb/rs6000-tdep.c
    gdb/rs6000-tdep.h
    gdb/s390-nat.c
    gdb/s390-tdep.c
    gdb/s390-tdep.h
    gdb/scm-exp.c
    gdb/scm-lang.c
    gdb/scm-lang.h
    gdb/scm-tags.h
    gdb/scm-valprint.c
    gdb/sentinel-frame.c
    gdb/sentinel-frame.h
    gdb/ser-base.c
    gdb/ser-base.h
    gdb/ser-e7kpc.c
    gdb/ser-go32.c
    gdb/ser-mingw.c
    gdb/ser-pipe.c
    gdb/ser-tcp.c
    gdb/ser-tcp.h
    gdb/ser-unix.c
    gdb/ser-unix.h
    gdb/serial.c
    gdb/serial.h
    gdb/sh-linux-tdep.c
    gdb/sh-stub.c
    gdb/sh-tdep.c
    gdb/sh-tdep.h
    gdb/sh3-rom.c
    gdb/sh64-tdep.c
    gdb/shnbsd-nat.c
    gdb/shnbsd-tdep.c
    gdb/shnbsd-tdep.h
    gdb/signals/signals.c
    gdb/sim-regno.h
    gdb/sol-thread.c
    gdb/sol2-tdep.c
    gdb/sol2-tdep.h
    gdb/solib-aix5.c
    gdb/solib-frv.c
    gdb/solib-irix.c
    gdb/solib-legacy.c
    gdb/solib-null.c
    gdb/solib-osf.c
    gdb/solib-pa64.c
    gdb/solib-pa64.h
    gdb/solib-som.c
    gdb/solib-som.h
    gdb/solib-sunos.c
    gdb/solib-svr4.c
    gdb/solib-svr4.h
    gdb/solib.c
    gdb/solib.h
    gdb/solist.h
    gdb/somread.c
    gdb/source.c
    gdb/source.h
    gdb/sparc-linux-nat.c
    gdb/sparc-linux-tdep.c
    gdb/sparc-nat.c
    gdb/sparc-nat.h
    gdb/sparc-sol2-nat.c
    gdb/sparc-sol2-tdep.c
    gdb/sparc-stub.c
    gdb/sparc-tdep.c
    gdb/sparc-tdep.h
    gdb/sparc64-linux-nat.c
    gdb/sparc64-linux-tdep.c
    gdb/sparc64-nat.c
    gdb/sparc64-sol2-tdep.c
    gdb/sparc64-tdep.c
    gdb/sparc64-tdep.h
    gdb/sparc64fbsd-nat.c
    gdb/sparc64fbsd-tdep.c
    gdb/sparc64nbsd-nat.c
    gdb/sparc64nbsd-tdep.c
    gdb/sparc64obsd-tdep.c
    gdb/sparcnbsd-nat.c
    gdb/sparcnbsd-tdep.c
    gdb/sparcobsd-tdep.c
    gdb/srec.h
    gdb/stabsread.c
    gdb/stabsread.h
    gdb/stack.c
    gdb/stack.h
    gdb/std-regs.c
    gdb/stop-gdb.c
    gdb/symfile-mem.c
    gdb/symfile.c
    gdb/symfile.h
    gdb/symmisc.c
    gdb/symtab.c
    gdb/symtab.h
    gdb/target.c
    gdb/target.h
    gdb/terminal.h
    gdb/testsuite/.gdbinit
    gdb/testsuite/ChangeLog
    gdb/testsuite/Makefile.in
    gdb/testsuite/TODO
    gdb/testsuite/aclocal.m4
    gdb/testsuite/config/abug.exp
    gdb/testsuite/config/arm-ice.exp
    gdb/testsuite/config/cfdbug.exp
    gdb/testsuite/config/cpu32bug.exp
    gdb/testsuite/config/cygmon.exp
    gdb/testsuite/config/d10v.exp
    gdb/testsuite/config/dve.exp
    gdb/testsuite/config/est.exp
    gdb/testsuite/config/gdbserver.exp
    gdb/testsuite/config/h8300.exp
    gdb/testsuite/config/hmsirom.exp
    gdb/testsuite/config/i386-bozo.exp
    gdb/testsuite/config/i960.exp
    gdb/testsuite/config/m32r-stub.exp
    gdb/testsuite/config/m32r.exp
    gdb/testsuite/config/m68k-emc.exp
    gdb/testsuite/config/mips-idt.exp
    gdb/testsuite/config/mips.exp
    gdb/testsuite/config/mn10300-eval.exp
    gdb/testsuite/config/monitor.exp
    gdb/testsuite/config/netware.exp
    gdb/testsuite/config/nind.exp
    gdb/testsuite/config/proelf.exp
    gdb/testsuite/config/rom68k.exp
    gdb/testsuite/config/sh.exp
    gdb/testsuite/config/sid.exp
    gdb/testsuite/config/sim.exp
    gdb/testsuite/config/slite.exp
    gdb/testsuite/config/unix.exp
    gdb/testsuite/config/unknown.exp
    gdb/testsuite/config/vr4300.exp
    gdb/testsuite/config/vr5000.exp
    gdb/testsuite/config/vx.exp
    gdb/testsuite/config/vxworks.exp
    gdb/testsuite/config/vxworks29k.exp
    gdb/testsuite/configure
    gdb/testsuite/configure.ac
    gdb/testsuite/gdb.ada/Makefile.in
    gdb/testsuite/gdb.ada/array_return.exp
    gdb/testsuite/gdb.ada/array_return/p.adb
    gdb/testsuite/gdb.ada/array_return/pck.adb
    gdb/testsuite/gdb.ada/array_return/pck.ads
    gdb/testsuite/gdb.ada/arrayidx.exp
    gdb/testsuite/gdb.ada/arrayidx/p.adb
    gdb/testsuite/gdb.ada/exec_changed.exp
    gdb/testsuite/gdb.ada/exec_changed/first.adb
    gdb/testsuite/gdb.ada/exec_changed/second.adb
    gdb/testsuite/gdb.ada/fixed_points.exp
    gdb/testsuite/gdb.ada/fixed_points/fixed_points.adb
    gdb/testsuite/gdb.ada/gnat_ada.gpr
    gdb/testsuite/gdb.ada/null_record.exp
    gdb/testsuite/gdb.ada/null_record/bar.adb
    gdb/testsuite/gdb.ada/null_record/bar.ads
    gdb/testsuite/gdb.ada/null_record/null_record.adb
    gdb/testsuite/gdb.ada/packed_array.exp
    gdb/testsuite/gdb.ada/packed_array/pa.adb
    gdb/testsuite/gdb.ada/start.exp
    gdb/testsuite/gdb.ada/start/dummy.adb
    gdb/testsuite/gdb.arch/Makefile.in
    gdb/testsuite/gdb.arch/alpha-step.c
    gdb/testsuite/gdb.arch/alpha-step.exp
    gdb/testsuite/gdb.arch/altivec-abi.c
    gdb/testsuite/gdb.arch/altivec-abi.exp
    gdb/testsuite/gdb.arch/altivec-regs.c
    gdb/testsuite/gdb.arch/altivec-regs.exp
    gdb/testsuite/gdb.arch/e500-abi.c
    gdb/testsuite/gdb.arch/e500-abi.exp
    gdb/testsuite/gdb.arch/e500-prologue.c
    gdb/testsuite/gdb.arch/e500-prologue.exp
    gdb/testsuite/gdb.arch/e500-regs.c
    gdb/testsuite/gdb.arch/e500-regs.exp
    gdb/testsuite/gdb.arch/gdb1291.exp
    gdb/testsuite/gdb.arch/gdb1291.s
    gdb/testsuite/gdb.arch/gdb1431.exp
    gdb/testsuite/gdb.arch/gdb1431.s
    gdb/testsuite/gdb.arch/gdb1558.c
    gdb/testsuite/gdb.arch/gdb1558.exp
    gdb/testsuite/gdb.arch/i386-cpuid.h
    gdb/testsuite/gdb.arch/i386-prologue.c
    gdb/testsuite/gdb.arch/i386-prologue.exp
    gdb/testsuite/gdb.arch/i386-size.c
    gdb/testsuite/gdb.arch/i386-size.exp
    gdb/testsuite/gdb.arch/i386-sse.c
    gdb/testsuite/gdb.arch/i386-sse.exp
    gdb/testsuite/gdb.arch/i386-unwind.c
    gdb/testsuite/gdb.arch/i386-unwind.exp
    gdb/testsuite/gdb.arch/pa-nullify.exp
    gdb/testsuite/gdb.arch/pa-nullify.s
    gdb/testsuite/gdb.arch/pa64-nullify.s
    gdb/testsuite/gdb.arch/powerpc-aix-prologue.c
    gdb/testsuite/gdb.arch/powerpc-aix-prologue.exp
    gdb/testsuite/gdb.arch/powerpc-prologue.c
    gdb/testsuite/gdb.arch/powerpc-prologue.exp
    gdb/testsuite/gdb.asm/Makefile.in
    gdb/testsuite/gdb.asm/alpha.inc
    gdb/testsuite/gdb.asm/arm.inc
    gdb/testsuite/gdb.asm/asm-source.exp
    gdb/testsuite/gdb.asm/asmsrc1.s
    gdb/testsuite/gdb.asm/asmsrc2.s
    gdb/testsuite/gdb.asm/common.inc
    gdb/testsuite/gdb.asm/d10v.inc
    gdb/testsuite/gdb.asm/empty.inc
    gdb/testsuite/gdb.asm/frv.inc
    gdb/testsuite/gdb.asm/h8300.inc
    gdb/testsuite/gdb.asm/i386.inc
    gdb/testsuite/gdb.asm/ia64.inc
    gdb/testsuite/gdb.asm/iq2000.inc
    gdb/testsuite/gdb.asm/m32c.inc
    gdb/testsuite/gdb.asm/m32r-linux.inc
    gdb/testsuite/gdb.asm/m32r.inc
    gdb/testsuite/gdb.asm/m68hc11.inc
    gdb/testsuite/gdb.asm/m68k.inc
    gdb/testsuite/gdb.asm/mips.inc
    gdb/testsuite/gdb.asm/netbsd.inc
    gdb/testsuite/gdb.asm/openbsd.inc
    gdb/testsuite/gdb.asm/pa.inc
    gdb/testsuite/gdb.asm/pa64.inc
    gdb/testsuite/gdb.asm/powerpc.inc
    gdb/testsuite/gdb.asm/s390.inc
    gdb/testsuite/gdb.asm/s390x.inc
    gdb/testsuite/gdb.asm/sh.inc
    gdb/testsuite/gdb.asm/sparc.inc
    gdb/testsuite/gdb.asm/sparc64.inc
    gdb/testsuite/gdb.asm/v850.inc
    gdb/testsuite/gdb.asm/x86_64.inc
    gdb/testsuite/gdb.asm/xstormy16.inc
    gdb/testsuite/gdb.base/Makefile.in
    gdb/testsuite/gdb.base/a2-run.exp
    gdb/testsuite/gdb.base/advance.c
    gdb/testsuite/gdb.base/advance.exp
    gdb/testsuite/gdb.base/all-bin.exp
    gdb/testsuite/gdb.base/all-types.c
    gdb/testsuite/gdb.base/annota1.c
    gdb/testsuite/gdb.base/annota1.exp
    gdb/testsuite/gdb.base/annota3.c
    gdb/testsuite/gdb.base/annota3.exp
    gdb/testsuite/gdb.base/args.c
    gdb/testsuite/gdb.base/args.exp
    gdb/testsuite/gdb.base/arithmet.exp
    gdb/testsuite/gdb.base/arrayidx.c
    gdb/testsuite/gdb.base/arrayidx.exp
    gdb/testsuite/gdb.base/assign.exp
    gdb/testsuite/gdb.base/async.c
    gdb/testsuite/gdb.base/async.exp
    gdb/testsuite/gdb.base/attach.c
    gdb/testsuite/gdb.base/attach.exp
    gdb/testsuite/gdb.base/attach2.c
    gdb/testsuite/gdb.base/auxv.c
    gdb/testsuite/gdb.base/auxv.exp
    gdb/testsuite/gdb.base/average.c
    gdb/testsuite/gdb.base/bang.exp
    gdb/testsuite/gdb.base/bar.c
    gdb/testsuite/gdb.base/baz.c
    gdb/testsuite/gdb.base/bfp-test.c
    gdb/testsuite/gdb.base/bfp-test.exp
    gdb/testsuite/gdb.base/bigcore.c
    gdb/testsuite/gdb.base/bigcore.exp
    gdb/testsuite/gdb.base/bitfields.c
    gdb/testsuite/gdb.base/bitfields.exp
    gdb/testsuite/gdb.base/bitfields2.c
    gdb/testsuite/gdb.base/bitfields2.exp
    gdb/testsuite/gdb.base/bitops.exp
    gdb/testsuite/gdb.base/branches.c
    gdb/testsuite/gdb.base/break.c
    gdb/testsuite/gdb.base/break.exp
    gdb/testsuite/gdb.base/break1.c
    gdb/testsuite/gdb.base/call-ar-st.c
    gdb/testsuite/gdb.base/call-ar-st.exp
    gdb/testsuite/gdb.base/call-rt-st.c
    gdb/testsuite/gdb.base/call-rt-st.exp
    gdb/testsuite/gdb.base/call-sc.c
    gdb/testsuite/gdb.base/call-sc.exp
    gdb/testsuite/gdb.base/call-strs.c
    gdb/testsuite/gdb.base/call-strs.exp
    gdb/testsuite/gdb.base/callfuncs.c
    gdb/testsuite/gdb.base/callfuncs.exp
    gdb/testsuite/gdb.base/charset.c
    gdb/testsuite/gdb.base/charset.exp
    gdb/testsuite/gdb.base/checkpoint.c
    gdb/testsuite/gdb.base/checkpoint.exp
    gdb/testsuite/gdb.base/chng-syms.c
    gdb/testsuite/gdb.base/chng-syms.exp
    gdb/testsuite/gdb.base/code-expr.exp
    gdb/testsuite/gdb.base/commands.exp
    gdb/testsuite/gdb.base/completion.exp
    gdb/testsuite/gdb.base/complex.c
    gdb/testsuite/gdb.base/complex.exp
    gdb/testsuite/gdb.base/cond-expr.exp
    gdb/testsuite/gdb.base/condbreak.exp
    gdb/testsuite/gdb.base/consecutive.c
    gdb/testsuite/gdb.base/consecutive.exp
    gdb/testsuite/gdb.base/constvars.c
    gdb/testsuite/gdb.base/constvars.exp
    gdb/testsuite/gdb.base/corefile.exp
    gdb/testsuite/gdb.base/coremaker.c
    gdb/testsuite/gdb.base/coremaker2.c
    gdb/testsuite/gdb.base/cursal.c
    gdb/testsuite/gdb.base/cursal.exp
    gdb/testsuite/gdb.base/cvexpr.c
    gdb/testsuite/gdb.base/cvexpr.exp
    gdb/testsuite/gdb.base/d10v.ld
    gdb/testsuite/gdb.base/d10vovly.c
    gdb/testsuite/gdb.base/dbx.exp
    gdb/testsuite/gdb.base/default.exp
    gdb/testsuite/gdb.base/define.exp
    gdb/testsuite/gdb.base/del.c
    gdb/testsuite/gdb.base/del.exp
    gdb/testsuite/gdb.base/detach.exp
    gdb/testsuite/gdb.base/display.c
    gdb/testsuite/gdb.base/display.exp
    gdb/testsuite/gdb.base/dump.c
    gdb/testsuite/gdb.base/dump.exp
    gdb/testsuite/gdb.base/echo.exp
    gdb/testsuite/gdb.base/ena-dis-br.exp
    gdb/testsuite/gdb.base/ending-run.c
    gdb/testsuite/gdb.base/ending-run.exp
    gdb/testsuite/gdb.base/environ.exp
    gdb/testsuite/gdb.base/eval-skip.exp
    gdb/testsuite/gdb.base/execd-prog.c
    gdb/testsuite/gdb.base/exprs.c
    gdb/testsuite/gdb.base/exprs.exp
    gdb/testsuite/gdb.base/fileio.c
    gdb/testsuite/gdb.base/fileio.exp
    gdb/testsuite/gdb.base/finish.exp
    gdb/testsuite/gdb.base/float.exp
    gdb/testsuite/gdb.base/foll-exec.c
    gdb/testsuite/gdb.base/foll-exec.exp
    gdb/testsuite/gdb.base/foll-fork.c
    gdb/testsuite/gdb.base/foll-fork.exp
    gdb/testsuite/gdb.base/foll-vfork.c
    gdb/testsuite/gdb.base/foll-vfork.exp
    gdb/testsuite/gdb.base/foo.c
    gdb/testsuite/gdb.base/freebpcmd.c
    gdb/testsuite/gdb.base/freebpcmd.exp
    gdb/testsuite/gdb.base/funcargs.c
    gdb/testsuite/gdb.base/funcargs.exp
    gdb/testsuite/gdb.base/gcore.c
    gdb/testsuite/gdb.base/gcore.exp
    gdb/testsuite/gdb.base/gdb1056.exp
    gdb/testsuite/gdb.base/gdb1090.c
    gdb/testsuite/gdb.base/gdb1090.exp
    gdb/testsuite/gdb.base/gdb1250.c
    gdb/testsuite/gdb.base/gdb1250.exp
    gdb/testsuite/gdb.base/gdb1555-main.c
    gdb/testsuite/gdb.base/gdb1555.c
    gdb/testsuite/gdb.base/gdb1555.exp
    gdb/testsuite/gdb.base/gdb1821.c
    gdb/testsuite/gdb.base/gdb1821.exp
    gdb/testsuite/gdb.base/gdb_history
    gdb/testsuite/gdb.base/gdbvars.exp
    gdb/testsuite/gdb.base/grbx.c
    gdb/testsuite/gdb.base/help.exp
    gdb/testsuite/gdb.base/huge.c
    gdb/testsuite/gdb.base/huge.exp
    gdb/testsuite/gdb.base/ifelse.exp
    gdb/testsuite/gdb.base/info-proc.exp
    gdb/testsuite/gdb.base/int-type.c
    gdb/testsuite/gdb.base/interp.exp
    gdb/testsuite/gdb.base/interrupt.c
    gdb/testsuite/gdb.base/interrupt.exp
    gdb/testsuite/gdb.base/jump.c
    gdb/testsuite/gdb.base/jump.exp
    gdb/testsuite/gdb.base/langs.exp
    gdb/testsuite/gdb.base/langs0.c
    gdb/testsuite/gdb.base/langs1.c
    gdb/testsuite/gdb.base/langs1.f
    gdb/testsuite/gdb.base/langs2.c
    gdb/testsuite/gdb.base/langs2.cxx
    gdb/testsuite/gdb.base/lineinc.c
    gdb/testsuite/gdb.base/lineinc.exp
    gdb/testsuite/gdb.base/lineinc1.h
    gdb/testsuite/gdb.base/lineinc2.h
    gdb/testsuite/gdb.base/lineinc3.h
    gdb/testsuite/gdb.base/list.exp
    gdb/testsuite/gdb.base/list0.c
    gdb/testsuite/gdb.base/list0.h
    gdb/testsuite/gdb.base/list1.c
    gdb/testsuite/gdb.base/logical.exp
    gdb/testsuite/gdb.base/long_long.c
    gdb/testsuite/gdb.base/long_long.exp
    gdb/testsuite/gdb.base/m32r.ld
    gdb/testsuite/gdb.base/m32rovly.c
    gdb/testsuite/gdb.base/macscp.exp
    gdb/testsuite/gdb.base/macscp1.c
    gdb/testsuite/gdb.base/macscp2.h
    gdb/testsuite/gdb.base/macscp3.h
    gdb/testsuite/gdb.base/macscp4.h
    gdb/testsuite/gdb.base/maint.exp
    gdb/testsuite/gdb.base/mips_pro.c
    gdb/testsuite/gdb.base/mips_pro.exp
    gdb/testsuite/gdb.base/miscexprs.c
    gdb/testsuite/gdb.base/miscexprs.exp
    gdb/testsuite/gdb.base/multi-forks.c
    gdb/testsuite/gdb.base/multi-forks.exp
    gdb/testsuite/gdb.base/nodebug.c
    gdb/testsuite/gdb.base/nodebug.exp
    gdb/testsuite/gdb.base/opaque.exp
    gdb/testsuite/gdb.base/opaque0.c
    gdb/testsuite/gdb.base/opaque1.c
    gdb/testsuite/gdb.base/overlays.c
    gdb/testsuite/gdb.base/overlays.exp
    gdb/testsuite/gdb.base/ovlymgr.c
    gdb/testsuite/gdb.base/ovlymgr.h
    gdb/testsuite/gdb.base/page.exp
    gdb/testsuite/gdb.base/pc-fp.c
    gdb/testsuite/gdb.base/pc-fp.exp
    gdb/testsuite/gdb.base/pending.c
    gdb/testsuite/gdb.base/pending.exp
    gdb/testsuite/gdb.base/pendshr.c
    gdb/testsuite/gdb.base/pi.txt
    gdb/testsuite/gdb.base/pointers.c
    gdb/testsuite/gdb.base/pointers.exp
    gdb/testsuite/gdb.base/prelink-lib.c
    gdb/testsuite/gdb.base/prelink.c
    gdb/testsuite/gdb.base/prelink.exp
    gdb/testsuite/gdb.base/printcmds.c
    gdb/testsuite/gdb.base/printcmds.exp
    gdb/testsuite/gdb.base/psymtab.exp
    gdb/testsuite/gdb.base/psymtab1.c
    gdb/testsuite/gdb.base/psymtab2.c
    gdb/testsuite/gdb.base/ptr-typedef.c
    gdb/testsuite/gdb.base/ptr-typedef.exp
    gdb/testsuite/gdb.base/ptype.c
    gdb/testsuite/gdb.base/ptype.exp
    gdb/testsuite/gdb.base/ptype1.c
    gdb/testsuite/gdb.base/radix.exp
    gdb/testsuite/gdb.base/readline.exp
    gdb/testsuite/gdb.base/recurse.c
    gdb/testsuite/gdb.base/recurse.exp
    gdb/testsuite/gdb.base/regs.exp
    gdb/testsuite/gdb.base/relational.exp
    gdb/testsuite/gdb.base/relocate.c
    gdb/testsuite/gdb.base/relocate.exp
    gdb/testsuite/gdb.base/remote.c
    gdb/testsuite/gdb.base/remote.exp
    gdb/testsuite/gdb.base/remotetimeout.exp
    gdb/testsuite/gdb.base/reread.exp
    gdb/testsuite/gdb.base/reread1.c
    gdb/testsuite/gdb.base/reread2.c
    gdb/testsuite/gdb.base/restore.c
    gdb/testsuite/gdb.base/restore.exp
    gdb/testsuite/gdb.base/return.c
    gdb/testsuite/gdb.base/return.exp
    gdb/testsuite/gdb.base/return2.c
    gdb/testsuite/gdb.base/return2.exp
    gdb/testsuite/gdb.base/run.c
    gdb/testsuite/gdb.base/savedregs.c
    gdb/testsuite/gdb.base/savedregs.exp
    gdb/testsuite/gdb.base/scope.exp
    gdb/testsuite/gdb.base/scope0.c
    gdb/testsuite/gdb.base/scope1.c
    gdb/testsuite/gdb.base/sect-cmd.exp
    gdb/testsuite/gdb.base/sep-proc.c
    gdb/testsuite/gdb.base/sep.c
    gdb/testsuite/gdb.base/sep.exp
    gdb/testsuite/gdb.base/sepdebug.c
    gdb/testsuite/gdb.base/sepdebug.exp
    gdb/testsuite/gdb.base/setshow.c
    gdb/testsuite/gdb.base/setshow.exp
    gdb/testsuite/gdb.base/setvar.c
    gdb/testsuite/gdb.base/setvar.exp
    gdb/testsuite/gdb.base/shlib-call.exp
    gdb/testsuite/gdb.base/shmain.c
    gdb/testsuite/gdb.base/shr1.c
    gdb/testsuite/gdb.base/shr2.c
    gdb/testsuite/gdb.base/shreloc.c
    gdb/testsuite/gdb.base/shreloc.exp
    gdb/testsuite/gdb.base/shreloc1.c
    gdb/testsuite/gdb.base/shreloc2.c
    gdb/testsuite/gdb.base/sigall.c
    gdb/testsuite/gdb.base/sigall.exp
    gdb/testsuite/gdb.base/sigaltstack.c
    gdb/testsuite/gdb.base/sigaltstack.exp
    gdb/testsuite/gdb.base/sigbpt.c
    gdb/testsuite/gdb.base/sigbpt.exp
    gdb/testsuite/gdb.base/siginfo.c
    gdb/testsuite/gdb.base/siginfo.exp
    gdb/testsuite/gdb.base/signals.c
    gdb/testsuite/gdb.base/signals.exp
    gdb/testsuite/gdb.base/signull.c
    gdb/testsuite/gdb.base/signull.exp
    gdb/testsuite/gdb.base/sigrepeat.c
    gdb/testsuite/gdb.base/sigrepeat.exp
    gdb/testsuite/gdb.base/sigstep.c
    gdb/testsuite/gdb.base/sigstep.exp
    gdb/testsuite/gdb.base/sizeof.c
    gdb/testsuite/gdb.base/sizeof.exp
    gdb/testsuite/gdb.base/so-impl-ld.c
    gdb/testsuite/gdb.base/so-impl-ld.exp
    gdb/testsuite/gdb.base/so-indr-cl.c
    gdb/testsuite/gdb.base/so-indr-cl.exp
    gdb/testsuite/gdb.base/solib.c
    gdb/testsuite/gdb.base/solib.exp
    gdb/testsuite/gdb.base/solib1.c
    gdb/testsuite/gdb.base/solib2.c
    gdb/testsuite/gdb.base/source-error.gdb
    gdb/testsuite/gdb.base/source.exp
    gdb/testsuite/gdb.base/ss.h
    gdb/testsuite/gdb.base/start.c
    gdb/testsuite/gdb.base/start.exp
    gdb/testsuite/gdb.base/step-line.c
    gdb/testsuite/gdb.base/step-line.exp
    gdb/testsuite/gdb.base/step-line.inp
    gdb/testsuite/gdb.base/step-test.c
    gdb/testsuite/gdb.base/step-test.exp
    gdb/testsuite/gdb.base/store.c
    gdb/testsuite/gdb.base/store.exp
    gdb/testsuite/gdb.base/structs.c
    gdb/testsuite/gdb.base/structs.exp
    gdb/testsuite/gdb.base/structs2.c
    gdb/testsuite/gdb.base/structs2.exp
    gdb/testsuite/gdb.base/sum.c
    gdb/testsuite/gdb.base/term.exp
    gdb/testsuite/gdb.base/twice.c
    gdb/testsuite/gdb.base/twice.exp
    gdb/testsuite/gdb.base/unload.c
    gdb/testsuite/gdb.base/unload.exp
    gdb/testsuite/gdb.base/unloadshr.c
    gdb/testsuite/gdb.base/until.exp
    gdb/testsuite/gdb.base/varargs.c
    gdb/testsuite/gdb.base/varargs.exp
    gdb/testsuite/gdb.base/vforked-prog.c
    gdb/testsuite/gdb.base/volatile.exp
    gdb/testsuite/gdb.base/watchpoint.c
    gdb/testsuite/gdb.base/watchpoint.exp
    gdb/testsuite/gdb.base/whatis-exp.exp
    gdb/testsuite/gdb.base/whatis.c
    gdb/testsuite/gdb.base/whatis.exp
    gdb/testsuite/gdb.cp/Makefile.in
    gdb/testsuite/gdb.cp/ambiguous.cc
    gdb/testsuite/gdb.cp/ambiguous.exp
    gdb/testsuite/gdb.cp/annota2.cc
    gdb/testsuite/gdb.cp/annota2.exp
    gdb/testsuite/gdb.cp/annota3.cc
    gdb/testsuite/gdb.cp/annota3.exp
    gdb/testsuite/gdb.cp/anon-union.cc
    gdb/testsuite/gdb.cp/anon-union.exp
    gdb/testsuite/gdb.cp/bool.cc
    gdb/testsuite/gdb.cp/bool.exp
    gdb/testsuite/gdb.cp/breakpoint.cc
    gdb/testsuite/gdb.cp/breakpoint.exp
    gdb/testsuite/gdb.cp/bs15503.cc
    gdb/testsuite/gdb.cp/bs15503.exp
    gdb/testsuite/gdb.cp/casts.cc
    gdb/testsuite/gdb.cp/casts.exp
    gdb/testsuite/gdb.cp/class2.cc
    gdb/testsuite/gdb.cp/class2.exp
    gdb/testsuite/gdb.cp/classes.cc
    gdb/testsuite/gdb.cp/classes.exp
    gdb/testsuite/gdb.cp/cplusfuncs.cc
    gdb/testsuite/gdb.cp/cplusfuncs.exp
    gdb/testsuite/gdb.cp/ctti.exp
    gdb/testsuite/gdb.cp/cttiadd.cc
    gdb/testsuite/gdb.cp/cttiadd1.cc
    gdb/testsuite/gdb.cp/cttiadd2.cc
    gdb/testsuite/gdb.cp/cttiadd3.cc
    gdb/testsuite/gdb.cp/demangle.exp
    gdb/testsuite/gdb.cp/derivation.cc
    gdb/testsuite/gdb.cp/derivation.exp
    gdb/testsuite/gdb.cp/exception.cc
    gdb/testsuite/gdb.cp/exception.exp
    gdb/testsuite/gdb.cp/gdb1355.cc
    gdb/testsuite/gdb.cp/gdb1355.exp
    gdb/testsuite/gdb.cp/hang.H
    gdb/testsuite/gdb.cp/hang.exp
    gdb/testsuite/gdb.cp/hang1.C
    gdb/testsuite/gdb.cp/hang2.C
    gdb/testsuite/gdb.cp/hang3.C
    gdb/testsuite/gdb.cp/inherit.exp
    gdb/testsuite/gdb.cp/local.cc
    gdb/testsuite/gdb.cp/local.exp
    gdb/testsuite/gdb.cp/m-data.cc
    gdb/testsuite/gdb.cp/m-data.exp
    gdb/testsuite/gdb.cp/m-static.cc
    gdb/testsuite/gdb.cp/m-static.exp
    gdb/testsuite/gdb.cp/m-static.h
    gdb/testsuite/gdb.cp/m-static1.cc
    gdb/testsuite/gdb.cp/maint.exp
    gdb/testsuite/gdb.cp/member-ptr.cc
    gdb/testsuite/gdb.cp/member-ptr.exp
    gdb/testsuite/gdb.cp/method.cc
    gdb/testsuite/gdb.cp/method.exp
    gdb/testsuite/gdb.cp/misc.cc
    gdb/testsuite/gdb.cp/misc.exp
    gdb/testsuite/gdb.cp/namespace.cc
    gdb/testsuite/gdb.cp/namespace.exp
    gdb/testsuite/gdb.cp/namespace1.cc
    gdb/testsuite/gdb.cp/overload.cc
    gdb/testsuite/gdb.cp/overload.exp
    gdb/testsuite/gdb.cp/ovldbreak.cc
    gdb/testsuite/gdb.cp/ovldbreak.exp
    gdb/testsuite/gdb.cp/pr-1023.cc
    gdb/testsuite/gdb.cp/pr-1023.exp
    gdb/testsuite/gdb.cp/pr-1210.cc
    gdb/testsuite/gdb.cp/pr-1210.exp
    gdb/testsuite/gdb.cp/pr-574.cc
    gdb/testsuite/gdb.cp/pr-574.exp
    gdb/testsuite/gdb.cp/printmethod.cc
    gdb/testsuite/gdb.cp/printmethod.exp
    gdb/testsuite/gdb.cp/psmang.exp
    gdb/testsuite/gdb.cp/psmang1.cc
    gdb/testsuite/gdb.cp/psmang2.cc
    gdb/testsuite/gdb.cp/ref-params.cc
    gdb/testsuite/gdb.cp/ref-params.exp
    gdb/testsuite/gdb.cp/ref-types.cc
    gdb/testsuite/gdb.cp/ref-types.exp
    gdb/testsuite/gdb.cp/rtti.exp
    gdb/testsuite/gdb.cp/rtti.h
    gdb/testsuite/gdb.cp/rtti1.cc
    gdb/testsuite/gdb.cp/rtti2.cc
    gdb/testsuite/gdb.cp/templates.cc
    gdb/testsuite/gdb.cp/templates.exp
    gdb/testsuite/gdb.cp/try_catch.cc
    gdb/testsuite/gdb.cp/try_catch.exp
    gdb/testsuite/gdb.cp/userdef.cc
    gdb/testsuite/gdb.cp/userdef.exp
    gdb/testsuite/gdb.cp/virtfunc.cc
    gdb/testsuite/gdb.cp/virtfunc.exp
    gdb/testsuite/gdb.disasm/Makefile.in
    gdb/testsuite/gdb.disasm/am33.exp
    gdb/testsuite/gdb.disasm/am33.s
    gdb/testsuite/gdb.disasm/h8300s.exp
    gdb/testsuite/gdb.disasm/h8300s.s
    gdb/testsuite/gdb.disasm/hppa.exp
    gdb/testsuite/gdb.disasm/hppa.s
    gdb/testsuite/gdb.disasm/mn10200.s
    gdb/testsuite/gdb.disasm/mn10300.exp
    gdb/testsuite/gdb.disasm/mn10300.s
    gdb/testsuite/gdb.disasm/sh3.exp
    gdb/testsuite/gdb.disasm/sh3.s
    gdb/testsuite/gdb.disasm/t01_mov.exp
    gdb/testsuite/gdb.disasm/t01_mov.s
    gdb/testsuite/gdb.disasm/t02_mova.exp
    gdb/testsuite/gdb.disasm/t02_mova.s
    gdb/testsuite/gdb.disasm/t03_add.exp
    gdb/testsuite/gdb.disasm/t03_add.s
    gdb/testsuite/gdb.disasm/t04_sub.exp
    gdb/testsuite/gdb.disasm/t04_sub.s
    gdb/testsuite/gdb.disasm/t05_cmp.exp
    gdb/testsuite/gdb.disasm/t05_cmp.s
    gdb/testsuite/gdb.disasm/t06_ari2.exp
    gdb/testsuite/gdb.disasm/t06_ari2.s
    gdb/testsuite/gdb.disasm/t07_ari3.exp
    gdb/testsuite/gdb.disasm/t07_ari3.s
    gdb/testsuite/gdb.disasm/t08_or.exp
    gdb/testsuite/gdb.disasm/t08_or.s
    gdb/testsuite/gdb.disasm/t09_xor.exp
    gdb/testsuite/gdb.disasm/t09_xor.s
    gdb/testsuite/gdb.disasm/t10_and.exp
    gdb/testsuite/gdb.disasm/t10_and.s
    gdb/testsuite/gdb.disasm/t11_logs.exp
    gdb/testsuite/gdb.disasm/t11_logs.s
    gdb/testsuite/gdb.disasm/t12_bit.exp
    gdb/testsuite/gdb.disasm/t12_bit.s
    gdb/testsuite/gdb.disasm/t13_otr.exp
    gdb/testsuite/gdb.disasm/t13_otr.s
    gdb/testsuite/gdb.dwarf2/Makefile.in
    gdb/testsuite/gdb.dwarf2/dup-psym.S
    gdb/testsuite/gdb.dwarf2/dup-psym.exp
    gdb/testsuite/gdb.dwarf2/dw2-basic.S
    gdb/testsuite/gdb.dwarf2/dw2-basic.exp
    gdb/testsuite/gdb.dwarf2/dw2-intercu.S
    gdb/testsuite/gdb.dwarf2/dw2-intercu.exp
    gdb/testsuite/gdb.dwarf2/dw2-intermix.S
    gdb/testsuite/gdb.dwarf2/dw2-intermix.exp
    gdb/testsuite/gdb.dwarf2/file1.txt
    gdb/testsuite/gdb.dwarf2/mac-fileno.S
    gdb/testsuite/gdb.dwarf2/mac-fileno.exp
    gdb/testsuite/gdb.dwarf2/main.c
    gdb/testsuite/gdb.fortran/Makefile.in
    gdb/testsuite/gdb.fortran/array-element.exp
    gdb/testsuite/gdb.fortran/array-element.f
    gdb/testsuite/gdb.fortran/derived-type.exp
    gdb/testsuite/gdb.fortran/derived-type.f90
    gdb/testsuite/gdb.fortran/exprs.exp
    gdb/testsuite/gdb.fortran/subarray.exp
    gdb/testsuite/gdb.fortran/subarray.f
    gdb/testsuite/gdb.fortran/types.exp
    gdb/testsuite/gdb.gdb/complaints.exp
    gdb/testsuite/gdb.gdb/observer.exp
    gdb/testsuite/gdb.gdb/selftest.exp
    gdb/testsuite/gdb.gdb/xfullpath.exp
    gdb/testsuite/gdb.hp/Makefile.in
    gdb/testsuite/gdb.hp/configure
    gdb/testsuite/gdb.hp/configure.ac
    gdb/testsuite/gdb.hp/gdb.aCC/Makefile.in
    gdb/testsuite/gdb.hp/gdb.aCC/configure
    gdb/testsuite/gdb.hp/gdb.aCC/configure.ac
    gdb/testsuite/gdb.hp/gdb.aCC/exception.exp
    gdb/testsuite/gdb.hp/gdb.aCC/optimize.c
    gdb/testsuite/gdb.hp/gdb.aCC/optimize.exp
    gdb/testsuite/gdb.hp/gdb.aCC/run.c
    gdb/testsuite/gdb.hp/gdb.aCC/watch-cmd.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/Makefile.in
    gdb/testsuite/gdb.hp/gdb.base-hp/callfwmall.c
    gdb/testsuite/gdb.hp/gdb.base-hp/callfwmall.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/configure
    gdb/testsuite/gdb.hp/gdb.base-hp/configure.ac
    gdb/testsuite/gdb.hp/gdb.base-hp/dollar.c
    gdb/testsuite/gdb.hp/gdb.base-hp/dollar.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/genso-thresh.c
    gdb/testsuite/gdb.hp/gdb.base-hp/hwwatchbus.c
    gdb/testsuite/gdb.hp/gdb.base-hp/hwwatchbus.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/pxdb.c
    gdb/testsuite/gdb.hp/gdb.base-hp/pxdb.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/reg-pa64.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/reg-pa64.s
    gdb/testsuite/gdb.hp/gdb.base-hp/reg.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/reg.s
    gdb/testsuite/gdb.hp/gdb.base-hp/sized-enum.c
    gdb/testsuite/gdb.hp/gdb.base-hp/sized-enum.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/so-thresh.exp
    gdb/testsuite/gdb.hp/gdb.base-hp/so-thresh.mk
    gdb/testsuite/gdb.hp/gdb.base-hp/so-thresh.sh
    gdb/testsuite/gdb.hp/gdb.compat/Makefile.in
    gdb/testsuite/gdb.hp/gdb.compat/average.c
    gdb/testsuite/gdb.hp/gdb.compat/configure
    gdb/testsuite/gdb.hp/gdb.compat/configure.ac
    gdb/testsuite/gdb.hp/gdb.compat/sum.c
    gdb/testsuite/gdb.hp/gdb.compat/xdb.c
    gdb/testsuite/gdb.hp/gdb.compat/xdb0.c
    gdb/testsuite/gdb.hp/gdb.compat/xdb0.h
    gdb/testsuite/gdb.hp/gdb.compat/xdb1.c
    gdb/testsuite/gdb.hp/gdb.compat/xdb1.exp
    gdb/testsuite/gdb.hp/gdb.compat/xdb2.exp
    gdb/testsuite/gdb.hp/gdb.compat/xdb3.exp
    gdb/testsuite/gdb.hp/gdb.defects/Makefile.in
    gdb/testsuite/gdb.hp/gdb.defects/bs14602.c
    gdb/testsuite/gdb.hp/gdb.defects/bs14602.exp
    gdb/testsuite/gdb.hp/gdb.defects/configure
    gdb/testsuite/gdb.hp/gdb.defects/configure.ac
    gdb/testsuite/gdb.hp/gdb.defects/solib-d.c
    gdb/testsuite/gdb.hp/gdb.defects/solib-d.exp
    gdb/testsuite/gdb.hp/gdb.defects/solib-d1.c
    gdb/testsuite/gdb.hp/gdb.defects/solib-d2.c
    gdb/testsuite/gdb.hp/gdb.objdbg/Makefile.in
    gdb/testsuite/gdb.hp/gdb.objdbg/configure
    gdb/testsuite/gdb.hp/gdb.objdbg/configure.ac
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg01.exp
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg01/x1.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg01/x2.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg01/x3.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg01/x3.h
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg02.exp
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg02/x1.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg02/x2.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg02/x3.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg03.exp
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg03/x1.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg03/x2.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg03/x3.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg04.exp
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg04/x.h
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg04/x1.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/objdbg04/x2.cc
    gdb/testsuite/gdb.hp/gdb.objdbg/tools/symaddr
    gdb/testsuite/gdb.hp/gdb.objdbg/tools/symaddr.pa64
    gdb/testsuite/gdb.hp/gdb.objdbg/tools/test-objdbg.cc
    gdb/testsuite/gdb.hp/tools/odump
    gdb/testsuite/gdb.java/Makefile.in
    gdb/testsuite/gdb.java/jmain.exp
    gdb/testsuite/gdb.java/jmain.java
    gdb/testsuite/gdb.java/jmisc.exp
    gdb/testsuite/gdb.java/jmisc.java
    gdb/testsuite/gdb.java/jmisc1.exp
    gdb/testsuite/gdb.java/jprint.exp
    gdb/testsuite/gdb.java/jprint.java
    gdb/testsuite/gdb.java/jv-exp.exp
    gdb/testsuite/gdb.java/jv-print.exp
    gdb/testsuite/gdb.mi/ChangeLog-1999-2003
    gdb/testsuite/gdb.mi/Makefile.in
    gdb/testsuite/gdb.mi/array.f
    gdb/testsuite/gdb.mi/basics.c
    gdb/testsuite/gdb.mi/gdb669.exp
    gdb/testsuite/gdb.mi/gdb680.exp
    gdb/testsuite/gdb.mi/gdb701.c
    gdb/testsuite/gdb.mi/gdb701.exp
    gdb/testsuite/gdb.mi/gdb792.cc
    gdb/testsuite/gdb.mi/gdb792.exp
    gdb/testsuite/gdb.mi/mi-basics.exp
    gdb/testsuite/gdb.mi/mi-break.exp
    gdb/testsuite/gdb.mi/mi-cli.exp
    gdb/testsuite/gdb.mi/mi-console.c
    gdb/testsuite/gdb.mi/mi-console.exp
    gdb/testsuite/gdb.mi/mi-disassemble.exp
    gdb/testsuite/gdb.mi/mi-eval.exp
    gdb/testsuite/gdb.mi/mi-file.exp
    gdb/testsuite/gdb.mi/mi-hack-cli.exp
    gdb/testsuite/gdb.mi/mi-pthreads.exp
    gdb/testsuite/gdb.mi/mi-read-memory.c
    gdb/testsuite/gdb.mi/mi-read-memory.exp
    gdb/testsuite/gdb.mi/mi-regs.exp
    gdb/testsuite/gdb.mi/mi-return.exp
    gdb/testsuite/gdb.mi/mi-simplerun.exp
    gdb/testsuite/gdb.mi/mi-stack.c
    gdb/testsuite/gdb.mi/mi-stack.exp
    gdb/testsuite/gdb.mi/mi-stepi.exp
    gdb/testsuite/gdb.mi/mi-syn-frame.c
    gdb/testsuite/gdb.mi/mi-syn-frame.exp
    gdb/testsuite/gdb.mi/mi-until.exp
    gdb/testsuite/gdb.mi/mi-var-block.exp
    gdb/testsuite/gdb.mi/mi-var-child-f.exp
    gdb/testsuite/gdb.mi/mi-var-child.c
    gdb/testsuite/gdb.mi/mi-var-child.exp
    gdb/testsuite/gdb.mi/mi-var-cmd.exp
    gdb/testsuite/gdb.mi/mi-var-display.exp
    gdb/testsuite/gdb.mi/mi-watch.exp
    gdb/testsuite/gdb.mi/mi2-basics.exp
    gdb/testsuite/gdb.mi/mi2-break.exp
    gdb/testsuite/gdb.mi/mi2-cli.exp
    gdb/testsuite/gdb.mi/mi2-console.exp
    gdb/testsuite/gdb.mi/mi2-disassemble.exp
    gdb/testsuite/gdb.mi/mi2-eval.exp
    gdb/testsuite/gdb.mi/mi2-file.exp
    gdb/testsuite/gdb.mi/mi2-hack-cli.exp
    gdb/testsuite/gdb.mi/mi2-pthreads.exp
    gdb/testsuite/gdb.mi/mi2-read-memory.exp
    gdb/testsuite/gdb.mi/mi2-regs.exp
    gdb/testsuite/gdb.mi/mi2-return.exp
    gdb/testsuite/gdb.mi/mi2-simplerun.exp
    gdb/testsuite/gdb.mi/mi2-stack.exp
    gdb/testsuite/gdb.mi/mi2-stepi.exp
    gdb/testsuite/gdb.mi/mi2-syn-frame.exp
    gdb/testsuite/gdb.mi/mi2-until.exp
    gdb/testsuite/gdb.mi/mi2-var-block.exp
    gdb/testsuite/gdb.mi/mi2-var-child.exp
    gdb/testsuite/gdb.mi/mi2-var-cmd.exp
    gdb/testsuite/gdb.mi/mi2-var-display.exp
    gdb/testsuite/gdb.mi/mi2-watch.exp
    gdb/testsuite/gdb.mi/pthreads.c
    gdb/testsuite/gdb.mi/testcmds
    gdb/testsuite/gdb.mi/until.c
    gdb/testsuite/gdb.mi/var-cmd.c
    gdb/testsuite/gdb.objc/Makefile.in
    gdb/testsuite/gdb.objc/basicclass.exp
    gdb/testsuite/gdb.objc/basicclass.m
    gdb/testsuite/gdb.objc/nondebug.exp
    gdb/testsuite/gdb.objc/nondebug.m
    gdb/testsuite/gdb.objc/objcdecode.exp
    gdb/testsuite/gdb.objc/objcdecode.m
    gdb/testsuite/gdb.server/Makefile.in
    gdb/testsuite/gdb.server/server-run.exp
    gdb/testsuite/gdb.server/server.c
    gdb/testsuite/gdb.stabs/Makefile.in
    gdb/testsuite/gdb.stabs/aout.sed
    gdb/testsuite/gdb.stabs/configure
    gdb/testsuite/gdb.stabs/configure.ac
    gdb/testsuite/gdb.stabs/ecoff.sed
    gdb/testsuite/gdb.stabs/exclfwd.exp
    gdb/testsuite/gdb.stabs/exclfwd.h
    gdb/testsuite/gdb.stabs/exclfwd1.c
    gdb/testsuite/gdb.stabs/exclfwd2.c
    gdb/testsuite/gdb.stabs/hppa.sed
    gdb/testsuite/gdb.stabs/weird.def
    gdb/testsuite/gdb.stabs/weird.exp
    gdb/testsuite/gdb.stabs/xcoff.sed
    gdb/testsuite/gdb.threads/Makefile.in
    gdb/testsuite/gdb.threads/bp_in_thread.c
    gdb/testsuite/gdb.threads/bp_in_thread.exp
    gdb/testsuite/gdb.threads/gcore-thread.exp
    gdb/testsuite/gdb.threads/killed.c
    gdb/testsuite/gdb.threads/killed.exp
    gdb/testsuite/gdb.threads/linux-dp.c
    gdb/testsuite/gdb.threads/linux-dp.exp
    gdb/testsuite/gdb.threads/manythreads.c
    gdb/testsuite/gdb.threads/manythreads.exp
    gdb/testsuite/gdb.threads/print-threads.c
    gdb/testsuite/gdb.threads/print-threads.exp
    gdb/testsuite/gdb.threads/pthread_cond_wait.c
    gdb/testsuite/gdb.threads/pthread_cond_wait.exp
    gdb/testsuite/gdb.threads/pthreads.c
    gdb/testsuite/gdb.threads/pthreads.exp
    gdb/testsuite/gdb.threads/schedlock.c
    gdb/testsuite/gdb.threads/schedlock.exp
    gdb/testsuite/gdb.threads/staticthreads.c
    gdb/testsuite/gdb.threads/staticthreads.exp
    gdb/testsuite/gdb.threads/step.c
    gdb/testsuite/gdb.threads/step.exp
    gdb/testsuite/gdb.threads/step2.exp
    gdb/testsuite/gdb.threads/switch-threads.c
    gdb/testsuite/gdb.threads/switch-threads.exp
    gdb/testsuite/gdb.threads/thread-specific.c
    gdb/testsuite/gdb.threads/thread-specific.exp
    gdb/testsuite/gdb.threads/thread_check.c
    gdb/testsuite/gdb.threads/thread_check.exp
    gdb/testsuite/gdb.threads/threadapply.c
    gdb/testsuite/gdb.threads/threadapply.exp
    gdb/testsuite/gdb.threads/tls-main.c
    gdb/testsuite/gdb.threads/tls-shared.c
    gdb/testsuite/gdb.threads/tls-shared.exp
    gdb/testsuite/gdb.threads/tls.c
    gdb/testsuite/gdb.threads/tls.exp
    gdb/testsuite/gdb.threads/watchthreads.c
    gdb/testsuite/gdb.threads/watchthreads.exp
    gdb/testsuite/gdb.trace/Makefile.in
    gdb/testsuite/gdb.trace/actions.c
    gdb/testsuite/gdb.trace/actions.exp
    gdb/testsuite/gdb.trace/backtrace.exp
    gdb/testsuite/gdb.trace/circ.c
    gdb/testsuite/gdb.trace/circ.exp
    gdb/testsuite/gdb.trace/collection.c
    gdb/testsuite/gdb.trace/collection.exp
    gdb/testsuite/gdb.trace/deltrace.exp
    gdb/testsuite/gdb.trace/gdb_c_test.c
    gdb/testsuite/gdb.trace/infotrace.exp
    gdb/testsuite/gdb.trace/limits.c
    gdb/testsuite/gdb.trace/limits.exp
    gdb/testsuite/gdb.trace/packetlen.exp
    gdb/testsuite/gdb.trace/passc-dyn.exp
    gdb/testsuite/gdb.trace/passcount.exp
    gdb/testsuite/gdb.trace/report.exp
    gdb/testsuite/gdb.trace/save-trace.exp
    gdb/testsuite/gdb.trace/tfind.exp
    gdb/testsuite/gdb.trace/tracecmd.exp
    gdb/testsuite/gdb.trace/while-dyn.exp
    gdb/testsuite/gdb.trace/while-stepping.exp
    gdb/testsuite/lib/ada.exp
    gdb/testsuite/lib/compiler.c
    gdb/testsuite/lib/compiler.cc
    gdb/testsuite/lib/cp-support.exp
    gdb/testsuite/lib/emc-support.exp
    gdb/testsuite/lib/gdb.exp
    gdb/testsuite/lib/gdbserver-support.exp
    gdb/testsuite/lib/java.exp
    gdb/testsuite/lib/mi-support.exp
    gdb/testsuite/lib/trace-support.exp
    gdb/thread.c
    gdb/top.c
    gdb/top.h
    gdb/tracepoint.c
    gdb/tracepoint.h
    gdb/trad-frame.c
    gdb/trad-frame.h
    gdb/tramp-frame.c
    gdb/tramp-frame.h
    gdb/tui/ChangeLog-1998-2003
    gdb/tui/tui-command.c
    gdb/tui/tui-command.h
    gdb/tui/tui-data.c
    gdb/tui/tui-data.h
    gdb/tui/tui-disasm.c
    gdb/tui/tui-disasm.h
    gdb/tui/tui-file.c
    gdb/tui/tui-file.h
    gdb/tui/tui-hooks.c
    gdb/tui/tui-hooks.h
    gdb/tui/tui-interp.c
    gdb/tui/tui-io.c
    gdb/tui/tui-io.h
    gdb/tui/tui-layout.c
    gdb/tui/tui-layout.h
    gdb/tui/tui-main.c
    gdb/tui/tui-out.c
    gdb/tui/tui-regs.c
    gdb/tui/tui-regs.h
    gdb/tui/tui-source.c
    gdb/tui/tui-source.h
    gdb/tui/tui-stack.c
    gdb/tui/tui-stack.h
    gdb/tui/tui-win.c
    gdb/tui/tui-win.h
    gdb/tui/tui-windata.c
    gdb/tui/tui-windata.h
    gdb/tui/tui-wingeneral.c
    gdb/tui/tui-wingeneral.h
    gdb/tui/tui-winsource.c
    gdb/tui/tui-winsource.h
    gdb/tui/tui.c
    gdb/tui/tui.h
    gdb/typeprint.c
    gdb/typeprint.h
    gdb/ui-file.c
    gdb/ui-file.h
    gdb/ui-out.c
    gdb/ui-out.h
    gdb/user-regs.c
    gdb/user-regs.h
    gdb/utils.c
    gdb/uw-thread.c
    gdb/v850-tdep.c
    gdb/valarith.c
    gdb/valops.c
    gdb/valprint.c
    gdb/valprint.h
    gdb/value.c
    gdb/value.h
    gdb/varobj.c
    gdb/varobj.h
    gdb/vax-nat.c
    gdb/vax-tdep.c
    gdb/vax-tdep.h
    gdb/vaxbsd-nat.c
    gdb/vaxnbsd-tdep.c
    gdb/vaxobsd-tdep.c
    gdb/version.h
    gdb/version.in
    gdb/vx-share/README
    gdb/win32-nat.c
    gdb/win32-termcap.c
    gdb/wince-stub.c
    gdb/wince-stub.h
    gdb/wince.c
    gdb/windows-nat.c
    gdb/windows-termcap.c
    gdb/wrapper.c
    gdb/wrapper.h
    gdb/xcoffread.c
    gdb/xcoffsolib.c
    gdb/xcoffsolib.h
    gdb/xstormy16-tdep.c
    gprof/.gdbinit
    gprof/ChangeLog
    gprof/ChangeLog-2004
    gprof/ChangeLog-2005
    gprof/ChangeLog-9203
    gprof/MAINTAINERS
    gprof/Makefile.am
    gprof/Makefile.in
    gprof/README
    gprof/TEST
    gprof/TODO
    gprof/acinclude.m4
    gprof/aclocal.m4
    gprof/alpha.c
    gprof/basic_blocks.c
    gprof/basic_blocks.h
    gprof/bb_exit_func.c
    gprof/bbconv.pl
    gprof/bsd_callg_bl.m
    gprof/call_graph.c
    gprof/call_graph.h
    gprof/cg_arcs.c
    gprof/cg_arcs.h
    gprof/cg_dfn.c
    gprof/cg_dfn.h
    gprof/cg_print.c
    gprof/cg_print.h
    gprof/configure
    gprof/configure.in
    gprof/corefile.c
    gprof/corefile.h
    gprof/dep-in.sed
    gprof/flat_bl.m
    gprof/fsf_callg_bl.m
    gprof/gconfig.in
    gprof/gen-c-prog.awk
    gprof/gmon.h
    gprof/gmon_io.c
    gprof/gmon_io.h
    gprof/gmon_out.h
    gprof/gprof.c
    gprof/gprof.h
    gprof/gprof.texi
    gprof/hertz.c
    gprof/hertz.h
    gprof/hist.c
    gprof/hist.h
    gprof/i386.c
    gprof/mips.c
    gprof/po/.cvsignore
    gprof/po/Make-in
    gprof/po/POTFILES.in
    gprof/po/da.po
    gprof/po/de.po
    gprof/po/es.po
    gprof/po/fr.po
    gprof/po/ga.po
    gprof/po/gprof.pot
    gprof/po/id.po
    gprof/po/pt_BR.po
    gprof/po/rw.po
    gprof/po/sv.po
    gprof/po/tr.po
    gprof/po/vi.po
    gprof/search_list.c
    gprof/search_list.h
    gprof/source.c
    gprof/source.h
    gprof/sparc.c
    gprof/stamp-h.in
    gprof/sym_ids.c
    gprof/sym_ids.h
    gprof/symtab.c
    gprof/symtab.h
    gprof/tahoe.c
    gprof/utils.c
    gprof/utils.h
    gprof/vax.c
    intl/ChangeLog
    intl/Makefile.in
    intl/README
    intl/VERSION
    intl/aclocal.m4
    intl/bindtextdom.c
    intl/config.h.in
    intl/config.intl.in
    intl/configure
    intl/configure.ac
    intl/dcgettext.c
    intl/dcigettext.c
    intl/dcngettext.c
    intl/dgettext.c
    intl/dngettext.c
    intl/eval-plural.h
    intl/explodename.c
    intl/finddomain.c
    intl/gettext.c
    intl/gettextP.h
    intl/gmo.h
    intl/hash-string.h
    intl/intl-compat.c
    intl/l10nflist.c
    intl/libgnuintl.h
    intl/loadinfo.h
    intl/loadmsgcat.c
    intl/localcharset.c
    intl/localcharset.h
    intl/locale.alias
    intl/localealias.c
    intl/localename.c
    intl/log.c
    intl/ngettext.c
    intl/osdep.c
    intl/plural-exp.c
    intl/plural-exp.h
    intl/plural.c
    intl/plural.y
    intl/relocatable.c
    intl/relocatable.h
    intl/textdomain.c
    ld/ChangeLog
    ld/ChangeLog-0001
    ld/ChangeLog-0203
    ld/ChangeLog-2004
    ld/ChangeLog-2005
    ld/ChangeLog-9197
    ld/ChangeLog-9899
    ld/MAINTAINERS
    ld/Makefile.am
    ld/Makefile.in
    ld/NEWS
    ld/README
    ld/TODO
    ld/acinclude.m4
    ld/aclocal.m4
    ld/config.in
    ld/configure
    ld/configure.host
    ld/configure.in
    ld/configure.tgt
    ld/deffile.h
    ld/deffilep.y
    ld/dep-in.sed
    ld/elf-hints-local.h
    ld/emulparams/README
    ld/emulparams/aix5ppc.sh
    ld/emulparams/aix5rs6.sh
    ld/emulparams/aixppc.sh
    ld/emulparams/aixrs6.sh
    ld/emulparams/alpha.sh
    ld/emulparams/arcelf.sh
    ld/emulparams/arm_epoc_pe.sh
    ld/emulparams/armaoutb.sh
    ld/emulparams/armaoutl.sh
    ld/emulparams/armcoff.sh
    ld/emulparams/armelf.sh
    ld/emulparams/armelf_fbsd.sh
    ld/emulparams/armelf_linux.sh
    ld/emulparams/armelf_linux_eabi.sh
    ld/emulparams/armelf_nbsd.sh
    ld/emulparams/armelf_vxworks.sh
    ld/emulparams/armelfb.sh
    ld/emulparams/armelfb_linux.sh
    ld/emulparams/armelfb_linux_eabi.sh
    ld/emulparams/armelfb_nbsd.sh
    ld/emulparams/armnbsd.sh
    ld/emulparams/armnto.sh
    ld/emulparams/armpe.sh
    ld/emulparams/armsymbian.sh
    ld/emulparams/avr1.sh
    ld/emulparams/avr2.sh
    ld/emulparams/avr3.sh
    ld/emulparams/avr4.sh
    ld/emulparams/avr5.sh
    ld/emulparams/avr6.sh
    ld/emulparams/bfin.sh
    ld/emulparams/coff_i860.sh
    ld/emulparams/coff_sparc.sh
    ld/emulparams/crisaout.sh
    ld/emulparams/criself.sh
    ld/emulparams/crislinux.sh
    ld/emulparams/d10velf.sh
    ld/emulparams/d30v_e.sh
    ld/emulparams/d30v_o.sh
    ld/emulparams/d30velf.sh
    ld/emulparams/delta68.sh
    ld/emulparams/elf32_dlx.sh
    ld/emulparams/elf32_i860.sh
    ld/emulparams/elf32_i960.sh
    ld/emulparams/elf32_sparc.sh
    ld/emulparams/elf32_sparc_vxworks.sh
    ld/emulparams/elf32am33lin.sh
    ld/emulparams/elf32b4300.sh
    ld/emulparams/elf32bfinfd.sh
    ld/emulparams/elf32bmip.sh
    ld/emulparams/elf32bmipn32-defs.sh
    ld/emulparams/elf32bmipn32.sh
    ld/emulparams/elf32bsmip.sh
    ld/emulparams/elf32btsmip.sh
    ld/emulparams/elf32btsmipn32.sh
    ld/emulparams/elf32cr16c.sh
    ld/emulparams/elf32crx.sh
    ld/emulparams/elf32ebmip.sh
    ld/emulparams/elf32ebmipvxworks.sh
    ld/emulparams/elf32elmip.sh
    ld/emulparams/elf32elmipvxworks.sh
    ld/emulparams/elf32fr30.sh
    ld/emulparams/elf32frv.sh
    ld/emulparams/elf32frvfd.sh
    ld/emulparams/elf32i370.sh
    ld/emulparams/elf32ip2k.sh
    ld/emulparams/elf32iq10.sh
    ld/emulparams/elf32iq2000.sh
    ld/emulparams/elf32l4300.sh
    ld/emulparams/elf32lmip.sh
    ld/emulparams/elf32lppc.sh
    ld/emulparams/elf32lppcnto.sh
    ld/emulparams/elf32lppcsim.sh
    ld/emulparams/elf32lsmip.sh
    ld/emulparams/elf32ltsmip.sh
    ld/emulparams/elf32ltsmipn32.sh
    ld/emulparams/elf32m32c.sh
    ld/emulparams/elf32mcore.sh
    ld/emulparams/elf32mipswindiss.sh
    ld/emulparams/elf32mt.sh
    ld/emulparams/elf32openrisc.sh
    ld/emulparams/elf32ppc.sh
    ld/emulparams/elf32ppc_fbsd.sh
    ld/emulparams/elf32ppccommon.sh
    ld/emulparams/elf32ppclinux.sh
    ld/emulparams/elf32ppcnto.sh
    ld/emulparams/elf32ppcsim.sh
    ld/emulparams/elf32ppcvxworks.sh
    ld/emulparams/elf32ppcwindiss.sh
    ld/emulparams/elf32vax.sh
    ld/emulparams/elf32xc16x.sh
    ld/emulparams/elf32xc16xl.sh
    ld/emulparams/elf32xc16xs.sh
    ld/emulparams/elf32xstormy16.sh
    ld/emulparams/elf32xtensa.sh
    ld/emulparams/elf64_aix.sh
    ld/emulparams/elf64_ia64.sh
    ld/emulparams/elf64_ia64_fbsd.sh
    ld/emulparams/elf64_s390.sh
    ld/emulparams/elf64_sparc.sh
    ld/emulparams/elf64_sparc_fbsd.sh
    ld/emulparams/elf64alpha.sh
    ld/emulparams/elf64alpha_fbsd.sh
    ld/emulparams/elf64alpha_nbsd.sh
    ld/emulparams/elf64bmip.sh
    ld/emulparams/elf64btsmip.sh
    ld/emulparams/elf64hppa.sh
    ld/emulparams/elf64lppc.sh
    ld/emulparams/elf64ltsmip.sh
    ld/emulparams/elf64mmix.sh
    ld/emulparams/elf64ppc.sh
    ld/emulparams/elf_fbsd.sh
    ld/emulparams/elf_i386.sh
    ld/emulparams/elf_i386_be.sh
    ld/emulparams/elf_i386_chaos.sh
    ld/emulparams/elf_i386_fbsd.sh
    ld/emulparams/elf_i386_ldso.sh
    ld/emulparams/elf_i386_vxworks.sh
    ld/emulparams/elf_s390.sh
    ld/emulparams/elf_x86_64.sh
    ld/emulparams/elf_x86_64_fbsd.sh
    ld/emulparams/gld960.sh
    ld/emulparams/gld960coff.sh
    ld/emulparams/h8300.sh
    ld/emulparams/h8300elf.sh
    ld/emulparams/h8300h.sh
    ld/emulparams/h8300helf.sh
    ld/emulparams/h8300hn.sh
    ld/emulparams/h8300hnelf.sh
    ld/emulparams/h8300s.sh
    ld/emulparams/h8300self.sh
    ld/emulparams/h8300sn.sh
    ld/emulparams/h8300snelf.sh
    ld/emulparams/h8300sx.sh
    ld/emulparams/h8300sxelf.sh
    ld/emulparams/h8300sxn.sh
    ld/emulparams/h8300sxnelf.sh
    ld/emulparams/h8500.sh
    ld/emulparams/h8500b.sh
    ld/emulparams/h8500c.sh
    ld/emulparams/h8500m.sh
    ld/emulparams/h8500s.sh
    ld/emulparams/hp300bsd.sh
    ld/emulparams/hp3hpux.sh
    ld/emulparams/hppa64linux.sh
    ld/emulparams/hppaelf.sh
    ld/emulparams/hppalinux.sh
    ld/emulparams/hppanbsd.sh
    ld/emulparams/hppaobsd.sh
    ld/emulparams/i386aout.sh
    ld/emulparams/i386beos.sh
    ld/emulparams/i386bsd.sh
    ld/emulparams/i386coff.sh
    ld/emulparams/i386go32.sh
    ld/emulparams/i386linux.sh
    ld/emulparams/i386lynx.sh
    ld/emulparams/i386mach.sh
    ld/emulparams/i386moss.sh
    ld/emulparams/i386msdos.sh
    ld/emulparams/i386nbsd.sh
    ld/emulparams/i386nto.sh
    ld/emulparams/i386nw.sh
    ld/emulparams/i386pe.sh
    ld/emulparams/i386pe_posix.sh
    ld/emulparams/lnk960.sh
    ld/emulparams/m32relf.sh
    ld/emulparams/m32relf_linux.sh
    ld/emulparams/m32rlelf.sh
    ld/emulparams/m32rlelf_linux.sh
    ld/emulparams/m68hc11elf.sh
    ld/emulparams/m68hc11elfb.sh
    ld/emulparams/m68hc12elf.sh
    ld/emulparams/m68hc12elfb.sh
    ld/emulparams/m68k4knbsd.sh
    ld/emulparams/m68kaout.sh
    ld/emulparams/m68kaux.sh
    ld/emulparams/m68kcoff.sh
    ld/emulparams/m68kelf.sh
    ld/emulparams/m68kelfnbsd.sh
    ld/emulparams/m68klinux.sh
    ld/emulparams/m68knbsd.sh
    ld/emulparams/m68kpsos.sh
    ld/emulparams/m88kbcs.sh
    ld/emulparams/maxqcoff.sh
    ld/emulparams/mcorepe.sh
    ld/emulparams/mipsbig.sh
    ld/emulparams/mipsbsd.sh
    ld/emulparams/mipsidt.sh
    ld/emulparams/mipsidtl.sh
    ld/emulparams/mipslit.sh
    ld/emulparams/mipslnews.sh
    ld/emulparams/mipspe.sh
    ld/emulparams/mmo.sh
    ld/emulparams/mn10200.sh
    ld/emulparams/mn10300.sh
    ld/emulparams/msp430all.sh
    ld/emulparams/news.sh
    ld/emulparams/ns32knbsd.sh
    ld/emulparams/or32.sh
    ld/emulparams/or32elf.sh
    ld/emulparams/pc532macha.sh
    ld/emulparams/pdp11.sh
    ld/emulparams/pjelf.sh
    ld/emulparams/pjlelf.sh
    ld/emulparams/ppclynx.sh
    ld/emulparams/ppcmacos.sh
    ld/emulparams/ppcnw.sh
    ld/emulparams/ppcpe.sh
    ld/emulparams/riscix.sh
    ld/emulparams/sh.sh
    ld/emulparams/shelf.sh
    ld/emulparams/shelf32.sh
    ld/emulparams/shelf32_linux.sh
    ld/emulparams/shelf32_nbsd.sh
    ld/emulparams/shelf64.sh
    ld/emulparams/shelf64_nbsd.sh
    ld/emulparams/shelf_linux.sh
    ld/emulparams/shelf_nbsd.sh
    ld/emulparams/shelf_nto.sh
    ld/emulparams/shl.sh
    ld/emulparams/shlelf.sh
    ld/emulparams/shlelf32.sh
    ld/emulparams/shlelf32_linux.sh
    ld/emulparams/shlelf32_nbsd.sh
    ld/emulparams/shlelf64.sh
    ld/emulparams/shlelf64_nbsd.sh
    ld/emulparams/shlelf_linux.sh
    ld/emulparams/shlelf_nbsd.sh
    ld/emulparams/shlelf_nto.sh
    ld/emulparams/shlsymbian.sh
    ld/emulparams/shpe.sh
    ld/emulparams/sparcaout.sh
    ld/emulparams/sparclinux.sh
    ld/emulparams/sparcnbsd.sh
    ld/emulparams/st2000.sh
    ld/emulparams/sun3.sh
    ld/emulparams/sun4.sh
    ld/emulparams/tic30aout.sh
    ld/emulparams/tic30coff.sh
    ld/emulparams/tic3xcoff.sh
    ld/emulparams/tic3xcoff_onchip.sh
    ld/emulparams/tic4xcoff.sh
    ld/emulparams/tic54xcoff.sh
    ld/emulparams/tic80coff.sh
    ld/emulparams/v850.sh
    ld/emulparams/vanilla.sh
    ld/emulparams/vax.sh
    ld/emulparams/vaxnbsd.sh
    ld/emulparams/vsta.sh
    ld/emulparams/vxworks.sh
    ld/emulparams/w65.sh
    ld/emulparams/xtensa-config.sh
    ld/emulparams/z80.sh
    ld/emulparams/z8001.sh
    ld/emulparams/z8002.sh
    ld/emultempl/README
    ld/emultempl/aix.em
    ld/emultempl/alphaelf.em
    ld/emultempl/armcoff.em
    ld/emultempl/armelf.em
    ld/emultempl/astring.sed
    ld/emultempl/avrelf.em
    ld/emultempl/beos.em
    ld/emultempl/crxelf.em
    ld/emultempl/elf-generic.em
    ld/emultempl/elf32.em
    ld/emultempl/genelf.em
    ld/emultempl/generic.em
    ld/emultempl/gld960.em
    ld/emultempl/gld960c.em
    ld/emultempl/hppaelf.em
    ld/emultempl/ia64elf.em
    ld/emultempl/irix.em
    ld/emultempl/linux.em
    ld/emultempl/lnk960.em
    ld/emultempl/m68hc1xelf.em
    ld/emultempl/m68kcoff.em
    ld/emultempl/m68kelf.em
    ld/emultempl/mipsecoff.em
    ld/emultempl/mmix-elfnmmo.em
    ld/emultempl/mmixelf.em
    ld/emultempl/mmo.em
    ld/emultempl/needrelax.em
    ld/emultempl/netbsd.em
    ld/emultempl/ostring.sed
    ld/emultempl/pe.em
    ld/emultempl/ppc32elf.em
    ld/emultempl/ppc64elf.em
    ld/emultempl/sh64elf.em
    ld/emultempl/sunos.em
    ld/emultempl/ticoff.em
    ld/emultempl/vanilla.em
    ld/emultempl/vxworks.em
    ld/emultempl/xtensaelf.em
    ld/emultempl/z80.em
    ld/fdl.texi
    ld/gen-doc.texi
    ld/genscripts.sh
    ld/h8-doc.texi
    ld/ld.h
    ld/ld.texinfo
    ld/ldcref.c
    ld/ldctor.c
    ld/ldctor.h
    ld/ldemul.c
    ld/ldemul.h
    ld/ldexp.c
    ld/ldexp.h
    ld/ldfile.c
    ld/ldfile.h
    ld/ldgram.y
    ld/ldint.texinfo
    ld/ldlang.c
    ld/ldlang.h
    ld/ldlex.h
    ld/ldlex.l
    ld/ldmain.c
    ld/ldmain.h
    ld/ldmisc.c
    ld/ldmisc.h
    ld/ldver.c
    ld/ldver.h
    ld/ldwrite.c
    ld/ldwrite.h
    ld/lexsup.c
    ld/mri.c
    ld/mri.h
    ld/pe-dll.c
    ld/pe-dll.h
    ld/po/.cvsignore
    ld/po/Make-in
    ld/po/POTFILES.in
    ld/po/da.po
    ld/po/es.po
    ld/po/fr.po
    ld/po/ld.pot
    ld/po/sv.po
    ld/po/tr.po
    ld/po/vi.po
    ld/po/zh_CN.po
    ld/po/zh_TW.po
    ld/scripttempl/README
    ld/scripttempl/a29k.sc
    ld/scripttempl/aix.sc
    ld/scripttempl/alpha.sc
    ld/scripttempl/aout.sc
    ld/scripttempl/armaout.sc
    ld/scripttempl/armbpabi.sc
    ld/scripttempl/armcoff.sc
    ld/scripttempl/avr.sc
    ld/scripttempl/crisaout.sc
    ld/scripttempl/delta68.sc
    ld/scripttempl/dlx.sc
    ld/scripttempl/ebmon29k.sc
    ld/scripttempl/elf.sc
    ld/scripttempl/elf32cr16c.sc
    ld/scripttempl/elf32crx.sc
    ld/scripttempl/elf32msp430.sc
    ld/scripttempl/elf32msp430_3.sc
    ld/scripttempl/elf32sh-symbian.sc
    ld/scripttempl/elf32xc16x.sc
    ld/scripttempl/elf32xc16xl.sc
    ld/scripttempl/elf32xc16xs.sc
    ld/scripttempl/elf_chaos.sc
    ld/scripttempl/elfd10v.sc
    ld/scripttempl/elfd30v.sc
    ld/scripttempl/elfi370.sc
    ld/scripttempl/elfm68hc11.sc
    ld/scripttempl/elfm68hc12.sc
    ld/scripttempl/elfxtensa.sc
    ld/scripttempl/epocpe.sc
    ld/scripttempl/h8300.sc
    ld/scripttempl/h8300h.sc
    ld/scripttempl/h8300hn.sc
    ld/scripttempl/h8300s.sc
    ld/scripttempl/h8300sn.sc
    ld/scripttempl/h8300sx.sc
    ld/scripttempl/h8300sxn.sc
    ld/scripttempl/h8500.sc
    ld/scripttempl/h8500b.sc
    ld/scripttempl/h8500c.sc
    ld/scripttempl/h8500m.sc
    ld/scripttempl/h8500s.sc
    ld/scripttempl/hppaelf.sc
    ld/scripttempl/i386beos.sc
    ld/scripttempl/i386coff.sc
    ld/scripttempl/i386go32.sc
    ld/scripttempl/i386msdos.sc
    ld/scripttempl/i860coff.sc
    ld/scripttempl/i960.sc
    ld/scripttempl/ip2k.sc
    ld/scripttempl/iq2000.sc
    ld/scripttempl/m68kaux.sc
    ld/scripttempl/m68kcoff.sc
    ld/scripttempl/m68klynx.sc
    ld/scripttempl/m88kbcs.sc
    ld/scripttempl/maxqcoff.sc
    ld/scripttempl/mcorepe.sc
    ld/scripttempl/mips.sc
    ld/scripttempl/mipsbsd.sc
    ld/scripttempl/mmo.sc
    ld/scripttempl/nw.sc
    ld/scripttempl/or32.sc
    ld/scripttempl/pe.sc
    ld/scripttempl/pj.sc
    ld/scripttempl/ppcpe.sc
    ld/scripttempl/psos.sc
    ld/scripttempl/riscix.sc
    ld/scripttempl/sa29200.sc
    ld/scripttempl/sh.sc
    ld/scripttempl/sparccoff.sc
    ld/scripttempl/sparclynx.sc
    ld/scripttempl/st2000.sc
    ld/scripttempl/tic30aout.sc
    ld/scripttempl/tic30coff.sc
    ld/scripttempl/tic4xcoff.sc
    ld/scripttempl/tic54xcoff.sc
    ld/scripttempl/tic80coff.sc
    ld/scripttempl/v850.sc
    ld/scripttempl/vanilla.sc
    ld/scripttempl/w65.sc
    ld/scripttempl/xstormy16.sc
    ld/scripttempl/z80.sc
    ld/scripttempl/z8000.sc
    ld/stamp-h.in
    ld/sysdep.h
    ld/testsuite/ChangeLog
    ld/testsuite/ChangeLog-2004
    ld/testsuite/ChangeLog-2005
    ld/testsuite/ChangeLog-9303
    ld/testsuite/config/default.exp
    ld/testsuite/ld-alpha/align.s
    ld/testsuite/ld-alpha/alpha.exp
    ld/testsuite/ld-alpha/tlsbin.dd
    ld/testsuite/ld-alpha/tlsbin.rd
    ld/testsuite/ld-alpha/tlsbin.s
    ld/testsuite/ld-alpha/tlsbin.sd
    ld/testsuite/ld-alpha/tlsbin.td
    ld/testsuite/ld-alpha/tlsbinpic.s
    ld/testsuite/ld-alpha/tlsbinr.dd
    ld/testsuite/ld-alpha/tlsbinr.rd
    ld/testsuite/ld-alpha/tlsbinr.sd
    ld/testsuite/ld-alpha/tlsg.s
    ld/testsuite/ld-alpha/tlsg.sd
    ld/testsuite/ld-alpha/tlslib.s
    ld/testsuite/ld-alpha/tlspic.dd
    ld/testsuite/ld-alpha/tlspic.rd
    ld/testsuite/ld-alpha/tlspic.sd
    ld/testsuite/ld-alpha/tlspic.td
    ld/testsuite/ld-alpha/tlspic1.s
    ld/testsuite/ld-alpha/tlspic2.s
    ld/testsuite/ld-arm/arm-app-abs32.d
    ld/testsuite/ld-arm/arm-app-abs32.r
    ld/testsuite/ld-arm/arm-app-abs32.s
    ld/testsuite/ld-arm/arm-app.d
    ld/testsuite/ld-arm/arm-app.r
    ld/testsuite/ld-arm/arm-app.s
    ld/testsuite/ld-arm/arm-be8.d
    ld/testsuite/ld-arm/arm-be8.s
    ld/testsuite/ld-arm/arm-call.d
    ld/testsuite/ld-arm/arm-call1.s
    ld/testsuite/ld-arm/arm-call2.s
    ld/testsuite/ld-arm/arm-dyn.ld
    ld/testsuite/ld-arm/arm-elf.exp
    ld/testsuite/ld-arm/arm-lib-plt32.d
    ld/testsuite/ld-arm/arm-lib-plt32.r
    ld/testsuite/ld-arm/arm-lib-plt32.s
    ld/testsuite/ld-arm/arm-lib.d
    ld/testsuite/ld-arm/arm-lib.ld
    ld/testsuite/ld-arm/arm-lib.r
    ld/testsuite/ld-arm/arm-lib.s
    ld/testsuite/ld-arm/arm-movwt.d
    ld/testsuite/ld-arm/arm-movwt.s
    ld/testsuite/ld-arm/arm-rel31.d
    ld/testsuite/ld-arm/arm-rel31.s
    ld/testsuite/ld-arm/arm-static-app.d
    ld/testsuite/ld-arm/arm-static-app.r
    ld/testsuite/ld-arm/arm-static-app.s
    ld/testsuite/ld-arm/arm-target1-abs.d
    ld/testsuite/ld-arm/arm-target1-rel.d
    ld/testsuite/ld-arm/arm-target1.s
    ld/testsuite/ld-arm/arm-target2-abs.d
    ld/testsuite/ld-arm/arm-target2-got-rel.d
    ld/testsuite/ld-arm/arm-target2-rel.d
    ld/testsuite/ld-arm/arm-target2.s
    ld/testsuite/ld-arm/arm.ld
    ld/testsuite/ld-arm/group-relocs-alu-bad.d
    ld/testsuite/ld-arm/group-relocs-alu-bad.s
    ld/testsuite/ld-arm/group-relocs-ldc-bad.d
    ld/testsuite/ld-arm/group-relocs-ldc-bad.s
    ld/testsuite/ld-arm/group-relocs-ldr-bad.d
    ld/testsuite/ld-arm/group-relocs-ldr-bad.s
    ld/testsuite/ld-arm/group-relocs-ldrs-bad.d
    ld/testsuite/ld-arm/group-relocs-ldrs-bad.s
    ld/testsuite/ld-arm/group-relocs.d
    ld/testsuite/ld-arm/group-relocs.s
    ld/testsuite/ld-arm/mixed-app-v5.d
    ld/testsuite/ld-arm/mixed-app.d
    ld/testsuite/ld-arm/mixed-app.r
    ld/testsuite/ld-arm/mixed-app.s
    ld/testsuite/ld-arm/mixed-app.sym
    ld/testsuite/ld-arm/mixed-lib.d
    ld/testsuite/ld-arm/mixed-lib.r
    ld/testsuite/ld-arm/mixed-lib.s
    ld/testsuite/ld-arm/mixed-lib.sym
    ld/testsuite/ld-arm/thumb-entry.d
    ld/testsuite/ld-arm/thumb-entry.s
    ld/testsuite/ld-arm/thumb-rel32.d
    ld/testsuite/ld-arm/thumb-rel32.s
    ld/testsuite/ld-arm/tls-app.d
    ld/testsuite/ld-arm/tls-app.r
    ld/testsuite/ld-arm/tls-app.s
    ld/testsuite/ld-arm/tls-lib.d
    ld/testsuite/ld-arm/tls-lib.r
    ld/testsuite/ld-arm/tls-lib.s
    ld/testsuite/ld-arm/use-thumb-lib.s
    ld/testsuite/ld-arm/use-thumb-lib.sym
    ld/testsuite/ld-arm/vxworks1-lib.dd
    ld/testsuite/ld-arm/vxworks1-lib.nd
    ld/testsuite/ld-arm/vxworks1-lib.rd
    ld/testsuite/ld-arm/vxworks1-lib.s
    ld/testsuite/ld-arm/vxworks1-static.d
    ld/testsuite/ld-arm/vxworks1.dd
    ld/testsuite/ld-arm/vxworks1.ld
    ld/testsuite/ld-arm/vxworks1.rd
    ld/testsuite/ld-arm/vxworks1.s
    ld/testsuite/ld-arm/vxworks2-static.sd
    ld/testsuite/ld-arm/vxworks2.s
    ld/testsuite/ld-arm/vxworks2.sd
    ld/testsuite/ld-auto-import/auto-import.exp
    ld/testsuite/ld-auto-import/client.c
    ld/testsuite/ld-auto-import/dll.c
    ld/testsuite/ld-bootstrap/bootstrap.exp
    ld/testsuite/ld-cdtest/cdtest-bar.cc
    ld/testsuite/ld-cdtest/cdtest-foo.cc
    ld/testsuite/ld-cdtest/cdtest-foo.h
    ld/testsuite/ld-cdtest/cdtest-main.cc
    ld/testsuite/ld-cdtest/cdtest-nrv.dat
    ld/testsuite/ld-cdtest/cdtest.dat
    ld/testsuite/ld-cdtest/cdtest.exp
    ld/testsuite/ld-checks/asm.s
    ld/testsuite/ld-checks/checks.exp
    ld/testsuite/ld-checks/script
    ld/testsuite/ld-cris/badgotr1.d
    ld/testsuite/ld-cris/comref1.s
    ld/testsuite/ld-cris/cris.exp
    ld/testsuite/ld-cris/def2.d
    ld/testsuite/ld-cris/def3.d
    ld/testsuite/ld-cris/dso-1.s
    ld/testsuite/ld-cris/dso-2.s
    ld/testsuite/ld-cris/dso-3.s
    ld/testsuite/ld-cris/dsofnf.s
    ld/testsuite/ld-cris/dsofnf2.s
    ld/testsuite/ld-cris/dsov32-1.s
    ld/testsuite/ld-cris/dsov32-2.s
    ld/testsuite/ld-cris/dsov32-3.s
    ld/testsuite/ld-cris/dsov32-4.s
    ld/testsuite/ld-cris/euwref1.s
    ld/testsuite/ld-cris/expdref1.s
    ld/testsuite/ld-cris/expdyn1.d
    ld/testsuite/ld-cris/expdyn1.s
    ld/testsuite/ld-cris/expdyn2.d
    ld/testsuite/ld-cris/expdyn3.d
    ld/testsuite/ld-cris/expdyn4.d
    ld/testsuite/ld-cris/expdyn5.d
    ld/testsuite/ld-cris/expdyn6.d
    ld/testsuite/ld-cris/expdyn7.d
    ld/testsuite/ld-cris/globsym1ref.s
    ld/testsuite/ld-cris/globsymw1.s
    ld/testsuite/ld-cris/globsymw2.s
    ld/testsuite/ld-cris/gotplt1.d
    ld/testsuite/ld-cris/gotplt2.d
    ld/testsuite/ld-cris/gotplt3.d
    ld/testsuite/ld-cris/gotrel1.s
    ld/testsuite/ld-cris/gotrel2.s
    ld/testsuite/ld-cris/hiddef1.d
    ld/testsuite/ld-cris/hiddef1.s
    ld/testsuite/ld-cris/hide1
    ld/testsuite/ld-cris/hidrefgotplt1.s
    ld/testsuite/ld-cris/ldsym1.d
    ld/testsuite/ld-cris/libdso-1.d
    ld/testsuite/ld-cris/libdso-10.d
    ld/testsuite/ld-cris/libdso-11.d
    ld/testsuite/ld-cris/libdso-12.d
    ld/testsuite/ld-cris/libdso-13.d
    ld/testsuite/ld-cris/libdso-14.d
    ld/testsuite/ld-cris/libdso-2.d
    ld/testsuite/ld-cris/libdso-3.d
    ld/testsuite/ld-cris/libdso-4.d
    ld/testsuite/ld-cris/locref1.d
    ld/testsuite/ld-cris/locref1.s
    ld/testsuite/ld-cris/locref2.d
    ld/testsuite/ld-cris/locref2.s
    ld/testsuite/ld-cris/move-1.s
    ld/testsuite/ld-cris/nodyn4.d
    ld/testsuite/ld-cris/nodyn5.d
    ld/testsuite/ld-cris/noglob1.d
    ld/testsuite/ld-cris/noglob1.s
    ld/testsuite/ld-cris/noov.d
    ld/testsuite/ld-cris/noov.s
    ld/testsuite/ld-cris/pv32-1.d
    ld/testsuite/ld-cris/pv32.s
    ld/testsuite/ld-cris/stabs1.s
    ld/testsuite/ld-cris/start1.s
    ld/testsuite/ld-cris/undef1.d
    ld/testsuite/ld-cris/undef2.d
    ld/testsuite/ld-cris/undef3.d
    ld/testsuite/ld-cris/v10-v32.d
    ld/testsuite/ld-cris/v10-va.d
    ld/testsuite/ld-cris/v32-ba-1.d
    ld/testsuite/ld-cris/v32-ba-1.s
    ld/testsuite/ld-cris/v32-bin-1.d
    ld/testsuite/ld-cris/v32-bin-1.s
    ld/testsuite/ld-cris/v32-v10.d
    ld/testsuite/ld-cris/v32-va.d
    ld/testsuite/ld-cris/va-v10.d
    ld/testsuite/ld-cris/va-v32.d
    ld/testsuite/ld-cris/warn1.d
    ld/testsuite/ld-cris/warn2.d
    ld/testsuite/ld-cris/warn3.d
    ld/testsuite/ld-cris/warn4.d
    ld/testsuite/ld-cris/weakref1.d
    ld/testsuite/ld-cris/weakref2.d
    ld/testsuite/ld-crx/crx.exp
    ld/testsuite/ld-crx/crx.ld
    ld/testsuite/ld-crx/reloc-abs32.d
    ld/testsuite/ld-crx/reloc-abs32.s
    ld/testsuite/ld-crx/reloc-imm16.d
    ld/testsuite/ld-crx/reloc-imm16.s
    ld/testsuite/ld-crx/reloc-imm32.d
    ld/testsuite/ld-crx/reloc-imm32.s
    ld/testsuite/ld-crx/reloc-num16.d
    ld/testsuite/ld-crx/reloc-num16.s
    ld/testsuite/ld-crx/reloc-num32.d
    ld/testsuite/ld-crx/reloc-num32.s
    ld/testsuite/ld-crx/reloc-num8.d
    ld/testsuite/ld-crx/reloc-num8.s
    ld/testsuite/ld-crx/reloc-regrel12.d
    ld/testsuite/ld-crx/reloc-regrel12.s
    ld/testsuite/ld-crx/reloc-regrel22.d
    ld/testsuite/ld-crx/reloc-regrel22.s
    ld/testsuite/ld-crx/reloc-regrel28.d
    ld/testsuite/ld-crx/reloc-regrel28.s
    ld/testsuite/ld-crx/reloc-regrel32.d
    ld/testsuite/ld-crx/reloc-regrel32.s
    ld/testsuite/ld-crx/reloc-rel16.d
    ld/testsuite/ld-crx/reloc-rel16.s
    ld/testsuite/ld-crx/reloc-rel24.d
    ld/testsuite/ld-crx/reloc-rel24.s
    ld/testsuite/ld-crx/reloc-rel32.d
    ld/testsuite/ld-crx/reloc-rel32.s
    ld/testsuite/ld-crx/reloc-rel4.d
    ld/testsuite/ld-crx/reloc-rel4.s
    ld/testsuite/ld-crx/reloc-rel8-cmp.d
    ld/testsuite/ld-crx/reloc-rel8-cmp.s
    ld/testsuite/ld-crx/reloc-rel8.d
    ld/testsuite/ld-crx/reloc-rel8.s
    ld/testsuite/ld-cygwin/exe-export.exp
    ld/testsuite/ld-cygwin/testdll.c
    ld/testsuite/ld-cygwin/testdll.def
    ld/testsuite/ld-cygwin/testexe.c
    ld/testsuite/ld-cygwin/testexe.def
    ld/testsuite/ld-d10v/d10v.exp
    ld/testsuite/ld-d10v/default_layout.d
    ld/testsuite/ld-d10v/linktest-001.s
    ld/testsuite/ld-d10v/linktest-002.lt
    ld/testsuite/ld-d10v/linktest-002.s
    ld/testsuite/ld-d10v/regression-001.lt
    ld/testsuite/ld-d10v/regression-001.s
    ld/testsuite/ld-d10v/reloc-001.d
    ld/testsuite/ld-d10v/reloc-001.ld
    ld/testsuite/ld-d10v/reloc-001.s
    ld/testsuite/ld-d10v/reloc-002.d
    ld/testsuite/ld-d10v/reloc-002.ld
    ld/testsuite/ld-d10v/reloc-003.d
    ld/testsuite/ld-d10v/reloc-003.ld
    ld/testsuite/ld-d10v/reloc-004.d
    ld/testsuite/ld-d10v/reloc-004.ld
    ld/testsuite/ld-d10v/reloc-005.d
    ld/testsuite/ld-d10v/reloc-005.ld
    ld/testsuite/ld-d10v/reloc-005.s
    ld/testsuite/ld-d10v/reloc-006.d
    ld/testsuite/ld-d10v/reloc-006.ld
    ld/testsuite/ld-d10v/reloc-007.d
    ld/testsuite/ld-d10v/reloc-007.ld
    ld/testsuite/ld-d10v/reloc-008.d
    ld/testsuite/ld-d10v/reloc-008.ld
    ld/testsuite/ld-d10v/reloc-009.d
    ld/testsuite/ld-d10v/reloc-009.ld
    ld/testsuite/ld-d10v/reloc-009.s
    ld/testsuite/ld-d10v/reloc-010.d
    ld/testsuite/ld-d10v/reloc-010.ld
    ld/testsuite/ld-d10v/reloc-011.d
    ld/testsuite/ld-d10v/reloc-011.ld
    ld/testsuite/ld-d10v/reloc-012.d
    ld/testsuite/ld-d10v/reloc-012.ld
    ld/testsuite/ld-d10v/reloc-013.d
    ld/testsuite/ld-d10v/reloc-013.ld
    ld/testsuite/ld-d10v/reloc-014.d
    ld/testsuite/ld-d10v/reloc-014.ld
    ld/testsuite/ld-d10v/reloc-015.d
    ld/testsuite/ld-d10v/reloc-015.ld
    ld/testsuite/ld-d10v/reloc-016.d
    ld/testsuite/ld-d10v/reloc-016.ld
    ld/testsuite/ld-d10v/simple.s
    ld/testsuite/ld-discard/discard.exp
    ld/testsuite/ld-discard/discard.ld
    ld/testsuite/ld-discard/exit.s
    ld/testsuite/ld-discard/extern.d
    ld/testsuite/ld-discard/extern.s
    ld/testsuite/ld-discard/start.d
    ld/testsuite/ld-discard/start.s
    ld/testsuite/ld-discard/static.d
    ld/testsuite/ld-discard/static.s
    ld/testsuite/ld-elf/begin.c
    ld/testsuite/ld-elf/binutils.exp
    ld/testsuite/ld-elf/commonpage1.d
    ld/testsuite/ld-elf/eh1.d
    ld/testsuite/ld-elf/eh1.s
    ld/testsuite/ld-elf/eh1a.s
    ld/testsuite/ld-elf/eh2.d
    ld/testsuite/ld-elf/eh2a.s
    ld/testsuite/ld-elf/eh3.d
    ld/testsuite/ld-elf/eh3.s
    ld/testsuite/ld-elf/eh3a.s
    ld/testsuite/ld-elf/elf.exp
    ld/testsuite/ld-elf/empty.d
    ld/testsuite/ld-elf/empty.s
    ld/testsuite/ld-elf/empty2.d
    ld/testsuite/ld-elf/empty2.s
    ld/testsuite/ld-elf/end.c
    ld/testsuite/ld-elf/endhidden.c
    ld/testsuite/ld-elf/endprotected.c
    ld/testsuite/ld-elf/exclude.exp
    ld/testsuite/ld-elf/exclude1.s
    ld/testsuite/ld-elf/exclude2.s
    ld/testsuite/ld-elf/fini.c
    ld/testsuite/ld-elf/fini.out
    ld/testsuite/ld-elf/foo.c
    ld/testsuite/ld-elf/foo.map
    ld/testsuite/ld-elf/frame.exp
    ld/testsuite/ld-elf/frame.s
    ld/testsuite/ld-elf/group.ld
    ld/testsuite/ld-elf/group1.d
    ld/testsuite/ld-elf/group1a.s
    ld/testsuite/ld-elf/group1b.s
    ld/testsuite/ld-elf/group2.d
    ld/testsuite/ld-elf/hidden.out
    ld/testsuite/ld-elf/init.c
    ld/testsuite/ld-elf/init.out
    ld/testsuite/ld-elf/main.c
    ld/testsuite/ld-elf/maxpage1.d
    ld/testsuite/ld-elf/maxpage1.s
    ld/testsuite/ld-elf/maxpage2.d
    ld/testsuite/ld-elf/merge.d
    ld/testsuite/ld-elf/merge.ld
    ld/testsuite/ld-elf/merge.s
    ld/testsuite/ld-elf/merge2.d
    ld/testsuite/ld-elf/merge2.s
    ld/testsuite/ld-elf/normal.out
    ld/testsuite/ld-elf/orphan.d
    ld/testsuite/ld-elf/orphan.ld
    ld/testsuite/ld-elf/orphan.s
    ld/testsuite/ld-elf/orphan2.d
    ld/testsuite/ld-elf/orphan2.s
    ld/testsuite/ld-elf/preinit.c
    ld/testsuite/ld-elf/preinit.out
    ld/testsuite/ld-elf/sec64k.exp
    ld/testsuite/ld-elf/shared.exp
    ld/testsuite/ld-elf/stab.d
    ld/testsuite/ld-elf/start.s
    ld/testsuite/ld-elf/symbol1ref.s
    ld/testsuite/ld-elf/symbol1w.s
    ld/testsuite/ld-elf/table.s
    ld/testsuite/ld-elf/tbss.s
    ld/testsuite/ld-elf/tbss1.s
    ld/testsuite/ld-elf/tbss2.s
    ld/testsuite/ld-elf/tdata1.s
    ld/testsuite/ld-elf/tdata2.s
    ld/testsuite/ld-elf/tls_common.exp
    ld/testsuite/ld-elf/tls_common.s
    ld/testsuite/ld-elf/unknown.d
    ld/testsuite/ld-elf/unknown2.d
    ld/testsuite/ld-elf/unknown2.s
    ld/testsuite/ld-elf/warn1.d
    ld/testsuite/ld-elfcomm/common1a.c
    ld/testsuite/ld-elfcomm/common1b.c
    ld/testsuite/ld-elfcomm/elfcomm.exp
    ld/testsuite/ld-elfvers/vers.exp
    ld/testsuite/ld-elfvers/vers1.c
    ld/testsuite/ld-elfvers/vers1.dsym
    ld/testsuite/ld-elfvers/vers1.map
    ld/testsuite/ld-elfvers/vers1.sym
    ld/testsuite/ld-elfvers/vers1.ver
    ld/testsuite/ld-elfvers/vers13.asym
    ld/testsuite/ld-elfvers/vers15.c
    ld/testsuite/ld-elfvers/vers15.dsym
    ld/testsuite/ld-elfvers/vers15.sym
    ld/testsuite/ld-elfvers/vers15.ver
    ld/testsuite/ld-elfvers/vers16.c
    ld/testsuite/ld-elfvers/vers16.dsym
    ld/testsuite/ld-elfvers/vers16.map
    ld/testsuite/ld-elfvers/vers16a.c
    ld/testsuite/ld-elfvers/vers16a.dsym
    ld/testsuite/ld-elfvers/vers16a.ver
    ld/testsuite/ld-elfvers/vers17.c
    ld/testsuite/ld-elfvers/vers17.dsym
    ld/testsuite/ld-elfvers/vers17.map
    ld/testsuite/ld-elfvers/vers17.ver
    ld/testsuite/ld-elfvers/vers18.c
    ld/testsuite/ld-elfvers/vers18.dsym
    ld/testsuite/ld-elfvers/vers18.map
    ld/testsuite/ld-elfvers/vers18.sym
    ld/testsuite/ld-elfvers/vers18.ver
    ld/testsuite/ld-elfvers/vers19.c
    ld/testsuite/ld-elfvers/vers19.dsym
    ld/testsuite/ld-elfvers/vers19.ver
    ld/testsuite/ld-elfvers/vers2.c
    ld/testsuite/ld-elfvers/vers2.dsym
    ld/testsuite/ld-elfvers/vers2.map
    ld/testsuite/ld-elfvers/vers2.ver
    ld/testsuite/ld-elfvers/vers20.c
    ld/testsuite/ld-elfvers/vers20.dsym
    ld/testsuite/ld-elfvers/vers20.map
    ld/testsuite/ld-elfvers/vers20.ver
    ld/testsuite/ld-elfvers/vers20a.ver
    ld/testsuite/ld-elfvers/vers21.c
    ld/testsuite/ld-elfvers/vers21.dsym
    ld/testsuite/ld-elfvers/vers21.map
    ld/testsuite/ld-elfvers/vers21.sym
    ld/testsuite/ld-elfvers/vers21.ver
    ld/testsuite/ld-elfvers/vers22.c
    ld/testsuite/ld-elfvers/vers22.dsym
    ld/testsuite/ld-elfvers/vers22.map
    ld/testsuite/ld-elfvers/vers22.ver
    ld/testsuite/ld-elfvers/vers22a.c
    ld/testsuite/ld-elfvers/vers22a.dsym
    ld/testsuite/ld-elfvers/vers22a.sym
    ld/testsuite/ld-elfvers/vers22a.ver
    ld/testsuite/ld-elfvers/vers22b.c
    ld/testsuite/ld-elfvers/vers22b.dsym
    ld/testsuite/ld-elfvers/vers22b.ver
    ld/testsuite/ld-elfvers/vers23.c
    ld/testsuite/ld-elfvers/vers23.dsym
    ld/testsuite/ld-elfvers/vers23.ver
    ld/testsuite/ld-elfvers/vers23a.c
    ld/testsuite/ld-elfvers/vers23a.dsym
    ld/testsuite/ld-elfvers/vers23a.map
    ld/testsuite/ld-elfvers/vers23a.sym
    ld/testsuite/ld-elfvers/vers23a.ver
    ld/testsuite/ld-elfvers/vers23b.c
    ld/testsuite/ld-elfvers/vers23b.dsym
    ld/testsuite/ld-elfvers/vers23b.map
    ld/testsuite/ld-elfvers/vers23b.ver
    ld/testsuite/ld-elfvers/vers23c.ver
    ld/testsuite/ld-elfvers/vers23d.dsym
    ld/testsuite/ld-elfvers/vers24.map
    ld/testsuite/ld-elfvers/vers24.rd
    ld/testsuite/ld-elfvers/vers24a.c
    ld/testsuite/ld-elfvers/vers24b.c
    ld/testsuite/ld-elfvers/vers24c.c
    ld/testsuite/ld-elfvers/vers25a.c
    ld/testsuite/ld-elfvers/vers25a.dsym
    ld/testsuite/ld-elfvers/vers25a.map
    ld/testsuite/ld-elfvers/vers25a.ver
    ld/testsuite/ld-elfvers/vers25b.c
    ld/testsuite/ld-elfvers/vers25b.dsym
    ld/testsuite/ld-elfvers/vers25b.ver
    ld/testsuite/ld-elfvers/vers26a.c
    ld/testsuite/ld-elfvers/vers26a.dsym
    ld/testsuite/ld-elfvers/vers26a.map
    ld/testsuite/ld-elfvers/vers26a.ver
    ld/testsuite/ld-elfvers/vers26b.c
    ld/testsuite/ld-elfvers/vers26b.dsym
    ld/testsuite/ld-elfvers/vers26b.ver
    ld/testsuite/ld-elfvers/vers27a.c
    ld/testsuite/ld-elfvers/vers27a.dsym
    ld/testsuite/ld-elfvers/vers27a.map
    ld/testsuite/ld-elfvers/vers27a.ver
    ld/testsuite/ld-elfvers/vers27b.c
    ld/testsuite/ld-elfvers/vers27b.dsym
    ld/testsuite/ld-elfvers/vers27b.ver
    ld/testsuite/ld-elfvers/vers27c.c
    ld/testsuite/ld-elfvers/vers27c.dsym
    ld/testsuite/ld-elfvers/vers27c.ver
    ld/testsuite/ld-elfvers/vers27d.dsym
    ld/testsuite/ld-elfvers/vers27d.sym
    ld/testsuite/ld-elfvers/vers27d.ver
    ld/testsuite/ld-elfvers/vers27d1.c
    ld/testsuite/ld-elfvers/vers27d2.c
    ld/testsuite/ld-elfvers/vers27d3.c
    ld/testsuite/ld-elfvers/vers27d4.dsym
    ld/testsuite/ld-elfvers/vers27d4.ver
    ld/testsuite/ld-elfvers/vers28a.c
    ld/testsuite/ld-elfvers/vers28a.dsym
    ld/testsuite/ld-elfvers/vers28a.ver
    ld/testsuite/ld-elfvers/vers28b.c
    ld/testsuite/ld-elfvers/vers28b.dsym
    ld/testsuite/ld-elfvers/vers28b.map
    ld/testsuite/ld-elfvers/vers28b.ver
    ld/testsuite/ld-elfvers/vers28c.c
    ld/testsuite/ld-elfvers/vers28c.dsym
    ld/testsuite/ld-elfvers/vers28c.ver
    ld/testsuite/ld-elfvers/vers29.c
    ld/testsuite/ld-elfvers/vers29.dsym
    ld/testsuite/ld-elfvers/vers29.ver
    ld/testsuite/ld-elfvers/vers3.c
    ld/testsuite/ld-elfvers/vers3.dsym
    ld/testsuite/ld-elfvers/vers3.ver
    ld/testsuite/ld-elfvers/vers30.c
    ld/testsuite/ld-elfvers/vers30.dsym
    ld/testsuite/ld-elfvers/vers30.map
    ld/testsuite/ld-elfvers/vers30.ver
    ld/testsuite/ld-elfvers/vers31.c
    ld/testsuite/ld-elfvers/vers31.dsym
    ld/testsuite/ld-elfvers/vers31.map
    ld/testsuite/ld-elfvers/vers31.ver
    ld/testsuite/ld-elfvers/vers4.c
    ld/testsuite/ld-elfvers/vers4.sym
    ld/testsuite/ld-elfvers/vers4a.dsym
    ld/testsuite/ld-elfvers/vers4a.sym
    ld/testsuite/ld-elfvers/vers4a.ver
    ld/testsuite/ld-elfvers/vers5.c
    ld/testsuite/ld-elfvers/vers6.c
    ld/testsuite/ld-elfvers/vers6.dsym
    ld/testsuite/ld-elfvers/vers6.sym
    ld/testsuite/ld-elfvers/vers6.ver
    ld/testsuite/ld-elfvers/vers7.c
    ld/testsuite/ld-elfvers/vers7.map
    ld/testsuite/ld-elfvers/vers7a.c
    ld/testsuite/ld-elfvers/vers7a.dsym
    ld/testsuite/ld-elfvers/vers7a.sym
    ld/testsuite/ld-elfvers/vers7a.ver
    ld/testsuite/ld-elfvers/vers8.c
    ld/testsuite/ld-elfvers/vers8.map
    ld/testsuite/ld-elfvers/vers8.ver
    ld/testsuite/ld-elfvers/vers9.c
    ld/testsuite/ld-elfvers/vers9.dsym
    ld/testsuite/ld-elfvers/vers9.sym
    ld/testsuite/ld-elfvers/vers9.ver
    ld/testsuite/ld-elfvsb/common.c
    ld/testsuite/ld-elfvsb/define.s
    ld/testsuite/ld-elfvsb/elf-offset.ld
    ld/testsuite/ld-elfvsb/elfvsb.dat
    ld/testsuite/ld-elfvsb/elfvsb.exp
    ld/testsuite/ld-elfvsb/hidden0.d
    ld/testsuite/ld-elfvsb/hidden1.d
    ld/testsuite/ld-elfvsb/hidden2.d
    ld/testsuite/ld-elfvsb/hidden2.ld
    ld/testsuite/ld-elfvsb/hidden2.s
    ld/testsuite/ld-elfvsb/internal0.d
    ld/testsuite/ld-elfvsb/internal1.d
    ld/testsuite/ld-elfvsb/main.c
    ld/testsuite/ld-elfvsb/protected0.d
    ld/testsuite/ld-elfvsb/protected1.d
    ld/testsuite/ld-elfvsb/sh1.c
    ld/testsuite/ld-elfvsb/sh2.c
    ld/testsuite/ld-elfvsb/sh3.c
    ld/testsuite/ld-elfvsb/test.c
    ld/testsuite/ld-elfvsb/undef.s
    ld/testsuite/ld-elfweak/bar.c
    ld/testsuite/ld-elfweak/bar1a.c
    ld/testsuite/ld-elfweak/bar1b.c
    ld/testsuite/ld-elfweak/bar1c.c
    ld/testsuite/ld-elfweak/dso.dsym
    ld/testsuite/ld-elfweak/dsodata.dsym
    ld/testsuite/ld-elfweak/dsow.dsym
    ld/testsuite/ld-elfweak/dsowdata.dsym
    ld/testsuite/ld-elfweak/elfweak.exp
    ld/testsuite/ld-elfweak/foo.c
    ld/testsuite/ld-elfweak/foo1a.c
    ld/testsuite/ld-elfweak/foo1b.c
    ld/testsuite/ld-elfweak/main.c
    ld/testsuite/ld-elfweak/main1.c
    ld/testsuite/ld-elfweak/size.dat
    ld/testsuite/ld-elfweak/size2.d
    ld/testsuite/ld-elfweak/size2a.s
    ld/testsuite/ld-elfweak/size2b.s
    ld/testsuite/ld-elfweak/size_bar.c
    ld/testsuite/ld-elfweak/size_foo.c
    ld/testsuite/ld-elfweak/size_main.c
    ld/testsuite/ld-elfweak/strong.dat
    ld/testsuite/ld-elfweak/strong.sym
    ld/testsuite/ld-elfweak/strongcomm.sym
    ld/testsuite/ld-elfweak/strongdata.dat
    ld/testsuite/ld-elfweak/strongdata.sym
    ld/testsuite/ld-elfweak/weak.dat
    ld/testsuite/ld-elfweak/weak.dsym
    ld/testsuite/ld-elfweak/weakdata.dat
    ld/testsuite/ld-elfweak/weakdata.dsym
    ld/testsuite/ld-fastcall/export.s
    ld/testsuite/ld-fastcall/fastcall.exp
    ld/testsuite/ld-fastcall/import.s
    ld/testsuite/ld-frv/fdpic-pie-1.d
    ld/testsuite/ld-frv/fdpic-pie-2.d
    ld/testsuite/ld-frv/fdpic-pie-5.d
    ld/testsuite/ld-frv/fdpic-pie-6-fail.d
    ld/testsuite/ld-frv/fdpic-pie-6.d
    ld/testsuite/ld-frv/fdpic-pie-7.d
    ld/testsuite/ld-frv/fdpic-pie-8.d
    ld/testsuite/ld-frv/fdpic-shared-1.d
    ld/testsuite/ld-frv/fdpic-shared-2-fail.d
    ld/testsuite/ld-frv/fdpic-shared-2.d
    ld/testsuite/ld-frv/fdpic-shared-3.d
    ld/testsuite/ld-frv/fdpic-shared-4.d
    ld/testsuite/ld-frv/fdpic-shared-5.d
    ld/testsuite/ld-frv/fdpic-shared-6-fail.d
    ld/testsuite/ld-frv/fdpic-shared-6.d
    ld/testsuite/ld-frv/fdpic-shared-7.d
    ld/testsuite/ld-frv/fdpic-shared-8-fail.d
    ld/testsuite/ld-frv/fdpic-shared-8.d
    ld/testsuite/ld-frv/fdpic-shared-local-2.d
    ld/testsuite/ld-frv/fdpic-shared-local-8.d
    ld/testsuite/ld-frv/fdpic-static-1.d
    ld/testsuite/ld-frv/fdpic-static-2.d
    ld/testsuite/ld-frv/fdpic-static-5.d
    ld/testsuite/ld-frv/fdpic-static-6.d
    ld/testsuite/ld-frv/fdpic-static-7.d
    ld/testsuite/ld-frv/fdpic-static-8.d
    ld/testsuite/ld-frv/fdpic.exp
    ld/testsuite/ld-frv/fdpic1.s
    ld/testsuite/ld-frv/fdpic2.ldv
    ld/testsuite/ld-frv/fdpic2.s
    ld/testsuite/ld-frv/fdpic2min.ldv
    ld/testsuite/ld-frv/fdpic3.s
    ld/testsuite/ld-frv/fdpic4.s
    ld/testsuite/ld-frv/fdpic5.s
    ld/testsuite/ld-frv/fdpic6.ldv
    ld/testsuite/ld-frv/fdpic6.s
    ld/testsuite/ld-frv/fdpic7.s
    ld/testsuite/ld-frv/fdpic8.ldv
    ld/testsuite/ld-frv/fdpic8.s
    ld/testsuite/ld-frv/fdpic8min.ldv
    ld/testsuite/ld-frv/fr450-link.d
    ld/testsuite/ld-frv/fr450-linka.s
    ld/testsuite/ld-frv/fr450-linkb.s
    ld/testsuite/ld-frv/fr450-linkc.s
    ld/testsuite/ld-frv/frv-elf.exp
    ld/testsuite/ld-frv/tls-1-dep.s
    ld/testsuite/ld-frv/tls-1-shared.lds
    ld/testsuite/ld-frv/tls-1.s
    ld/testsuite/ld-frv/tls-2.s
    ld/testsuite/ld-frv/tls-3.s
    ld/testsuite/ld-frv/tls-dynamic-1.d
    ld/testsuite/ld-frv/tls-dynamic-2.d
    ld/testsuite/ld-frv/tls-dynamic-3.d
    ld/testsuite/ld-frv/tls-initial-shared-2.d
    ld/testsuite/ld-frv/tls-pie-1.d
    ld/testsuite/ld-frv/tls-pie-3.d
    ld/testsuite/ld-frv/tls-relax-dynamic-1.d
    ld/testsuite/ld-frv/tls-relax-dynamic-2.d
    ld/testsuite/ld-frv/tls-relax-dynamic-3.d
    ld/testsuite/ld-frv/tls-relax-initial-shared-2.d
    ld/testsuite/ld-frv/tls-relax-pie-1.d
    ld/testsuite/ld-frv/tls-relax-pie-3.d
    ld/testsuite/ld-frv/tls-relax-shared-1.d
    ld/testsuite/ld-frv/tls-relax-shared-2.d
    ld/testsuite/ld-frv/tls-relax-shared-3.d
    ld/testsuite/ld-frv/tls-relax-static-1.d
    ld/testsuite/ld-frv/tls-relax-static-3.d
    ld/testsuite/ld-frv/tls-shared-1-fail.d
    ld/testsuite/ld-frv/tls-shared-1.d
    ld/testsuite/ld-frv/tls-shared-2.d
    ld/testsuite/ld-frv/tls-shared-3.d
    ld/testsuite/ld-frv/tls-static-1.d
    ld/testsuite/ld-frv/tls-static-3.d
    ld/testsuite/ld-frv/tls.exp
    ld/testsuite/ld-h8300/gcsection.d
    ld/testsuite/ld-h8300/gcsection.s
    ld/testsuite/ld-h8300/h8300.exp
    ld/testsuite/ld-h8300/relax-2.d
    ld/testsuite/ld-h8300/relax-2.s
    ld/testsuite/ld-h8300/relax-3-coff.d
    ld/testsuite/ld-h8300/relax-3.d
    ld/testsuite/ld-h8300/relax-3.s
    ld/testsuite/ld-h8300/relax-4-coff.d
    ld/testsuite/ld-h8300/relax-4.d
    ld/testsuite/ld-h8300/relax-4.s
    ld/testsuite/ld-h8300/relax-5-coff.d
    ld/testsuite/ld-h8300/relax-5.d
    ld/testsuite/ld-h8300/relax-5.s
    ld/testsuite/ld-h8300/relax-6-coff.d
    ld/testsuite/ld-h8300/relax-6.d
    ld/testsuite/ld-h8300/relax-6.s
    ld/testsuite/ld-h8300/relax.d
    ld/testsuite/ld-h8300/relax.s
    ld/testsuite/ld-i386/abs.d
    ld/testsuite/ld-i386/abs.s
    ld/testsuite/ld-i386/combreloc.d
    ld/testsuite/ld-i386/combreloc.s
    ld/testsuite/ld-i386/emit-relocs.d
    ld/testsuite/ld-i386/emit-relocs.s
    ld/testsuite/ld-i386/i386.exp
    ld/testsuite/ld-i386/pcrel16.d
    ld/testsuite/ld-i386/pcrel16.s
    ld/testsuite/ld-i386/pcrel8.d
    ld/testsuite/ld-i386/pcrel8.s
    ld/testsuite/ld-i386/reloc.d
    ld/testsuite/ld-i386/reloc.s
    ld/testsuite/ld-i386/tlsbin.dd
    ld/testsuite/ld-i386/tlsbin.rd
    ld/testsuite/ld-i386/tlsbin.s
    ld/testsuite/ld-i386/tlsbin.sd
    ld/testsuite/ld-i386/tlsbin.td
    ld/testsuite/ld-i386/tlsbindesc.dd
    ld/testsuite/ld-i386/tlsbindesc.rd
    ld/testsuite/ld-i386/tlsbindesc.s
    ld/testsuite/ld-i386/tlsbindesc.sd
    ld/testsuite/ld-i386/tlsbindesc.td
    ld/testsuite/ld-i386/tlsbinpic.s
    ld/testsuite/ld-i386/tlsdesc.dd
    ld/testsuite/ld-i386/tlsdesc.rd
    ld/testsuite/ld-i386/tlsdesc.s
    ld/testsuite/ld-i386/tlsdesc.sd
    ld/testsuite/ld-i386/tlsdesc.td
    ld/testsuite/ld-i386/tlsg.s
    ld/testsuite/ld-i386/tlsg.sd
    ld/testsuite/ld-i386/tlsgdesc.dd
    ld/testsuite/ld-i386/tlsgdesc.rd
    ld/testsuite/ld-i386/tlsgdesc.s
    ld/testsuite/ld-i386/tlsindntpoff.dd
    ld/testsuite/ld-i386/tlsindntpoff.s
    ld/testsuite/ld-i386/tlslib.s
    ld/testsuite/ld-i386/tlsnopic.dd
    ld/testsuite/ld-i386/tlsnopic.rd
    ld/testsuite/ld-i386/tlsnopic.sd
    ld/testsuite/ld-i386/tlsnopic1.s
    ld/testsuite/ld-i386/tlsnopic2.s
    ld/testsuite/ld-i386/tlspic.dd
    ld/testsuite/ld-i386/tlspic.rd
    ld/testsuite/ld-i386/tlspic.sd
    ld/testsuite/ld-i386/tlspic.td
    ld/testsuite/ld-i386/tlspic1.s
    ld/testsuite/ld-i386/tlspic2.s
    ld/testsuite/ld-i386/vxworks1-lib.dd
    ld/testsuite/ld-i386/vxworks1-lib.nd
    ld/testsuite/ld-i386/vxworks1-lib.rd
    ld/testsuite/ld-i386/vxworks1-lib.s
    ld/testsuite/ld-i386/vxworks1-static.d
    ld/testsuite/ld-i386/vxworks1.dd
    ld/testsuite/ld-i386/vxworks1.ld
    ld/testsuite/ld-i386/vxworks1.rd
    ld/testsuite/ld-i386/vxworks1.s
    ld/testsuite/ld-i386/vxworks2-static.sd
    ld/testsuite/ld-i386/vxworks2.s
    ld/testsuite/ld-i386/vxworks2.sd
    ld/testsuite/ld-i386/zero.s
    ld/testsuite/ld-ia64/ia64.exp
    ld/testsuite/ld-ia64/link-order.d
    ld/testsuite/ld-ia64/tlsbin.dd
    ld/testsuite/ld-ia64/tlsbin.rd
    ld/testsuite/ld-ia64/tlsbin.s
    ld/testsuite/ld-ia64/tlsbin.sd
    ld/testsuite/ld-ia64/tlsbin.td
    ld/testsuite/ld-ia64/tlsbinpic.s
    ld/testsuite/ld-ia64/tlsg.s
    ld/testsuite/ld-ia64/tlsg.sd
    ld/testsuite/ld-ia64/tlslib.s
    ld/testsuite/ld-ia64/tlspic.dd
    ld/testsuite/ld-ia64/tlspic.rd
    ld/testsuite/ld-ia64/tlspic.sd
    ld/testsuite/ld-ia64/tlspic.td
    ld/testsuite/ld-ia64/tlspic1.s
    ld/testsuite/ld-ia64/tlspic2.s
    ld/testsuite/ld-linkonce/linkonce.exp
    ld/testsuite/ld-linkonce/x.s
    ld/testsuite/ld-linkonce/y.s
    ld/testsuite/ld-linkonce/zeroeh.ld
    ld/testsuite/ld-linkonce/zeroehl32.d
    ld/testsuite/ld-m68hc11/adj-brset.d
    ld/testsuite/ld-m68hc11/adj-brset.s
    ld/testsuite/ld-m68hc11/adj-jump.d
    ld/testsuite/ld-m68hc11/adj-jump.s
    ld/testsuite/ld-m68hc11/bug-1403.d
    ld/testsuite/ld-m68hc11/bug-1403.s
    ld/testsuite/ld-m68hc11/bug-1417.d
    ld/testsuite/ld-m68hc11/bug-1417.s
    ld/testsuite/ld-m68hc11/bug-3331.d
    ld/testsuite/ld-m68hc11/bug-3331.s
    ld/testsuite/ld-m68hc11/far-hc11.d
    ld/testsuite/ld-m68hc11/far-hc11.s
    ld/testsuite/ld-m68hc11/far-hc12.d
    ld/testsuite/ld-m68hc11/far-hc12.ld
    ld/testsuite/ld-m68hc11/far-hc12.s
    ld/testsuite/ld-m68hc11/link-hc12.s
    ld/testsuite/ld-m68hc11/link-hcs12.d
    ld/testsuite/ld-m68hc11/link-hcs12.s
    ld/testsuite/ld-m68hc11/m68hc11.exp
    ld/testsuite/ld-m68hc11/relax-direct.d
    ld/testsuite/ld-m68hc11/relax-direct.s
    ld/testsuite/ld-m68hc11/relax-group.d
    ld/testsuite/ld-m68hc11/relax-group.s
    ld/testsuite/ld-m68k/isaa-mac.d
    ld/testsuite/ld-m68k/isaa-mac.s
    ld/testsuite/ld-m68k/isaa-nodiv.s
    ld/testsuite/ld-m68k/isaa.d
    ld/testsuite/ld-m68k/isaa.s
    ld/testsuite/ld-m68k/isaaplus.d
    ld/testsuite/ld-m68k/isaaplus.s
    ld/testsuite/ld-m68k/isab-float.d
    ld/testsuite/ld-m68k/isab-float.s
    ld/testsuite/ld-m68k/isab-nousp.s
    ld/testsuite/ld-m68k/isab.d
    ld/testsuite/ld-m68k/isab.s
    ld/testsuite/ld-m68k/m68k.exp
    ld/testsuite/ld-m68k/merge-error-1a.d
    ld/testsuite/ld-m68k/merge-error-1a.s
    ld/testsuite/ld-m68k/merge-error-1b.d
    ld/testsuite/ld-m68k/merge-error-1b.s
    ld/testsuite/ld-m68k/merge-error-1c.d
    ld/testsuite/ld-m68k/merge-error-1d.d
    ld/testsuite/ld-m68k/merge-error-1e.d
    ld/testsuite/ld-m68k/merge-ok-1a.d
    ld/testsuite/ld-m68k/merge-ok-1b.d
    ld/testsuite/ld-m68k/merge-ok-1c.d
    ld/testsuite/ld-m68k/merge.ld
    ld/testsuite/ld-m68k/plt1-68020.d
    ld/testsuite/ld-m68k/plt1-cpu32.d
    ld/testsuite/ld-m68k/plt1-empty.s
    ld/testsuite/ld-m68k/plt1-isab.d
    ld/testsuite/ld-m68k/plt1.ld
    ld/testsuite/ld-m68k/plt1.s
    ld/testsuite/ld-maxq/addend.dd
    ld/testsuite/ld-maxq/addend.s
    ld/testsuite/ld-maxq/maxq.exp
    ld/testsuite/ld-maxq/paddr.dd
    ld/testsuite/ld-maxq/paddr.s
    ld/testsuite/ld-maxq/paddr1.dd
    ld/testsuite/ld-maxq/paddr1.s
    ld/testsuite/ld-maxq/r32-1.s
    ld/testsuite/ld-maxq/r32-2.s
    ld/testsuite/ld-maxq/r32.dd
    ld/testsuite/ld-mips-elf/branch-misc-1.d
    ld/testsuite/ld-mips-elf/eh-frame1-n32.d
    ld/testsuite/ld-mips-elf/eh-frame1-n64.d
    ld/testsuite/ld-mips-elf/eh-frame1.ld
    ld/testsuite/ld-mips-elf/eh-frame1.s
    ld/testsuite/ld-mips-elf/eh-frame2-n32.d
    ld/testsuite/ld-mips-elf/eh-frame2-n64.d
    ld/testsuite/ld-mips-elf/eh-frame3.d
    ld/testsuite/ld-mips-elf/eh-frame4.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n32.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d
    ld/testsuite/ld-mips-elf/elf-rel-got-n64.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d
    ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d
    ld/testsuite/ld-mips-elf/emit-relocs-1.d
    ld/testsuite/ld-mips-elf/emit-relocs-1.ld
    ld/testsuite/ld-mips-elf/emit-relocs-1a.s
    ld/testsuite/ld-mips-elf/emit-relocs-1b.s
    ld/testsuite/ld-mips-elf/jalbal.d
    ld/testsuite/ld-mips-elf/jalbal.s
    ld/testsuite/ld-mips-elf/jaloverflow-2.d
    ld/testsuite/ld-mips-elf/jaloverflow-2.s
    ld/testsuite/ld-mips-elf/jaloverflow.d
    ld/testsuite/ld-mips-elf/jaloverflow.s
    ld/testsuite/ld-mips-elf/jr.s
    ld/testsuite/ld-mips-elf/mips-dyn.ld
    ld/testsuite/ld-mips-elf/mips-elf-flags.exp
    ld/testsuite/ld-mips-elf/mips-elf.exp
    ld/testsuite/ld-mips-elf/mips-lib.ld
    ld/testsuite/ld-mips-elf/mips16-1.d
    ld/testsuite/ld-mips-elf/mips16-1a.s
    ld/testsuite/ld-mips-elf/mips16-1b.s
    ld/testsuite/ld-mips-elf/mips16-call-global-1.s
    ld/testsuite/ld-mips-elf/mips16-call-global-2.s
    ld/testsuite/ld-mips-elf/mips16-call-global-3.s
    ld/testsuite/ld-mips-elf/mips16-call-global.d
    ld/testsuite/ld-mips-elf/mips16-hilo-n32.d
    ld/testsuite/ld-mips-elf/mips16-hilo.d
    ld/testsuite/ld-mips-elf/mips16-hilo.ld
    ld/testsuite/ld-mips-elf/mips16-hilo.s
    ld/testsuite/ld-mips-elf/multi-got-1-1.s
    ld/testsuite/ld-mips-elf/multi-got-1-2.s
    ld/testsuite/ld-mips-elf/multi-got-1.d
    ld/testsuite/ld-mips-elf/multi-got-no-shared-1.s
    ld/testsuite/ld-mips-elf/multi-got-no-shared-2.s
    ld/testsuite/ld-mips-elf/multi-got-no-shared.d
    ld/testsuite/ld-mips-elf/region1.d
    ld/testsuite/ld-mips-elf/region1.t
    ld/testsuite/ld-mips-elf/region1a.s
    ld/testsuite/ld-mips-elf/region1b.s
    ld/testsuite/ld-mips-elf/rel32-n32.d
    ld/testsuite/ld-mips-elf/rel32-o32.d
    ld/testsuite/ld-mips-elf/rel32.s
    ld/testsuite/ld-mips-elf/rel64.d
    ld/testsuite/ld-mips-elf/rel64.s
    ld/testsuite/ld-mips-elf/relax-jalr-n32-shared.d
    ld/testsuite/ld-mips-elf/relax-jalr-n32.d
    ld/testsuite/ld-mips-elf/relax-jalr-n64-shared.d
    ld/testsuite/ld-mips-elf/relax-jalr-n64.d
    ld/testsuite/ld-mips-elf/relax-jalr.s
    ld/testsuite/ld-mips-elf/reloc-1-n32.d
    ld/testsuite/ld-mips-elf/reloc-1-n64.d
    ld/testsuite/ld-mips-elf/reloc-1-rel.d
    ld/testsuite/ld-mips-elf/reloc-1a.s
    ld/testsuite/ld-mips-elf/reloc-1b.s
    ld/testsuite/ld-mips-elf/reloc-2.d
    ld/testsuite/ld-mips-elf/reloc-2.ld
    ld/testsuite/ld-mips-elf/reloc-2a.s
    ld/testsuite/ld-mips-elf/reloc-2b.s
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.d
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.ld
    ld/testsuite/ld-mips-elf/reloc-merge-lo16.s
    ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
    ld/testsuite/ld-mips-elf/stub-dynsym-1.ld
    ld/testsuite/ld-mips-elf/stub-dynsym-1.s
    ld/testsuite/ld-mips-elf/textrel-1.d
    ld/testsuite/ld-mips-elf/textrel-1.s
    ld/testsuite/ld-mips-elf/tls-hidden2-got.d
    ld/testsuite/ld-mips-elf/tls-hidden2.d
    ld/testsuite/ld-mips-elf/tls-hidden2a.s
    ld/testsuite/ld-mips-elf/tls-hidden2b.s
    ld/testsuite/ld-mips-elf/tls-hidden3.d
    ld/testsuite/ld-mips-elf/tls-hidden3.got
    ld/testsuite/ld-mips-elf/tls-hidden3.ld
    ld/testsuite/ld-mips-elf/tls-hidden3.r
    ld/testsuite/ld-mips-elf/tls-hidden3a.s
    ld/testsuite/ld-mips-elf/tls-hidden3b.s
    ld/testsuite/ld-mips-elf/tls-hidden4.got
    ld/testsuite/ld-mips-elf/tls-hidden4.r
    ld/testsuite/ld-mips-elf/tls-hidden4a.s
    ld/testsuite/ld-mips-elf/tls-hidden4b.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1-1.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1-2.s
    ld/testsuite/ld-mips-elf/tls-multi-got-1.d
    ld/testsuite/ld-mips-elf/tls-multi-got-1.got
    ld/testsuite/ld-mips-elf/tls-multi-got-1.r
    ld/testsuite/ld-mips-elf/tlsbin-o32.d
    ld/testsuite/ld-mips-elf/tlsbin-o32.got
    ld/testsuite/ld-mips-elf/tlsbin-o32.s
    ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-1.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32-2.s
    ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32-3.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32.d
    ld/testsuite/ld-mips-elf/tlsdyn-o32.got
    ld/testsuite/ld-mips-elf/tlsdyn-o32.s
    ld/testsuite/ld-mips-elf/tlslib-hidden.ver
    ld/testsuite/ld-mips-elf/tlslib-o32-hidden.got
    ld/testsuite/ld-mips-elf/tlslib-o32-ver.got
    ld/testsuite/ld-mips-elf/tlslib-o32.d
    ld/testsuite/ld-mips-elf/tlslib-o32.got
    ld/testsuite/ld-mips-elf/tlslib-o32.s
    ld/testsuite/ld-mips-elf/tlslib.ver
    ld/testsuite/ld-mips-elf/vxworks1-lib.dd
    ld/testsuite/ld-mips-elf/vxworks1-lib.nd
    ld/testsuite/ld-mips-elf/vxworks1-lib.rd
    ld/testsuite/ld-mips-elf/vxworks1-lib.s
    ld/testsuite/ld-mips-elf/vxworks1-static.d
    ld/testsuite/ld-mips-elf/vxworks1.dd
    ld/testsuite/ld-mips-elf/vxworks1.ld
    ld/testsuite/ld-mips-elf/vxworks1.rd
    ld/testsuite/ld-mips-elf/vxworks1.s
    ld/testsuite/ld-mips-elf/vxworks2-static.sd
    ld/testsuite/ld-mips-elf/vxworks2.s
    ld/testsuite/ld-mips-elf/vxworks2.sd
    ld/testsuite/ld-mmix/a.s
    ld/testsuite/ld-mmix/areg-256.s
    ld/testsuite/ld-mmix/areg-t.s
    ld/testsuite/ld-mmix/aregm.s
    ld/testsuite/ld-mmix/b-badfil1.d
    ld/testsuite/ld-mmix/b-badfil1.s
    ld/testsuite/ld-mmix/b-badfil2.d
    ld/testsuite/ld-mmix/b-badfil2.s
    ld/testsuite/ld-mmix/b-badfixo.d
    ld/testsuite/ld-mmix/b-badfixo.s
    ld/testsuite/ld-mmix/b-badloc.d
    ld/testsuite/ld-mmix/b-badloc.s
    ld/testsuite/ld-mmix/b-badlop.d
    ld/testsuite/ld-mmix/b-badlop.s
    ld/testsuite/ld-mmix/b-badm.d
    ld/testsuite/ld-mmix/b-badm2.s
    ld/testsuite/ld-mmix/b-badmain.s
    ld/testsuite/ld-mmix/b-badquot.d
    ld/testsuite/ld-mmix/b-badquot.s
    ld/testsuite/ld-mmix/b-badrx1.d
    ld/testsuite/ld-mmix/b-badrx1.s
    ld/testsuite/ld-mmix/b-badrx2.d
    ld/testsuite/ld-mmix/b-badrx2.s
    ld/testsuite/ld-mmix/b-badrx3.d
    ld/testsuite/ld-mmix/b-badrx3.s
    ld/testsuite/ld-mmix/b-bend.s
    ld/testsuite/ld-mmix/b-bend1.d
    ld/testsuite/ld-mmix/b-bend2.d
    ld/testsuite/ld-mmix/b-bend3.d
    ld/testsuite/ld-mmix/b-bstab1.d
    ld/testsuite/ld-mmix/b-bstab1.s
    ld/testsuite/ld-mmix/b-fixo2.d
    ld/testsuite/ld-mmix/b-fixo2.s
    ld/testsuite/ld-mmix/b-goodmain.s
    ld/testsuite/ld-mmix/b-loc64k.d
    ld/testsuite/ld-mmix/b-loc64k.s
    ld/testsuite/ld-mmix/b-nosym.d
    ld/testsuite/ld-mmix/b-nosym.s
    ld/testsuite/ld-mmix/b-offloc.s
    ld/testsuite/ld-mmix/b-post1.s
    ld/testsuite/ld-mmix/b-twoinsn.s
    ld/testsuite/ld-mmix/b-widec.s
    ld/testsuite/ld-mmix/b-widec1.d
    ld/testsuite/ld-mmix/b-widec2.d
    ld/testsuite/ld-mmix/b-widec2.s
    ld/testsuite/ld-mmix/b-widec3.d
    ld/testsuite/ld-mmix/b-widec3.s
    ld/testsuite/ld-mmix/bpo-1.d
    ld/testsuite/ld-mmix/bpo-1.s
    ld/testsuite/ld-mmix/bpo-10.d
    ld/testsuite/ld-mmix/bpo-10.s
    ld/testsuite/ld-mmix/bpo-11.d
    ld/testsuite/ld-mmix/bpo-11.s
    ld/testsuite/ld-mmix/bpo-12.d
    ld/testsuite/ld-mmix/bpo-12m.d
    ld/testsuite/ld-mmix/bpo-13.d
    ld/testsuite/ld-mmix/bpo-13m.d
    ld/testsuite/ld-mmix/bpo-14.d
    ld/testsuite/ld-mmix/bpo-14m.d
    ld/testsuite/ld-mmix/bpo-15.d
    ld/testsuite/ld-mmix/bpo-15m.d
    ld/testsuite/ld-mmix/bpo-16.d
    ld/testsuite/ld-mmix/bpo-16m.d
    ld/testsuite/ld-mmix/bpo-17.d
    ld/testsuite/ld-mmix/bpo-17m.d
    ld/testsuite/ld-mmix/bpo-18.d
    ld/testsuite/ld-mmix/bpo-18m.d
    ld/testsuite/ld-mmix/bpo-19.d
    ld/testsuite/ld-mmix/bpo-19m.d
    ld/testsuite/ld-mmix/bpo-1m.d
    ld/testsuite/ld-mmix/bpo-2.d
    ld/testsuite/ld-mmix/bpo-2.s
    ld/testsuite/ld-mmix/bpo-20.d
    ld/testsuite/ld-mmix/bpo-20m.d
    ld/testsuite/ld-mmix/bpo-21.d
    ld/testsuite/ld-mmix/bpo-21m.d
    ld/testsuite/ld-mmix/bpo-22.d
    ld/testsuite/ld-mmix/bpo-2m.d
    ld/testsuite/ld-mmix/bpo-3.d
    ld/testsuite/ld-mmix/bpo-3.s
    ld/testsuite/ld-mmix/bpo-3m.d
    ld/testsuite/ld-mmix/bpo-4.d
    ld/testsuite/ld-mmix/bpo-4.s
    ld/testsuite/ld-mmix/bpo-4m.d
    ld/testsuite/ld-mmix/bpo-5.d
    ld/testsuite/ld-mmix/bpo-5.s
    ld/testsuite/ld-mmix/bpo-5m.d
    ld/testsuite/ld-mmix/bpo-6.d
    ld/testsuite/ld-mmix/bpo-6.s
    ld/testsuite/ld-mmix/bpo-6m.d
    ld/testsuite/ld-mmix/bpo-7.d
    ld/testsuite/ld-mmix/bpo-7.s
    ld/testsuite/ld-mmix/bpo-7m.d
    ld/testsuite/ld-mmix/bpo-8.d
    ld/testsuite/ld-mmix/bpo-8.s
    ld/testsuite/ld-mmix/bpo-8m.d
    ld/testsuite/ld-mmix/bpo-9.d
    ld/testsuite/ld-mmix/bpo-9.s
    ld/testsuite/ld-mmix/bpo-9m.d
    ld/testsuite/ld-mmix/bpo64addr.ld
    ld/testsuite/ld-mmix/bspec1.d
    ld/testsuite/ld-mmix/bspec1.s
    ld/testsuite/ld-mmix/bspec1m.d
    ld/testsuite/ld-mmix/bspec2.d
    ld/testsuite/ld-mmix/bspec2.s
    ld/testsuite/ld-mmix/bspec2m.d
    ld/testsuite/ld-mmix/bspec801.s
    ld/testsuite/ld-mmix/bspec802.s
    ld/testsuite/ld-mmix/bspec803.s
    ld/testsuite/ld-mmix/bspec804.s
    ld/testsuite/ld-mmix/bspec805.s
    ld/testsuite/ld-mmix/bspec806.s
    ld/testsuite/ld-mmix/bspec807.s
    ld/testsuite/ld-mmix/bspec808.s
    ld/testsuite/ld-mmix/bza-1b.d
    ld/testsuite/ld-mmix/bza-1f.d
    ld/testsuite/ld-mmix/bza-2b.d
    ld/testsuite/ld-mmix/bza-2f.d
    ld/testsuite/ld-mmix/bza-7b.d
    ld/testsuite/ld-mmix/bza-7f.d
    ld/testsuite/ld-mmix/bza-8b.d
    ld/testsuite/ld-mmix/bza-8f.d
    ld/testsuite/ld-mmix/bza.s
    ld/testsuite/ld-mmix/data1.s
    ld/testsuite/ld-mmix/dloc1.s
    ld/testsuite/ld-mmix/dloc2.s
    ld/testsuite/ld-mmix/ext1-254.s
    ld/testsuite/ld-mmix/ext1.s
    ld/testsuite/ld-mmix/ext1g.s
    ld/testsuite/ld-mmix/ext1l.s
    ld/testsuite/ld-mmix/getaa-1b.d
    ld/testsuite/ld-mmix/getaa-1f.d
    ld/testsuite/ld-mmix/getaa-2b.d
    ld/testsuite/ld-mmix/getaa-2f.d
    ld/testsuite/ld-mmix/getaa-4b.d
    ld/testsuite/ld-mmix/getaa-4f.d
    ld/testsuite/ld-mmix/getaa-6b.d
    ld/testsuite/ld-mmix/getaa-6f.d
    ld/testsuite/ld-mmix/getaa-7b.d
    ld/testsuite/ld-mmix/getaa-7f.d
    ld/testsuite/ld-mmix/getaa-8b.d
    ld/testsuite/ld-mmix/getaa-8f.d
    ld/testsuite/ld-mmix/getaa.s
    ld/testsuite/ld-mmix/getaa12b.d
    ld/testsuite/ld-mmix/getaa12f.d
    ld/testsuite/ld-mmix/getaa14b.d
    ld/testsuite/ld-mmix/getaa14f.d
    ld/testsuite/ld-mmix/greg-1.d
    ld/testsuite/ld-mmix/greg-1.s
    ld/testsuite/ld-mmix/greg-10.d
    ld/testsuite/ld-mmix/greg-11.d
    ld/testsuite/ld-mmix/greg-11b.d
    ld/testsuite/ld-mmix/greg-12.d
    ld/testsuite/ld-mmix/greg-13.d
    ld/testsuite/ld-mmix/greg-14.d
    ld/testsuite/ld-mmix/greg-14s.d
    ld/testsuite/ld-mmix/greg-15.d
    ld/testsuite/ld-mmix/greg-16.d
    ld/testsuite/ld-mmix/greg-17.d
    ld/testsuite/ld-mmix/greg-18.d
    ld/testsuite/ld-mmix/greg-19.d
    ld/testsuite/ld-mmix/greg-2.d
    ld/testsuite/ld-mmix/greg-2.s
    ld/testsuite/ld-mmix/greg-20.d
    ld/testsuite/ld-mmix/greg-3.d
    ld/testsuite/ld-mmix/greg-3.s
    ld/testsuite/ld-mmix/greg-4.d
    ld/testsuite/ld-mmix/greg-4.s
    ld/testsuite/ld-mmix/greg-5.d
    ld/testsuite/ld-mmix/greg-5.s
    ld/testsuite/ld-mmix/greg-5s.d
    ld/testsuite/ld-mmix/greg-6.d
    ld/testsuite/ld-mmix/greg-7.d
    ld/testsuite/ld-mmix/greg-8.d
    ld/testsuite/ld-mmix/greg-9.d
    ld/testsuite/ld-mmix/gregbza1.s
    ld/testsuite/ld-mmix/gregget1.s
    ld/testsuite/ld-mmix/gregget2.s
    ld/testsuite/ld-mmix/gregldo1.s
    ld/testsuite/ld-mmix/gregpsj1.s
    ld/testsuite/ld-mmix/hdr-1.d
    ld/testsuite/ld-mmix/jumpa-1b.d
    ld/testsuite/ld-mmix/jumpa-1f.d
    ld/testsuite/ld-mmix/jumpa-2b.d
    ld/testsuite/ld-mmix/jumpa-2f.d
    ld/testsuite/ld-mmix/jumpa-3b.d
    ld/testsuite/ld-mmix/jumpa-3f.d
    ld/testsuite/ld-mmix/jumpa-4b.d
    ld/testsuite/ld-mmix/jumpa-4f.d
    ld/testsuite/ld-mmix/jumpa-5b.d
    ld/testsuite/ld-mmix/jumpa-5f.d
    ld/testsuite/ld-mmix/jumpa-6b.d
    ld/testsuite/ld-mmix/jumpa-6f.d
    ld/testsuite/ld-mmix/jumpa-7b.d
    ld/testsuite/ld-mmix/jumpa-7f.d
    ld/testsuite/ld-mmix/jumpa-8b.d
    ld/testsuite/ld-mmix/jumpa-8f.d
    ld/testsuite/ld-mmix/jumpa-9b.d
    ld/testsuite/ld-mmix/jumpa-9f.d
    ld/testsuite/ld-mmix/jumpa.s
    ld/testsuite/ld-mmix/jumpa12b.d
    ld/testsuite/ld-mmix/jumpa12f.d
    ld/testsuite/ld-mmix/jumpa13b.d
    ld/testsuite/ld-mmix/jumpa13f.d
    ld/testsuite/ld-mmix/jumpa14b.d
    ld/testsuite/ld-mmix/jumpa14f.d
    ld/testsuite/ld-mmix/loc1.d
    ld/testsuite/ld-mmix/loc1.s
    ld/testsuite/ld-mmix/loc1m.d
    ld/testsuite/ld-mmix/loc2.d
    ld/testsuite/ld-mmix/loc2.s
    ld/testsuite/ld-mmix/loc2m.d
    ld/testsuite/ld-mmix/loc3.d
    ld/testsuite/ld-mmix/loc3m.d
    ld/testsuite/ld-mmix/loc4.d
    ld/testsuite/ld-mmix/loc4m.d
    ld/testsuite/ld-mmix/loc5.d
    ld/testsuite/ld-mmix/loc5m.d
    ld/testsuite/ld-mmix/loc6.d
    ld/testsuite/ld-mmix/loc6m.d
    ld/testsuite/ld-mmix/loc7.d
    ld/testsuite/ld-mmix/loc7m.d
    ld/testsuite/ld-mmix/local1.d
    ld/testsuite/ld-mmix/local1.s
    ld/testsuite/ld-mmix/local10.d
    ld/testsuite/ld-mmix/local10m.d
    ld/testsuite/ld-mmix/local11.d
    ld/testsuite/ld-mmix/local11m.d
    ld/testsuite/ld-mmix/local12.d
    ld/testsuite/ld-mmix/local12m.d
    ld/testsuite/ld-mmix/local1m.d
    ld/testsuite/ld-mmix/local2.d
    ld/testsuite/ld-mmix/local2.s
    ld/testsuite/ld-mmix/local2m.d
    ld/testsuite/ld-mmix/local3.d
    ld/testsuite/ld-mmix/local3m.d
    ld/testsuite/ld-mmix/local4.d
    ld/testsuite/ld-mmix/local4m.d
    ld/testsuite/ld-mmix/local5.d
    ld/testsuite/ld-mmix/local5m.d
    ld/testsuite/ld-mmix/local6.d
    ld/testsuite/ld-mmix/local6m.d
    ld/testsuite/ld-mmix/local7.d
    ld/testsuite/ld-mmix/local7m.d
    ld/testsuite/ld-mmix/local8.d
    ld/testsuite/ld-mmix/local8m.d
    ld/testsuite/ld-mmix/local9.d
    ld/testsuite/ld-mmix/local9m.d
    ld/testsuite/ld-mmix/locdo-1.d
    ld/testsuite/ld-mmix/locdo.s
    ld/testsuite/ld-mmix/loct-1.d
    ld/testsuite/ld-mmix/loct.s
    ld/testsuite/ld-mmix/locto-1.d
    ld/testsuite/ld-mmix/locto.s
    ld/testsuite/ld-mmix/main1.s
    ld/testsuite/ld-mmix/mmix.exp
    ld/testsuite/ld-mmix/mmohdr1.ld
    ld/testsuite/ld-mmix/mmosec1.ld
    ld/testsuite/ld-mmix/mmosec2.ld
    ld/testsuite/ld-mmix/nop123.s
    ld/testsuite/ld-mmix/pad16.s
    ld/testsuite/ld-mmix/pad2p18m32.s
    ld/testsuite/ld-mmix/pad2p26m32.s
    ld/testsuite/ld-mmix/pad4.s
    ld/testsuite/ld-mmix/pushja.s
    ld/testsuite/ld-mmix/pushja1b-s.d
    ld/testsuite/ld-mmix/pushja1b.d
    ld/testsuite/ld-mmix/pushja1f-s.d
    ld/testsuite/ld-mmix/pushja1f.d
    ld/testsuite/ld-mmix/pushja2b.d
    ld/testsuite/ld-mmix/pushja2f.d
    ld/testsuite/ld-mmix/pushja7b-s.d
    ld/testsuite/ld-mmix/pushja7b.d
    ld/testsuite/ld-mmix/pushja7f-s.d
    ld/testsuite/ld-mmix/pushja7f.d
    ld/testsuite/ld-mmix/pushja8b.d
    ld/testsuite/ld-mmix/pushja8f.d
    ld/testsuite/ld-mmix/pushjs1.d
    ld/testsuite/ld-mmix/pushjs1b.d
    ld/testsuite/ld-mmix/pushjs1bm.d
    ld/testsuite/ld-mmix/pushjs1m.d
    ld/testsuite/ld-mmix/pushjs1r.d
    ld/testsuite/ld-mmix/pushjs2.d
    ld/testsuite/ld-mmix/pushjs2b.d
    ld/testsuite/ld-mmix/pushjs2bm.d
    ld/testsuite/ld-mmix/pushjs2m.d
    ld/testsuite/ld-mmix/pushjs2r.d
    ld/testsuite/ld-mmix/pushjs3.d
    ld/testsuite/ld-mmix/pushjs3b.d
    ld/testsuite/ld-mmix/pushjs3bm.d
    ld/testsuite/ld-mmix/pushjs3m.d
    ld/testsuite/ld-mmix/pushjs3r.d
    ld/testsuite/ld-mmix/pushjs4.d
    ld/testsuite/ld-mmix/pushjs4b.d
    ld/testsuite/ld-mmix/pushjs4bm.d
    ld/testsuite/ld-mmix/pushjs4m.d
    ld/testsuite/ld-mmix/pushjs4r.d
    ld/testsuite/ld-mmix/reg-1.d
    ld/testsuite/ld-mmix/reg-1m.d
    ld/testsuite/ld-mmix/reg-2.d
    ld/testsuite/ld-mmix/reg-2m.d
    ld/testsuite/ld-mmix/regext1.s
    ld/testsuite/ld-mmix/sec-1.d
    ld/testsuite/ld-mmix/sec-1.s
    ld/testsuite/ld-mmix/sec-2.d
    ld/testsuite/ld-mmix/sec-2.s
    ld/testsuite/ld-mmix/sec-3.d
    ld/testsuite/ld-mmix/sec-4.d
    ld/testsuite/ld-mmix/sec-5.d
    ld/testsuite/ld-mmix/sec-6.d
    ld/testsuite/ld-mmix/sec-6.s
    ld/testsuite/ld-mmix/sec-6m.d
    ld/testsuite/ld-mmix/sec-7a.s
    ld/testsuite/ld-mmix/sec-7b.s
    ld/testsuite/ld-mmix/sec-7c.s
    ld/testsuite/ld-mmix/sec-7d.s
    ld/testsuite/ld-mmix/sec-7e.s
    ld/testsuite/ld-mmix/sec-7m.d
    ld/testsuite/ld-mmix/sec-8a.s
    ld/testsuite/ld-mmix/sec-8b.s
    ld/testsuite/ld-mmix/sec-8d.s
    ld/testsuite/ld-mmix/sec-8m.d
    ld/testsuite/ld-mmix/sec-8m.s
    ld/testsuite/ld-mmix/sec-9.d
    ld/testsuite/ld-mmix/spec801.d
    ld/testsuite/ld-mmix/spec802.d
    ld/testsuite/ld-mmix/spec803.d
    ld/testsuite/ld-mmix/spec804.d
    ld/testsuite/ld-mmix/spec805.d
    ld/testsuite/ld-mmix/spec806.d
    ld/testsuite/ld-mmix/spec807.d
    ld/testsuite/ld-mmix/spec808.d
    ld/testsuite/ld-mmix/start-1.d
    ld/testsuite/ld-mmix/start-2.d
    ld/testsuite/ld-mmix/start.s
    ld/testsuite/ld-mmix/start2.s
    ld/testsuite/ld-mmix/start3.s
    ld/testsuite/ld-mmix/start4.s
    ld/testsuite/ld-mmix/sym-1.d
    ld/testsuite/ld-mmix/sym-2.d
    ld/testsuite/ld-mmix/sym-2.s
    ld/testsuite/ld-mmix/undef-1.d
    ld/testsuite/ld-mmix/undef-1.s
    ld/testsuite/ld-mmix/undef-1m.d
    ld/testsuite/ld-mmix/undef-2.d
    ld/testsuite/ld-mmix/undef-2.s
    ld/testsuite/ld-mmix/undef-2m.d
    ld/testsuite/ld-mmix/undef-3.d
    ld/testsuite/ld-mmix/undef-3m.d
    ld/testsuite/ld-mmix/x.s
    ld/testsuite/ld-mmix/y.s
    ld/testsuite/ld-mmix/zeroeh.ld
    ld/testsuite/ld-mmix/zeroehelf.d
    ld/testsuite/ld-mmix/zeroehmmo.d
    ld/testsuite/ld-pe/pe.exp
    ld/testsuite/ld-pe/secrel.d
    ld/testsuite/ld-pe/secrel1.s
    ld/testsuite/ld-pe/secrel2.s
    ld/testsuite/ld-pie/pie.c
    ld/testsuite/ld-pie/pie.exp
    ld/testsuite/ld-pie/weakundef-data.c
    ld/testsuite/ld-pie/weakundef.c
    ld/testsuite/ld-pie/weakundef.out
    ld/testsuite/ld-powerpc/apuinfo.rd
    ld/testsuite/ld-powerpc/apuinfo1.s
    ld/testsuite/ld-powerpc/apuinfo2.s
    ld/testsuite/ld-powerpc/powerpc.exp
    ld/testsuite/ld-powerpc/reloc.d
    ld/testsuite/ld-powerpc/reloc.s
    ld/testsuite/ld-powerpc/sdadyn.d
    ld/testsuite/ld-powerpc/sdadyn.s
    ld/testsuite/ld-powerpc/sdalib.s
    ld/testsuite/ld-powerpc/symtocbase-1.s
    ld/testsuite/ld-powerpc/symtocbase-2.s
    ld/testsuite/ld-powerpc/symtocbase.d
    ld/testsuite/ld-powerpc/tls.d
    ld/testsuite/ld-powerpc/tls.g
    ld/testsuite/ld-powerpc/tls.s
    ld/testsuite/ld-powerpc/tls.t
    ld/testsuite/ld-powerpc/tls32.d
    ld/testsuite/ld-powerpc/tls32.g
    ld/testsuite/ld-powerpc/tls32.s
    ld/testsuite/ld-powerpc/tls32.t
    ld/testsuite/ld-powerpc/tlsexe.d
    ld/testsuite/ld-powerpc/tlsexe.g
    ld/testsuite/ld-powerpc/tlsexe.r
    ld/testsuite/ld-powerpc/tlsexe.t
    ld/testsuite/ld-powerpc/tlsexe32.d
    ld/testsuite/ld-powerpc/tlsexe32.g
    ld/testsuite/ld-powerpc/tlsexe32.r
    ld/testsuite/ld-powerpc/tlsexe32.t
    ld/testsuite/ld-powerpc/tlsexetoc.d
    ld/testsuite/ld-powerpc/tlsexetoc.g
    ld/testsuite/ld-powerpc/tlsexetoc.r
    ld/testsuite/ld-powerpc/tlsexetoc.t
    ld/testsuite/ld-powerpc/tlslib.s
    ld/testsuite/ld-powerpc/tlslib32.s
    ld/testsuite/ld-powerpc/tlsso.d
    ld/testsuite/ld-powerpc/tlsso.g
    ld/testsuite/ld-powerpc/tlsso.r
    ld/testsuite/ld-powerpc/tlsso.t
    ld/testsuite/ld-powerpc/tlsso32.d
    ld/testsuite/ld-powerpc/tlsso32.g
    ld/testsuite/ld-powerpc/tlsso32.r
    ld/testsuite/ld-powerpc/tlsso32.t
    ld/testsuite/ld-powerpc/tlstoc.d
    ld/testsuite/ld-powerpc/tlstoc.g
    ld/testsuite/ld-powerpc/tlstoc.s
    ld/testsuite/ld-powerpc/tlstoc.t
    ld/testsuite/ld-powerpc/tlstocso.d
    ld/testsuite/ld-powerpc/tlstocso.g
    ld/testsuite/ld-powerpc/tlstocso.r
    ld/testsuite/ld-powerpc/tlstocso.t
    ld/testsuite/ld-powerpc/vxworks1-lib.dd
    ld/testsuite/ld-powerpc/vxworks1-lib.nd
    ld/testsuite/ld-powerpc/vxworks1-lib.rd
    ld/testsuite/ld-powerpc/vxworks1-lib.s
    ld/testsuite/ld-powerpc/vxworks1-lib.sd
    ld/testsuite/ld-powerpc/vxworks1-static.d
    ld/testsuite/ld-powerpc/vxworks1.dd
    ld/testsuite/ld-powerpc/vxworks1.ld
    ld/testsuite/ld-powerpc/vxworks1.rd
    ld/testsuite/ld-powerpc/vxworks1.s
    ld/testsuite/ld-powerpc/vxworks2-static.sd
    ld/testsuite/ld-powerpc/vxworks2.s
    ld/testsuite/ld-powerpc/vxworks2.sd
    ld/testsuite/ld-s390/s390.exp
    ld/testsuite/ld-s390/tlsbin.dd
    ld/testsuite/ld-s390/tlsbin.rd
    ld/testsuite/ld-s390/tlsbin.s
    ld/testsuite/ld-s390/tlsbin.sd
    ld/testsuite/ld-s390/tlsbin.td
    ld/testsuite/ld-s390/tlsbin_64.dd
    ld/testsuite/ld-s390/tlsbin_64.rd
    ld/testsuite/ld-s390/tlsbin_64.s
    ld/testsuite/ld-s390/tlsbin_64.sd
    ld/testsuite/ld-s390/tlsbin_64.td
    ld/testsuite/ld-s390/tlsbinpic.s
    ld/testsuite/ld-s390/tlsbinpic_64.s
    ld/testsuite/ld-s390/tlslib.s
    ld/testsuite/ld-s390/tlslib_64.s
    ld/testsuite/ld-s390/tlspic.dd
    ld/testsuite/ld-s390/tlspic.rd
    ld/testsuite/ld-s390/tlspic.sd
    ld/testsuite/ld-s390/tlspic.td
    ld/testsuite/ld-s390/tlspic1.s
    ld/testsuite/ld-s390/tlspic1_64.s
    ld/testsuite/ld-s390/tlspic2.s
    ld/testsuite/ld-s390/tlspic2_64.s
    ld/testsuite/ld-s390/tlspic_64.dd
    ld/testsuite/ld-s390/tlspic_64.rd
    ld/testsuite/ld-s390/tlspic_64.sd
    ld/testsuite/ld-s390/tlspic_64.td
    ld/testsuite/ld-scripts/align.exp
    ld/testsuite/ld-scripts/align.s
    ld/testsuite/ld-scripts/align.t
    ld/testsuite/ld-scripts/align2.t
    ld/testsuite/ld-scripts/align2a.d
    ld/testsuite/ld-scripts/align2a.s
    ld/testsuite/ld-scripts/align2b.d
    ld/testsuite/ld-scripts/align2b.s
    ld/testsuite/ld-scripts/align2c.d
    ld/testsuite/ld-scripts/align2c.s
    ld/testsuite/ld-scripts/assert.exp
    ld/testsuite/ld-scripts/assert.s
    ld/testsuite/ld-scripts/assert.t
    ld/testsuite/ld-scripts/cross1.c
    ld/testsuite/ld-scripts/cross1.t
    ld/testsuite/ld-scripts/cross2.c
    ld/testsuite/ld-scripts/cross2.t
    ld/testsuite/ld-scripts/cross3.c
    ld/testsuite/ld-scripts/cross3.t
    ld/testsuite/ld-scripts/cross4.c
    ld/testsuite/ld-scripts/crossref.exp
    ld/testsuite/ld-scripts/data.d
    ld/testsuite/ld-scripts/data.exp
    ld/testsuite/ld-scripts/data.s
    ld/testsuite/ld-scripts/data.t
    ld/testsuite/ld-scripts/defined.exp
    ld/testsuite/ld-scripts/defined.s
    ld/testsuite/ld-scripts/defined.t
    ld/testsuite/ld-scripts/defined2.d
    ld/testsuite/ld-scripts/defined2.t
    ld/testsuite/ld-scripts/defined3.d
    ld/testsuite/ld-scripts/defined3.t
    ld/testsuite/ld-scripts/dynamic-sections-1.s
    ld/testsuite/ld-scripts/dynamic-sections-2.s
    ld/testsuite/ld-scripts/dynamic-sections.d
    ld/testsuite/ld-scripts/dynamic-sections.exp
    ld/testsuite/ld-scripts/dynamic-sections.t
    ld/testsuite/ld-scripts/empty-aligned.d
    ld/testsuite/ld-scripts/empty-aligned.exp
    ld/testsuite/ld-scripts/empty-aligned.s
    ld/testsuite/ld-scripts/empty-aligned.t
    ld/testsuite/ld-scripts/empty-orphan.d
    ld/testsuite/ld-scripts/empty-orphan.exp
    ld/testsuite/ld-scripts/empty-orphan.s
    ld/testsuite/ld-scripts/empty-orphan.t
    ld/testsuite/ld-scripts/map-address.d
    ld/testsuite/ld-scripts/map-address.exp
    ld/testsuite/ld-scripts/map-address.t
    ld/testsuite/ld-scripts/memory.t
    ld/testsuite/ld-scripts/overlay-size-map.d
    ld/testsuite/ld-scripts/overlay-size.d
    ld/testsuite/ld-scripts/overlay-size.exp
    ld/testsuite/ld-scripts/overlay-size.s
    ld/testsuite/ld-scripts/overlay-size.t
    ld/testsuite/ld-scripts/phdrs.exp
    ld/testsuite/ld-scripts/phdrs.s
    ld/testsuite/ld-scripts/phdrs.t
    ld/testsuite/ld-scripts/phdrs2.exp
    ld/testsuite/ld-scripts/phdrs2.s
    ld/testsuite/ld-scripts/phdrs2.t
    ld/testsuite/ld-scripts/provide-1.d
    ld/testsuite/ld-scripts/provide-1.s
    ld/testsuite/ld-scripts/provide-1.t
    ld/testsuite/ld-scripts/provide-2.d
    ld/testsuite/ld-scripts/provide-2.s
    ld/testsuite/ld-scripts/provide-2.t
    ld/testsuite/ld-scripts/provide-3.d
    ld/testsuite/ld-scripts/provide-3.s
    ld/testsuite/ld-scripts/provide-3.t
    ld/testsuite/ld-scripts/provide.exp
    ld/testsuite/ld-scripts/script.exp
    ld/testsuite/ld-scripts/script.s
    ld/testsuite/ld-scripts/script.t
    ld/testsuite/ld-scripts/scriptm.t
    ld/testsuite/ld-scripts/size-1.d
    ld/testsuite/ld-scripts/size-1.s
    ld/testsuite/ld-scripts/size-1.t
    ld/testsuite/ld-scripts/size-2.d
    ld/testsuite/ld-scripts/size-2.s
    ld/testsuite/ld-scripts/size-2.t
    ld/testsuite/ld-scripts/size.exp
    ld/testsuite/ld-scripts/sizeof.exp
    ld/testsuite/ld-scripts/sizeof.s
    ld/testsuite/ld-scripts/sizeof.t
    ld/testsuite/ld-scripts/sort.exp
    ld/testsuite/ld-scripts/sort_b_a.d
    ld/testsuite/ld-scripts/sort_b_a.s
    ld/testsuite/ld-scripts/sort_b_a.t
    ld/testsuite/ld-scripts/sort_b_a_a-1.d
    ld/testsuite/ld-scripts/sort_b_a_a-2.d
    ld/testsuite/ld-scripts/sort_b_a_a-3.d
    ld/testsuite/ld-scripts/sort_b_a_a.t
    ld/testsuite/ld-scripts/sort_b_a_n-1.d
    ld/testsuite/ld-scripts/sort_b_a_n-2.d
    ld/testsuite/ld-scripts/sort_b_a_n-3.d
    ld/testsuite/ld-scripts/sort_b_a_n.t
    ld/testsuite/ld-scripts/sort_b_n.d
    ld/testsuite/ld-scripts/sort_b_n.s
    ld/testsuite/ld-scripts/sort_b_n.t
    ld/testsuite/ld-scripts/sort_b_n_a-1.d
    ld/testsuite/ld-scripts/sort_b_n_a-2.d
    ld/testsuite/ld-scripts/sort_b_n_a-3.d
    ld/testsuite/ld-scripts/sort_b_n_a.t
    ld/testsuite/ld-scripts/sort_b_n_n-1.d
    ld/testsuite/ld-scripts/sort_b_n_n-2.d
    ld/testsuite/ld-scripts/sort_b_n_n-3.d
    ld/testsuite/ld-scripts/sort_b_n_n.t
    ld/testsuite/ld-scripts/sort_n_a-a.s
    ld/testsuite/ld-scripts/sort_n_a-b.s
    ld/testsuite/ld-scripts/sort_no-1.d
    ld/testsuite/ld-scripts/sort_no-2.d
    ld/testsuite/ld-scripts/sort_no.t
    ld/testsuite/ld-scripts/weak.exp
    ld/testsuite/ld-scripts/weak.t
    ld/testsuite/ld-scripts/weak1.s
    ld/testsuite/ld-scripts/weak2.s
    ld/testsuite/ld-selective/1.c
    ld/testsuite/ld-selective/2.c
    ld/testsuite/ld-selective/3.cc
    ld/testsuite/ld-selective/4.cc
    ld/testsuite/ld-selective/5.cc
    ld/testsuite/ld-selective/keepdot.d
    ld/testsuite/ld-selective/keepdot.ld
    ld/testsuite/ld-selective/keepdot.s
    ld/testsuite/ld-selective/keepdot0.d
    ld/testsuite/ld-selective/keepdot0.ld
    ld/testsuite/ld-selective/sel-dump.exp
    ld/testsuite/ld-selective/selective.exp
    ld/testsuite/ld-sh/arch/arch.exp
    ld/testsuite/ld-sh/arch/arch_expected.txt
    ld/testsuite/ld-sh/arch/sh-dsp.s
    ld/testsuite/ld-sh/arch/sh.s
    ld/testsuite/ld-sh/arch/sh2.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
    ld/testsuite/ld-sh/arch/sh2a-nofpu.s
    ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s
    ld/testsuite/ld-sh/arch/sh2a-or-sh4.s
    ld/testsuite/ld-sh/arch/sh2a.s
    ld/testsuite/ld-sh/arch/sh2e.s
    ld/testsuite/ld-sh/arch/sh3-dsp.s
    ld/testsuite/ld-sh/arch/sh3-nommu.s
    ld/testsuite/ld-sh/arch/sh3.s
    ld/testsuite/ld-sh/arch/sh3e.s
    ld/testsuite/ld-sh/arch/sh4-nofpu.s
    ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s
    ld/testsuite/ld-sh/arch/sh4.s
    ld/testsuite/ld-sh/arch/sh4a-nofpu.s
    ld/testsuite/ld-sh/arch/sh4a.s
    ld/testsuite/ld-sh/arch/sh4al-dsp.s
    ld/testsuite/ld-sh/ld-r-1.d
    ld/testsuite/ld-sh/ldr1.s
    ld/testsuite/ld-sh/ldr2.s
    ld/testsuite/ld-sh/rd-sh.exp
    ld/testsuite/ld-sh/refdbg-0-dso.d
    ld/testsuite/ld-sh/refdbg-1.d
    ld/testsuite/ld-sh/refdbg.s
    ld/testsuite/ld-sh/refdbglib.s
    ld/testsuite/ld-sh/sh.exp
    ld/testsuite/ld-sh/sh1.s
    ld/testsuite/ld-sh/sh2.c
    ld/testsuite/ld-sh/sh64/abi32.sd
    ld/testsuite/ld-sh/sh64/abi32.xd
    ld/testsuite/ld-sh/sh64/abi64.sd
    ld/testsuite/ld-sh/sh64/abi64.xd
    ld/testsuite/ld-sh/sh64/abixx-noexp.sd
    ld/testsuite/ld-sh/sh64/cmpct1.sd
    ld/testsuite/ld-sh/sh64/cmpct1.xd
    ld/testsuite/ld-sh/sh64/crange-1.s
    ld/testsuite/ld-sh/sh64/crange-2a.s
    ld/testsuite/ld-sh/sh64/crange-2b.s
    ld/testsuite/ld-sh/sh64/crange-2c.s
    ld/testsuite/ld-sh/sh64/crange-2d.s
    ld/testsuite/ld-sh/sh64/crange-2e.s
    ld/testsuite/ld-sh/sh64/crange-2f.s
    ld/testsuite/ld-sh/sh64/crange-2g.s
    ld/testsuite/ld-sh/sh64/crange-2h.s
    ld/testsuite/ld-sh/sh64/crange-2i.s
    ld/testsuite/ld-sh/sh64/crange1.rd
    ld/testsuite/ld-sh/sh64/crange2.rd
    ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
    ld/testsuite/ld-sh/sh64/crange3-media.rd
    ld/testsuite/ld-sh/sh64/crange3.dd
    ld/testsuite/ld-sh/sh64/crange3.rd
    ld/testsuite/ld-sh/sh64/crangerel1.rd
    ld/testsuite/ld-sh/sh64/crangerel2.rd
    ld/testsuite/ld-sh/sh64/dlsection-1.s
    ld/testsuite/ld-sh/sh64/dlsection.sd
    ld/testsuite/ld-sh/sh64/endian.dbd
    ld/testsuite/ld-sh/sh64/endian.dld
    ld/testsuite/ld-sh/sh64/endian.ld
    ld/testsuite/ld-sh/sh64/endian.s
    ld/testsuite/ld-sh/sh64/endian.sbd
    ld/testsuite/ld-sh/sh64/endian.sld
    ld/testsuite/ld-sh/sh64/gotplt.d
    ld/testsuite/ld-sh/sh64/gotplt.map
    ld/testsuite/ld-sh/sh64/gotplt.s
    ld/testsuite/ld-sh/sh64/init-cmpct.d
    ld/testsuite/ld-sh/sh64/init-media.d
    ld/testsuite/ld-sh/sh64/init.s
    ld/testsuite/ld-sh/sh64/init64.d
    ld/testsuite/ld-sh/sh64/mix1-noexp.sd
    ld/testsuite/ld-sh/sh64/mix1.sd
    ld/testsuite/ld-sh/sh64/mix1.xd
    ld/testsuite/ld-sh/sh64/mix2-noexp.sd
    ld/testsuite/ld-sh/sh64/mix2.sd
    ld/testsuite/ld-sh/sh64/mix2.xd
    ld/testsuite/ld-sh/sh64/rd-sh64.exp
    ld/testsuite/ld-sh/sh64/rel-1.s
    ld/testsuite/ld-sh/sh64/rel-2.s
    ld/testsuite/ld-sh/sh64/rel32.xd
    ld/testsuite/ld-sh/sh64/rel64.xd
    ld/testsuite/ld-sh/sh64/relax.exp
    ld/testsuite/ld-sh/sh64/relax1.s
    ld/testsuite/ld-sh/sh64/relax2.s
    ld/testsuite/ld-sh/sh64/relax3.s
    ld/testsuite/ld-sh/sh64/relax4.s
    ld/testsuite/ld-sh/sh64/reldl-1.s
    ld/testsuite/ld-sh/sh64/reldl-2.s
    ld/testsuite/ld-sh/sh64/reldl32.rd
    ld/testsuite/ld-sh/sh64/reldl64.rd
    ld/testsuite/ld-sh/sh64/relfail.exp
    ld/testsuite/ld-sh/sh64/relfail.s
    ld/testsuite/ld-sh/sh64/sh64-1.s
    ld/testsuite/ld-sh/sh64/sh64-2.s
    ld/testsuite/ld-sh/sh64/sh64.exp
    ld/testsuite/ld-sh/sh64/shcmp-1.s
    ld/testsuite/ld-sh/sh64/shdl-1.s
    ld/testsuite/ld-sh/sh64/shdl-2.s
    ld/testsuite/ld-sh/sh64/shdl32.xd
    ld/testsuite/ld-sh/sh64/shdl64.sd
    ld/testsuite/ld-sh/sh64/shdl64.xd
    ld/testsuite/ld-sh/sh64/shmix-1.s
    ld/testsuite/ld-sh/sh64/shmix-2.s
    ld/testsuite/ld-sh/sh64/shmix-3.s
    ld/testsuite/ld-sh/sh64/stobin-0-dso.d
    ld/testsuite/ld-sh/sh64/stobin-1.d
    ld/testsuite/ld-sh/sh64/stobin.s
    ld/testsuite/ld-sh/sh64/stolib.s
    ld/testsuite/ld-sh/shared-1.d
    ld/testsuite/ld-sh/shared-2.d
    ld/testsuite/ld-sh/start.s
    ld/testsuite/ld-sh/sub2l-1.d
    ld/testsuite/ld-sh/sub2l.s
    ld/testsuite/ld-sh/textrel1.s
    ld/testsuite/ld-sh/textrel2.s
    ld/testsuite/ld-sh/tlsbin-0-dso.d
    ld/testsuite/ld-sh/tlsbin-1.d
    ld/testsuite/ld-sh/tlsbin-2.d
    ld/testsuite/ld-sh/tlsbin-3.d
    ld/testsuite/ld-sh/tlsbin-4.d
    ld/testsuite/ld-sh/tlsbin.s
    ld/testsuite/ld-sh/tlsbinpic.s
    ld/testsuite/ld-sh/tlslib.s
    ld/testsuite/ld-sh/tlspic-1.d
    ld/testsuite/ld-sh/tlspic-2.d
    ld/testsuite/ld-sh/tlspic-3.d
    ld/testsuite/ld-sh/tlspic-4.d
    ld/testsuite/ld-sh/tlspic1.s
    ld/testsuite/ld-sh/tlspic2.s
    ld/testsuite/ld-sh/tlstpoff-1.d
    ld/testsuite/ld-sh/tlstpoff-2.d
    ld/testsuite/ld-sh/tlstpoff1.s
    ld/testsuite/ld-sh/tlstpoff2.s
    ld/testsuite/ld-sh/weak1.d
    ld/testsuite/ld-sh/weak1.s
    ld/testsuite/ld-shared/elf-offset.ld
    ld/testsuite/ld-shared/main.c
    ld/testsuite/ld-shared/sh1.c
    ld/testsuite/ld-shared/sh2.c
    ld/testsuite/ld-shared/shared.dat
    ld/testsuite/ld-shared/shared.exp
    ld/testsuite/ld-shared/sun4.dat
    ld/testsuite/ld-shared/symbolic.dat
    ld/testsuite/ld-shared/xcoff.dat
    ld/testsuite/ld-sparc/sparc.exp
    ld/testsuite/ld-sparc/tlsg32.s
    ld/testsuite/ld-sparc/tlsg32.sd
    ld/testsuite/ld-sparc/tlsg64.s
    ld/testsuite/ld-sparc/tlsg64.sd
    ld/testsuite/ld-sparc/tlslib.s
    ld/testsuite/ld-sparc/tlsnopic.s
    ld/testsuite/ld-sparc/tlspic.s
    ld/testsuite/ld-sparc/tlssunbin32.dd
    ld/testsuite/ld-sparc/tlssunbin32.rd
    ld/testsuite/ld-sparc/tlssunbin32.s
    ld/testsuite/ld-sparc/tlssunbin32.sd
    ld/testsuite/ld-sparc/tlssunbin32.td
    ld/testsuite/ld-sparc/tlssunbin64.dd
    ld/testsuite/ld-sparc/tlssunbin64.rd
    ld/testsuite/ld-sparc/tlssunbin64.s
    ld/testsuite/ld-sparc/tlssunbin64.sd
    ld/testsuite/ld-sparc/tlssunbin64.td
    ld/testsuite/ld-sparc/tlssunbinpic32.s
    ld/testsuite/ld-sparc/tlssunbinpic64.s
    ld/testsuite/ld-sparc/tlssunnopic32.dd
    ld/testsuite/ld-sparc/tlssunnopic32.rd
    ld/testsuite/ld-sparc/tlssunnopic32.s
    ld/testsuite/ld-sparc/tlssunnopic32.sd
    ld/testsuite/ld-sparc/tlssunnopic64.dd
    ld/testsuite/ld-sparc/tlssunnopic64.rd
    ld/testsuite/ld-sparc/tlssunnopic64.s
    ld/testsuite/ld-sparc/tlssunnopic64.sd
    ld/testsuite/ld-sparc/tlssunpic32.dd
    ld/testsuite/ld-sparc/tlssunpic32.rd
    ld/testsuite/ld-sparc/tlssunpic32.s
    ld/testsuite/ld-sparc/tlssunpic32.sd
    ld/testsuite/ld-sparc/tlssunpic32.td
    ld/testsuite/ld-sparc/tlssunpic64.dd
    ld/testsuite/ld-sparc/tlssunpic64.rd
    ld/testsuite/ld-sparc/tlssunpic64.s
    ld/testsuite/ld-sparc/tlssunpic64.sd
    ld/testsuite/ld-sparc/tlssunpic64.td
    ld/testsuite/ld-sparc/vxworks1-lib.dd
    ld/testsuite/ld-sparc/vxworks1-lib.nd
    ld/testsuite/ld-sparc/vxworks1-lib.rd
    ld/testsuite/ld-sparc/vxworks1-lib.s
    ld/testsuite/ld-sparc/vxworks1-static.d
    ld/testsuite/ld-sparc/vxworks1.dd
    ld/testsuite/ld-sparc/vxworks1.ld
    ld/testsuite/ld-sparc/vxworks1.rd
    ld/testsuite/ld-sparc/vxworks1.s
    ld/testsuite/ld-sparc/vxworks2-static.sd
    ld/testsuite/ld-sparc/vxworks2.s
    ld/testsuite/ld-sparc/vxworks2.sd
    ld/testsuite/ld-srec/sr1.c
    ld/testsuite/ld-srec/sr2.c
    ld/testsuite/ld-srec/sr3.cc
    ld/testsuite/ld-srec/srec.exp
    ld/testsuite/ld-undefined/undefined.c
    ld/testsuite/ld-undefined/undefined.exp
    ld/testsuite/ld-undefined/weak-undef.exp
    ld/testsuite/ld-undefined/weak-undef.s
    ld/testsuite/ld-undefined/weak-undef.t
    ld/testsuite/ld-v850/split-lo16.d
    ld/testsuite/ld-v850/split-lo16.ld
    ld/testsuite/ld-v850/split-lo16.s
    ld/testsuite/ld-v850/v850.exp
    ld/testsuite/ld-versados/t1-1.ro
    ld/testsuite/ld-versados/t1-2.ro
    ld/testsuite/ld-versados/t1.ld
    ld/testsuite/ld-versados/t1.ook
    ld/testsuite/ld-versados/t2-1.ro
    ld/testsuite/ld-versados/t2-2.ro
    ld/testsuite/ld-versados/t2-3.ro
    ld/testsuite/ld-versados/t2.ld
    ld/testsuite/ld-versados/t2.ook
    ld/testsuite/ld-versados/versados.exp
    ld/testsuite/ld-x86-64/abs.d
    ld/testsuite/ld-x86-64/pcrel16.d
    ld/testsuite/ld-x86-64/pcrel8.d
    ld/testsuite/ld-x86-64/tlsbin.dd
    ld/testsuite/ld-x86-64/tlsbin.rd
    ld/testsuite/ld-x86-64/tlsbin.s
    ld/testsuite/ld-x86-64/tlsbin.sd
    ld/testsuite/ld-x86-64/tlsbin.td
    ld/testsuite/ld-x86-64/tlsbindesc.dd
    ld/testsuite/ld-x86-64/tlsbindesc.rd
    ld/testsuite/ld-x86-64/tlsbindesc.s
    ld/testsuite/ld-x86-64/tlsbindesc.sd
    ld/testsuite/ld-x86-64/tlsbindesc.td
    ld/testsuite/ld-x86-64/tlsbinpic.s
    ld/testsuite/ld-x86-64/tlsdesc.dd
    ld/testsuite/ld-x86-64/tlsdesc.pd
    ld/testsuite/ld-x86-64/tlsdesc.rd
    ld/testsuite/ld-x86-64/tlsdesc.s
    ld/testsuite/ld-x86-64/tlsdesc.sd
    ld/testsuite/ld-x86-64/tlsdesc.td
    ld/testsuite/ld-x86-64/tlsg.s
    ld/testsuite/ld-x86-64/tlsg.sd
    ld/testsuite/ld-x86-64/tlsgdesc.dd
    ld/testsuite/ld-x86-64/tlsgdesc.rd
    ld/testsuite/ld-x86-64/tlsgdesc.s
    ld/testsuite/ld-x86-64/tlslib.s
    ld/testsuite/ld-x86-64/tlspic.dd
    ld/testsuite/ld-x86-64/tlspic.rd
    ld/testsuite/ld-x86-64/tlspic.sd
    ld/testsuite/ld-x86-64/tlspic.td
    ld/testsuite/ld-x86-64/tlspic1.s
    ld/testsuite/ld-x86-64/tlspic2.s
    ld/testsuite/ld-x86-64/x86-64.exp
    ld/testsuite/ld-xc16x/absrel.d
    ld/testsuite/ld-xc16x/absrel.s
    ld/testsuite/ld-xc16x/offset.d
    ld/testsuite/ld-xc16x/offset.s
    ld/testsuite/ld-xc16x/pcreloc.d
    ld/testsuite/ld-xc16x/pcreloc.s
    ld/testsuite/ld-xc16x/pcrelocl.d
    ld/testsuite/ld-xc16x/xc16x.exp
    ld/testsuite/ld-xstormy16/external.s
    ld/testsuite/ld-xstormy16/pcrel.d
    ld/testsuite/ld-xstormy16/pcrel.s
    ld/testsuite/ld-xstormy16/xstormy16.exp
    ld/testsuite/ld-xtensa/coalesce.exp
    ld/testsuite/ld-xtensa/coalesce.t
    ld/testsuite/ld-xtensa/coalesce1.s
    ld/testsuite/ld-xtensa/coalesce2.s
    ld/testsuite/ld-xtensa/lcall.exp
    ld/testsuite/ld-xtensa/lcall.t
    ld/testsuite/ld-xtensa/lcall1.s
    ld/testsuite/ld-xtensa/lcall2.s
    ld/testsuite/lib/ld-lib.exp
    opcodes/ChangeLog
    opcodes/ChangeLog-0001
    opcodes/ChangeLog-0203
    opcodes/ChangeLog-2004
    opcodes/ChangeLog-2005
    opcodes/ChangeLog-9297
    opcodes/ChangeLog-9899
    opcodes/MAINTAINERS
    opcodes/Makefile.am
    opcodes/Makefile.in
    opcodes/acinclude.m4
    opcodes/aclocal.m4
    opcodes/alpha-dis.c
    opcodes/alpha-opc.c
    opcodes/arc-dis.c
    opcodes/arc-dis.h
    opcodes/arc-ext.c
    opcodes/arc-ext.h
    opcodes/arc-opc.c
    opcodes/arm-dis.c
    opcodes/avr-dis.c
    opcodes/bfin-dis.c
    opcodes/cgen-asm.c
    opcodes/cgen-asm.in
    opcodes/cgen-bitset.c
    opcodes/cgen-dis.c
    opcodes/cgen-dis.in
    opcodes/cgen-ibld.in
    opcodes/cgen-opc.c
    opcodes/cgen-ops.h
    opcodes/cgen-types.h
    opcodes/cgen.sh
    opcodes/config.in
    opcodes/configure
    opcodes/configure.in
    opcodes/cris-dis.c
    opcodes/cris-opc.c
    opcodes/crx-dis.c
    opcodes/crx-opc.c
    opcodes/d10v-dis.c
    opcodes/d10v-opc.c
    opcodes/d30v-dis.c
    opcodes/d30v-opc.c
    opcodes/dep-in.sed
    opcodes/dis-buf.c
    opcodes/dis-init.c
    opcodes/disassemble.c
    opcodes/dlx-dis.c
    opcodes/fr30-asm.c
    opcodes/fr30-desc.c
    opcodes/fr30-desc.h
    opcodes/fr30-dis.c
    opcodes/fr30-ibld.c
    opcodes/fr30-opc.c
    opcodes/fr30-opc.h
    opcodes/frv-asm.c
    opcodes/frv-desc.c
    opcodes/frv-desc.h
    opcodes/frv-dis.c
    opcodes/frv-ibld.c
    opcodes/frv-opc.c
    opcodes/frv-opc.h
    opcodes/h8300-dis.c
    opcodes/h8500-dis.c
    opcodes/h8500-opc.h
    opcodes/hppa-dis.c
    opcodes/i370-dis.c
    opcodes/i370-opc.c
    opcodes/i386-dis.c
    opcodes/i860-dis.c
    opcodes/i960-dis.c
    opcodes/ia64-asmtab.c
    opcodes/ia64-asmtab.h
    opcodes/ia64-dis.c
    opcodes/ia64-gen.c
    opcodes/ia64-ic.tbl
    opcodes/ia64-opc-a.c
    opcodes/ia64-opc-b.c
    opcodes/ia64-opc-d.c
    opcodes/ia64-opc-f.c
    opcodes/ia64-opc-i.c
    opcodes/ia64-opc-m.c
    opcodes/ia64-opc-x.c
    opcodes/ia64-opc.c
    opcodes/ia64-opc.h
    opcodes/ia64-raw.tbl
    opcodes/ia64-war.tbl
    opcodes/ia64-waw.tbl
    opcodes/ip2k-asm.c
    opcodes/ip2k-desc.c
    opcodes/ip2k-desc.h
    opcodes/ip2k-dis.c
    opcodes/ip2k-ibld.c
    opcodes/ip2k-opc.c
    opcodes/ip2k-opc.h
    opcodes/iq2000-asm.c
    opcodes/iq2000-desc.c
    opcodes/iq2000-desc.h
    opcodes/iq2000-dis.c
    opcodes/iq2000-ibld.c
    opcodes/iq2000-opc.c
    opcodes/iq2000-opc.h
    opcodes/m10200-dis.c
    opcodes/m10200-opc.c
    opcodes/m10300-dis.c
    opcodes/m10300-opc.c
    opcodes/m32c-asm.c
    opcodes/m32c-desc.c
    opcodes/m32c-desc.h
    opcodes/m32c-dis.c
    opcodes/m32c-ibld.c
    opcodes/m32c-opc.c
    opcodes/m32c-opc.h
    opcodes/m32r-asm.c
    opcodes/m32r-desc.c
    opcodes/m32r-desc.h
    opcodes/m32r-dis.c
    opcodes/m32r-ibld.c
    opcodes/m32r-opc.c
    opcodes/m32r-opc.h
    opcodes/m32r-opinst.c
    opcodes/m68hc11-dis.c
    opcodes/m68hc11-opc.c
    opcodes/m68k-dis.c
    opcodes/m68k-opc.c
    opcodes/m88k-dis.c
    opcodes/makefile.vms
    opcodes/maxq-dis.c
    opcodes/mcore-dis.c
    opcodes/mcore-opc.h
    opcodes/mips-dis.c
    opcodes/mips-opc.c
    opcodes/mips16-opc.c
    opcodes/mmix-dis.c
    opcodes/mmix-opc.c
    opcodes/msp430-dis.c
    opcodes/mt-asm.c
    opcodes/mt-desc.c
    opcodes/mt-desc.h
    opcodes/mt-dis.c
    opcodes/mt-ibld.c
    opcodes/mt-opc.c
    opcodes/mt-opc.h
    opcodes/ns32k-dis.c
    opcodes/openrisc-asm.c
    opcodes/openrisc-desc.c
    opcodes/openrisc-desc.h
    opcodes/openrisc-dis.c
    opcodes/openrisc-ibld.c
    opcodes/openrisc-opc.c
    opcodes/openrisc-opc.h
    opcodes/opintl.h
    opcodes/or32-dis.c
    opcodes/or32-opc.c
    opcodes/pdp11-dis.c
    opcodes/pdp11-opc.c
    opcodes/pj-dis.c
    opcodes/pj-opc.c
    opcodes/po/.cvsignore
    opcodes/po/Make-in
    opcodes/po/POTFILES.in
    opcodes/po/da.po
    opcodes/po/de.po
    opcodes/po/es.po
    opcodes/po/fi.po
    opcodes/po/fr.po
    opcodes/po/ga.po
    opcodes/po/id.po
    opcodes/po/nl.po
    opcodes/po/opcodes.pot
    opcodes/po/pt_BR.po
    opcodes/po/ro.po
    opcodes/po/sv.po
    opcodes/po/tr.po
    opcodes/po/vi.po
    opcodes/po/zh_CN.po
    opcodes/ppc-dis.c
    opcodes/ppc-opc.c
    opcodes/s390-dis.c
    opcodes/s390-mkopc.c
    opcodes/s390-opc.c
    opcodes/s390-opc.txt
    opcodes/sh-dis.c
    opcodes/sh-opc.h
    opcodes/sh64-dis.c
    opcodes/sh64-opc.c
    opcodes/sh64-opc.h
    opcodes/sparc-dis.c
    opcodes/sparc-opc.c
    opcodes/stamp-h.in
    opcodes/sysdep.h
    opcodes/tic30-dis.c
    opcodes/tic4x-dis.c
    opcodes/tic54x-dis.c
    opcodes/tic54x-opc.c
    opcodes/tic80-dis.c
    opcodes/tic80-opc.c
    opcodes/v850-dis.c
    opcodes/v850-opc.c
    opcodes/vax-dis.c
    opcodes/w65-dis.c
    opcodes/w65-opc.h
    opcodes/xc16x-asm.c
    opcodes/xc16x-desc.c
    opcodes/xc16x-desc.h
    opcodes/xc16x-dis.c
    opcodes/xc16x-ibld.c
    opcodes/xc16x-opc.c
    opcodes/xc16x-opc.h
    opcodes/xstormy16-asm.c
    opcodes/xstormy16-desc.c
    opcodes/xstormy16-desc.h
    opcodes/xstormy16-dis.c
    opcodes/xstormy16-ibld.c
    opcodes/xstormy16-opc.c
    opcodes/xstormy16-opc.h
    opcodes/xtensa-dis.c
    opcodes/z80-dis.c
    opcodes/z8k-dis.c
    opcodes/z8k-opc.h
    opcodes/z8kgen.c
    readline/CHANGELOG
    readline/CHANGES
    readline/COPYING
    readline/ChangeLog.gdb
    readline/INSTALL
    readline/MANIFEST
    readline/Makefile.in
    readline/NEWS
    readline/README
    readline/USAGE
    readline/aclocal.m4
    readline/ansi_stdlib.h
    readline/bind.c
    readline/callback.c
    readline/chardefs.h
    readline/compat.c
    readline/complete.c
    readline/config.h.in
    readline/configure
    readline/configure.in
    readline/cross-build/cygwin.cache
    readline/display.c
    readline/doc/ChangeLog.gdb
    readline/doc/Makefile.in
    readline/doc/fdl.texi
    readline/doc/history.3
    readline/doc/history.texi
    readline/doc/hstech.texi
    readline/doc/hsuser.texi
    readline/doc/inc-hist.texinfo
    readline/doc/readline.3
    readline/doc/rlman.texi
    readline/doc/rltech.texi
    readline/doc/rluser.texi
    readline/doc/rluserman.texi
    readline/doc/texi2dvi
    readline/doc/texi2html
    readline/doc/version.texi
    readline/emacs_keymap.c
    readline/examples/ChangeLog.gdb
    readline/examples/Inputrc
    readline/examples/Makefile.in
    readline/examples/excallback.c
    readline/examples/fileman.c
    readline/examples/histexamp.c
    readline/examples/manexamp.c
    readline/examples/readlinebuf.h
    readline/examples/rl-fgets.c
    readline/examples/rl.c
    readline/examples/rlcat.c
    readline/examples/rlfe/ChangeLog
    readline/examples/rlfe/Makefile.in
    readline/examples/rlfe/README
    readline/examples/rlfe/config.h.in
    readline/examples/rlfe/configure
    readline/examples/rlfe/configure.in
    readline/examples/rlfe/extern.h
    readline/examples/rlfe/os.h
    readline/examples/rlfe/pty.c
    readline/examples/rlfe/rlfe.c
    readline/examples/rlfe/screen.h
    readline/examples/rlptytest.c
    readline/examples/rltest.c
    readline/examples/rlversion.c
    readline/funmap.c
    readline/histexpand.c
    readline/histfile.c
    readline/histlib.h
    readline/history.c
    readline/history.h
    readline/histsearch.c
    readline/input.c
    readline/isearch.c
    readline/keymaps.c
    readline/keymaps.h
    readline/kill.c
    readline/macro.c
    readline/mbutil.c
    readline/misc.c
    readline/nls.c
    readline/parens.c
    readline/posixdir.h
    readline/posixjmp.h
    readline/posixstat.h
    readline/readline.c
    readline/readline.h
    readline/rlconf.h
    readline/rldefs.h
    readline/rlmbutil.h
    readline/rlprivate.h
    readline/rlshell.h
    readline/rlstdc.h
    readline/rltty.c
    readline/rltty.h
    readline/rltypedefs.h
    readline/rlwinsize.h
    readline/savestring.c
    readline/search.c
    readline/shell.c
    readline/shlib/Makefile.in
    readline/signals.c
    readline/support/config.guess
    readline/support/config.rpath
    readline/support/config.sub
    readline/support/install.sh
    readline/support/mkdirs
    readline/support/mkdist
    readline/support/mkinstalldirs
    readline/support/shlib-install
    readline/support/shobj-conf
    readline/support/wcwidth.c
    readline/tcap.h
    readline/terminal.c
    readline/text.c
    readline/tilde.c
    readline/tilde.h
    readline/undo.c
    readline/util.c
    readline/vi_keymap.c
    readline/vi_mode.c
    readline/xmalloc.c
    readline/xmalloc.h
    sim/ChangeLog
    sim/MAINTAINERS
    sim/Makefile.in
    sim/README-HACKING
    sim/arm/COPYING
    sim/arm/ChangeLog
    sim/arm/Makefile.in
    sim/arm/README
    sim/arm/acconfig.h
    sim/arm/armcopro.c
    sim/arm/armdefs.h
    sim/arm/armemu.c
    sim/arm/armemu.h
    sim/arm/armfpe.h
    sim/arm/arminit.c
    sim/arm/armopts.h
    sim/arm/armos.c
    sim/arm/armos.h
    sim/arm/armrdi.c
    sim/arm/armsupp.c
    sim/arm/armvirt.c
    sim/arm/bag.c
    sim/arm/bag.h
    sim/arm/communicate.c
    sim/arm/communicate.h
    sim/arm/config.in
    sim/arm/configure
    sim/arm/configure.ac
    sim/arm/dbg_conf.h
    sim/arm/dbg_cp.h
    sim/arm/dbg_hif.h
    sim/arm/dbg_rdi.h
    sim/arm/gdbhost.c
    sim/arm/gdbhost.h
    sim/arm/iwmmxt.c
    sim/arm/iwmmxt.h
    sim/arm/kid.c
    sim/arm/main.c
    sim/arm/maverick.c
    sim/arm/parent.c
    sim/arm/tconfig.in
    sim/arm/thumbemu.c
    sim/arm/wrapper.c
    sim/common/ChangeLog
    sim/common/Make-common.in
    sim/common/Makefile.in
    sim/common/acconfig.h
    sim/common/aclocal.m4
    sim/common/callback.c
    sim/common/cgen-accfp.c
    sim/common/cgen-cpu.h
    sim/common/cgen-defs.h
    sim/common/cgen-engine.h
    sim/common/cgen-fpu.c
    sim/common/cgen-fpu.h
    sim/common/cgen-mem.h
    sim/common/cgen-ops.h
    sim/common/cgen-par.c
    sim/common/cgen-par.h
    sim/common/cgen-run.c
    sim/common/cgen-scache.c
    sim/common/cgen-scache.h
    sim/common/cgen-sim.h
    sim/common/cgen-trace.c
    sim/common/cgen-trace.h
    sim/common/cgen-types.h
    sim/common/cgen-utils.c
    sim/common/cgen.sh
    sim/common/common.m4
    sim/common/config.in
    sim/common/configure
    sim/common/configure.ac
    sim/common/dv-core.c
    sim/common/dv-glue.c
    sim/common/dv-pal.c
    sim/common/dv-sockser.c
    sim/common/dv-sockser.h
    sim/common/gdbinit.in
    sim/common/genmloop.sh
    sim/common/gennltvals.sh
    sim/common/gentmap.c
    sim/common/gentvals.sh
    sim/common/hw-alloc.c
    sim/common/hw-alloc.h
    sim/common/hw-base.c
    sim/common/hw-base.h
    sim/common/hw-device.c
    sim/common/hw-device.h
    sim/common/hw-events.c
    sim/common/hw-events.h
    sim/common/hw-handles.c
    sim/common/hw-handles.h
    sim/common/hw-instances.c
    sim/common/hw-instances.h
    sim/common/hw-main.h
    sim/common/hw-ports.c
    sim/common/hw-ports.h
    sim/common/hw-properties.c
    sim/common/hw-properties.h
    sim/common/hw-tree.c
    sim/common/hw-tree.h
    sim/common/nltvals.def
    sim/common/nrun.c
    sim/common/run-sim.h
    sim/common/run.1
    sim/common/run.c
    sim/common/sim-abort.c
    sim/common/sim-alu.h
    sim/common/sim-arange.c
    sim/common/sim-arange.h
    sim/common/sim-assert.h
    sim/common/sim-base.h
    sim/common/sim-basics.h
    sim/common/sim-bits.c
    sim/common/sim-bits.h
    sim/common/sim-config.c
    sim/common/sim-config.h
    sim/common/sim-core.c
    sim/common/sim-core.h
    sim/common/sim-cpu.c
    sim/common/sim-cpu.h
    sim/common/sim-endian.c
    sim/common/sim-endian.h
    sim/common/sim-engine.c
    sim/common/sim-engine.h
    sim/common/sim-events.c
    sim/common/sim-events.h
    sim/common/sim-fpu.c
    sim/common/sim-fpu.h
    sim/common/sim-hload.c
    sim/common/sim-hrw.c
    sim/common/sim-hw.c
    sim/common/sim-hw.h
    sim/common/sim-info.c
    sim/common/sim-inline.c
    sim/common/sim-inline.h
    sim/common/sim-io.c
    sim/common/sim-io.h
    sim/common/sim-load.c
    sim/common/sim-memopt.c
    sim/common/sim-memopt.h
    sim/common/sim-model.c
    sim/common/sim-model.h
    sim/common/sim-module.c
    sim/common/sim-module.h
    sim/common/sim-n-bits.h
    sim/common/sim-n-core.h
    sim/common/sim-n-endian.h
    sim/common/sim-options.c
    sim/common/sim-options.h
    sim/common/sim-profile.c
    sim/common/sim-profile.h
    sim/common/sim-reason.c
    sim/common/sim-reg.c
    sim/common/sim-resume.c
    sim/common/sim-run.c
    sim/common/sim-signal.c
    sim/common/sim-signal.h
    sim/common/sim-stop.c
    sim/common/sim-trace.c
    sim/common/sim-trace.h
    sim/common/sim-types.h
    sim/common/sim-utils.c
    sim/common/sim-utils.h
    sim/common/sim-watch.c
    sim/common/sim-watch.h
    sim/common/syscall.c
    sim/common/tconfig.in
    sim/configure
    sim/configure.ac
    sim/cris/Makefile.in
    sim/cris/arch.c
    sim/cris/arch.h
    sim/cris/config.in
    sim/cris/configure
    sim/cris/configure.ac
    sim/cris/cpuall.h
    sim/cris/cpuv10.c
    sim/cris/cpuv10.h
    sim/cris/cpuv32.c
    sim/cris/cpuv32.h
    sim/cris/cris-desc.c
    sim/cris/cris-desc.h
    sim/cris/cris-opc.h
    sim/cris/cris-sim.h
    sim/cris/cris-tmpl.c
    sim/cris/crisv10f.c
    sim/cris/crisv32f.c
    sim/cris/decodev10.c
    sim/cris/decodev10.h
    sim/cris/decodev32.c
    sim/cris/decodev32.h
    sim/cris/devices.c
    sim/cris/dv-cris.c
    sim/cris/dv-rv.c
    sim/cris/mloop.in
    sim/cris/modelv10.c
    sim/cris/modelv32.c
    sim/cris/rvdummy.c
    sim/cris/semcrisv10f-switch.c
    sim/cris/semcrisv32f-switch.c
    sim/cris/sim-if.c
    sim/cris/sim-main.h
    sim/cris/tconfig.in
    sim/cris/traps.c
    sim/d10v/ChangeLog
    sim/d10v/Makefile.in
    sim/d10v/acconfig.h
    sim/d10v/config.in
    sim/d10v/configure
    sim/d10v/configure.ac
    sim/d10v/d10v_sim.h
    sim/d10v/endian.c
    sim/d10v/gencode.c
    sim/d10v/interp.c
    sim/d10v/simops.c
    sim/erc32/ChangeLog
    sim/erc32/Makefile.in
    sim/erc32/NEWS
    sim/erc32/README.erc32
    sim/erc32/README.gdb
    sim/erc32/README.sis
    sim/erc32/acconfig.h
    sim/erc32/config.in
    sim/erc32/configure
    sim/erc32/configure.ac
    sim/erc32/end.c
    sim/erc32/erc32.c
    sim/erc32/exec.c
    sim/erc32/float.c
    sim/erc32/func.c
    sim/erc32/help.c
    sim/erc32/interf.c
    sim/erc32/sis.c
    sim/erc32/sis.h
    sim/erc32/startsim
    sim/frv/ChangeLog
    sim/frv/Makefile.in
    sim/frv/README
    sim/frv/TODO
    sim/frv/arch.c
    sim/frv/arch.h
    sim/frv/cache.c
    sim/frv/cache.h
    sim/frv/config.in
    sim/frv/configure
    sim/frv/configure.ac
    sim/frv/cpu.c
    sim/frv/cpu.h
    sim/frv/cpuall.h
    sim/frv/decode.c
    sim/frv/decode.h
    sim/frv/devices.c
    sim/frv/frv-sim.h
    sim/frv/frv.c
    sim/frv/interrupts.c
    sim/frv/memory.c
    sim/frv/mloop.in
    sim/frv/model.c
    sim/frv/options.c
    sim/frv/pipeline.c
    sim/frv/profile-fr400.c
    sim/frv/profile-fr400.h
    sim/frv/profile-fr450.c
    sim/frv/profile-fr500.c
    sim/frv/profile-fr500.h
    sim/frv/profile-fr550.c
    sim/frv/profile-fr550.h
    sim/frv/profile.c
    sim/frv/profile.h
    sim/frv/registers.c
    sim/frv/registers.h
    sim/frv/reset.c
    sim/frv/sem.c
    sim/frv/sim-if.c
    sim/frv/sim-main.h
    sim/frv/tconfig.in
    sim/frv/traps.c
    sim/h8300/ChangeLog
    sim/h8300/Makefile.in
    sim/h8300/acconfig.h
    sim/h8300/compile.c
    sim/h8300/config.in
    sim/h8300/configure
    sim/h8300/configure.ac
    sim/h8300/inst.h
    sim/h8300/sim-main.h
    sim/h8300/tconfig.in
    sim/h8300/writecode.c
    sim/igen/ChangeLog
    sim/igen/Makefile.in
    sim/igen/acconfig.h
    sim/igen/compare_igen_models
    sim/igen/config.in
    sim/igen/configure
    sim/igen/configure.ac
    sim/igen/filter.c
    sim/igen/filter.h
    sim/igen/filter_host.c
    sim/igen/filter_host.h
    sim/igen/gen-engine.c
    sim/igen/gen-engine.h
    sim/igen/gen-icache.c
    sim/igen/gen-icache.h
    sim/igen/gen-idecode.c
    sim/igen/gen-idecode.h
    sim/igen/gen-itable.c
    sim/igen/gen-itable.h
    sim/igen/gen-model.c
    sim/igen/gen-model.h
    sim/igen/gen-semantics.c
    sim/igen/gen-semantics.h
    sim/igen/gen-support.c
    sim/igen/gen-support.h
    sim/igen/gen.c
    sim/igen/gen.h
    sim/igen/igen.c
    sim/igen/igen.h
    sim/igen/ld-cache.c
    sim/igen/ld-cache.h
    sim/igen/ld-decode.c
    sim/igen/ld-decode.h
    sim/igen/ld-insn.c
    sim/igen/ld-insn.h
    sim/igen/lf.c
    sim/igen/lf.h
    sim/igen/misc.c
    sim/igen/misc.h
    sim/igen/table.c
    sim/igen/table.h
    sim/iq2000/ChangeLog
    sim/iq2000/Makefile.in
    sim/iq2000/acconfig.h
    sim/iq2000/arch.c
    sim/iq2000/arch.h
    sim/iq2000/config.in
    sim/iq2000/configure
    sim/iq2000/configure.ac
    sim/iq2000/cpu.c
    sim/iq2000/cpu.h
    sim/iq2000/cpuall.h
    sim/iq2000/decode.c
    sim/iq2000/decode.h
    sim/iq2000/iq2000-sim.h
    sim/iq2000/iq2000.c
    sim/iq2000/mloop.in
    sim/iq2000/model.c
    sim/iq2000/sem-switch.c
    sim/iq2000/sem.c
    sim/iq2000/sim-if.c
    sim/iq2000/sim-main.h
    sim/iq2000/tconfig.in
    sim/m32c/ChangeLog
    sim/m32c/Makefile.in
    sim/m32c/blinky.S
    sim/m32c/config.in
    sim/m32c/configure
    sim/m32c/configure.in
    sim/m32c/cpu.h
    sim/m32c/gdb-if.c
    sim/m32c/gloss.S
    sim/m32c/int.c
    sim/m32c/int.h
    sim/m32c/load.c
    sim/m32c/load.h
    sim/m32c/m32c.opc
    sim/m32c/main.c
    sim/m32c/mem.c
    sim/m32c/mem.h
    sim/m32c/misc.c
    sim/m32c/misc.h
    sim/m32c/opc2c.c
    sim/m32c/r8c.opc
    sim/m32c/reg.c
    sim/m32c/safe-fgets.c
    sim/m32c/safe-fgets.h
    sim/m32c/sample.S
    sim/m32c/sample.ld
    sim/m32c/sample2.c
    sim/m32c/srcdest.c
    sim/m32c/syscall.h
    sim/m32c/syscalls.c
    sim/m32c/syscalls.h
    sim/m32c/trace.c
    sim/m32c/trace.h
    sim/m32r/ChangeLog
    sim/m32r/Makefile.in
    sim/m32r/README
    sim/m32r/TODO
    sim/m32r/acconfig.h
    sim/m32r/arch.c
    sim/m32r/arch.h
    sim/m32r/config.in
    sim/m32r/configure
    sim/m32r/configure.ac
    sim/m32r/cpu.c
    sim/m32r/cpu.h
    sim/m32r/cpu2.c
    sim/m32r/cpu2.h
    sim/m32r/cpuall.h
    sim/m32r/cpux.c
    sim/m32r/cpux.h
    sim/m32r/decode.c
    sim/m32r/decode.h
    sim/m32r/decode2.c
    sim/m32r/decode2.h
    sim/m32r/decodex.c
    sim/m32r/decodex.h
    sim/m32r/devices.c
    sim/m32r/m32r-sim.h
    sim/m32r/m32r.c
    sim/m32r/m32r2.c
    sim/m32r/m32rx.c
    sim/m32r/mloop.in
    sim/m32r/mloop2.in
    sim/m32r/mloopx.in
    sim/m32r/model.c
    sim/m32r/model2.c
    sim/m32r/modelx.c
    sim/m32r/sem-switch.c
    sim/m32r/sem.c
    sim/m32r/sem2-switch.c
    sim/m32r/semx-switch.c
    sim/m32r/sim-if.c
    sim/m32r/sim-main.h
    sim/m32r/syscall.h
    sim/m32r/tconfig.in
    sim/m32r/traps-linux.c
    sim/m32r/traps.c
    sim/m68hc11/ChangeLog
    sim/m68hc11/Makefile.in
    sim/m68hc11/config.in
    sim/m68hc11/configure
    sim/m68hc11/configure.ac
    sim/m68hc11/dv-m68hc11.c
    sim/m68hc11/dv-m68hc11eepr.c
    sim/m68hc11/dv-m68hc11sio.c
    sim/m68hc11/dv-m68hc11spi.c
    sim/m68hc11/dv-m68hc11tim.c
    sim/m68hc11/dv-nvram.c
    sim/m68hc11/emulos.c
    sim/m68hc11/gencode.c
    sim/m68hc11/interp.c
    sim/m68hc11/interrupts.c
    sim/m68hc11/interrupts.h
    sim/m68hc11/m68hc11_sim.c
    sim/m68hc11/sim-main.h
    sim/mcore/ChangeLog
    sim/mcore/Makefile.in
    sim/mcore/config.in
    sim/mcore/configure
    sim/mcore/configure.ac
    sim/mcore/interp.c
    sim/mcore/sysdep.h
    sim/mips/ChangeLog
    sim/mips/Makefile.in
    sim/mips/acconfig.h
    sim/mips/config.in
    sim/mips/configure
    sim/mips/configure.ac
    sim/mips/cp1.c
    sim/mips/cp1.h
    sim/mips/dsp.c
    sim/mips/dsp.igen
    sim/mips/dv-tx3904cpu.c
    sim/mips/dv-tx3904irc.c
    sim/mips/dv-tx3904sio.c
    sim/mips/dv-tx3904tmr.c
    sim/mips/interp.c
    sim/mips/m16.dc
    sim/mips/m16.igen
    sim/mips/m16e.igen
    sim/mips/m16run.c
    sim/mips/mdmx.c
    sim/mips/mdmx.igen
    sim/mips/mips.dc
    sim/mips/mips.igen
    sim/mips/mips3264r2.igen
    sim/mips/mips3d.igen
    sim/mips/sb1.igen
    sim/mips/sim-main.c
    sim/mips/sim-main.h
    sim/mips/tconfig.in
    sim/mips/tx.igen
    sim/mips/vr.igen
    sim/mn10300/ChangeLog
    sim/mn10300/Makefile.in
    sim/mn10300/acconfig.h
    sim/mn10300/am33-2.igen
    sim/mn10300/am33.igen
    sim/mn10300/config.in
    sim/mn10300/configure
    sim/mn10300/configure.ac
    sim/mn10300/dv-mn103cpu.c
    sim/mn10300/dv-mn103int.c
    sim/mn10300/dv-mn103iop.c
    sim/mn10300/dv-mn103ser.c
    sim/mn10300/dv-mn103tim.c
    sim/mn10300/interp.c
    sim/mn10300/mn10300.dc
    sim/mn10300/mn10300.igen
    sim/mn10300/mn10300_sim.h
    sim/mn10300/op_utils.c
    sim/mn10300/sim-main.c
    sim/mn10300/sim-main.h
    sim/mn10300/tconfig.in
    sim/ppc/.gdbinit
    sim/ppc/BUGS
    sim/ppc/COPYING
    sim/ppc/COPYING.LIB
    sim/ppc/ChangeLog
    sim/ppc/ChangeLog.00
    sim/ppc/INSTALL
    sim/ppc/Makefile.in
    sim/ppc/README
    sim/ppc/RUN
    sim/ppc/acconfig.h
    sim/ppc/aclocal.m4
    sim/ppc/altivec.igen
    sim/ppc/altivec_expression.h
    sim/ppc/altivec_registers.h
    sim/ppc/basics.h
    sim/ppc/bits.c
    sim/ppc/bits.h
    sim/ppc/cap.c
    sim/ppc/cap.h
    sim/ppc/config.in
    sim/ppc/configure
    sim/ppc/configure.ac
    sim/ppc/corefile-n.h
    sim/ppc/corefile.c
    sim/ppc/corefile.h
    sim/ppc/cpu.c
    sim/ppc/cpu.h
    sim/ppc/dc-complex
    sim/ppc/dc-simple
    sim/ppc/dc-stupid
    sim/ppc/dc-test.01
    sim/ppc/dc-test.02
    sim/ppc/debug.c
    sim/ppc/debug.h
    sim/ppc/device.c
    sim/ppc/device.h
    sim/ppc/device_table.c
    sim/ppc/device_table.h
    sim/ppc/dgen.c
    sim/ppc/double.c
    sim/ppc/dp-bit.c
    sim/ppc/e500.igen
    sim/ppc/e500_expression.h
    sim/ppc/e500_registers.h
    sim/ppc/emul_bugapi.c
    sim/ppc/emul_bugapi.h
    sim/ppc/emul_chirp.c
    sim/ppc/emul_chirp.h
    sim/ppc/emul_generic.c
    sim/ppc/emul_generic.h
    sim/ppc/emul_netbsd.c
    sim/ppc/emul_netbsd.h
    sim/ppc/emul_unix.c
    sim/ppc/emul_unix.h
    sim/ppc/events.c
    sim/ppc/events.h
    sim/ppc/filter.c
    sim/ppc/filter.h
    sim/ppc/filter_filename.c
    sim/ppc/filter_filename.h
    sim/ppc/gdb-sim.c
    sim/ppc/gen-icache.c
    sim/ppc/gen-icache.h
    sim/ppc/gen-idecode.c
    sim/ppc/gen-idecode.h
    sim/ppc/gen-itable.c
    sim/ppc/gen-itable.h
    sim/ppc/gen-model.c
    sim/ppc/gen-model.h
    sim/ppc/gen-semantics.c
    sim/ppc/gen-semantics.h
    sim/ppc/gen-support.c
    sim/ppc/gen-support.h
    sim/ppc/hw_com.c
    sim/ppc/hw_core.c
    sim/ppc/hw_cpu.c
    sim/ppc/hw_cpu.h
    sim/ppc/hw_disk.c
    sim/ppc/hw_eeprom.c
    sim/ppc/hw_glue.c
    sim/ppc/hw_htab.c
    sim/ppc/hw_ide.c
    sim/ppc/hw_init.c
    sim/ppc/hw_iobus.c
    sim/ppc/hw_memory.c
    sim/ppc/hw_nvram.c
    sim/ppc/hw_opic.c
    sim/ppc/hw_pal.c
    sim/ppc/hw_phb.c
    sim/ppc/hw_phb.h
    sim/ppc/hw_register.c
    sim/ppc/hw_trace.c
    sim/ppc/hw_vm.c
    sim/ppc/idecode_branch.h
    sim/ppc/idecode_expression.h
    sim/ppc/idecode_fields.h
    sim/ppc/igen.c
    sim/ppc/igen.h
    sim/ppc/inline.c
    sim/ppc/inline.h
    sim/ppc/interrupts.c
    sim/ppc/interrupts.h
    sim/ppc/ld-cache.c
    sim/ppc/ld-cache.h
    sim/ppc/ld-decode.c
    sim/ppc/ld-decode.h
    sim/ppc/ld-insn.c
    sim/ppc/ld-insn.h
    sim/ppc/lf.c
    sim/ppc/lf.h
    sim/ppc/main.c
    sim/ppc/misc.c
    sim/ppc/misc.h
    sim/ppc/mon.c
    sim/ppc/mon.h
    sim/ppc/options.c
    sim/ppc/options.h
    sim/ppc/os_emul.c
    sim/ppc/os_emul.h
    sim/ppc/pk_disklabel.c
    sim/ppc/ppc-instructions
    sim/ppc/ppc-spr-table
    sim/ppc/ppc.mt
    sim/ppc/psim.c
    sim/ppc/psim.h
    sim/ppc/psim.texinfo
    sim/ppc/registers.c
    sim/ppc/registers.h
    sim/ppc/sim-endian-n.h
    sim/ppc/sim-endian.c
    sim/ppc/sim-endian.h
    sim/ppc/sim-main.h
    sim/ppc/sim_callbacks.h
    sim/ppc/sim_calls.c
    sim/ppc/std-config.h
    sim/ppc/table.c
    sim/ppc/table.h
    sim/ppc/tree.c
    sim/ppc/tree.h
    sim/ppc/vm.c
    sim/ppc/vm.h
    sim/ppc/vm_n.h
    sim/ppc/words.h
    sim/sh/ChangeLog
    sim/sh/Makefile.in
    sim/sh/acconfig.h
    sim/sh/config.in
    sim/sh/configure
    sim/sh/configure.ac
    sim/sh/gencode.c
    sim/sh/interp.c
    sim/sh/syscall.h
    sim/sh/tconfig.in
    sim/sh64/ChangeLog
    sim/sh64/Makefile.in
    sim/sh64/arch.c
    sim/sh64/arch.h
    sim/sh64/config.in
    sim/sh64/configure
    sim/sh64/configure.ac
    sim/sh64/cpu.c
    sim/sh64/cpu.h
    sim/sh64/cpuall.h
    sim/sh64/decode-compact.c
    sim/sh64/decode-compact.h
    sim/sh64/decode-media.c
    sim/sh64/decode-media.h
    sim/sh64/decode.h
    sim/sh64/defs-compact.h
    sim/sh64/defs-media.h
    sim/sh64/eng-compact.h
    sim/sh64/eng-media.h
    sim/sh64/eng.h
    sim/sh64/mloop-compact.c
    sim/sh64/mloop-media.c
    sim/sh64/sem-compact-switch.c
    sim/sh64/sem-compact.c
    sim/sh64/sem-media-switch.c
    sim/sh64/sem-media.c
    sim/sh64/sh-desc.c
    sim/sh64/sh-desc.h
    sim/sh64/sh-opc.h
    sim/sh64/sh64-sim.h
    sim/sh64/sh64.c
    sim/sh64/sim-if.c
    sim/sh64/sim-main.h
    sim/sh64/tconfig.in
    sim/testsuite/ChangeLog
    sim/testsuite/Makefile.in
    sim/testsuite/common/Make-common.in
    sim/testsuite/common/Makefile.in
    sim/testsuite/common/alu-n-tst.h
    sim/testsuite/common/alu-tst.c
    sim/testsuite/common/bits-gen.c
    sim/testsuite/common/bits-tst.c
    sim/testsuite/common/fpu-tst.c
    sim/testsuite/config/default.exp
    sim/testsuite/configure
    sim/testsuite/configure.ac
    sim/testsuite/d10v-elf/ChangeLog
    sim/testsuite/d10v-elf/Makefile.in
    sim/testsuite/d10v-elf/configure
    sim/testsuite/d10v-elf/configure.ac
    sim/testsuite/d10v-elf/exit47.s
    sim/testsuite/d10v-elf/hello.s
    sim/testsuite/d10v-elf/loop.s
    sim/testsuite/d10v-elf/t-ae-ld-d.s
    sim/testsuite/d10v-elf/t-ae-ld-i.s
    sim/testsuite/d10v-elf/t-ae-ld-id.s
    sim/testsuite/d10v-elf/t-ae-ld-im.s
    sim/testsuite/d10v-elf/t-ae-ld-ip.s
    sim/testsuite/d10v-elf/t-ae-ld2w-d.s
    sim/testsuite/d10v-elf/t-ae-ld2w-i.s
    sim/testsuite/d10v-elf/t-ae-ld2w-id.s
    sim/testsuite/d10v-elf/t-ae-ld2w-im.s
    sim/testsuite/d10v-elf/t-ae-ld2w-ip.s
    sim/testsuite/d10v-elf/t-ae-st-d.s
    sim/testsuite/d10v-elf/t-ae-st-i.s
    sim/testsuite/d10v-elf/t-ae-st-id.s
    sim/testsuite/d10v-elf/t-ae-st-im.s
    sim/testsuite/d10v-elf/t-ae-st-ip.s
    sim/testsuite/d10v-elf/t-ae-st-is.s
    sim/testsuite/d10v-elf/t-ae-st2w-d.s
    sim/testsuite/d10v-elf/t-ae-st2w-i.s
    sim/testsuite/d10v-elf/t-ae-st2w-id.s
    sim/testsuite/d10v-elf/t-ae-st2w-im.s
    sim/testsuite/d10v-elf/t-ae-st2w-ip.s
    sim/testsuite/d10v-elf/t-ae-st2w-is.s
    sim/testsuite/d10v-elf/t-dbt.s
    sim/testsuite/d10v-elf/t-ld-st.s
    sim/testsuite/d10v-elf/t-mac.s
    sim/testsuite/d10v-elf/t-macros.i
    sim/testsuite/d10v-elf/t-mod-ld-pre.s
    sim/testsuite/d10v-elf/t-msbu.s
    sim/testsuite/d10v-elf/t-mulxu.s
    sim/testsuite/d10v-elf/t-mvtac.s
    sim/testsuite/d10v-elf/t-mvtc.s
    sim/testsuite/d10v-elf/t-rac.s
    sim/testsuite/d10v-elf/t-rachi.s
    sim/testsuite/d10v-elf/t-rdt.s
    sim/testsuite/d10v-elf/t-rep.s
    sim/testsuite/d10v-elf/t-rie-xx.s
    sim/testsuite/d10v-elf/t-rte.s
    sim/testsuite/d10v-elf/t-sac.s
    sim/testsuite/d10v-elf/t-sachi.s
    sim/testsuite/d10v-elf/t-sadd.s
    sim/testsuite/d10v-elf/t-slae.s
    sim/testsuite/d10v-elf/t-sp.s
    sim/testsuite/d10v-elf/t-sub.s
    sim/testsuite/d10v-elf/t-sub2w.s
    sim/testsuite/d10v-elf/t-subi.s
    sim/testsuite/d10v-elf/t-trap.s
    sim/testsuite/frv-elf/ChangeLog
    sim/testsuite/frv-elf/Makefile.in
    sim/testsuite/frv-elf/cache.s
    sim/testsuite/frv-elf/configure
    sim/testsuite/frv-elf/configure.ac
    sim/testsuite/frv-elf/exit47.s
    sim/testsuite/frv-elf/grloop.s
    sim/testsuite/frv-elf/hello.s
    sim/testsuite/frv-elf/loop.s
    sim/testsuite/lib/sim-defs.exp
    sim/testsuite/m32r-elf/ChangeLog
    sim/testsuite/m32r-elf/Makefile.in
    sim/testsuite/m32r-elf/configure
    sim/testsuite/m32r-elf/configure.ac
    sim/testsuite/m32r-elf/exit47.s
    sim/testsuite/m32r-elf/hello.s
    sim/testsuite/m32r-elf/loop.s
    sim/testsuite/mips64el-elf/ChangeLog
    sim/testsuite/mips64el-elf/Makefile.in
    sim/testsuite/mips64el-elf/configure
    sim/testsuite/mips64el-elf/configure.ac
    sim/testsuite/sim/arm/adc.cgs
    sim/testsuite/sim/arm/add.cgs
    sim/testsuite/sim/arm/allinsn.exp
    sim/testsuite/sim/arm/and.cgs
    sim/testsuite/sim/arm/b.cgs
    sim/testsuite/sim/arm/bic.cgs
    sim/testsuite/sim/arm/bl.cgs
    sim/testsuite/sim/arm/bx.cgs
    sim/testsuite/sim/arm/cmn.cgs
    sim/testsuite/sim/arm/cmp.cgs
    sim/testsuite/sim/arm/eor.cgs
    sim/testsuite/sim/arm/hello.ms
    sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp
    sim/testsuite/sim/arm/iwmmxt/tbcst.cgs
    sim/testsuite/sim/arm/iwmmxt/testutils.inc
    sim/testsuite/sim/arm/iwmmxt/textrm.cgs
    sim/testsuite/sim/arm/iwmmxt/tinsr.cgs
    sim/testsuite/sim/arm/iwmmxt/tmia.cgs
    sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs
    sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs
    sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs
    sim/testsuite/sim/arm/iwmmxt/wacc.cgs
    sim/testsuite/sim/arm/iwmmxt/wadd.cgs
    sim/testsuite/sim/arm/iwmmxt/waligni.cgs
    sim/testsuite/sim/arm/iwmmxt/walignr.cgs
    sim/testsuite/sim/arm/iwmmxt/wand.cgs
    sim/testsuite/sim/arm/iwmmxt/wandn.cgs
    sim/testsuite/sim/arm/iwmmxt/wavg2.cgs
    sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs
    sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs
    sim/testsuite/sim/arm/iwmmxt/wmac.cgs
    sim/testsuite/sim/arm/iwmmxt/wmadd.cgs
    sim/testsuite/sim/arm/iwmmxt/wmax.cgs
    sim/testsuite/sim/arm/iwmmxt/wmin.cgs
    sim/testsuite/sim/arm/iwmmxt/wmov.cgs
    sim/testsuite/sim/arm/iwmmxt/wmul.cgs
    sim/testsuite/sim/arm/iwmmxt/wor.cgs
    sim/testsuite/sim/arm/iwmmxt/wpack.cgs
    sim/testsuite/sim/arm/iwmmxt/wror.cgs
    sim/testsuite/sim/arm/iwmmxt/wsad.cgs
    sim/testsuite/sim/arm/iwmmxt/wshufh.cgs
    sim/testsuite/sim/arm/iwmmxt/wsll.cgs
    sim/testsuite/sim/arm/iwmmxt/wsra.cgs
    sim/testsuite/sim/arm/iwmmxt/wsrl.cgs
    sim/testsuite/sim/arm/iwmmxt/wsub.cgs
    sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs
    sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs
    sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs
    sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs
    sim/testsuite/sim/arm/iwmmxt/wxor.cgs
    sim/testsuite/sim/arm/iwmmxt/wzero.cgs
    sim/testsuite/sim/arm/ldm.cgs
    sim/testsuite/sim/arm/ldr.cgs
    sim/testsuite/sim/arm/ldrb.cgs
    sim/testsuite/sim/arm/ldrh.cgs
    sim/testsuite/sim/arm/ldrsb.cgs
    sim/testsuite/sim/arm/ldrsh.cgs
    sim/testsuite/sim/arm/misaligned1.ms
    sim/testsuite/sim/arm/misaligned2.ms
    sim/testsuite/sim/arm/misaligned3.ms
    sim/testsuite/sim/arm/misc.exp
    sim/testsuite/sim/arm/mla.cgs
    sim/testsuite/sim/arm/mov.cgs
    sim/testsuite/sim/arm/mrs.cgs
    sim/testsuite/sim/arm/msr.cgs
    sim/testsuite/sim/arm/mul.cgs
    sim/testsuite/sim/arm/mvn.cgs
    sim/testsuite/sim/arm/orr.cgs
    sim/testsuite/sim/arm/rsb.cgs
    sim/testsuite/sim/arm/rsc.cgs
    sim/testsuite/sim/arm/sbc.cgs
    sim/testsuite/sim/arm/smlal.cgs
    sim/testsuite/sim/arm/smull.cgs
    sim/testsuite/sim/arm/stm.cgs
    sim/testsuite/sim/arm/str.cgs
    sim/testsuite/sim/arm/strb.cgs
    sim/testsuite/sim/arm/strh.cgs
    sim/testsuite/sim/arm/sub.cgs
    sim/testsuite/sim/arm/swi.cgs
    sim/testsuite/sim/arm/swp.cgs
    sim/testsuite/sim/arm/swpb.cgs
    sim/testsuite/sim/arm/teq.cgs
    sim/testsuite/sim/arm/testutils.inc
    sim/testsuite/sim/arm/thumb/adc.cgs
    sim/testsuite/sim/arm/thumb/add-hd-hs.cgs
    sim/testsuite/sim/arm/thumb/add-hd-rs.cgs
    sim/testsuite/sim/arm/thumb/add-rd-hs.cgs
    sim/testsuite/sim/arm/thumb/add-sp.cgs
    sim/testsuite/sim/arm/thumb/add.cgs
    sim/testsuite/sim/arm/thumb/addi.cgs
    sim/testsuite/sim/arm/thumb/addi8.cgs
    sim/testsuite/sim/arm/thumb/allthumb.exp
    sim/testsuite/sim/arm/thumb/and.cgs
    sim/testsuite/sim/arm/thumb/asr.cgs
    sim/testsuite/sim/arm/thumb/b.cgs
    sim/testsuite/sim/arm/thumb/bcc.cgs
    sim/testsuite/sim/arm/thumb/bcs.cgs
    sim/testsuite/sim/arm/thumb/beq.cgs
    sim/testsuite/sim/arm/thumb/bge.cgs
    sim/testsuite/sim/arm/thumb/bgt.cgs
    sim/testsuite/sim/arm/thumb/bhi.cgs
    sim/testsuite/sim/arm/thumb/bic.cgs
    sim/testsuite/sim/arm/thumb/bl-hi.cgs
    sim/testsuite/sim/arm/thumb/bl-lo.cgs
    sim/testsuite/sim/arm/thumb/ble.cgs
    sim/testsuite/sim/arm/thumb/bls.cgs
    sim/testsuite/sim/arm/thumb/blt.cgs
    sim/testsuite/sim/arm/thumb/bmi.cgs
    sim/testsuite/sim/arm/thumb/bne.cgs
    sim/testsuite/sim/arm/thumb/bpl.cgs
    sim/testsuite/sim/arm/thumb/bvc.cgs
    sim/testsuite/sim/arm/thumb/bvs.cgs
    sim/testsuite/sim/arm/thumb/bx-hs.cgs
    sim/testsuite/sim/arm/thumb/bx-rs.cgs
    sim/testsuite/sim/arm/thumb/cmn.cgs
    sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs
    sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs
    sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs
    sim/testsuite/sim/arm/thumb/cmp.cgs
    sim/testsuite/sim/arm/thumb/eor.cgs
    sim/testsuite/sim/arm/thumb/lda-pc.cgs
    sim/testsuite/sim/arm/thumb/lda-sp.cgs
    sim/testsuite/sim/arm/thumb/ldmia.cgs
    sim/testsuite/sim/arm/thumb/ldr-imm.cgs
    sim/testsuite/sim/arm/thumb/ldr-pc.cgs
    sim/testsuite/sim/arm/thumb/ldr-sprel.cgs
    sim/testsuite/sim/arm/thumb/ldr.cgs
    sim/testsuite/sim/arm/thumb/ldrb-imm.cgs
    sim/testsuite/sim/arm/thumb/ldrb.cgs
    sim/testsuite/sim/arm/thumb/ldrh-imm.cgs
    sim/testsuite/sim/arm/thumb/ldrh.cgs
    sim/testsuite/sim/arm/thumb/ldsb.cgs
    sim/testsuite/sim/arm/thumb/ldsh.cgs
    sim/testsuite/sim/arm/thumb/lsl.cgs
    sim/testsuite/sim/arm/thumb/lsr.cgs
    sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs
    sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs
    sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs
    sim/testsuite/sim/arm/thumb/mov.cgs
    sim/testsuite/sim/arm/thumb/mul.cgs
    sim/testsuite/sim/arm/thumb/mvn.cgs
    sim/testsuite/sim/arm/thumb/neg.cgs
    sim/testsuite/sim/arm/thumb/orr.cgs
    sim/testsuite/sim/arm/thumb/pop-pc.cgs
    sim/testsuite/sim/arm/thumb/pop.cgs
    sim/testsuite/sim/arm/thumb/push-lr.cgs
    sim/testsuite/sim/arm/thumb/push.cgs
    sim/testsuite/sim/arm/thumb/ror.cgs
    sim/testsuite/sim/arm/thumb/sbc.cgs
    sim/testsuite/sim/arm/thumb/stmia.cgs
    sim/testsuite/sim/arm/thumb/str-imm.cgs
    sim/testsuite/sim/arm/thumb/str-sprel.cgs
    sim/testsuite/sim/arm/thumb/str.cgs
    sim/testsuite/sim/arm/thumb/strb-imm.cgs
    sim/testsuite/sim/arm/thumb/strb.cgs
    sim/testsuite/sim/arm/thumb/strh-imm.cgs
    sim/testsuite/sim/arm/thumb/strh.cgs
    sim/testsuite/sim/arm/thumb/sub-sp.cgs
    sim/testsuite/sim/arm/thumb/sub.cgs
    sim/testsuite/sim/arm/thumb/subi.cgs
    sim/testsuite/sim/arm/thumb/subi8.cgs
    sim/testsuite/sim/arm/thumb/swi.cgs
    sim/testsuite/sim/arm/thumb/testutils.inc
    sim/testsuite/sim/arm/thumb/tst.cgs
    sim/testsuite/sim/arm/tst.cgs
    sim/testsuite/sim/arm/umlal.cgs
    sim/testsuite/sim/arm/umull.cgs
    sim/testsuite/sim/arm/xscale/blx.cgs
    sim/testsuite/sim/arm/xscale/mia.cgs
    sim/testsuite/sim/arm/xscale/miaph.cgs
    sim/testsuite/sim/arm/xscale/miaxy.cgs
    sim/testsuite/sim/arm/xscale/mra.cgs
    sim/testsuite/sim/arm/xscale/testutils.inc
    sim/testsuite/sim/arm/xscale/xscale.exp
    sim/testsuite/sim/cris/asm/abs.ms
    sim/testsuite/sim/cris/asm/addc.ms
    sim/testsuite/sim/cris/asm/addcpc.ms
    sim/testsuite/sim/cris/asm/addcv32c.ms
    sim/testsuite/sim/cris/asm/addcv32m.ms
    sim/testsuite/sim/cris/asm/addcv32r.ms
    sim/testsuite/sim/cris/asm/addi.ms
    sim/testsuite/sim/cris/asm/addiv32.ms
    sim/testsuite/sim/cris/asm/addm.ms
    sim/testsuite/sim/cris/asm/addoc.ms
    sim/testsuite/sim/cris/asm/addom.ms
    sim/testsuite/sim/cris/asm/addoq.ms
    sim/testsuite/sim/cris/asm/addq.ms
    sim/testsuite/sim/cris/asm/addqpc.ms
    sim/testsuite/sim/cris/asm/addr.ms
    sim/testsuite/sim/cris/asm/addswpc.ms
    sim/testsuite/sim/cris/asm/addxc.ms
    sim/testsuite/sim/cris/asm/addxm.ms
    sim/testsuite/sim/cris/asm/addxr.ms
    sim/testsuite/sim/cris/asm/andc.ms
    sim/testsuite/sim/cris/asm/andm.ms
    sim/testsuite/sim/cris/asm/andq.ms
    sim/testsuite/sim/cris/asm/andr.ms
    sim/testsuite/sim/cris/asm/asm.exp
    sim/testsuite/sim/cris/asm/asr.ms
    sim/testsuite/sim/cris/asm/ba.ms
    sim/testsuite/sim/cris/asm/bare1.ms
    sim/testsuite/sim/cris/asm/bare2.ms
    sim/testsuite/sim/cris/asm/bas.ms
    sim/testsuite/sim/cris/asm/bccb.ms
    sim/testsuite/sim/cris/asm/bdapc.ms
    sim/testsuite/sim/cris/asm/bdapm.ms
    sim/testsuite/sim/cris/asm/bdapq.ms
    sim/testsuite/sim/cris/asm/bdapqpc.ms
    sim/testsuite/sim/cris/asm/biap.ms
    sim/testsuite/sim/cris/asm/boundc.ms
    sim/testsuite/sim/cris/asm/boundm.ms
    sim/testsuite/sim/cris/asm/boundmv32.ms
    sim/testsuite/sim/cris/asm/boundr.ms
    sim/testsuite/sim/cris/asm/break.ms
    sim/testsuite/sim/cris/asm/btst.ms
    sim/testsuite/sim/cris/asm/ccr-v10.ms
    sim/testsuite/sim/cris/asm/ccs-v32.ms
    sim/testsuite/sim/cris/asm/clearfv10.ms
    sim/testsuite/sim/cris/asm/clearfv32.ms
    sim/testsuite/sim/cris/asm/clrjmp1.ms
    sim/testsuite/sim/cris/asm/cmpc.ms
    sim/testsuite/sim/cris/asm/cmpm.ms
    sim/testsuite/sim/cris/asm/cmpq.ms
    sim/testsuite/sim/cris/asm/cmpr.ms
    sim/testsuite/sim/cris/asm/cmpxc.ms
    sim/testsuite/sim/cris/asm/cmpxm.ms
    sim/testsuite/sim/cris/asm/dflags.ms
    sim/testsuite/sim/cris/asm/dip.ms
    sim/testsuite/sim/cris/asm/dstep.ms
    sim/testsuite/sim/cris/asm/fidxd.ms
    sim/testsuite/sim/cris/asm/fidxi.ms
    sim/testsuite/sim/cris/asm/ftagd.ms
    sim/testsuite/sim/cris/asm/ftagi.ms
    sim/testsuite/sim/cris/asm/halt.ms
    sim/testsuite/sim/cris/asm/io1.ms
    sim/testsuite/sim/cris/asm/io2.ms
    sim/testsuite/sim/cris/asm/io3.ms
    sim/testsuite/sim/cris/asm/io4.ms
    sim/testsuite/sim/cris/asm/io5.ms
    sim/testsuite/sim/cris/asm/io6.ms
    sim/testsuite/sim/cris/asm/io7.ms
    sim/testsuite/sim/cris/asm/io8.ms
    sim/testsuite/sim/cris/asm/io9.ms
    sim/testsuite/sim/cris/asm/jsr.ms
    sim/testsuite/sim/cris/asm/jsrmv10.ms
    sim/testsuite/sim/cris/asm/jumpmp.ms
    sim/testsuite/sim/cris/asm/jumppv32.ms
    sim/testsuite/sim/cris/asm/lapc.ms
    sim/testsuite/sim/cris/asm/lsl.ms
    sim/testsuite/sim/cris/asm/lsr.ms
    sim/testsuite/sim/cris/asm/lz.ms
    sim/testsuite/sim/cris/asm/mcp.ms
    sim/testsuite/sim/cris/asm/movdelsr1.ms
    sim/testsuite/sim/cris/asm/movecpc.ms
    sim/testsuite/sim/cris/asm/movecr.ms
    sim/testsuite/sim/cris/asm/movecrt10.ms
    sim/testsuite/sim/cris/asm/movecrt32.ms
    sim/testsuite/sim/cris/asm/movect10.ms
    sim/testsuite/sim/cris/asm/movei.ms
    sim/testsuite/sim/cris/asm/movempc.ms
    sim/testsuite/sim/cris/asm/movemr.ms
    sim/testsuite/sim/cris/asm/movemrv10.ms
    sim/testsuite/sim/cris/asm/movemrv32.ms
    sim/testsuite/sim/cris/asm/movepcb.ms
    sim/testsuite/sim/cris/asm/movepcd.ms
    sim/testsuite/sim/cris/asm/movepcw.ms
    sim/testsuite/sim/cris/asm/moveq.ms
    sim/testsuite/sim/cris/asm/moveqpc.ms
    sim/testsuite/sim/cris/asm/mover.ms
    sim/testsuite/sim/cris/asm/moverbpc.ms
    sim/testsuite/sim/cris/asm/moverdpc.ms
    sim/testsuite/sim/cris/asm/moverm.ms
    sim/testsuite/sim/cris/asm/moverpcb.ms
    sim/testsuite/sim/cris/asm/moverpcd.ms
    sim/testsuite/sim/cris/asm/moverpcw.ms
    sim/testsuite/sim/cris/asm/moverwpc.ms
    sim/testsuite/sim/cris/asm/movesmp.ms
    sim/testsuite/sim/cris/asm/movmp.ms
    sim/testsuite/sim/cris/asm/movmp8.ms
    sim/testsuite/sim/cris/asm/movpmv10.ms
    sim/testsuite/sim/cris/asm/movpmv32.ms
    sim/testsuite/sim/cris/asm/movppc.ms
    sim/testsuite/sim/cris/asm/movpr.ms
    sim/testsuite/sim/cris/asm/movprv10.ms
    sim/testsuite/sim/cris/asm/movprv32.ms
    sim/testsuite/sim/cris/asm/movrss.ms
    sim/testsuite/sim/cris/asm/movscpc.ms
    sim/testsuite/sim/cris/asm/movscr.ms
    sim/testsuite/sim/cris/asm/movsm.ms
    sim/testsuite/sim/cris/asm/movsmpc.ms
    sim/testsuite/sim/cris/asm/movsr.ms
    sim/testsuite/sim/cris/asm/movsrpc.ms
    sim/testsuite/sim/cris/asm/movssr.ms
    sim/testsuite/sim/cris/asm/movucpc.ms
    sim/testsuite/sim/cris/asm/movucr.ms
    sim/testsuite/sim/cris/asm/movum.ms
    sim/testsuite/sim/cris/asm/movumpc.ms
    sim/testsuite/sim/cris/asm/movur.ms
    sim/testsuite/sim/cris/asm/movurpc.ms
    sim/testsuite/sim/cris/asm/mstep.ms
    sim/testsuite/sim/cris/asm/msteppc1.ms
    sim/testsuite/sim/cris/asm/msteppc2.ms
    sim/testsuite/sim/cris/asm/msteppc3.ms
    sim/testsuite/sim/cris/asm/mulv10.ms
    sim/testsuite/sim/cris/asm/mulv32.ms
    sim/testsuite/sim/cris/asm/mulx.ms
    sim/testsuite/sim/cris/asm/neg.ms
    sim/testsuite/sim/cris/asm/nopv10t.ms
    sim/testsuite/sim/cris/asm/nopv32t.ms
    sim/testsuite/sim/cris/asm/nopv32t2.ms
    sim/testsuite/sim/cris/asm/nopv32t3.ms
    sim/testsuite/sim/cris/asm/nopv32t4.ms
    sim/testsuite/sim/cris/asm/not.ms
    sim/testsuite/sim/cris/asm/op3.ms
    sim/testsuite/sim/cris/asm/opterr1.ms
    sim/testsuite/sim/cris/asm/opterr2.ms
    sim/testsuite/sim/cris/asm/option1.ms
    sim/testsuite/sim/cris/asm/option2.ms
    sim/testsuite/sim/cris/asm/orc.ms
    sim/testsuite/sim/cris/asm/orm.ms
    sim/testsuite/sim/cris/asm/orq.ms
    sim/testsuite/sim/cris/asm/orr.ms
    sim/testsuite/sim/cris/asm/pcplus.ms
    sim/testsuite/sim/cris/asm/raw1.ms
    sim/testsuite/sim/cris/asm/raw10.ms
    sim/testsuite/sim/cris/asm/raw11.ms
    sim/testsuite/sim/cris/asm/raw12.ms
    sim/testsuite/sim/cris/asm/raw13.ms
    sim/testsuite/sim/cris/asm/raw14.ms
    sim/testsuite/sim/cris/asm/raw15.ms
    sim/testsuite/sim/cris/asm/raw16.ms
    sim/testsuite/sim/cris/asm/raw17.ms
    sim/testsuite/sim/cris/asm/raw2.ms
    sim/testsuite/sim/cris/asm/raw3.ms
    sim/testsuite/sim/cris/asm/raw4.ms
    sim/testsuite/sim/cris/asm/raw5.ms
    sim/testsuite/sim/cris/asm/raw6.ms
    sim/testsuite/sim/cris/asm/raw7.ms
    sim/testsuite/sim/cris/asm/raw8.ms
    sim/testsuite/sim/cris/asm/raw9.ms
    sim/testsuite/sim/cris/asm/ret.ms
    sim/testsuite/sim/cris/asm/rfe.ms
    sim/testsuite/sim/cris/asm/rfg.ms
    sim/testsuite/sim/cris/asm/rfn.ms
    sim/testsuite/sim/cris/asm/sbfs.ms
    sim/testsuite/sim/cris/asm/scc.ms
    sim/testsuite/sim/cris/asm/sfe.ms
    sim/testsuite/sim/cris/asm/subc.ms
    sim/testsuite/sim/cris/asm/subm.ms
    sim/testsuite/sim/cris/asm/subq.ms
    sim/testsuite/sim/cris/asm/subqpc.ms
    sim/testsuite/sim/cris/asm/subr.ms
    sim/testsuite/sim/cris/asm/subxc.ms
    sim/testsuite/sim/cris/asm/subxm.ms
    sim/testsuite/sim/cris/asm/subxr.ms
    sim/testsuite/sim/cris/asm/swap.ms
    sim/testsuite/sim/cris/asm/tb.ms
    sim/testsuite/sim/cris/asm/test.ms
    sim/testsuite/sim/cris/asm/testutils.inc
    sim/testsuite/sim/cris/asm/tjmpsrv32-2.ms
    sim/testsuite/sim/cris/asm/tjmpsrv32.ms
    sim/testsuite/sim/cris/asm/tjsrcv10.ms
    sim/testsuite/sim/cris/asm/tjsrcv32.ms
    sim/testsuite/sim/cris/asm/tmemv10.ms
    sim/testsuite/sim/cris/asm/tmemv32.ms
    sim/testsuite/sim/cris/asm/tmulv10.ms
    sim/testsuite/sim/cris/asm/tmulv32.ms
    sim/testsuite/sim/cris/asm/tmvm1.ms
    sim/testsuite/sim/cris/asm/tmvm2.ms
    sim/testsuite/sim/cris/asm/tmvmrv10.ms
    sim/testsuite/sim/cris/asm/tmvmrv32.ms
    sim/testsuite/sim/cris/asm/tmvrmv10.ms
    sim/testsuite/sim/cris/asm/tmvrmv32.ms
    sim/testsuite/sim/cris/asm/user.ms
    sim/testsuite/sim/cris/asm/x0-v10.ms
    sim/testsuite/sim/cris/asm/x0-v32.ms
    sim/testsuite/sim/cris/asm/x1-v10.ms
    sim/testsuite/sim/cris/asm/x1-v32.ms
    sim/testsuite/sim/cris/asm/x10-v10.ms
    sim/testsuite/sim/cris/asm/x2-v10.ms
    sim/testsuite/sim/cris/asm/x2-v32.ms
    sim/testsuite/sim/cris/asm/x3-v10.ms
    sim/testsuite/sim/cris/asm/x3-v32.ms
    sim/testsuite/sim/cris/asm/x4-v32.ms
    sim/testsuite/sim/cris/asm/x5-v10.ms
    sim/testsuite/sim/cris/asm/x5-v32.ms
    sim/testsuite/sim/cris/asm/x6-v10.ms
    sim/testsuite/sim/cris/asm/x6-v32.ms
    sim/testsuite/sim/cris/asm/x7-v10.ms
    sim/testsuite/sim/cris/asm/x7-v32.ms
    sim/testsuite/sim/cris/asm/x8-v10.ms
    sim/testsuite/sim/cris/asm/x9-v10.ms
    sim/testsuite/sim/cris/asm/xor.ms
    sim/testsuite/sim/cris/c/append1.c
    sim/testsuite/sim/cris/c/c.exp
    sim/testsuite/sim/cris/c/clone1.c
    sim/testsuite/sim/cris/c/clone2.c
    sim/testsuite/sim/cris/c/clone3.c
    sim/testsuite/sim/cris/c/clone4.c
    sim/testsuite/sim/cris/c/clone5.c
    sim/testsuite/sim/cris/c/ex1.c
    sim/testsuite/sim/cris/c/fcntl1.c
    sim/testsuite/sim/cris/c/fdopen1.c
    sim/testsuite/sim/cris/c/fdopen2.c
    sim/testsuite/sim/cris/c/freopen1.c
    sim/testsuite/sim/cris/c/ftruncate1.c
    sim/testsuite/sim/cris/c/ftruncate2.c
    sim/testsuite/sim/cris/c/getcwd1.c
    sim/testsuite/sim/cris/c/gettod.c
    sim/testsuite/sim/cris/c/hello.c
    sim/testsuite/sim/cris/c/kill1.c
    sim/testsuite/sim/cris/c/kill2.c
    sim/testsuite/sim/cris/c/kill3.c
    sim/testsuite/sim/cris/c/mapbrk.c
    sim/testsuite/sim/cris/c/mmap1.c
    sim/testsuite/sim/cris/c/mmap2.c
    sim/testsuite/sim/cris/c/mmap3.c
    sim/testsuite/sim/cris/c/mprotect1.c
    sim/testsuite/sim/cris/c/mremap.c
    sim/testsuite/sim/cris/c/openpf1.c
    sim/testsuite/sim/cris/c/openpf2.c
    sim/testsuite/sim/cris/c/openpf3.c
    sim/testsuite/sim/cris/c/openpf4.c
    sim/testsuite/sim/cris/c/openpf5.c
    sim/testsuite/sim/cris/c/pipe1.c
    sim/testsuite/sim/cris/c/pipe2.c
    sim/testsuite/sim/cris/c/pipe3.c
    sim/testsuite/sim/cris/c/pipe4.c
    sim/testsuite/sim/cris/c/pipe5.c
    sim/testsuite/sim/cris/c/pipe6.c
    sim/testsuite/sim/cris/c/pipe7.c
    sim/testsuite/sim/cris/c/readlink1.c
    sim/testsuite/sim/cris/c/readlink10.c
    sim/testsuite/sim/cris/c/readlink2.c
    sim/testsuite/sim/cris/c/readlink3.c
    sim/testsuite/sim/cris/c/readlink4.c
    sim/testsuite/sim/cris/c/readlink5.c
    sim/testsuite/sim/cris/c/readlink6.c
    sim/testsuite/sim/cris/c/readlink7.c
    sim/testsuite/sim/cris/c/readlink8.c
    sim/testsuite/sim/cris/c/readlink9.c
    sim/testsuite/sim/cris/c/rename2.c
    sim/testsuite/sim/cris/c/rtsigprocmask1.c
    sim/testsuite/sim/cris/c/rtsigsuspend1.c
    sim/testsuite/sim/cris/c/sched1.c
    sim/testsuite/sim/cris/c/sched2.c
    sim/testsuite/sim/cris/c/sched3.c
    sim/testsuite/sim/cris/c/sched4.c
    sim/testsuite/sim/cris/c/sched5.c
    sim/testsuite/sim/cris/c/sched6.c
    sim/testsuite/sim/cris/c/sched7.c
    sim/testsuite/sim/cris/c/sched8.c
    sim/testsuite/sim/cris/c/sched9.c
    sim/testsuite/sim/cris/c/seek1.c
    sim/testsuite/sim/cris/c/seek2.c
    sim/testsuite/sim/cris/c/setrlimit1.c
    sim/testsuite/sim/cris/c/sig1.c
    sim/testsuite/sim/cris/c/sig10.c
    sim/testsuite/sim/cris/c/sig11.c
    sim/testsuite/sim/cris/c/sig12.c
    sim/testsuite/sim/cris/c/sig2.c
    sim/testsuite/sim/cris/c/sig3.c
    sim/testsuite/sim/cris/c/sig4.c
    sim/testsuite/sim/cris/c/sig5.c
    sim/testsuite/sim/cris/c/sig6.c
    sim/testsuite/sim/cris/c/sig7.c
    sim/testsuite/sim/cris/c/sig8.c
    sim/testsuite/sim/cris/c/sig9.c
    sim/testsuite/sim/cris/c/sigreturn1.c
    sim/testsuite/sim/cris/c/sigreturn2.c
    sim/testsuite/sim/cris/c/sjlj.c
    sim/testsuite/sim/cris/c/sock1.c
    sim/testsuite/sim/cris/c/stat1.c
    sim/testsuite/sim/cris/c/stat2.c
    sim/testsuite/sim/cris/c/stat3.c
    sim/testsuite/sim/cris/c/stat4.c
    sim/testsuite/sim/cris/c/stat5.c
    sim/testsuite/sim/cris/c/stat7.c
    sim/testsuite/sim/cris/c/stat8.c
    sim/testsuite/sim/cris/c/syscall1.c
    sim/testsuite/sim/cris/c/syscall2.c
    sim/testsuite/sim/cris/c/sysctl1.c
    sim/testsuite/sim/cris/c/sysctl2.c
    sim/testsuite/sim/cris/c/thread2.c
    sim/testsuite/sim/cris/c/thread3.c
    sim/testsuite/sim/cris/c/thread4.c
    sim/testsuite/sim/cris/c/thread5.c
    sim/testsuite/sim/cris/c/time1.c
    sim/testsuite/sim/cris/c/time2.c
    sim/testsuite/sim/cris/c/truncate1.c
    sim/testsuite/sim/cris/c/truncate2.c
    sim/testsuite/sim/cris/c/ugetrlimit1.c
    sim/testsuite/sim/cris/hw/rv-n-cris/host1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq2.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq3.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq4.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq5.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/irq6.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/mbox1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/mem1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/mem2.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/poll1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/quit.s
    sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp
    sim/testsuite/sim/cris/hw/rv-n-cris/std.dev
    sim/testsuite/sim/cris/hw/rv-n-cris/testutils.inc
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial1.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial2.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial3.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial4.r
    sim/testsuite/sim/cris/hw/rv-n-cris/trivial5.ms
    sim/testsuite/sim/cris/hw/rv-n-cris/wd1.ms
    sim/testsuite/sim/fr30/add.cgs
    sim/testsuite/sim/fr30/add.ms
    sim/testsuite/sim/fr30/add2.cgs
    sim/testsuite/sim/fr30/addc.cgs
    sim/testsuite/sim/fr30/addn.cgs
    sim/testsuite/sim/fr30/addn2.cgs
    sim/testsuite/sim/fr30/addsp.cgs
    sim/testsuite/sim/fr30/allinsn.exp
    sim/testsuite/sim/fr30/and.cgs
    sim/testsuite/sim/fr30/andb.cgs
    sim/testsuite/sim/fr30/andccr.cgs
    sim/testsuite/sim/fr30/andh.cgs
    sim/testsuite/sim/fr30/asr.cgs
    sim/testsuite/sim/fr30/asr2.cgs
    sim/testsuite/sim/fr30/bandh.cgs
    sim/testsuite/sim/fr30/bandl.cgs
    sim/testsuite/sim/fr30/bc.cgs
    sim/testsuite/sim/fr30/beorh.cgs
    sim/testsuite/sim/fr30/beorl.cgs
    sim/testsuite/sim/fr30/beq.cgs
    sim/testsuite/sim/fr30/bge.cgs
    sim/testsuite/sim/fr30/bgt.cgs
    sim/testsuite/sim/fr30/bhi.cgs
    sim/testsuite/sim/fr30/ble.cgs
    sim/testsuite/sim/fr30/bls.cgs
    sim/testsuite/sim/fr30/blt.cgs
    sim/testsuite/sim/fr30/bn.cgs
    sim/testsuite/sim/fr30/bnc.cgs
    sim/testsuite/sim/fr30/bne.cgs
    sim/testsuite/sim/fr30/bno.cgs
    sim/testsuite/sim/fr30/bnv.cgs
    sim/testsuite/sim/fr30/borh.cgs
    sim/testsuite/sim/fr30/borl.cgs
    sim/testsuite/sim/fr30/bp.cgs
    sim/testsuite/sim/fr30/bra.cgs
    sim/testsuite/sim/fr30/btsth.cgs
    sim/testsuite/sim/fr30/btstl.cgs
    sim/testsuite/sim/fr30/bv.cgs
    sim/testsuite/sim/fr30/call.cgs
    sim/testsuite/sim/fr30/cmp.cgs
    sim/testsuite/sim/fr30/cmp2.cgs
    sim/testsuite/sim/fr30/copld.cgs
    sim/testsuite/sim/fr30/copop.cgs
    sim/testsuite/sim/fr30/copst.cgs
    sim/testsuite/sim/fr30/copsv.cgs
    sim/testsuite/sim/fr30/div.ms
    sim/testsuite/sim/fr30/div0s.cgs
    sim/testsuite/sim/fr30/div0u.cgs
    sim/testsuite/sim/fr30/div1.cgs
    sim/testsuite/sim/fr30/div2.cgs
    sim/testsuite/sim/fr30/div3.cgs
    sim/testsuite/sim/fr30/div4s.cgs
    sim/testsuite/sim/fr30/dmov.cgs
    sim/testsuite/sim/fr30/dmovb.cgs
    sim/testsuite/sim/fr30/dmovh.cgs
    sim/testsuite/sim/fr30/enter.cgs
    sim/testsuite/sim/fr30/eor.cgs
    sim/testsuite/sim/fr30/eorb.cgs
    sim/testsuite/sim/fr30/eorh.cgs
    sim/testsuite/sim/fr30/extsb.cgs
    sim/testsuite/sim/fr30/extsh.cgs
    sim/testsuite/sim/fr30/extub.cgs
    sim/testsuite/sim/fr30/extuh.cgs
    sim/testsuite/sim/fr30/hello.ms
    sim/testsuite/sim/fr30/int.cgs
    sim/testsuite/sim/fr30/inte.cgs
    sim/testsuite/sim/fr30/jmp.cgs
    sim/testsuite/sim/fr30/ld.cgs
    sim/testsuite/sim/fr30/ldi20.cgs
    sim/testsuite/sim/fr30/ldi32.cgs
    sim/testsuite/sim/fr30/ldi8.cgs
    sim/testsuite/sim/fr30/ldm0.cgs
    sim/testsuite/sim/fr30/ldm1.cgs
    sim/testsuite/sim/fr30/ldres.cgs
    sim/testsuite/sim/fr30/ldub.cgs
    sim/testsuite/sim/fr30/lduh.cgs
    sim/testsuite/sim/fr30/leave.cgs
    sim/testsuite/sim/fr30/lsl.cgs
    sim/testsuite/sim/fr30/lsl2.cgs
    sim/testsuite/sim/fr30/lsr.cgs
    sim/testsuite/sim/fr30/lsr2.cgs
    sim/testsuite/sim/fr30/misc.exp
    sim/testsuite/sim/fr30/mov.cgs
    sim/testsuite/sim/fr30/mul.cgs
    sim/testsuite/sim/fr30/mulh.cgs
    sim/testsuite/sim/fr30/mulu.cgs
    sim/testsuite/sim/fr30/muluh.cgs
    sim/testsuite/sim/fr30/nop.cgs
    sim/testsuite/sim/fr30/or.cgs
    sim/testsuite/sim/fr30/orb.cgs
    sim/testsuite/sim/fr30/orccr.cgs
    sim/testsuite/sim/fr30/orh.cgs
    sim/testsuite/sim/fr30/ret.cgs
    sim/testsuite/sim/fr30/reti.cgs
    sim/testsuite/sim/fr30/st.cgs
    sim/testsuite/sim/fr30/stb.cgs
    sim/testsuite/sim/fr30/sth.cgs
    sim/testsuite/sim/fr30/stilm.cgs
    sim/testsuite/sim/fr30/stm0.cgs
    sim/testsuite/sim/fr30/stm1.cgs
    sim/testsuite/sim/fr30/stres.cgs
    sim/testsuite/sim/fr30/sub.cgs
    sim/testsuite/sim/fr30/subc.cgs
    sim/testsuite/sim/fr30/subn.cgs
    sim/testsuite/sim/fr30/testutils.inc
    sim/testsuite/sim/fr30/xchb.cgs
    sim/testsuite/sim/frv/add.cgs
    sim/testsuite/sim/frv/add.pcgs
    sim/testsuite/sim/frv/addcc.cgs
    sim/testsuite/sim/frv/addi.cgs
    sim/testsuite/sim/frv/addicc.cgs
    sim/testsuite/sim/frv/addx.cgs
    sim/testsuite/sim/frv/addxcc.cgs
    sim/testsuite/sim/frv/addxi.cgs
    sim/testsuite/sim/frv/addxicc.cgs
    sim/testsuite/sim/frv/allinsn.exp
    sim/testsuite/sim/frv/and.cgs
    sim/testsuite/sim/frv/andcc.cgs
    sim/testsuite/sim/frv/andcr.cgs
    sim/testsuite/sim/frv/andi.cgs
    sim/testsuite/sim/frv/andicc.cgs
    sim/testsuite/sim/frv/andncr.cgs
    sim/testsuite/sim/frv/bar.cgs
    sim/testsuite/sim/frv/bc.cgs
    sim/testsuite/sim/frv/bcclr.cgs
    sim/testsuite/sim/frv/bceqlr.cgs
    sim/testsuite/sim/frv/bcgelr.cgs
    sim/testsuite/sim/frv/bcgtlr.cgs
    sim/testsuite/sim/frv/bchilr.cgs
    sim/testsuite/sim/frv/bclelr.cgs
    sim/testsuite/sim/frv/bclr.cgs
    sim/testsuite/sim/frv/bclslr.cgs
    sim/testsuite/sim/frv/bcltlr.cgs
    sim/testsuite/sim/frv/bcnclr.cgs
    sim/testsuite/sim/frv/bcnelr.cgs
    sim/testsuite/sim/frv/bcnlr.cgs
    sim/testsuite/sim/frv/bcnolr.cgs
    sim/testsuite/sim/frv/bcnvlr.cgs
    sim/testsuite/sim/frv/bcplr.cgs
    sim/testsuite/sim/frv/bcralr.cgs
    sim/testsuite/sim/frv/bctrlr.cgs
    sim/testsuite/sim/frv/bcvlr.cgs
    sim/testsuite/sim/frv/beq.cgs
    sim/testsuite/sim/frv/beqlr.cgs
    sim/testsuite/sim/frv/bge.cgs
    sim/testsuite/sim/frv/bgelr.cgs
    sim/testsuite/sim/frv/bgt.cgs
    sim/testsuite/sim/frv/bgtlr.cgs
    sim/testsuite/sim/frv/bhi.cgs
    sim/testsuite/sim/frv/bhilr.cgs
    sim/testsuite/sim/frv/ble.cgs
    sim/testsuite/sim/frv/blelr.cgs
    sim/testsuite/sim/frv/bls.cgs
    sim/testsuite/sim/frv/blslr.cgs
    sim/testsuite/sim/frv/blt.cgs
    sim/testsuite/sim/frv/bltlr.cgs
    sim/testsuite/sim/frv/bn.cgs
    sim/testsuite/sim/frv/bnc.cgs
    sim/testsuite/sim/frv/bnclr.cgs
    sim/testsuite/sim/frv/bne.cgs
    sim/testsuite/sim/frv/bnelr.cgs
    sim/testsuite/sim/frv/bnlr.cgs
    sim/testsuite/sim/frv/bno.cgs
    sim/testsuite/sim/frv/bnolr.cgs
    sim/testsuite/sim/frv/bnv.cgs
    sim/testsuite/sim/frv/bnvlr.cgs
    sim/testsuite/sim/frv/bp.cgs
    sim/testsuite/sim/frv/bplr.cgs
    sim/testsuite/sim/frv/bra.cgs
    sim/testsuite/sim/frv/bralr.cgs
    sim/testsuite/sim/frv/branch.pcgs
    sim/testsuite/sim/frv/break.cgs
    sim/testsuite/sim/frv/bv.cgs
    sim/testsuite/sim/frv/bvlr.cgs
    sim/testsuite/sim/frv/cadd.cgs
    sim/testsuite/sim/frv/caddcc.cgs
    sim/testsuite/sim/frv/call.cgs
    sim/testsuite/sim/frv/call.pcgs
    sim/testsuite/sim/frv/callil.cgs
    sim/testsuite/sim/frv/calll.cgs
    sim/testsuite/sim/frv/cand.cgs
    sim/testsuite/sim/frv/candcc.cgs
    sim/testsuite/sim/frv/ccalll.cgs
    sim/testsuite/sim/frv/cckc.cgs
    sim/testsuite/sim/frv/cckeq.cgs
    sim/testsuite/sim/frv/cckge.cgs
    sim/testsuite/sim/frv/cckgt.cgs
    sim/testsuite/sim/frv/cckhi.cgs
    sim/testsuite/sim/frv/cckle.cgs
    sim/testsuite/sim/frv/cckls.cgs
    sim/testsuite/sim/frv/ccklt.cgs
    sim/testsuite/sim/frv/cckn.cgs
    sim/testsuite/sim/frv/ccknc.cgs
    sim/testsuite/sim/frv/cckne.cgs
    sim/testsuite/sim/frv/cckno.cgs
    sim/testsuite/sim/frv/ccknv.cgs
    sim/testsuite/sim/frv/cckp.cgs
    sim/testsuite/sim/frv/cckra.cgs
    sim/testsuite/sim/frv/cckv.cgs
    sim/testsuite/sim/frv/ccmp.cgs
    sim/testsuite/sim/frv/cfabss.cgs
    sim/testsuite/sim/frv/cfadds.cgs
    sim/testsuite/sim/frv/cfckeq.cgs
    sim/testsuite/sim/frv/cfckge.cgs
    sim/testsuite/sim/frv/cfckgt.cgs
    sim/testsuite/sim/frv/cfckle.cgs
    sim/testsuite/sim/frv/cfcklg.cgs
    sim/testsuite/sim/frv/cfcklt.cgs
    sim/testsuite/sim/frv/cfckne.cgs
    sim/testsuite/sim/frv/cfckno.cgs
    sim/testsuite/sim/frv/cfcko.cgs
    sim/testsuite/sim/frv/cfckra.cgs
    sim/testsuite/sim/frv/cfcku.cgs
    sim/testsuite/sim/frv/cfckue.cgs
    sim/testsuite/sim/frv/cfckug.cgs
    sim/testsuite/sim/frv/cfckuge.cgs
    sim/testsuite/sim/frv/cfckul.cgs
    sim/testsuite/sim/frv/cfckule.cgs
    sim/testsuite/sim/frv/cfcmps.cgs
    sim/testsuite/sim/frv/cfdivs.cgs
    sim/testsuite/sim/frv/cfitos.cgs
    sim/testsuite/sim/frv/cfmadds.cgs
    sim/testsuite/sim/frv/cfmas.cgs
    sim/testsuite/sim/frv/cfmovs.cgs
    sim/testsuite/sim/frv/cfmss.cgs
    sim/testsuite/sim/frv/cfmsubs.cgs
    sim/testsuite/sim/frv/cfmuls.cgs
    sim/testsuite/sim/frv/cfnegs.cgs
    sim/testsuite/sim/frv/cfsqrts.cgs
    sim/testsuite/sim/frv/cfstoi.cgs
    sim/testsuite/sim/frv/cfsubs.cgs
    sim/testsuite/sim/frv/cjmpl.cgs
    sim/testsuite/sim/frv/ckc.cgs
    sim/testsuite/sim/frv/ckeq.cgs
    sim/testsuite/sim/frv/ckge.cgs
    sim/testsuite/sim/frv/ckgt.cgs
    sim/testsuite/sim/frv/ckhi.cgs
    sim/testsuite/sim/frv/ckle.cgs
    sim/testsuite/sim/frv/ckls.cgs
    sim/testsuite/sim/frv/cklt.cgs
    sim/testsuite/sim/frv/ckn.cgs
    sim/testsuite/sim/frv/cknc.cgs
    sim/testsuite/sim/frv/ckne.cgs
    sim/testsuite/sim/frv/ckno.cgs
    sim/testsuite/sim/frv/cknv.cgs
    sim/testsuite/sim/frv/ckp.cgs
    sim/testsuite/sim/frv/ckra.cgs
    sim/testsuite/sim/frv/ckv.cgs
    sim/testsuite/sim/frv/cld.cgs
    sim/testsuite/sim/frv/cldbf.cgs
    sim/testsuite/sim/frv/cldbfu.cgs
    sim/testsuite/sim/frv/cldd.cgs
    sim/testsuite/sim/frv/clddf.cgs
    sim/testsuite/sim/frv/clddfu.cgs
    sim/testsuite/sim/frv/clddu.cgs
    sim/testsuite/sim/frv/cldf.cgs
    sim/testsuite/sim/frv/cldfu.cgs
    sim/testsuite/sim/frv/cldhf.cgs
    sim/testsuite/sim/frv/cldhfu.cgs
    sim/testsuite/sim/frv/cldq.cgs
    sim/testsuite/sim/frv/cldqu.cgs
    sim/testsuite/sim/frv/cldsb.cgs
    sim/testsuite/sim/frv/cldsbu.cgs
    sim/testsuite/sim/frv/cldsh.cgs
    sim/testsuite/sim/frv/cldshu.cgs
    sim/testsuite/sim/frv/cldu.cgs
    sim/testsuite/sim/frv/cldub.cgs
    sim/testsuite/sim/frv/cldubu.cgs
    sim/testsuite/sim/frv/clduh.cgs
    sim/testsuite/sim/frv/clduhu.cgs
    sim/testsuite/sim/frv/clrfa.cgs
    sim/testsuite/sim/frv/clrfr.cgs
    sim/testsuite/sim/frv/clrga.cgs
    sim/testsuite/sim/frv/clrgr.cgs
    sim/testsuite/sim/frv/cmaddhss.cgs
    sim/testsuite/sim/frv/cmaddhus.cgs
    sim/testsuite/sim/frv/cmand.cgs
    sim/testsuite/sim/frv/cmbtoh.cgs
    sim/testsuite/sim/frv/cmbtohe.cgs
    sim/testsuite/sim/frv/cmcpxis.cgs
    sim/testsuite/sim/frv/cmcpxiu.cgs
    sim/testsuite/sim/frv/cmcpxrs.cgs
    sim/testsuite/sim/frv/cmcpxru.cgs
    sim/testsuite/sim/frv/cmexpdhd.cgs
    sim/testsuite/sim/frv/cmexpdhw.cgs
    sim/testsuite/sim/frv/cmhtob.cgs
    sim/testsuite/sim/frv/cmmachs.cgs
    sim/testsuite/sim/frv/cmmachu.cgs
    sim/testsuite/sim/frv/cmmulhs.cgs
    sim/testsuite/sim/frv/cmmulhu.cgs
    sim/testsuite/sim/frv/cmnot.cgs
    sim/testsuite/sim/frv/cmor.cgs
    sim/testsuite/sim/frv/cmov.cgs
    sim/testsuite/sim/frv/cmovfg.cgs
    sim/testsuite/sim/frv/cmovfgd.cgs
    sim/testsuite/sim/frv/cmovgf.cgs
    sim/testsuite/sim/frv/cmovgfd.cgs
    sim/testsuite/sim/frv/cmp.cgs
    sim/testsuite/sim/frv/cmpb.cgs
    sim/testsuite/sim/frv/cmpba.cgs
    sim/testsuite/sim/frv/cmpi.cgs
    sim/testsuite/sim/frv/cmqmachs.cgs
    sim/testsuite/sim/frv/cmqmachu.cgs
    sim/testsuite/sim/frv/cmqmulhs.cgs
    sim/testsuite/sim/frv/cmqmulhu.cgs
    sim/testsuite/sim/frv/cmsubhss.cgs
    sim/testsuite/sim/frv/cmsubhus.cgs
    sim/testsuite/sim/frv/cmxor.cgs
    sim/testsuite/sim/frv/cnot.cgs
    sim/testsuite/sim/frv/commitfa.cgs
    sim/testsuite/sim/frv/commitfr.cgs
    sim/testsuite/sim/frv/commitga.cgs
    sim/testsuite/sim/frv/commitgr.cgs
    sim/testsuite/sim/frv/cop1.cgs
    sim/testsuite/sim/frv/cop2.cgs
    sim/testsuite/sim/frv/cor.cgs
    sim/testsuite/sim/frv/corcc.cgs
    sim/testsuite/sim/frv/cscan.cgs
    sim/testsuite/sim/frv/csdiv.cgs
    sim/testsuite/sim/frv/csll.cgs
    sim/testsuite/sim/frv/csllcc.cgs
    sim/testsuite/sim/frv/csmul.cgs
    sim/testsuite/sim/frv/csmulcc.cgs
    sim/testsuite/sim/frv/csra.cgs
    sim/testsuite/sim/frv/csracc.cgs
    sim/testsuite/sim/frv/csrl.cgs
    sim/testsuite/sim/frv/csrlcc.cgs
    sim/testsuite/sim/frv/cst.cgs
    sim/testsuite/sim/frv/cstb.cgs
    sim/testsuite/sim/frv/cstbf.cgs
    sim/testsuite/sim/frv/cstbfu.cgs
    sim/testsuite/sim/frv/cstbu.cgs
    sim/testsuite/sim/frv/cstd.cgs
    sim/testsuite/sim/frv/cstdf.cgs
    sim/testsuite/sim/frv/cstdfu.cgs
    sim/testsuite/sim/frv/cstdu.cgs
    sim/testsuite/sim/frv/cstf.cgs
    sim/testsuite/sim/frv/cstfu.cgs
    sim/testsuite/sim/frv/csth.cgs
    sim/testsuite/sim/frv/csthf.cgs
    sim/testsuite/sim/frv/csthfu.cgs
    sim/testsuite/sim/frv/csthu.cgs
    sim/testsuite/sim/frv/cstq.cgs
    sim/testsuite/sim/frv/cstu.cgs
    sim/testsuite/sim/frv/csub.cgs
    sim/testsuite/sim/frv/csubcc.cgs
    sim/testsuite/sim/frv/cswap.cgs
    sim/testsuite/sim/frv/cudiv.cgs
    sim/testsuite/sim/frv/cxor.cgs
    sim/testsuite/sim/frv/cxorcc.cgs
    sim/testsuite/sim/frv/dcef.cgs
    sim/testsuite/sim/frv/dcei.cgs
    sim/testsuite/sim/frv/dcf.cgs
    sim/testsuite/sim/frv/dci.cgs
    sim/testsuite/sim/frv/fabsd.cgs
    sim/testsuite/sim/frv/fabss.cgs
    sim/testsuite/sim/frv/faddd.cgs
    sim/testsuite/sim/frv/fadds.cgs
    sim/testsuite/sim/frv/fbeq.cgs
    sim/testsuite/sim/frv/fbeqlr.cgs
    sim/testsuite/sim/frv/fbge.cgs
    sim/testsuite/sim/frv/fbgelr.cgs
    sim/testsuite/sim/frv/fbgt.cgs
    sim/testsuite/sim/frv/fbgtlr.cgs
    sim/testsuite/sim/frv/fble.cgs
    sim/testsuite/sim/frv/fblelr.cgs
    sim/testsuite/sim/frv/fblg.cgs
    sim/testsuite/sim/frv/fblglr.cgs
    sim/testsuite/sim/frv/fblt.cgs
    sim/testsuite/sim/frv/fbltlr.cgs
    sim/testsuite/sim/frv/fbne.cgs
    sim/testsuite/sim/frv/fbnelr.cgs
    sim/testsuite/sim/frv/fbno.cgs
    sim/testsuite/sim/frv/fbnolr.cgs
    sim/testsuite/sim/frv/fbo.cgs
    sim/testsuite/sim/frv/fbolr.cgs
    sim/testsuite/sim/frv/fbra.cgs
    sim/testsuite/sim/frv/fbralr.cgs
    sim/testsuite/sim/frv/fbu.cgs
    sim/testsuite/sim/frv/fbue.cgs
    sim/testsuite/sim/frv/fbuelr.cgs
    sim/testsuite/sim/frv/fbug.cgs
    sim/testsuite/sim/frv/fbuge.cgs
    sim/testsuite/sim/frv/fbugelr.cgs
    sim/testsuite/sim/frv/fbuglr.cgs
    sim/testsuite/sim/frv/fbul.cgs
    sim/testsuite/sim/frv/fbule.cgs
    sim/testsuite/sim/frv/fbulelr.cgs
    sim/testsuite/sim/frv/fbullr.cgs
    sim/testsuite/sim/frv/fbulr.cgs
    sim/testsuite/sim/frv/fcbeqlr.cgs
    sim/testsuite/sim/frv/fcbgelr.cgs
    sim/testsuite/sim/frv/fcbgtlr.cgs
    sim/testsuite/sim/frv/fcblelr.cgs
    sim/testsuite/sim/frv/fcblglr.cgs
    sim/testsuite/sim/frv/fcbltlr.cgs
    sim/testsuite/sim/frv/fcbnelr.cgs
    sim/testsuite/sim/frv/fcbnolr.cgs
    sim/testsuite/sim/frv/fcbolr.cgs
    sim/testsuite/sim/frv/fcbralr.cgs
    sim/testsuite/sim/frv/fcbuelr.cgs
    sim/testsuite/sim/frv/fcbugelr.cgs
    sim/testsuite/sim/frv/fcbuglr.cgs
    sim/testsuite/sim/frv/fcbulelr.cgs
    sim/testsuite/sim/frv/fcbullr.cgs
    sim/testsuite/sim/frv/fcbulr.cgs
    sim/testsuite/sim/frv/fckeq.cgs
    sim/testsuite/sim/frv/fckge.cgs
    sim/testsuite/sim/frv/fckgt.cgs
    sim/testsuite/sim/frv/fckle.cgs
    sim/testsuite/sim/frv/fcklg.cgs
    sim/testsuite/sim/frv/fcklt.cgs
    sim/testsuite/sim/frv/fckne.cgs
    sim/testsuite/sim/frv/fckno.cgs
    sim/testsuite/sim/frv/fcko.cgs
    sim/testsuite/sim/frv/fckra.cgs
    sim/testsuite/sim/frv/fcku.cgs
    sim/testsuite/sim/frv/fckue.cgs
    sim/testsuite/sim/frv/fckug.cgs
    sim/testsuite/sim/frv/fckuge.cgs
    sim/testsuite/sim/frv/fckul.cgs
    sim/testsuite/sim/frv/fckule.cgs
    sim/testsuite/sim/frv/fcmpd.cgs
    sim/testsuite/sim/frv/fcmps.cgs
    sim/testsuite/sim/frv/fdabss.cgs
    sim/testsuite/sim/frv/fdadds.cgs
    sim/testsuite/sim/frv/fdcmps.cgs
    sim/testsuite/sim/frv/fddivs.cgs
    sim/testsuite/sim/frv/fditos.cgs
    sim/testsuite/sim/frv/fdivd.cgs
    sim/testsuite/sim/frv/fdivs.cgs
    sim/testsuite/sim/frv/fdmadds.cgs
    sim/testsuite/sim/frv/fdmas.cgs
    sim/testsuite/sim/frv/fdmovs.cgs
    sim/testsuite/sim/frv/fdmss.cgs
    sim/testsuite/sim/frv/fdmulcs.cgs
    sim/testsuite/sim/frv/fdmuls.cgs
    sim/testsuite/sim/frv/fdnegs.cgs
    sim/testsuite/sim/frv/fdsads.cgs
    sim/testsuite/sim/frv/fdsqrts.cgs
    sim/testsuite/sim/frv/fdstoi.cgs
    sim/testsuite/sim/frv/fdsubs.cgs
    sim/testsuite/sim/frv/fdtoi.cgs
    sim/testsuite/sim/frv/fitod.cgs
    sim/testsuite/sim/frv/fitos.cgs
    sim/testsuite/sim/frv/fmad.cgs
    sim/testsuite/sim/frv/fmaddd.cgs
    sim/testsuite/sim/frv/fmadds.cgs
    sim/testsuite/sim/frv/fmas.cgs
    sim/testsuite/sim/frv/fmovd.cgs
    sim/testsuite/sim/frv/fmovs.cgs
    sim/testsuite/sim/frv/fmsd.cgs
    sim/testsuite/sim/frv/fmss.cgs
    sim/testsuite/sim/frv/fmsubd.cgs
    sim/testsuite/sim/frv/fmsubs.cgs
    sim/testsuite/sim/frv/fmuld.cgs
    sim/testsuite/sim/frv/fmuls.cgs
    sim/testsuite/sim/frv/fnegd.cgs
    sim/testsuite/sim/frv/fnegs.cgs
    sim/testsuite/sim/frv/fnop.cgs
    sim/testsuite/sim/frv/fr400/addss.cgs
    sim/testsuite/sim/frv/fr400/allinsn.exp
    sim/testsuite/sim/frv/fr400/csdiv.cgs
    sim/testsuite/sim/frv/fr400/maddaccs.cgs
    sim/testsuite/sim/frv/fr400/masaccs.cgs
    sim/testsuite/sim/frv/fr400/maveh.cgs
    sim/testsuite/sim/frv/fr400/mclracc.cgs
    sim/testsuite/sim/frv/fr400/mhdseth.cgs
    sim/testsuite/sim/frv/fr400/mhdsets.cgs
    sim/testsuite/sim/frv/fr400/mhsethih.cgs
    sim/testsuite/sim/frv/fr400/mhsethis.cgs
    sim/testsuite/sim/frv/fr400/mhsetloh.cgs
    sim/testsuite/sim/frv/fr400/mhsetlos.cgs
    sim/testsuite/sim/frv/fr400/movgs.cgs
    sim/testsuite/sim/frv/fr400/movsg.cgs
    sim/testsuite/sim/frv/fr400/msubaccs.cgs
    sim/testsuite/sim/frv/fr400/scutss.cgs
    sim/testsuite/sim/frv/fr400/sdiv.cgs
    sim/testsuite/sim/frv/fr400/sdivi.cgs
    sim/testsuite/sim/frv/fr400/slass.cgs
    sim/testsuite/sim/frv/fr400/smass.cgs
    sim/testsuite/sim/frv/fr400/smsss.cgs
    sim/testsuite/sim/frv/fr400/smu.cgs
    sim/testsuite/sim/frv/fr400/subss.cgs
    sim/testsuite/sim/frv/fr400/udiv.cgs
    sim/testsuite/sim/frv/fr400/udivi.cgs
    sim/testsuite/sim/frv/fr500/allinsn.exp
    sim/testsuite/sim/frv/fr500/cmqaddhss.cgs
    sim/testsuite/sim/frv/fr500/cmqaddhus.cgs
    sim/testsuite/sim/frv/fr500/cmqsubhss.cgs
    sim/testsuite/sim/frv/fr500/cmqsubhus.cgs
    sim/testsuite/sim/frv/fr500/dcpl.cgs
    sim/testsuite/sim/frv/fr500/dcul.cgs
    sim/testsuite/sim/frv/fr500/mclracc.cgs
    sim/testsuite/sim/frv/fr500/mqaddhss.cgs
    sim/testsuite/sim/frv/fr500/mqaddhus.cgs
    sim/testsuite/sim/frv/fr500/mqsubhss.cgs
    sim/testsuite/sim/frv/fr500/mqsubhus.cgs
    sim/testsuite/sim/frv/fr550/allinsn.exp
    sim/testsuite/sim/frv/fr550/cmaddhss.cgs
    sim/testsuite/sim/frv/fr550/cmaddhus.cgs
    sim/testsuite/sim/frv/fr550/cmcpxiu.cgs
    sim/testsuite/sim/frv/fr550/cmcpxru.cgs
    sim/testsuite/sim/frv/fr550/cmmachs.cgs
    sim/testsuite/sim/frv/fr550/cmmachu.cgs
    sim/testsuite/sim/frv/fr550/cmqaddhss.cgs
    sim/testsuite/sim/frv/fr550/cmqaddhus.cgs
    sim/testsuite/sim/frv/fr550/cmqmachs.cgs
    sim/testsuite/sim/frv/fr550/cmqmachu.cgs
    sim/testsuite/sim/frv/fr550/cmqsubhss.cgs
    sim/testsuite/sim/frv/fr550/cmqsubhus.cgs
    sim/testsuite/sim/frv/fr550/cmsubhss.cgs
    sim/testsuite/sim/frv/fr550/cmsubhus.cgs
    sim/testsuite/sim/frv/fr550/dcpl.cgs
    sim/testsuite/sim/frv/fr550/dcul.cgs
    sim/testsuite/sim/frv/fr550/mabshs.cgs
    sim/testsuite/sim/frv/fr550/maddaccs.cgs
    sim/testsuite/sim/frv/fr550/maddhss.cgs
    sim/testsuite/sim/frv/fr550/maddhus.cgs
    sim/testsuite/sim/frv/fr550/masaccs.cgs
    sim/testsuite/sim/frv/fr550/mdaddaccs.cgs
    sim/testsuite/sim/frv/fr550/mdasaccs.cgs
    sim/testsuite/sim/frv/fr550/mdsubaccs.cgs
    sim/testsuite/sim/frv/fr550/mmachs.cgs
    sim/testsuite/sim/frv/fr550/mmachu.cgs
    sim/testsuite/sim/frv/fr550/mmrdhs.cgs
    sim/testsuite/sim/frv/fr550/mmrdhu.cgs
    sim/testsuite/sim/frv/fr550/mqaddhss.cgs
    sim/testsuite/sim/frv/fr550/mqaddhus.cgs
    sim/testsuite/sim/frv/fr550/mqmachs.cgs
    sim/testsuite/sim/frv/fr550/mqmachu.cgs
    sim/testsuite/sim/frv/fr550/mqmacxhs.cgs
    sim/testsuite/sim/frv/fr550/mqsubhss.cgs
    sim/testsuite/sim/frv/fr550/mqsubhus.cgs
    sim/testsuite/sim/frv/fr550/mqxmachs.cgs
    sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs
    sim/testsuite/sim/frv/fr550/msubaccs.cgs
    sim/testsuite/sim/frv/fr550/msubhss.cgs
    sim/testsuite/sim/frv/fr550/msubhus.cgs
    sim/testsuite/sim/frv/fr550/mtrap.cgs
    sim/testsuite/sim/frv/fr550/udiv.cgs
    sim/testsuite/sim/frv/fr550/udivi.cgs
    sim/testsuite/sim/frv/fsqrtd.cgs
    sim/testsuite/sim/frv/fsqrts.cgs
    sim/testsuite/sim/frv/fstoi.cgs
    sim/testsuite/sim/frv/fsubd.cgs
    sim/testsuite/sim/frv/fsubs.cgs
    sim/testsuite/sim/frv/fteq.cgs
    sim/testsuite/sim/frv/ftge.cgs
    sim/testsuite/sim/frv/ftgt.cgs
    sim/testsuite/sim/frv/ftieq.cgs
    sim/testsuite/sim/frv/ftige.cgs
    sim/testsuite/sim/frv/ftigt.cgs
    sim/testsuite/sim/frv/ftile.cgs
    sim/testsuite/sim/frv/ftilg.cgs
    sim/testsuite/sim/frv/ftilt.cgs
    sim/testsuite/sim/frv/ftine.cgs
    sim/testsuite/sim/frv/ftino.cgs
    sim/testsuite/sim/frv/ftio.cgs
    sim/testsuite/sim/frv/ftira.cgs
    sim/testsuite/sim/frv/ftiu.cgs
    sim/testsuite/sim/frv/ftiue.cgs
    sim/testsuite/sim/frv/ftiug.cgs
    sim/testsuite/sim/frv/ftiuge.cgs
    sim/testsuite/sim/frv/ftiul.cgs
    sim/testsuite/sim/frv/ftle.cgs
    sim/testsuite/sim/frv/ftlg.cgs
    sim/testsuite/sim/frv/ftlt.cgs
    sim/testsuite/sim/frv/ftne.cgs
    sim/testsuite/sim/frv/ftno.cgs
    sim/testsuite/sim/frv/fto.cgs
    sim/testsuite/sim/frv/ftra.cgs
    sim/testsuite/sim/frv/ftu.cgs
    sim/testsuite/sim/frv/ftue.cgs
    sim/testsuite/sim/frv/ftug.cgs
    sim/testsuite/sim/frv/ftuge.cgs
    sim/testsuite/sim/frv/ftul.cgs
    sim/testsuite/sim/frv/ftule.cgs
    sim/testsuite/sim/frv/icei.cgs
    sim/testsuite/sim/frv/ici.cgs
    sim/testsuite/sim/frv/icpl.cgs
    sim/testsuite/sim/frv/icul.cgs
    sim/testsuite/sim/frv/interrupts.exp
    sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs
    sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs
    sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs
    sim/testsuite/sim/frv/interrupts/badalign.cgs
    sim/testsuite/sim/frv/interrupts/compound-fr550.cgs
    sim/testsuite/sim/frv/interrupts/compound.cgs
    sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs
    sim/testsuite/sim/frv/interrupts/data_store_error.cgs
    sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
    sim/testsuite/sim/frv/interrupts/fp_exception.cgs
    sim/testsuite/sim/frv/interrupts/illinsn.cgs
    sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs
    sim/testsuite/sim/frv/interrupts/insn_access_error.cgs
    sim/testsuite/sim/frv/interrupts/mp_exception.cgs
    sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs
    sim/testsuite/sim/frv/interrupts/regalign.cgs
    sim/testsuite/sim/frv/interrupts/reset.cgs
    sim/testsuite/sim/frv/interrupts/shadow_regs.cgs
    sim/testsuite/sim/frv/interrupts/timer.cgs
    sim/testsuite/sim/frv/jmpil.cgs
    sim/testsuite/sim/frv/jmpl.cgs
    sim/testsuite/sim/frv/jmpl.pcgs
    sim/testsuite/sim/frv/ld.cgs
    sim/testsuite/sim/frv/ldbf.cgs
    sim/testsuite/sim/frv/ldbfi.cgs
    sim/testsuite/sim/frv/ldbfu.cgs
    sim/testsuite/sim/frv/ldc.cgs
    sim/testsuite/sim/frv/ldcu.cgs
    sim/testsuite/sim/frv/ldd.cgs
    sim/testsuite/sim/frv/lddc.cgs
    sim/testsuite/sim/frv/lddcu.cgs
    sim/testsuite/sim/frv/lddf.cgs
    sim/testsuite/sim/frv/lddfi.cgs
    sim/testsuite/sim/frv/lddfu.cgs
    sim/testsuite/sim/frv/lddi.cgs
    sim/testsuite/sim/frv/lddu.cgs
    sim/testsuite/sim/frv/ldf.cgs
    sim/testsuite/sim/frv/ldfi.cgs
    sim/testsuite/sim/frv/ldfu.cgs
    sim/testsuite/sim/frv/ldhf.cgs
    sim/testsuite/sim/frv/ldhfi.cgs
    sim/testsuite/sim/frv/ldhfu.cgs
    sim/testsuite/sim/frv/ldi.cgs
    sim/testsuite/sim/frv/ldq.cgs
    sim/testsuite/sim/frv/ldqc.cgs
    sim/testsuite/sim/frv/ldqcu.cgs
    sim/testsuite/sim/frv/ldqf.cgs
    sim/testsuite/sim/frv/ldqfi.cgs
    sim/testsuite/sim/frv/ldqfu.cgs
    sim/testsuite/sim/frv/ldqi.cgs
    sim/testsuite/sim/frv/ldqu.cgs
    sim/testsuite/sim/frv/ldsb.cgs
    sim/testsuite/sim/frv/ldsbi.cgs
    sim/testsuite/sim/frv/ldsbu.cgs
    sim/testsuite/sim/frv/ldsh.cgs
    sim/testsuite/sim/frv/ldshi.cgs
    sim/testsuite/sim/frv/ldshu.cgs
    sim/testsuite/sim/frv/ldu.cgs
    sim/testsuite/sim/frv/ldub.cgs
    sim/testsuite/sim/frv/ldubi.cgs
    sim/testsuite/sim/frv/ldubu.cgs
    sim/testsuite/sim/frv/lduh.cgs
    sim/testsuite/sim/frv/lduhi.cgs
    sim/testsuite/sim/frv/lduhu.cgs
    sim/testsuite/sim/frv/lrbranch.pcgs
    sim/testsuite/sim/frv/mabshs.cgs
    sim/testsuite/sim/frv/maddhss.cgs
    sim/testsuite/sim/frv/maddhus.cgs
    sim/testsuite/sim/frv/mand.cgs
    sim/testsuite/sim/frv/maveh.cgs
    sim/testsuite/sim/frv/mbtoh.cgs
    sim/testsuite/sim/frv/mbtohe.cgs
    sim/testsuite/sim/frv/mclracc.cgs
    sim/testsuite/sim/frv/mcmpsh.cgs
    sim/testsuite/sim/frv/mcmpuh.cgs
    sim/testsuite/sim/frv/mcop1.cgs
    sim/testsuite/sim/frv/mcop2.cgs
    sim/testsuite/sim/frv/mcplhi.cgs
    sim/testsuite/sim/frv/mcpli.cgs
    sim/testsuite/sim/frv/mcpxis.cgs
    sim/testsuite/sim/frv/mcpxiu.cgs
    sim/testsuite/sim/frv/mcpxrs.cgs
    sim/testsuite/sim/frv/mcpxru.cgs
    sim/testsuite/sim/frv/mcut.cgs
    sim/testsuite/sim/frv/mcuti.cgs
    sim/testsuite/sim/frv/mcutss.cgs
    sim/testsuite/sim/frv/mcutssi.cgs
    sim/testsuite/sim/frv/mdaddaccs.cgs
    sim/testsuite/sim/frv/mdasaccs.cgs
    sim/testsuite/sim/frv/mdcutssi.cgs
    sim/testsuite/sim/frv/mdpackh.cgs
    sim/testsuite/sim/frv/mdrotli.cgs
    sim/testsuite/sim/frv/mdsubaccs.cgs
    sim/testsuite/sim/frv/mdunpackh.cgs
    sim/testsuite/sim/frv/membar.cgs
    sim/testsuite/sim/frv/mexpdhd.cgs
    sim/testsuite/sim/frv/mexpdhw.cgs
    sim/testsuite/sim/frv/mhdseth.cgs
    sim/testsuite/sim/frv/mhdsets.cgs
    sim/testsuite/sim/frv/mhsethih.cgs
    sim/testsuite/sim/frv/mhsethis.cgs
    sim/testsuite/sim/frv/mhsetloh.cgs
    sim/testsuite/sim/frv/mhsetlos.cgs
    sim/testsuite/sim/frv/mhtob.cgs
    sim/testsuite/sim/frv/mmachs.cgs
    sim/testsuite/sim/frv/mmachu.cgs
    sim/testsuite/sim/frv/mmrdhs.cgs
    sim/testsuite/sim/frv/mmrdhu.cgs
    sim/testsuite/sim/frv/mmulhs.cgs
    sim/testsuite/sim/frv/mmulhu.cgs
    sim/testsuite/sim/frv/mmulxhs.cgs
    sim/testsuite/sim/frv/mmulxhu.cgs
    sim/testsuite/sim/frv/mnop.cgs
    sim/testsuite/sim/frv/mnot.cgs
    sim/testsuite/sim/frv/mor.cgs
    sim/testsuite/sim/frv/mov.cgs
    sim/testsuite/sim/frv/movfg.cgs
    sim/testsuite/sim/frv/movfgd.cgs
    sim/testsuite/sim/frv/movfgq.cgs
    sim/testsuite/sim/frv/movgf.cgs
    sim/testsuite/sim/frv/movgfd.cgs
    sim/testsuite/sim/frv/movgfq.cgs
    sim/testsuite/sim/frv/movgs.cgs
    sim/testsuite/sim/frv/movsg.cgs
    sim/testsuite/sim/frv/mpackh.cgs
    sim/testsuite/sim/frv/mqcpxis.cgs
    sim/testsuite/sim/frv/mqcpxiu.cgs
    sim/testsuite/sim/frv/mqcpxrs.cgs
    sim/testsuite/sim/frv/mqcpxru.cgs
    sim/testsuite/sim/frv/mqlclrhs.cgs
    sim/testsuite/sim/frv/mqlmths.cgs
    sim/testsuite/sim/frv/mqmachs.cgs
    sim/testsuite/sim/frv/mqmachu.cgs
    sim/testsuite/sim/frv/mqmacxhs.cgs
    sim/testsuite/sim/frv/mqmulhs.cgs
    sim/testsuite/sim/frv/mqmulhu.cgs
    sim/testsuite/sim/frv/mqmulxhs.cgs
    sim/testsuite/sim/frv/mqmulxhu.cgs
    sim/testsuite/sim/frv/mqsaths.cgs
    sim/testsuite/sim/frv/mqsllhi.cgs
    sim/testsuite/sim/frv/mqsrahi.cgs
    sim/testsuite/sim/frv/mqxmachs.cgs
    sim/testsuite/sim/frv/mqxmacxhs.cgs
    sim/testsuite/sim/frv/mrdacc.cgs
    sim/testsuite/sim/frv/mrdaccg.cgs
    sim/testsuite/sim/frv/mrotli.cgs
    sim/testsuite/sim/frv/mrotri.cgs
    sim/testsuite/sim/frv/msaths.cgs
    sim/testsuite/sim/frv/msathu.cgs
    sim/testsuite/sim/frv/msllhi.cgs
    sim/testsuite/sim/frv/msrahi.cgs
    sim/testsuite/sim/frv/msrlhi.cgs
    sim/testsuite/sim/frv/msubhss.cgs
    sim/testsuite/sim/frv/msubhus.cgs
    sim/testsuite/sim/frv/mtrap.cgs
    sim/testsuite/sim/frv/munpackh.cgs
    sim/testsuite/sim/frv/mwcut.cgs
    sim/testsuite/sim/frv/mwcuti.cgs
    sim/testsuite/sim/frv/mwtacc.cgs
    sim/testsuite/sim/frv/mwtaccg.cgs
    sim/testsuite/sim/frv/mxor.cgs
    sim/testsuite/sim/frv/nandcr.cgs
    sim/testsuite/sim/frv/nandncr.cgs
    sim/testsuite/sim/frv/nfadds.cgs
    sim/testsuite/sim/frv/nfdadds.cgs
    sim/testsuite/sim/frv/nfdcmps.cgs
    sim/testsuite/sim/frv/nfddivs.cgs
    sim/testsuite/sim/frv/nfditos.cgs
    sim/testsuite/sim/frv/nfdivs.cgs
    sim/testsuite/sim/frv/nfdmadds.cgs
    sim/testsuite/sim/frv/nfdmas.cgs
    sim/testsuite/sim/frv/nfdmss.cgs
    sim/testsuite/sim/frv/nfdmulcs.cgs
    sim/testsuite/sim/frv/nfdmuls.cgs
    sim/testsuite/sim/frv/nfdsads.cgs
    sim/testsuite/sim/frv/nfdsqrts.cgs
    sim/testsuite/sim/frv/nfdstoi.cgs
    sim/testsuite/sim/frv/nfdsubs.cgs
    sim/testsuite/sim/frv/nfitos.cgs
    sim/testsuite/sim/frv/nfmadds.cgs
    sim/testsuite/sim/frv/nfmas.cgs
    sim/testsuite/sim/frv/nfmss.cgs
    sim/testsuite/sim/frv/nfmsubs.cgs
    sim/testsuite/sim/frv/nfmuls.cgs
    sim/testsuite/sim/frv/nfsqrts.cgs
    sim/testsuite/sim/frv/nfstoi.cgs
    sim/testsuite/sim/frv/nfsubs.cgs
    sim/testsuite/sim/frv/nld.cgs
    sim/testsuite/sim/frv/nldbf.cgs
    sim/testsuite/sim/frv/nldbfi.cgs
    sim/testsuite/sim/frv/nldbfu.cgs
    sim/testsuite/sim/frv/nldd.cgs
    sim/testsuite/sim/frv/nlddf.cgs
    sim/testsuite/sim/frv/nlddfi.cgs
    sim/testsuite/sim/frv/nlddfu.cgs
    sim/testsuite/sim/frv/nlddi.cgs
    sim/testsuite/sim/frv/nlddu.cgs
    sim/testsuite/sim/frv/nldf.cgs
    sim/testsuite/sim/frv/nldfi.cgs
    sim/testsuite/sim/frv/nldfu.cgs
    sim/testsuite/sim/frv/nldhf.cgs
    sim/testsuite/sim/frv/nldhfi.cgs
    sim/testsuite/sim/frv/nldhfu.cgs
    sim/testsuite/sim/frv/nldi.cgs
    sim/testsuite/sim/frv/nldq.cgs
    sim/testsuite/sim/frv/nldqf.cgs
    sim/testsuite/sim/frv/nldqfi.cgs
    sim/testsuite/sim/frv/nldqfu.cgs
    sim/testsuite/sim/frv/nldqu.cgs
    sim/testsuite/sim/frv/nldsb.cgs
    sim/testsuite/sim/frv/nldsbi.cgs
    sim/testsuite/sim/frv/nldsbu.cgs
    sim/testsuite/sim/frv/nldsh.cgs
    sim/testsuite/sim/frv/nldshi.cgs
    sim/testsuite/sim/frv/nldshu.cgs
    sim/testsuite/sim/frv/nldu.cgs
    sim/testsuite/sim/frv/nldub.cgs
    sim/testsuite/sim/frv/nldubi.cgs
    sim/testsuite/sim/frv/nldubu.cgs
    sim/testsuite/sim/frv/nlduh.cgs
    sim/testsuite/sim/frv/nlduhi.cgs
    sim/testsuite/sim/frv/nlduhu.cgs
    sim/testsuite/sim/frv/nop.cgs
    sim/testsuite/sim/frv/norcr.cgs
    sim/testsuite/sim/frv/norncr.cgs
    sim/testsuite/sim/frv/not.cgs
    sim/testsuite/sim/frv/notcr.cgs
    sim/testsuite/sim/frv/nsdiv.cgs
    sim/testsuite/sim/frv/nsdivi.cgs
    sim/testsuite/sim/frv/nudiv.cgs
    sim/testsuite/sim/frv/nudivi.cgs
    sim/testsuite/sim/frv/or.cgs
    sim/testsuite/sim/frv/orcc.cgs
    sim/testsuite/sim/frv/orcr.cgs
    sim/testsuite/sim/frv/ori.cgs
    sim/testsuite/sim/frv/oricc.cgs
    sim/testsuite/sim/frv/orncr.cgs
    sim/testsuite/sim/frv/parallel.exp
    sim/testsuite/sim/frv/ret.cgs
    sim/testsuite/sim/frv/rett.cgs
    sim/testsuite/sim/frv/scan.cgs
    sim/testsuite/sim/frv/scani.cgs
    sim/testsuite/sim/frv/sdiv.cgs
    sim/testsuite/sim/frv/sdivi.cgs
    sim/testsuite/sim/frv/sethi.cgs
    sim/testsuite/sim/frv/sethilo.pcgs
    sim/testsuite/sim/frv/setlo.cgs
    sim/testsuite/sim/frv/setlos.cgs
    sim/testsuite/sim/frv/sll.cgs
    sim/testsuite/sim/frv/sllcc.cgs
    sim/testsuite/sim/frv/slli.cgs
    sim/testsuite/sim/frv/sllicc.cgs
    sim/testsuite/sim/frv/smul.cgs
    sim/testsuite/sim/frv/smulcc.cgs
    sim/testsuite/sim/frv/smuli.cgs
    sim/testsuite/sim/frv/smulicc.cgs
    sim/testsuite/sim/frv/sra.cgs
    sim/testsuite/sim/frv/sracc.cgs
    sim/testsuite/sim/frv/srai.cgs
    sim/testsuite/sim/frv/sraicc.cgs
    sim/testsuite/sim/frv/srl.cgs
    sim/testsuite/sim/frv/srlcc.cgs
    sim/testsuite/sim/frv/srli.cgs
    sim/testsuite/sim/frv/srlicc.cgs
    sim/testsuite/sim/frv/st.cgs
    sim/testsuite/sim/frv/stb.cgs
    sim/testsuite/sim/frv/stbf.cgs
    sim/testsuite/sim/frv/stbfi.cgs
    sim/testsuite/sim/frv/stbfu.cgs
    sim/testsuite/sim/frv/stbi.cgs
    sim/testsuite/sim/frv/stbu.cgs
    sim/testsuite/sim/frv/stc.cgs
    sim/testsuite/sim/frv/stcu.cgs
    sim/testsuite/sim/frv/std.cgs
    sim/testsuite/sim/frv/std.pcgs
    sim/testsuite/sim/frv/stdc.cgs
    sim/testsuite/sim/frv/stdc.pcgs
    sim/testsuite/sim/frv/stdcu.cgs
    sim/testsuite/sim/frv/stdf.cgs
    sim/testsuite/sim/frv/stdf.pcgs
    sim/testsuite/sim/frv/stdfi.cgs
    sim/testsuite/sim/frv/stdfu.cgs
    sim/testsuite/sim/frv/stdi.cgs
    sim/testsuite/sim/frv/stdu.cgs
    sim/testsuite/sim/frv/stf.cgs
    sim/testsuite/sim/frv/stfi.cgs
    sim/testsuite/sim/frv/stfu.cgs
    sim/testsuite/sim/frv/sth.cgs
    sim/testsuite/sim/frv/sthf.cgs
    sim/testsuite/sim/frv/sthfi.cgs
    sim/testsuite/sim/frv/sthfu.cgs
    sim/testsuite/sim/frv/sthi.cgs
    sim/testsuite/sim/frv/sthu.cgs
    sim/testsuite/sim/frv/sti.cgs
    sim/testsuite/sim/frv/stq.cgs
    sim/testsuite/sim/frv/stq.pcgs
    sim/testsuite/sim/frv/stqc.cgs
    sim/testsuite/sim/frv/stqc.pcgs
    sim/testsuite/sim/frv/stqcu.cgs
    sim/testsuite/sim/frv/stqf.cgs
    sim/testsuite/sim/frv/stqf.pcgs
    sim/testsuite/sim/frv/stqfi.cgs
    sim/testsuite/sim/frv/stqfu.cgs
    sim/testsuite/sim/frv/stqi.cgs
    sim/testsuite/sim/frv/stqu.cgs
    sim/testsuite/sim/frv/stu.cgs
    sim/testsuite/sim/frv/sub.cgs
    sim/testsuite/sim/frv/subcc.cgs
    sim/testsuite/sim/frv/subi.cgs
    sim/testsuite/sim/frv/subicc.cgs
    sim/testsuite/sim/frv/subx.cgs
    sim/testsuite/sim/frv/subxcc.cgs
    sim/testsuite/sim/frv/subxi.cgs
    sim/testsuite/sim/frv/subxicc.cgs
    sim/testsuite/sim/frv/swap.cgs
    sim/testsuite/sim/frv/swapi.cgs
    sim/testsuite/sim/frv/tc.cgs
    sim/testsuite/sim/frv/teq.cgs
    sim/testsuite/sim/frv/testutils.inc
    sim/testsuite/sim/frv/tge.cgs
    sim/testsuite/sim/frv/tgt.cgs
    sim/testsuite/sim/frv/thi.cgs
    sim/testsuite/sim/frv/tic.cgs
    sim/testsuite/sim/frv/tieq.cgs
    sim/testsuite/sim/frv/tige.cgs
    sim/testsuite/sim/frv/tigt.cgs
    sim/testsuite/sim/frv/tihi.cgs
    sim/testsuite/sim/frv/tile.cgs
    sim/testsuite/sim/frv/tils.cgs
    sim/testsuite/sim/frv/tilt.cgs
    sim/testsuite/sim/frv/tin.cgs
    sim/testsuite/sim/frv/tinc.cgs
    sim/testsuite/sim/frv/tine.cgs
    sim/testsuite/sim/frv/tino.cgs
    sim/testsuite/sim/frv/tinv.cgs
    sim/testsuite/sim/frv/tip.cgs
    sim/testsuite/sim/frv/tira.cgs
    sim/testsuite/sim/frv/tiv.cgs
    sim/testsuite/sim/frv/tle.cgs
    sim/testsuite/sim/frv/tls.cgs
    sim/testsuite/sim/frv/tlt.cgs
    sim/testsuite/sim/frv/tn.cgs
    sim/testsuite/sim/frv/tnc.cgs
    sim/testsuite/sim/frv/tne.cgs
    sim/testsuite/sim/frv/tno.cgs
    sim/testsuite/sim/frv/tnv.cgs
    sim/testsuite/sim/frv/tp.cgs
    sim/testsuite/sim/frv/tra.cgs
    sim/testsuite/sim/frv/tv.cgs
    sim/testsuite/sim/frv/udiv.cgs
    sim/testsuite/sim/frv/udivi.cgs
    sim/testsuite/sim/frv/umul.cgs
    sim/testsuite/sim/frv/umulcc.cgs
    sim/testsuite/sim/frv/umuli.cgs
    sim/testsuite/sim/frv/umulicc.cgs
    sim/testsuite/sim/frv/xor.cgs
    sim/testsuite/sim/frv/xorcc.cgs
    sim/testsuite/sim/frv/xorcr.cgs
    sim/testsuite/sim/frv/xori.cgs
    sim/testsuite/sim/frv/xoricc.cgs
    sim/testsuite/sim/h8300/ChangeLog
    sim/testsuite/sim/h8300/addb.s
    sim/testsuite/sim/h8300/addl.s
    sim/testsuite/sim/h8300/adds.s
    sim/testsuite/sim/h8300/addw.s
    sim/testsuite/sim/h8300/addx.s
    sim/testsuite/sim/h8300/allinsn.exp
    sim/testsuite/sim/h8300/andb.s
    sim/testsuite/sim/h8300/andl.s
    sim/testsuite/sim/h8300/andw.s
    sim/testsuite/sim/h8300/band.s
    sim/testsuite/sim/h8300/bfld.s
    sim/testsuite/sim/h8300/biand.s
    sim/testsuite/sim/h8300/bra.s
    sim/testsuite/sim/h8300/brabc.s
    sim/testsuite/sim/h8300/bset.s
    sim/testsuite/sim/h8300/cmpb.s
    sim/testsuite/sim/h8300/cmpl.s
    sim/testsuite/sim/h8300/cmpw.s
    sim/testsuite/sim/h8300/daa.s
    sim/testsuite/sim/h8300/das.s
    sim/testsuite/sim/h8300/dec.s
    sim/testsuite/sim/h8300/div.s
    sim/testsuite/sim/h8300/extl.s
    sim/testsuite/sim/h8300/extw.s
    sim/testsuite/sim/h8300/inc.s
    sim/testsuite/sim/h8300/jmp.s
    sim/testsuite/sim/h8300/ldc.s
    sim/testsuite/sim/h8300/ldm.s
    sim/testsuite/sim/h8300/mac.s
    sim/testsuite/sim/h8300/mova.s
    sim/testsuite/sim/h8300/movb.s
    sim/testsuite/sim/h8300/movl.s
    sim/testsuite/sim/h8300/movmd.s
    sim/testsuite/sim/h8300/movsd.s
    sim/testsuite/sim/h8300/movw.s
    sim/testsuite/sim/h8300/mul.s
    sim/testsuite/sim/h8300/neg.s
    sim/testsuite/sim/h8300/nop.s
    sim/testsuite/sim/h8300/not.s
    sim/testsuite/sim/h8300/orb.s
    sim/testsuite/sim/h8300/orl.s
    sim/testsuite/sim/h8300/orw.s
    sim/testsuite/sim/h8300/rotl.s
    sim/testsuite/sim/h8300/rotr.s
    sim/testsuite/sim/h8300/rotxl.s
    sim/testsuite/sim/h8300/rotxr.s
    sim/testsuite/sim/h8300/shal.s
    sim/testsuite/sim/h8300/shar.s
    sim/testsuite/sim/h8300/shll.s
    sim/testsuite/sim/h8300/shlr.s
    sim/testsuite/sim/h8300/stack.s
    sim/testsuite/sim/h8300/stc.s
    sim/testsuite/sim/h8300/subb.s
    sim/testsuite/sim/h8300/subl.s
    sim/testsuite/sim/h8300/subs.s
    sim/testsuite/sim/h8300/subw.s
    sim/testsuite/sim/h8300/subx.s
    sim/testsuite/sim/h8300/tas.s
    sim/testsuite/sim/h8300/testutils.inc
    sim/testsuite/sim/h8300/xorb.s
    sim/testsuite/sim/h8300/xorl.s
    sim/testsuite/sim/h8300/xorw.s
    sim/testsuite/sim/m32r/add.cgs
    sim/testsuite/sim/m32r/add3.cgs
    sim/testsuite/sim/m32r/addi.cgs
    sim/testsuite/sim/m32r/addv.cgs
    sim/testsuite/sim/m32r/addv3.cgs
    sim/testsuite/sim/m32r/addx.cgs
    sim/testsuite/sim/m32r/allinsn.exp
    sim/testsuite/sim/m32r/and.cgs
    sim/testsuite/sim/m32r/and3.cgs
    sim/testsuite/sim/m32r/bc24.cgs
    sim/testsuite/sim/m32r/bc8.cgs
    sim/testsuite/sim/m32r/beq.cgs
    sim/testsuite/sim/m32r/beqz.cgs
    sim/testsuite/sim/m32r/bgez.cgs
    sim/testsuite/sim/m32r/bgtz.cgs
    sim/testsuite/sim/m32r/bl24.cgs
    sim/testsuite/sim/m32r/bl8.cgs
    sim/testsuite/sim/m32r/blez.cgs
    sim/testsuite/sim/m32r/bltz.cgs
    sim/testsuite/sim/m32r/bnc24.cgs
    sim/testsuite/sim/m32r/bnc8.cgs
    sim/testsuite/sim/m32r/bne.cgs
    sim/testsuite/sim/m32r/bnez.cgs
    sim/testsuite/sim/m32r/bra24.cgs
    sim/testsuite/sim/m32r/bra8.cgs
    sim/testsuite/sim/m32r/cmp.cgs
    sim/testsuite/sim/m32r/cmpi.cgs
    sim/testsuite/sim/m32r/cmpu.cgs
    sim/testsuite/sim/m32r/cmpui.cgs
    sim/testsuite/sim/m32r/div.cgs
    sim/testsuite/sim/m32r/divu.cgs
    sim/testsuite/sim/m32r/hello.ms
    sim/testsuite/sim/m32r/hw-trap.ms
    sim/testsuite/sim/m32r/jl.cgs
    sim/testsuite/sim/m32r/jmp.cgs
    sim/testsuite/sim/m32r/ld-d.cgs
    sim/testsuite/sim/m32r/ld-plus.cgs
    sim/testsuite/sim/m32r/ld.cgs
    sim/testsuite/sim/m32r/ld24.cgs
    sim/testsuite/sim/m32r/ldb-d.cgs
    sim/testsuite/sim/m32r/ldb.cgs
    sim/testsuite/sim/m32r/ldh-d.cgs
    sim/testsuite/sim/m32r/ldh.cgs
    sim/testsuite/sim/m32r/ldi16.cgs
    sim/testsuite/sim/m32r/ldi8.cgs
    sim/testsuite/sim/m32r/ldub-d.cgs
    sim/testsuite/sim/m32r/ldub.cgs
    sim/testsuite/sim/m32r/lduh-d.cgs
    sim/testsuite/sim/m32r/lduh.cgs
    sim/testsuite/sim/m32r/lock.cgs
    sim/testsuite/sim/m32r/machi.cgs
    sim/testsuite/sim/m32r/maclo.cgs
    sim/testsuite/sim/m32r/macwhi.cgs
    sim/testsuite/sim/m32r/macwlo.cgs
    sim/testsuite/sim/m32r/misc.exp
    sim/testsuite/sim/m32r/mul.cgs
    sim/testsuite/sim/m32r/mulhi.cgs
    sim/testsuite/sim/m32r/mullo.cgs
    sim/testsuite/sim/m32r/mulwhi.cgs
    sim/testsuite/sim/m32r/mulwlo.cgs
    sim/testsuite/sim/m32r/mv.cgs
    sim/testsuite/sim/m32r/mvfachi.cgs
    sim/testsuite/sim/m32r/mvfaclo.cgs
    sim/testsuite/sim/m32r/mvfacmi.cgs
    sim/testsuite/sim/m32r/mvfc.cgs
    sim/testsuite/sim/m32r/mvtachi.cgs
    sim/testsuite/sim/m32r/mvtaclo.cgs
    sim/testsuite/sim/m32r/mvtc.cgs
    sim/testsuite/sim/m32r/neg.cgs
    sim/testsuite/sim/m32r/nop.cgs
    sim/testsuite/sim/m32r/not.cgs
    sim/testsuite/sim/m32r/or.cgs
    sim/testsuite/sim/m32r/or3.cgs
    sim/testsuite/sim/m32r/rac.cgs
    sim/testsuite/sim/m32r/rach.cgs
    sim/testsuite/sim/m32r/rem.cgs
    sim/testsuite/sim/m32r/remu.cgs
    sim/testsuite/sim/m32r/rte.cgs
    sim/testsuite/sim/m32r/seth.cgs
    sim/testsuite/sim/m32r/sll.cgs
    sim/testsuite/sim/m32r/sll3.cgs
    sim/testsuite/sim/m32r/slli.cgs
    sim/testsuite/sim/m32r/sra.cgs
    sim/testsuite/sim/m32r/sra3.cgs
    sim/testsuite/sim/m32r/srai.cgs
    sim/testsuite/sim/m32r/srl.cgs
    sim/testsuite/sim/m32r/srl3.cgs
    sim/testsuite/sim/m32r/srli.cgs
    sim/testsuite/sim/m32r/st-d.cgs
    sim/testsuite/sim/m32r/st-minus.cgs
    sim/testsuite/sim/m32r/st-plus.cgs
    sim/testsuite/sim/m32r/st.cgs
    sim/testsuite/sim/m32r/stb-d.cgs
    sim/testsuite/sim/m32r/stb.cgs
    sim/testsuite/sim/m32r/sth-d.cgs
    sim/testsuite/sim/m32r/sth.cgs
    sim/testsuite/sim/m32r/sub.cgs
    sim/testsuite/sim/m32r/subv.cgs
    sim/testsuite/sim/m32r/subx.cgs
    sim/testsuite/sim/m32r/testutils.inc
    sim/testsuite/sim/m32r/trap.cgs
    sim/testsuite/sim/m32r/unlock.cgs
    sim/testsuite/sim/m32r/uread16.ms
    sim/testsuite/sim/m32r/uread32.ms
    sim/testsuite/sim/m32r/uwrite16.ms
    sim/testsuite/sim/m32r/uwrite32.ms
    sim/testsuite/sim/m32r/xor.cgs
    sim/testsuite/sim/m32r/xor3.cgs
    sim/testsuite/sim/mips/ChangeLog
    sim/testsuite/sim/mips/basic.exp
    sim/testsuite/sim/mips/fpu64-ps-sb1.s
    sim/testsuite/sim/mips/fpu64-ps.s
    sim/testsuite/sim/mips/hilo-hazard-1.s
    sim/testsuite/sim/mips/hilo-hazard-2.s
    sim/testsuite/sim/mips/hilo-hazard-3.s
    sim/testsuite/sim/mips/mdmx-ob-sb1.s
    sim/testsuite/sim/mips/mdmx-ob.s
    sim/testsuite/sim/mips/mips32-dsp.s
    sim/testsuite/sim/mips/sanity.s
    sim/testsuite/sim/mips/testutils.inc
    sim/testsuite/sim/mips/utils-dsp.inc
    sim/testsuite/sim/mips/utils-fpu.inc
    sim/testsuite/sim/mips/utils-mdmx.inc
    sim/testsuite/sim/sh/ChangeLog
    sim/testsuite/sim/sh/add.s
    sim/testsuite/sim/sh/allinsn.exp
    sim/testsuite/sim/sh/and.s
    sim/testsuite/sim/sh/bandor.s
    sim/testsuite/sim/sh/bandornot.s
    sim/testsuite/sim/sh/bclr.s
    sim/testsuite/sim/sh/bld.s
    sim/testsuite/sim/sh/bldnot.s
    sim/testsuite/sim/sh/bset.s
    sim/testsuite/sim/sh/bst.s
    sim/testsuite/sim/sh/bxor.s
    sim/testsuite/sim/sh/clip.s
    sim/testsuite/sim/sh/div.s
    sim/testsuite/sim/sh/dmxy.s
    sim/testsuite/sim/sh/fabs.s
    sim/testsuite/sim/sh/fadd.s
    sim/testsuite/sim/sh/fail.s
    sim/testsuite/sim/sh/fcmpeq.s
    sim/testsuite/sim/sh/fcmpgt.s
    sim/testsuite/sim/sh/fcnvds.s
    sim/testsuite/sim/sh/fcnvsd.s
    sim/testsuite/sim/sh/fdiv.s
    sim/testsuite/sim/sh/fipr.s
    sim/testsuite/sim/sh/fldi0.s
    sim/testsuite/sim/sh/fldi1.s
    sim/testsuite/sim/sh/flds.s
    sim/testsuite/sim/sh/float.s
    sim/testsuite/sim/sh/fmac.s
    sim/testsuite/sim/sh/fmov.s
    sim/testsuite/sim/sh/fmul.s
    sim/testsuite/sim/sh/fneg.s
    sim/testsuite/sim/sh/fpchg.s
    sim/testsuite/sim/sh/frchg.s
    sim/testsuite/sim/sh/fsca.s
    sim/testsuite/sim/sh/fschg.s
    sim/testsuite/sim/sh/fsqrt.s
    sim/testsuite/sim/sh/fsrra.s
    sim/testsuite/sim/sh/fsub.s
    sim/testsuite/sim/sh/ftrc.s
    sim/testsuite/sim/sh/ldrc.s
    sim/testsuite/sim/sh/loop.s
    sim/testsuite/sim/sh/macl.s
    sim/testsuite/sim/sh/macw.s
    sim/testsuite/sim/sh/mov.s
    sim/testsuite/sim/sh/movi.s
    sim/testsuite/sim/sh/movli.s
    sim/testsuite/sim/sh/movua.s
    sim/testsuite/sim/sh/movxy.s
    sim/testsuite/sim/sh/mulr.s
    sim/testsuite/sim/sh/pabs.s
    sim/testsuite/sim/sh/padd.s
    sim/testsuite/sim/sh/paddc.s
    sim/testsuite/sim/sh/pand.s
    sim/testsuite/sim/sh/pass.s
    sim/testsuite/sim/sh/pclr.s
    sim/testsuite/sim/sh/pdec.s
    sim/testsuite/sim/sh/pdmsb.s
    sim/testsuite/sim/sh/pinc.s
    sim/testsuite/sim/sh/pmuls.s
    sim/testsuite/sim/sh/prnd.s
    sim/testsuite/sim/sh/pshai.s
    sim/testsuite/sim/sh/pshar.s
    sim/testsuite/sim/sh/pshli.s
    sim/testsuite/sim/sh/pshlr.s
    sim/testsuite/sim/sh/psub.s
    sim/testsuite/sim/sh/pswap.s
    sim/testsuite/sim/sh/pushpop.s
    sim/testsuite/sim/sh/resbank.s
    sim/testsuite/sim/sh/sett.s
    sim/testsuite/sim/sh/shll.s
    sim/testsuite/sim/sh/shll16.s
    sim/testsuite/sim/sh/shll2.s
    sim/testsuite/sim/sh/shll8.s
    sim/testsuite/sim/sh/shlr.s
    sim/testsuite/sim/sh/shlr16.s
    sim/testsuite/sim/sh/shlr2.s
    sim/testsuite/sim/sh/shlr8.s
    sim/testsuite/sim/sh/swap.s
    sim/testsuite/sim/sh/testutils.inc
    sim/testsuite/sim/sh64/ChangeLog
    sim/testsuite/sim/sh64/compact.exp
    sim/testsuite/sim/sh64/compact/ChangeLog
    sim/testsuite/sim/sh64/compact/add.cgs
    sim/testsuite/sim/sh64/compact/addc.cgs
    sim/testsuite/sim/sh64/compact/addi.cgs
    sim/testsuite/sim/sh64/compact/addv.cgs
    sim/testsuite/sim/sh64/compact/and.cgs
    sim/testsuite/sim/sh64/compact/andb.cgs
    sim/testsuite/sim/sh64/compact/andi.cgs
    sim/testsuite/sim/sh64/compact/bf.cgs
    sim/testsuite/sim/sh64/compact/bfs.cgs
    sim/testsuite/sim/sh64/compact/bra.cgs
    sim/testsuite/sim/sh64/compact/braf.cgs
    sim/testsuite/sim/sh64/compact/brk.cgs
    sim/testsuite/sim/sh64/compact/bsr.cgs
    sim/testsuite/sim/sh64/compact/bsrf.cgs
    sim/testsuite/sim/sh64/compact/bt.cgs
    sim/testsuite/sim/sh64/compact/bts.cgs
    sim/testsuite/sim/sh64/compact/clrmac.cgs
    sim/testsuite/sim/sh64/compact/clrs.cgs
    sim/testsuite/sim/sh64/compact/clrt.cgs
    sim/testsuite/sim/sh64/compact/cmpeq.cgs
    sim/testsuite/sim/sh64/compact/cmpeqi.cgs
    sim/testsuite/sim/sh64/compact/cmpge.cgs
    sim/testsuite/sim/sh64/compact/cmpgt.cgs
    sim/testsuite/sim/sh64/compact/cmphi.cgs
    sim/testsuite/sim/sh64/compact/cmphs.cgs
    sim/testsuite/sim/sh64/compact/cmppl.cgs
    sim/testsuite/sim/sh64/compact/cmppz.cgs
    sim/testsuite/sim/sh64/compact/cmpstr.cgs
    sim/testsuite/sim/sh64/compact/div0s.cgs
    sim/testsuite/sim/sh64/compact/div0u.cgs
    sim/testsuite/sim/sh64/compact/div1.cgs
    sim/testsuite/sim/sh64/compact/dmulsl.cgs
    sim/testsuite/sim/sh64/compact/dmulul.cgs
    sim/testsuite/sim/sh64/compact/dt.cgs
    sim/testsuite/sim/sh64/compact/extsb.cgs
    sim/testsuite/sim/sh64/compact/extsw.cgs
    sim/testsuite/sim/sh64/compact/extub.cgs
    sim/testsuite/sim/sh64/compact/extuw.cgs
    sim/testsuite/sim/sh64/compact/fabs.cgs
    sim/testsuite/sim/sh64/compact/fadd.cgs
    sim/testsuite/sim/sh64/compact/fcmpeq.cgs
    sim/testsuite/sim/sh64/compact/fcmpgt.cgs
    sim/testsuite/sim/sh64/compact/fcnvds.cgs
    sim/testsuite/sim/sh64/compact/fcnvsd.cgs
    sim/testsuite/sim/sh64/compact/fdiv.cgs
    sim/testsuite/sim/sh64/compact/fipr.cgs
    sim/testsuite/sim/sh64/compact/fldi0.cgs
    sim/testsuite/sim/sh64/compact/fldi1.cgs
    sim/testsuite/sim/sh64/compact/flds.cgs
    sim/testsuite/sim/sh64/compact/float.cgs
    sim/testsuite/sim/sh64/compact/fmac.cgs
    sim/testsuite/sim/sh64/compact/fmov.cgs
    sim/testsuite/sim/sh64/compact/fmul.cgs
    sim/testsuite/sim/sh64/compact/fneg.cgs
    sim/testsuite/sim/sh64/compact/frchg.cgs
    sim/testsuite/sim/sh64/compact/fschg.cgs
    sim/testsuite/sim/sh64/compact/fsqrt.cgs
    sim/testsuite/sim/sh64/compact/fsts.cgs
    sim/testsuite/sim/sh64/compact/fsub.cgs
    sim/testsuite/sim/sh64/compact/ftrc.cgs
    sim/testsuite/sim/sh64/compact/ftrv.cgs
    sim/testsuite/sim/sh64/compact/jmp.cgs
    sim/testsuite/sim/sh64/compact/jsr.cgs
    sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
    sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs
    sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
    sim/testsuite/sim/sh64/compact/lds-fpul.cgs
    sim/testsuite/sim/sh64/compact/lds-mach.cgs
    sim/testsuite/sim/sh64/compact/lds-macl.cgs
    sim/testsuite/sim/sh64/compact/lds-pr.cgs
    sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
    sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
    sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
    sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
    sim/testsuite/sim/sh64/compact/ldsl-pr.cgs
    sim/testsuite/sim/sh64/compact/macl.cgs
    sim/testsuite/sim/sh64/compact/macw.cgs
    sim/testsuite/sim/sh64/compact/mov.cgs
    sim/testsuite/sim/sh64/compact/mova.cgs
    sim/testsuite/sim/sh64/compact/movb1.cgs
    sim/testsuite/sim/sh64/compact/movb10.cgs
    sim/testsuite/sim/sh64/compact/movb2.cgs
    sim/testsuite/sim/sh64/compact/movb3.cgs
    sim/testsuite/sim/sh64/compact/movb4.cgs
    sim/testsuite/sim/sh64/compact/movb5.cgs
    sim/testsuite/sim/sh64/compact/movb6.cgs
    sim/testsuite/sim/sh64/compact/movb7.cgs
    sim/testsuite/sim/sh64/compact/movb8.cgs
    sim/testsuite/sim/sh64/compact/movb9.cgs
    sim/testsuite/sim/sh64/compact/movcal.cgs
    sim/testsuite/sim/sh64/compact/movi.cgs
    sim/testsuite/sim/sh64/compact/movl1.cgs
    sim/testsuite/sim/sh64/compact/movl10.cgs
    sim/testsuite/sim/sh64/compact/movl11.cgs
    sim/testsuite/sim/sh64/compact/movl2.cgs
    sim/testsuite/sim/sh64/compact/movl3.cgs
    sim/testsuite/sim/sh64/compact/movl4.cgs
    sim/testsuite/sim/sh64/compact/movl5.cgs
    sim/testsuite/sim/sh64/compact/movl6.cgs
    sim/testsuite/sim/sh64/compact/movl7.cgs
    sim/testsuite/sim/sh64/compact/movl8.cgs
    sim/testsuite/sim/sh64/compact/movl9.cgs
    sim/testsuite/sim/sh64/compact/movt.cgs
    sim/testsuite/sim/sh64/compact/movw1.cgs
    sim/testsuite/sim/sh64/compact/movw10.cgs
    sim/testsuite/sim/sh64/compact/movw11.cgs
    sim/testsuite/sim/sh64/compact/movw2.cgs
    sim/testsuite/sim/sh64/compact/movw3.cgs
    sim/testsuite/sim/sh64/compact/movw4.cgs
    sim/testsuite/sim/sh64/compact/movw5.cgs
    sim/testsuite/sim/sh64/compact/movw6.cgs
    sim/testsuite/sim/sh64/compact/movw7.cgs
    sim/testsuite/sim/sh64/compact/movw8.cgs
    sim/testsuite/sim/sh64/compact/movw9.cgs
    sim/testsuite/sim/sh64/compact/mull.cgs
    sim/testsuite/sim/sh64/compact/mulsw.cgs
    sim/testsuite/sim/sh64/compact/muluw.cgs
    sim/testsuite/sim/sh64/compact/neg.cgs
    sim/testsuite/sim/sh64/compact/negc.cgs
    sim/testsuite/sim/sh64/compact/nop.cgs
    sim/testsuite/sim/sh64/compact/not.cgs
    sim/testsuite/sim/sh64/compact/ocbi.cgs
    sim/testsuite/sim/sh64/compact/ocbp.cgs
    sim/testsuite/sim/sh64/compact/ocbwb.cgs
    sim/testsuite/sim/sh64/compact/or.cgs
    sim/testsuite/sim/sh64/compact/orb.cgs
    sim/testsuite/sim/sh64/compact/ori.cgs
    sim/testsuite/sim/sh64/compact/pref.cgs
    sim/testsuite/sim/sh64/compact/rotcl.cgs
    sim/testsuite/sim/sh64/compact/rotcr.cgs
    sim/testsuite/sim/sh64/compact/rotl.cgs
    sim/testsuite/sim/sh64/compact/rotr.cgs
    sim/testsuite/sim/sh64/compact/rts.cgs
    sim/testsuite/sim/sh64/compact/sets.cgs
    sim/testsuite/sim/sh64/compact/sett.cgs
    sim/testsuite/sim/sh64/compact/shad.cgs
    sim/testsuite/sim/sh64/compact/shal.cgs
    sim/testsuite/sim/sh64/compact/shar.cgs
    sim/testsuite/sim/sh64/compact/shld.cgs
    sim/testsuite/sim/sh64/compact/shll.cgs
    sim/testsuite/sim/sh64/compact/shll16.cgs
    sim/testsuite/sim/sh64/compact/shll2.cgs
    sim/testsuite/sim/sh64/compact/shll8.cgs
    sim/testsuite/sim/sh64/compact/shlr.cgs
    sim/testsuite/sim/sh64/compact/shlr16.cgs
    sim/testsuite/sim/sh64/compact/shlr2.cgs
    sim/testsuite/sim/sh64/compact/shlr8.cgs
    sim/testsuite/sim/sh64/compact/stc-gbr.cgs
    sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
    sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
    sim/testsuite/sim/sh64/compact/sts-fpul.cgs
    sim/testsuite/sim/sh64/compact/sts-mach.cgs
    sim/testsuite/sim/sh64/compact/sts-macl.cgs
    sim/testsuite/sim/sh64/compact/sts-pr.cgs
    sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
    sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
    sim/testsuite/sim/sh64/compact/stsl-mach.cgs
    sim/testsuite/sim/sh64/compact/stsl-macl.cgs
    sim/testsuite/sim/sh64/compact/stsl-pr.cgs
    sim/testsuite/sim/sh64/compact/sub.cgs
    sim/testsuite/sim/sh64/compact/subc.cgs
    sim/testsuite/sim/sh64/compact/subv.cgs
    sim/testsuite/sim/sh64/compact/swapb.cgs
    sim/testsuite/sim/sh64/compact/swapw.cgs
    sim/testsuite/sim/sh64/compact/tasb.cgs
    sim/testsuite/sim/sh64/compact/testutils.inc
    sim/testsuite/sim/sh64/compact/trapa.cgs
    sim/testsuite/sim/sh64/compact/tst.cgs
    sim/testsuite/sim/sh64/compact/tstb.cgs
    sim/testsuite/sim/sh64/compact/tsti.cgs
    sim/testsuite/sim/sh64/compact/xor.cgs
    sim/testsuite/sim/sh64/compact/xorb.cgs
    sim/testsuite/sim/sh64/compact/xori.cgs
    sim/testsuite/sim/sh64/compact/xtrct.cgs
    sim/testsuite/sim/sh64/interwork.exp
    sim/testsuite/sim/sh64/media.exp
    sim/testsuite/sim/sh64/media/ChangeLog
    sim/testsuite/sim/sh64/media/add.cgs
    sim/testsuite/sim/sh64/media/addi.cgs
    sim/testsuite/sim/sh64/media/addil.cgs
    sim/testsuite/sim/sh64/media/addl.cgs
    sim/testsuite/sim/sh64/media/addzl.cgs
    sim/testsuite/sim/sh64/media/alloco.cgs
    sim/testsuite/sim/sh64/media/and.cgs
    sim/testsuite/sim/sh64/media/andc.cgs
    sim/testsuite/sim/sh64/media/andi.cgs
    sim/testsuite/sim/sh64/media/beq.cgs
    sim/testsuite/sim/sh64/media/beqi.cgs
    sim/testsuite/sim/sh64/media/bge.cgs
    sim/testsuite/sim/sh64/media/bgeu.cgs
    sim/testsuite/sim/sh64/media/bgt.cgs
    sim/testsuite/sim/sh64/media/bgtu.cgs
    sim/testsuite/sim/sh64/media/blink.cgs
    sim/testsuite/sim/sh64/media/bne.cgs
    sim/testsuite/sim/sh64/media/bnei.cgs
    sim/testsuite/sim/sh64/media/brk.cgs
    sim/testsuite/sim/sh64/media/byterev.cgs
    sim/testsuite/sim/sh64/media/cmpeq.cgs
    sim/testsuite/sim/sh64/media/cmpgt.cgs
    sim/testsuite/sim/sh64/media/cmpgtu.cgs
    sim/testsuite/sim/sh64/media/cmveq.cgs
    sim/testsuite/sim/sh64/media/cmvne.cgs
    sim/testsuite/sim/sh64/media/fabsd.cgs
    sim/testsuite/sim/sh64/media/fabss.cgs
    sim/testsuite/sim/sh64/media/faddd.cgs
    sim/testsuite/sim/sh64/media/fadds.cgs
    sim/testsuite/sim/sh64/media/fcmpeqd.cgs
    sim/testsuite/sim/sh64/media/fcmpeqs.cgs
    sim/testsuite/sim/sh64/media/fcmpged.cgs
    sim/testsuite/sim/sh64/media/fcmpges.cgs
    sim/testsuite/sim/sh64/media/fcmpgtd.cgs
    sim/testsuite/sim/sh64/media/fcmpgts.cgs
    sim/testsuite/sim/sh64/media/fcmpund.cgs
    sim/testsuite/sim/sh64/media/fcmpuns.cgs
    sim/testsuite/sim/sh64/media/fcnvds.cgs
    sim/testsuite/sim/sh64/media/fcnvsd.cgs
    sim/testsuite/sim/sh64/media/fdivd.cgs
    sim/testsuite/sim/sh64/media/fdivs.cgs
    sim/testsuite/sim/sh64/media/fgetscr.cgs
    sim/testsuite/sim/sh64/media/fiprs.cgs
    sim/testsuite/sim/sh64/media/fldd.cgs
    sim/testsuite/sim/sh64/media/fldp.cgs
    sim/testsuite/sim/sh64/media/flds.cgs
    sim/testsuite/sim/sh64/media/fldxd.cgs
    sim/testsuite/sim/sh64/media/fldxp.cgs
    sim/testsuite/sim/sh64/media/fldxs.cgs
    sim/testsuite/sim/sh64/media/floatld.cgs
    sim/testsuite/sim/sh64/media/floatls.cgs
    sim/testsuite/sim/sh64/media/floatqd.cgs
    sim/testsuite/sim/sh64/media/floatqs.cgs
    sim/testsuite/sim/sh64/media/fmacs.cgs
    sim/testsuite/sim/sh64/media/fmovd.cgs
    sim/testsuite/sim/sh64/media/fmovdq.cgs
    sim/testsuite/sim/sh64/media/fmovls.cgs
    sim/testsuite/sim/sh64/media/fmovqd.cgs
    sim/testsuite/sim/sh64/media/fmovs.cgs
    sim/testsuite/sim/sh64/media/fmovsl.cgs
    sim/testsuite/sim/sh64/media/fmuld.cgs
    sim/testsuite/sim/sh64/media/fmuls.cgs
    sim/testsuite/sim/sh64/media/fnegd.cgs
    sim/testsuite/sim/sh64/media/fnegs.cgs
    sim/testsuite/sim/sh64/media/fputscr.cgs
    sim/testsuite/sim/sh64/media/fsqrtd.cgs
    sim/testsuite/sim/sh64/media/fsqrts.cgs
    sim/testsuite/sim/sh64/media/fstd.cgs
    sim/testsuite/sim/sh64/media/fstp.cgs
    sim/testsuite/sim/sh64/media/fsts.cgs
    sim/testsuite/sim/sh64/media/fstxd.cgs
    sim/testsuite/sim/sh64/media/fstxp.cgs
    sim/testsuite/sim/sh64/media/fstxs.cgs
    sim/testsuite/sim/sh64/media/fsubd.cgs
    sim/testsuite/sim/sh64/media/fsubs.cgs
    sim/testsuite/sim/sh64/media/ftrcdl.cgs
    sim/testsuite/sim/sh64/media/ftrcdq.cgs
    sim/testsuite/sim/sh64/media/ftrcsl.cgs
    sim/testsuite/sim/sh64/media/ftrcsq.cgs
    sim/testsuite/sim/sh64/media/ftrvs.cgs
    sim/testsuite/sim/sh64/media/getcfg.cgs
    sim/testsuite/sim/sh64/media/getcon.cgs
    sim/testsuite/sim/sh64/media/gettr.cgs
    sim/testsuite/sim/sh64/media/icbi.cgs
    sim/testsuite/sim/sh64/media/ldb.cgs
    sim/testsuite/sim/sh64/media/ldhil.cgs
    sim/testsuite/sim/sh64/media/ldhiq.cgs
    sim/testsuite/sim/sh64/media/ldl.cgs
    sim/testsuite/sim/sh64/media/ldlol.cgs
    sim/testsuite/sim/sh64/media/ldloq.cgs
    sim/testsuite/sim/sh64/media/ldq.cgs
    sim/testsuite/sim/sh64/media/ldub.cgs
    sim/testsuite/sim/sh64/media/lduw.cgs
    sim/testsuite/sim/sh64/media/ldw.cgs
    sim/testsuite/sim/sh64/media/ldxb.cgs
    sim/testsuite/sim/sh64/media/ldxl.cgs
    sim/testsuite/sim/sh64/media/ldxq.cgs
    sim/testsuite/sim/sh64/media/ldxub.cgs
    sim/testsuite/sim/sh64/media/ldxuw.cgs
    sim/testsuite/sim/sh64/media/ldxw.cgs
    sim/testsuite/sim/sh64/media/mabsl.cgs
    sim/testsuite/sim/sh64/media/mabsw.cgs
    sim/testsuite/sim/sh64/media/maddl.cgs
    sim/testsuite/sim/sh64/media/maddsl.cgs
    sim/testsuite/sim/sh64/media/maddsub.cgs
    sim/testsuite/sim/sh64/media/maddsw.cgs
    sim/testsuite/sim/sh64/media/maddw.cgs
    sim/testsuite/sim/sh64/media/mcmpeqb.cgs
    sim/testsuite/sim/sh64/media/mcmpeql.cgs
    sim/testsuite/sim/sh64/media/mcmpeqw.cgs
    sim/testsuite/sim/sh64/media/mcmpgtl.cgs
    sim/testsuite/sim/sh64/media/mcmpgtub.cgs
    sim/testsuite/sim/sh64/media/mcmpgtw.cgs
    sim/testsuite/sim/sh64/media/mcmv.cgs
    sim/testsuite/sim/sh64/media/mcnvslw.cgs
    sim/testsuite/sim/sh64/media/mcnvswb.cgs
    sim/testsuite/sim/sh64/media/mcnvswub.cgs
    sim/testsuite/sim/sh64/media/mextr1.cgs
    sim/testsuite/sim/sh64/media/mextr2.cgs
    sim/testsuite/sim/sh64/media/mextr3.cgs
    sim/testsuite/sim/sh64/media/mextr4.cgs
    sim/testsuite/sim/sh64/media/mextr5.cgs
    sim/testsuite/sim/sh64/media/mextr6.cgs
    sim/testsuite/sim/sh64/media/mextr7.cgs
    sim/testsuite/sim/sh64/media/mmacfxwl.cgs
    sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
    sim/testsuite/sim/sh64/media/mmulfxl.cgs
    sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
    sim/testsuite/sim/sh64/media/mmulfxw.cgs
    sim/testsuite/sim/sh64/media/mmulhiwl.cgs
    sim/testsuite/sim/sh64/media/mmull.cgs
    sim/testsuite/sim/sh64/media/mmullowl.cgs
    sim/testsuite/sim/sh64/media/mmulsumwq.cgs
    sim/testsuite/sim/sh64/media/mmulw.cgs
    sim/testsuite/sim/sh64/media/movi.cgs
    sim/testsuite/sim/sh64/media/mpermw.cgs
    sim/testsuite/sim/sh64/media/msadubq.cgs
    sim/testsuite/sim/sh64/media/mshaldsl.cgs
    sim/testsuite/sim/sh64/media/mshaldsw.cgs
    sim/testsuite/sim/sh64/media/mshardl.cgs
    sim/testsuite/sim/sh64/media/mshardsq.cgs
    sim/testsuite/sim/sh64/media/mshardw.cgs
    sim/testsuite/sim/sh64/media/mshfhib.cgs
    sim/testsuite/sim/sh64/media/mshfhil.cgs
    sim/testsuite/sim/sh64/media/mshfhiw.cgs
    sim/testsuite/sim/sh64/media/mshflob.cgs
    sim/testsuite/sim/sh64/media/mshflol.cgs
    sim/testsuite/sim/sh64/media/mshflow.cgs
    sim/testsuite/sim/sh64/media/mshlldl.cgs
    sim/testsuite/sim/sh64/media/mshlldw.cgs
    sim/testsuite/sim/sh64/media/mshlrdl.cgs
    sim/testsuite/sim/sh64/media/mshlrdw.cgs
    sim/testsuite/sim/sh64/media/msubl.cgs
    sim/testsuite/sim/sh64/media/msubsl.cgs
    sim/testsuite/sim/sh64/media/msubsub.cgs
    sim/testsuite/sim/sh64/media/msubsw.cgs
    sim/testsuite/sim/sh64/media/msubw.cgs
    sim/testsuite/sim/sh64/media/mulsl.cgs
    sim/testsuite/sim/sh64/media/mulul.cgs
    sim/testsuite/sim/sh64/media/nop.cgs
    sim/testsuite/sim/sh64/media/nsb.cgs
    sim/testsuite/sim/sh64/media/ocbi.cgs
    sim/testsuite/sim/sh64/media/ocbp.cgs
    sim/testsuite/sim/sh64/media/ocbwb.cgs
    sim/testsuite/sim/sh64/media/or.cgs
    sim/testsuite/sim/sh64/media/ori.cgs
    sim/testsuite/sim/sh64/media/prefi.cgs
    sim/testsuite/sim/sh64/media/pta.cgs
    sim/testsuite/sim/sh64/media/ptabs.cgs
    sim/testsuite/sim/sh64/media/ptb.cgs
    sim/testsuite/sim/sh64/media/ptrel.cgs
    sim/testsuite/sim/sh64/media/putcfg.cgs
    sim/testsuite/sim/sh64/media/putcon.cgs
    sim/testsuite/sim/sh64/media/rte.cgs
    sim/testsuite/sim/sh64/media/shard.cgs
    sim/testsuite/sim/sh64/media/shardl.cgs
    sim/testsuite/sim/sh64/media/shari.cgs
    sim/testsuite/sim/sh64/media/sharil.cgs
    sim/testsuite/sim/sh64/media/shlld.cgs
    sim/testsuite/sim/sh64/media/shlldl.cgs
    sim/testsuite/sim/sh64/media/shlli.cgs
    sim/testsuite/sim/sh64/media/shllil.cgs
    sim/testsuite/sim/sh64/media/shlrd.cgs
    sim/testsuite/sim/sh64/media/shlrdl.cgs
    sim/testsuite/sim/sh64/media/shlri.cgs
    sim/testsuite/sim/sh64/media/shlril.cgs
    sim/testsuite/sim/sh64/media/shori.cgs
    sim/testsuite/sim/sh64/media/sleep.cgs
    sim/testsuite/sim/sh64/media/stb.cgs
    sim/testsuite/sim/sh64/media/sthil.cgs
    sim/testsuite/sim/sh64/media/sthiq.cgs
    sim/testsuite/sim/sh64/media/stl.cgs
    sim/testsuite/sim/sh64/media/stlol.cgs
    sim/testsuite/sim/sh64/media/stloq.cgs
    sim/testsuite/sim/sh64/media/stq.cgs
    sim/testsuite/sim/sh64/media/stw.cgs
    sim/testsuite/sim/sh64/media/stxb.cgs
    sim/testsuite/sim/sh64/media/stxl.cgs
    sim/testsuite/sim/sh64/media/stxq.cgs
    sim/testsuite/sim/sh64/media/stxw.cgs
    sim/testsuite/sim/sh64/media/sub.cgs
    sim/testsuite/sim/sh64/media/subl.cgs
    sim/testsuite/sim/sh64/media/swapq.cgs
    sim/testsuite/sim/sh64/media/synci.cgs
    sim/testsuite/sim/sh64/media/synco.cgs
    sim/testsuite/sim/sh64/media/testutils.inc
    sim/testsuite/sim/sh64/media/trapa.cgs
    sim/testsuite/sim/sh64/media/xor.cgs
    sim/testsuite/sim/sh64/media/xori.cgs
    sim/testsuite/sim/sh64/misc/fr-dr.s
    sim/v850/ChangeLog
    sim/v850/Makefile.in
    sim/v850/acconfig.h
    sim/v850/config.in
    sim/v850/configure
    sim/v850/configure.ac
    sim/v850/interp.c
    sim/v850/sim-main.h
    sim/v850/simops.c
    sim/v850/simops.h
    sim/v850/v850-dc
    sim/v850/v850.igen
    sim/v850/v850_sim.h
    texinfo/texinfo.tex

31 files changed, 0 insertions, 31330 deletions

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
deleted file mode 100644
index 6ea29d6..0000000
--- a/sim/mips/ChangeLog
+++ /dev/null
@@ -1,3045 +0,0 @@
-2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
-
-	* configure: Regenerated.
-
-2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
-
-	* configure: Regenerated.
-
-2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
-
-	* configure: Regenerated.
-
-2006-05-15 Chao-ying Fu  <fu@mips.com>
-
-	* dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
-
-2006-04-18  Nick Clifton  <nickc@redhat.com>
-
-	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
-	statement.
-
-2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
-
-	* configure: Regenerate.
-
-2005-12-14  Chao-ying Fu  <fu@mips.com>
-
-	* Makefile.in (SIM_OBJS): Add dsp.o.
-	(dsp.o): New dependency.
-	(IGEN_INCLUDE): Add dsp.igen.
-	* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
-	mipsisa64*-*-*): Add dsp to sim_igen_machine.
-	* configure: Regenerate.
-	* mips.igen: Add dsp model and include dsp.igen.
-	(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
-	because these instructions are extended in DSP ASE.
-	* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
-	adding 6 DSP accumulator registers and 1 DSP control register.
-	(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
-	AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
-	DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
-	DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
-	DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
-	DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
-	DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
-	DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
-	DSPCR_CCOND_SMASK): New define.
-	(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
-	* dsp.c, dsp.igen: New files for MIPS DSP ASE.
-
-2005-07-08  Ian Lance Taylor  <ian@airs.com>
-
-	* tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
-
-2005-06-16  David Ung  <davidu@mips.com>
-            Nigel Stephens  <nigel@mips.com>
-
-        * mips.igen: New mips16e model and include m16e.igen.
-        (check_u64): Add mips16e tag.
-        * m16e.igen: New file for MIPS16e instructions.
-        * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
-        mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
-        models.
-        * configure: Regenerate.
-
-2005-05-26  David Ung  <davidu@mips.com>
- 
- 	* mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
-	tags to all instructions which are applicable to the new ISAs.
- 	(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
-	vr.igen.
- 	* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
- 	instructions. 
- 	* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
-	to mips.igen.
- 	* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
-	* configure: Regenerate.
- 
-2005-03-23  Mark Kettenis  <kettenis@gnu.org>
-
-	* configure: Regenerate.
-
-2005-01-14  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Sinclude aclocal.m4 before common.m4.  Add
-	explicit call to AC_CONFIG_HEADER.
-	* configure: Regenerate.
-
-2005-01-12  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Update to use ../common/common.m4.
-	* configure: Re-generate.
-
-2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2005-01-07  Andrew Cagney  <cagney@gnu.org>
-
-	* configure.ac: Rename configure.in, require autoconf 2.59.
-	* configure: Re-generate.
-
-2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
-
-	* configure: Regenerate for ../common/aclocal.m4 update.
-
-2004-09-24  Monika Chaddha  <monika@acmet.com>
-	
-	Committed by Andrew Cagney.
-	* m16.igen (CMP, CMPI): Fix assembler.
-
-2004-08-18  Chris Demetriou  <cgd@broadcom.com>
-
-	* configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
-	* configure: Regenerate.
-
-2004-06-25  Chris Demetriou  <cgd@broadcom.com>
-
-	* configure.in (sim_m16_machine): Include mipsIII.
-	* configure: Regenerate.
-
-2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
-
-	* mips/interp.c (decode_coproc): Sign-extend the address retrieved 
-	from COP0_BADVADDR.
-	* mips/sim-main.h (COP0_BADVADDR): Remove a cast.
-
-2004-04-10  Chris Demetriou  <cgd@broadcom.com>
-
-	* sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
-
-2004-04-09  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (check_fmt): Remove.
-	(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
-	(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
-	(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
-	(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
-	(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
-	(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
-	(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
-	(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
-	(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
-	(C.cnd.fmta): Remove incorrect call to check_fmt_p.
-
-2004-04-09  Chris Demetriou  <cgd@broadcom.com>
-
-	* sb1.igen (check_sbx): New function.
-	(PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
-
-2004-03-29  Chris Demetriou  <cgd@broadcom.com>
-	    Richard Sandiford  <rsandifo@redhat.com>
-
-	* sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
-	(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
-	* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
-	separate implementations for mipsIV and mipsV.  Use new macros to
-	determine whether the restrictions apply.
-
-2004-01-19  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
-	(check_mult_hilo): Improve comments.
-	(check_div_hilo): Likewise.  Also, fork off a new version
-	to handle mips32/mips64 (since there are no hazards to check
-	in MIPS32/MIPS64).
-
-2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
-
-	* mips.igen (do_dmultx): Fix check for negative operands.
-
-2003-05-16  Ian Lance Taylor  <ian@airs.com>
-
-	* Makefile.in (SHELL): Make sure this is defined.
-	(various): Use $(SHELL) whenever we invoke move-if-change.
-
-2003-05-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: Tweak attribution slightly.
-	* cp1.h: Likewise.
-	* mdmx.c: Likewise.
-	* mdmx.igen: Likewise.
-	* mips3d.igen: Likewise.
-	* sb1.igen: Likewise.
-
-2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
-
-	* vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
-	unsigned operands.
-
-2003-02-27  Andrew Cagney  <cagney@redhat.com>
-
-	* interp.c (sim_open): Rename _bfd to bfd.
-	(sim_create_inferior): Ditto.
-
-2003-01-14  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
-
-2003-01-14  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (EI, DI): Remove.
-
-2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
-
-	* Makefile.in (tmp-run-multi): Fix mips16 filter.
-
-2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
-	    Andrew Cagney  <ac131313@redhat.com>
-	    Gavin Romig-Koch  <gavin@redhat.com>
-	    Graydon Hoare  <graydon@redhat.com>
-	    Aldy Hernandez  <aldyh@redhat.com>
-	    Dave Brolley  <brolley@redhat.com>
-	    Chris Demetriou  <cgd@broadcom.com>
-
-	* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
-	(sim_mach_default): New variable.
-	(mips64vr-*-*, mips64vrel-*-*): New configurations.
-	Add a new simulator generator, MULTI.
-	* configure: Regenerate.
-	* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
-	(multi-run.o): New dependency.
-	(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
-	(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
-	(tmp-multi): Combine them.
-	(BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
-	(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
-	(distclean-extra): New rule.
-	* sim-main.h: Include bfd.h.
-	(MIPS_MACH): New macro.
-	* mips.igen (vr4120, vr5400, vr5500): New models.
-	(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
-	* vr.igen: Replace with new version.
-
-2003-01-04  Chris Demetriou  <cgd@broadcom.com>
-
-	* configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
-	* configure: Regenerate.
-
-2002-12-31  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (check_branch_bug, mark_branch_bug): Remove.
-	* mips.igen: Remove all invocations of check_branch_bug and
-	mark_branch_bug.
-
-2002-12-16  Chris Demetriou  <cgd@broadcom.com>
-
-        * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
-
-2002-07-30  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (do_load_double, do_store_double): New functions.
-	(LDC1, SDC1): Rename to...
-	(LDC1b, SDC1b): respectively.
-	(LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
-
-2002-07-29  Michael Snyder  <msnyder@redhat.com>
-
-	* cp1.c (fp_recip2): Modify initialization expression so that
-	GCC will recognize it as constant.
-
-2002-06-18  Chris Demetriou  <cgd@broadcom.com>
-
-	* mdmx.c (SD_): Delete.
-	(Unpredictable): Re-define, for now, to directly invoke
-	unpredictable_action().
-	(mdmx_acc_op): Fix error in .ob immediate handling.
-
-2002-06-18  Andrew Cagney  <cagney@redhat.com>
-
-	* interp.c (sim_firmware_command): Initialize `address'.
-
-2002-06-16  Andrew Cagney  <ac131313@redhat.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-2002-06-14  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* mips3d.igen: New file which contains MIPS-3D ASE instructions.
-	* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
-	* mips.igen: Include mips3d.igen.
-	(mips3d): New model name for MIPS-3D ASE instructions.
-	(CVT.W.fmt): Don't use this instruction for word (source) format
-	instructions. 
-	* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
-	(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
-	(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
-	(NR_FRAC_GUARD, IMPLICIT_1): New macros.
-	* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
-	(RSquareRoot1, RSquareRoot2): New macros.
-	(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
-	(fp_rsqrt2): New functions.
-	* configure.in: Add MIPS-3D support to mipsisa64 simulator.
-	* configure: Regenerate.
-
-2002-06-13  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
-	(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
-	(fp_inv_sqrt, fpu_format_name): Add paired-single support.
-	(convert): Note that this function is not used for paired-single
-	format conversions.
-	(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
-	* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
-	(check_fmt_p): Enable paired-single support.
-	(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
-	(PUU.PS): New instructions.
-	(CVT.S.fmt): Don't use this instruction for paired-single format
-	destinations.
-	* sim-main.h (FP_formats): New value 'fmt_ps.'
-	(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
-	(PSLower, PSUpper, PackPS, ConvertPS): New macros.
-
-2002-06-12  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Fix formatting of function calls in
-	many FP operations.
-
-2002-06-12  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (MOVN, MOVZ): Trace result.
-	(TNEI): Print "tnei" as the opcode name in traces.
-	(CEIL.W): Add disassembly string for traces.
-	(RSQRT.fmt): Make location of disassembly string consistent
-	with other instructions.
-
-2002-06-12  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (X): Delete unused function.
-
-2002-06-08  Andrew Cagney  <cagney@redhat.com>
-
-	* interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
-
-2002-06-07  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
-	(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
-	* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
-	(fp_nmsub): New prototypes.
-	(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
-	(NegMultiplySub): New defines.
-	* mips.igen (RSQRT.fmt): Use RSquareRoot().
-	(MADD.D, MADD.S): Replace with...
-	(MADD.fmt): New instruction.
-	(MSUB.D, MSUB.S): Replace with...
-	(MSUB.fmt): New instruction.
-	(NMADD.D, NMADD.S): Replace with...
-	(NMADD.fmt): New instruction.
-	(NMSUB.D, MSUB.S): Replace with...
-	(NMSUB.fmt): New instruction.
-
-2002-06-07  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* cp1.c: Fix more comment spelling and formatting.
-	(value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
-	(denorm_mode): New function.
-	(fpu_unary, fpu_binary): Round results after operation, collect
-	status from rounding operations, and update the FCSR.
-	(convert): Collect status from integer conversions and rounding
-	operations, and update the FCSR.  Adjust NaN values that result
-	from conversions.  Convert to use sim_io_eprintf rather than
-	fprintf, and remove some debugging code.
-	* cp1.h (fenr_FS): New define.
-
-2002-06-07  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c (convert): Remove unusable debugging code, and move MIPS
-	rounding mode to sim FP rounding mode flag conversion code into...
-	(rounding_mode): New function.
-
-2002-06-07  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: Clean up formatting of a few comments.
-	(value_fpr): Reformat switch statement.
-
-2002-06-06  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* cp1.h: New file.
-	* sim-main.h: Include cp1.h.
-	(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
-	(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
-	(FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
-	(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
-	(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
-	(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
-	* cp1.c: Don't include sim-fpu.h; already included by
-	sim-main.h.  Clean up formatting of some comments.
-	(NaN, Equal, Less): Remove.
-	(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
-	(fp_cmp): New functions.
-	* mips.igen (do_c_cond_fmt): Remove.
-	(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
-	Compare.  Add result tracing.
-	(CxC1): Remove, replace with...
-	(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
-	(DMxC1): Remove, replace with...
-	(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
-	(MxC1): Remove, replace with... 
-	(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.  
-
-2002-06-04  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (FGRIDX): Remove, replace all uses with...
-	(FGR_BASE): New macro.
-	(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
-	(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
-	(NR_FGR, FGR): Likewise.
-	* interp.c: Replace all uses of FGRIDX with FGR_BASE.
-	* mips.igen: Likewise.
-
-2002-06-04  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: Add an FSF Copyright notice to this file.
-
-2002-06-04  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* cp1.c (Infinity): Remove.
-	* sim-main.h (Infinity): Likewise.
-
-	* cp1.c (fp_unary, fp_binary): New functions.
-	(fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
-	(fp_sqrt): New functions, implemented in terms of the above.
-	(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
-	(Recip, SquareRoot): Remove (replaced by functions above).
-	* sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
-	(fp_recip, fp_sqrt): New prototypes.
-	(AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
-	(Recip, SquareRoot): Replace prototypes with #defines which
-	invoke the functions above.
-	
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
-	(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
-	file, remove PARAMS from prototypes.
-	(value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
-	simulator state arguments.
-	(ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
-	pass simulator state arguments.
-	* cp1.c (SD): Redefine as CPU_STATE(cpu).
-	(store_fpr, convert): Remove 'sd' argument.
-	(value_fpr): Likewise.  Convert to use 'SD' instead.
-
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c (Min, Max): Remove #if 0'd functions.
-	* sim-main.h (Min, Max): Remove.
-
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: fix formatting of switch case and default labels.
-	* interp.c: Likewise.
-	* sim-main.c: Likewise.
-
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: Clean up comments which describe FP formats.
-	 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
-
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* configure.in (mipsisa64sb1*-*-*): New target for supporting
-	Broadcom SiByte SB-1 processor configurations.
-	* configure: Regenerate.
-	* sb1.igen: New file.
-	* mips.igen: Include sb1.igen.
-	(sb1): New model.
-	* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
-	* mdmx.igen: Add "sb1" model to all appropriate functions and
-	instructions.
-	* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
-	(ob_func, ob_acc): Reference the above.
-	(qh_acc): Adjust to keep the same size as ob_acc.
-	* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
-	(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
-
-2002-06-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
-
-2002-06-02  Chris Demetriou  <cgd@broadcom.com>
-            Ed Satterthwaite  <ehs@broadcom.com>
-
-	* mips.igen (mdmx): New (pseudo-)model.
-	* mdmx.c, mdmx.igen: New files.
-	* Makefile.in (SIM_OBJS): Add mdmx.o.
-	* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
-	New typedefs.
-	(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
-	(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
-	(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
-	(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
-	(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
-	(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
-	(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
-	(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
-	(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
-	(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
-	(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
-	(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
-	(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
-	(qh_fmtsel): New macros.
-	(_sim_cpu): New member "acc".
-	(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
-	(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
-
-2002-05-01  Chris Demetriou  <cgd@broadcom.com>
-
-	* interp.c: Use 'deprecated' rather than 'depreciated.'
-	* sim-main.h: Likewise.
-
-2002-05-01  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
-	which wouldn't compile anyway.
-	* sim-main.h (unpredictable_action): New function prototype.
-	(Unpredictable): Define to call igen function unpredictable().
-	(NotWordValue): New macro to call igen function not_word_value().
-	(UndefinedResult): Remove.
-	* interp.c (undefined_result): Remove.
-	(unpredictable_action): New function.
-	* mips.igen (not_word_value, unpredictable): New functions.
-	(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
-	(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
-	(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
-	NotWordValue() to check for unpredictable inputs, then
-	Unpredictable() to handle them.
-
-2002-02-24  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Fix formatting of calls to Unpredictable().
-
-2002-04-20  Andrew Cagney  <ac131313@redhat.com>
-
-	* interp.c (sim_open): Revert previous change.
-
-2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
-
-	* interp.c (sim_open): Disable chunk of code that wrote code in
-	vector table entries.
-
-2002-03-19  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
-	(FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
-	unused definitions.
-
-2002-03-19  Chris Demetriou  <cgd@broadcom.com>
-
-	* cp1.c: Fix many formatting issues.
-
-2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
-
-	* cp1.c (fpu_format_name): New function to replace...
-	(DOFMT): This.  Delete, and update all callers.
-	(fpu_rounding_mode_name): New function to replace...
-	(RMMODE): This.  Delete, and update all callers.
-
-2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
-
-	* interp.c: Move FPU support routines from here to...
-	* cp1.c: Here.  New file.
-	* Makefile.in (SIM_OBJS): Add cp1.o to object list.
-	(cp1.o): New target.
-
-2002-03-12  Chris Demetriou  <cgd@broadcom.com>
-
-	* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
-	* mips.igen (mips32, mips64): New models, add to all instructions
-	and functions as appropriate.
-	(loadstore_ea, check_u64): New variant for model mips64.
-	(check_fmt_p): New variant for models mipsV and mips64, remove
-	mipsV model marking fro other variant.
-	(SLL) Rename to...
-	(SLLa) this.
-	(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
-	for mips32 and mips64.
-	(DCLO, DCLZ): New instructions for mips64.
-
-2002-03-07  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
-	immediate or code as a hex value with the "%#lx" format.
-	(ANDI): Likewise, and fix printed instruction name.
-
-2002-03-05  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (UndefinedResult, Unpredictable): New macros
-	which currently do nothing.
-
-2002-03-05  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (status_UX, status_SX, status_KX, status_TS)
-	(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
-	(status_CU3): New definitions.
-
-	* sim-main.h (ExceptionCause): Add new values for MIPS32
-	and MIPS64: MDMX, MCheck, CacheErr.  Update comments
-	for DebugBreakPoint and NMIReset to note their status in
-	MIPS32 and MIPS64.
-	(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
-	(SignalExceptionCacheErr): New exception macros.
-
-2002-03-05  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
-	* sim-main.h (COP_Usable): Define, but for now coprocessor 1
-	is always enabled.
-	(SignalExceptionCoProcessorUnusable): Take as argument the
-	unusable coprocessor number.
-
-2002-03-05  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Fix formatting of all SignalException calls.
-
-2002-03-05  Chris Demetriou  <cgd@broadcom.com>
-
-	* sim-main.h (SIGNEXTEND): Remove.
-
-2002-03-04  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Remove gencode comment from top of file, fix
-	spelling in another comment.
-
-2002-03-04  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (check_fmt, check_fmt_p): New functions to check
-	whether specific floating point formats are usable.
-	(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
-	(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
-	(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
-	Use the new functions.
-	(do_c_cond_fmt): Remove format checks...
-	(C.cond.fmta, C.cond.fmtb): And move them into all callers.
-
-2002-03-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Fix formatting of check_fpu calls.
-
-2002-03-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (FLOOR.L.fmt): Store correct destination register.
-
-2002-03-03  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Remove whitespace at end of lines.
-
-2002-03-02  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (loadstore_ea): New function to do effective
-	address calculations.
-	(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
-	do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
-	CACHE): Use loadstore_ea to do effective address computations.
-
-2002-03-02  Chris Demetriou  <cgd@broadcom.com>
-
-	* interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
-	* mips.igen (LL, CxC1, MxC1): Likewise.
-
-2002-03-02  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
-	CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
-	FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
-	MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
-	NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
-	SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
-	Don't split opcode fields by hand, use the opcode field values
-	provided by igen.
-
-2002-03-01  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (do_divu): Fix spacing.
-
-	* mips.igen (do_dsllv): Move to be right before DSLLV,
-	to match the rest of the do_<shift> functions.
-
-2002-03-01  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
-	DSRL32, do_dsrlv): Trace inputs and results.
-
-2002-03-01  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (CACHE): Provide instruction-printing string.
-
-	* interp.c (signal_exception): Comment tokens after #endif.
-
-2002-02-28  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
-	(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, 
-	NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, 
-	ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, 
-	CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, 
-	C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, 
-	SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, 
-	LWC1, SWC1): Add "f" to filter, since these are FP instructions.
-
-2002-02-28  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (DSRA32, DSRAV): Fix order of arguments in
-	instruction-printing string.
-	(LWU): Use '64' as the filter flag.
-
-2002-02-28  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (SDXC1): Fix instruction-printing string.
-
-2002-02-28  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
-	filter flags "32,f".
-
-2002-02-27  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (PREFX): This is a 64-bit instruction, use '64'
-	as the filter flag.
-
-2002-02-27  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
-	add a comma) so that it more closely match the MIPS ISA
-	documentation opcode partitioning.
-	(PREF): Put useful names on opcode fields, and include
-	instruction-printing string.
-
-2002-02-27  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (check_u64): New function which in the future will
-	check whether 64-bit instructions are usable and signal an
-	exception if not.  Currently a no-op.
-	(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
-	DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
-	DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
-	LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
-
-	* mips.igen (check_fpu): New function which in the future will
-	check whether FPU instructions are usable and signal an exception
-	if not.  Currently a no-op.
-	(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
-	CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
-	CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
-	LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
-	MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
-	NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
-	ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
-	SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
-
-2002-02-27  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (do_load_left, do_load_right): Move to be immediately
-	following do_load.
-	(do_store_left, do_store_right): Move to be immediately following
-	do_store.
-
-2002-02-27  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (mipsV): New model name.  Also, add it to
-	all instructions and functions where it is appropriate.
-
-2002-02-18  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: For all functions and instructions, list model
-	names that support that instruction one per line.
-
-2002-02-11  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen: Add some additional comments about supported
-	models, and about which instructions go where.
-	(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
-	order as is used in the rest of the file.
-
-2002-02-11  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
-	indicating that ALU32_END or ALU64_END are there to check
-	for overflow.
-	(DADD): Likewise, but also remove previous comment about
-	overflow checking.
-
-2002-02-10  Chris Demetriou  <cgd@broadcom.com>
-
-	* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
-	DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
-	JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
-	SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
-	ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
-	fields (i.e., add and move commas) so that they more closely
-	match the MIPS ISA documentation opcode partitioning.
-
-2002-02-10  Chris Demetriou  <cgd@broadcom.com>
-
-        * mips.igen (ADDI): Print immediate value.
-        (BREAK): Print code.
-        (DADDIU, DSRAV, DSRLV): Print correct instruction name.
-        (SLL): Print "nop" specially, and don't run the code
-        that does the shift for the "nop" case.
-
-2001-11-17  Fred Fish  <fnf@redhat.com>
-
-	* sim-main.h (float_operation): Move enum declaration outside
-	of _sim_cpu struct declaration.
-
-2001-04-12  Jim Blandy  <jimb@redhat.com>
-
-	* mips.igen (CFC1, CTC1): Pass the correct register numbers to
-	PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
-	set of the FCSR.
-	* sim-main.h (COCIDX): Remove definition; this isn't supported by
-	PENDING_FILL, and you can get the intended effect gracefully by
-	calling PENDING_SCHED directly.
-
-2001-02-23  Ben Elliston  <bje@redhat.com>
-
-	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
-	already defined elsewhere.
-
-2001-02-19  Ben Elliston  <bje@redhat.com>
-
-	* sim-main.h (sim_monitor): Return an int.
-	* interp.c (sim_monitor): Add return values.
-	(signal_exception): Handle error conditions from sim_monitor.
-
-2001-02-08  Ben Elliston  <bje@redhat.com>
-
-	* sim-main.c (load_memory): Pass cia to sim_core_read* functions.
-	(store_memory): Likewise, pass cia to sim_core_write*.
-
-2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
-
-	On advice from Chris G. Demetriou <cgd@sibyte.com>:
-	* sim-main.h (GPR_CLEAR): Remove unused alternative macro.
-
-Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
-	* Makefile.in: Don't delete *.igen when cleaning directory.
-
-Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* m16.igen (break): Call SignalException not sim_engine_halt.
-
-Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	From Jason Eckhardt:
-	* mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
-
-Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (MxC1, DMxC1): Fix printf formatting.
-
-2000-05-24  Michael Hayes  <mhayes@cygnus.com>
-
-	* mips.igen (do_dmultx): Fix typo.
-
-Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
-
-2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
-
-	* sim-main.h (GPR_CLEAR): Define macro.
-
-Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (decode_coproc): Output long using %lx and not %s.
-
-2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
-
-	* interp.c (sim_open): Sort & extend dummy memory regions for
-	--board=jmr3904 for eCos.
-
-2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
-
-	* configure: Regenerated.
-
-Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
-
-	* interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
-	calls, conditional on the simulator being in verbose mode.
-
-Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
-
-	* sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
-	cache don't get ReservedInstruction traps.
-
-1999-11-29  Mark Salter  <msalter@cygnus.com>
-
-	* dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
-	to clear status bits in sdisr register. This is how the hardware works.
-
-	* interp.c (sim_open): Added more memory aliases for jmr3904 hardware
-	being used by cygmon.
-
-1999-11-11  Andrew Haley  <aph@cygnus.com>
-
-	* interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
-	instructions.
-
-Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
-
-	* mips.igen (MULT): Correct previous mis-applied patch.
-
-Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
-
-	* mips.igen (delayslot32): Handle sequence like
-	mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
-	correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
-	(MULT): Actually pass the third register...
-
-1999-09-03  Mark Salter  <msalter@cygnus.com>
-
-	* interp.c (sim_open): Added more memory aliases for additional
-	hardware being touched by cygmon on jmr3904 board.
-
-Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
-
-	* interp.c (sim_store_register): Handle case where client - GDB -
- 	specifies that a 4 byte register is 8 bytes in size.
-	(sim_fetch_register): Ditto.
-	
-1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
-
-	Implement "sim firmware" option, inspired by jimb's version of 1998-01.
-	* interp.c (firmware_option_p): New global flag: "sim firmware" given.
-	(idt_monitor_base): Base address for IDT monitor traps.
-	(pmon_monitor_base): Ditto for PMON.
-	(lsipmon_monitor_base): Ditto for LSI PMON.
-	(MONITOR_BASE, MONITOR_SIZE): Removed macros.
-	(mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
-	(sim_firmware_command): New function.
-	(mips_option_handler): Call it for OPTION_FIRMWARE.
-	(sim_open): Allocate memory for idt_monitor region.  If "--board"
-	option was given, add no monitor by default.  Add BREAK hooks only if
-	monitors are also there.
-	
-Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
-
-	* interp.c (sim_monitor): Flush output before reading input.
-
-Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* tconfig.in (SIM_HANDLES_LMA): Always define.
-
-Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	From Mark Salter <msalter@cygnus.com>:
-	* interp.c (BOARD_BSP): Define.  Add to list of possible boards.
-	(sim_open): Add setup for BSP board.
-
-Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (MULT, MULTU): Add syntax for two operand version.
-	(DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
- 	them as unimplemented.
-
-1999-05-08  Felix Lee  <flee@cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	
-1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
-
-Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
-
-	* configure.in: Any mips64vr5*-*-* target should have
- 	-DTARGET_ENABLE_FR=1.
-	(default_endian): Any mips64vr*el-*-* target should default to
-	LITTLE_ENDIAN.
-	* configure: Re-generate.
-
-1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* mips.igen (ldl): Extend from _16_, not 32.
-
-Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
-
-	* interp.c (sim_store_register): Force registers written to by GDB
- 	into an un-interpreted state.
-
-1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
- 	CPU, start periodic background I/O polls.
-	(tx3904sio_poll): New function: periodic I/O poller. 
-
-1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
-	
-Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
-
-	* configure.in, configure (mips64vr5*-*-*): Added missing ;; in
- 	case statement.
-
-1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
-	
-	* interp.c (sim_open): Allocate jm3904 memory in smaller chunks. 
-	(load_word): Call SIM_CORE_SIGNAL hook on error.
-	(signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
-	starting.  For exception dispatching, pass PC instead of NULL_CIA.
-	(decode_coproc): Use COP0_BADVADDR to store faulting address.
-	* sim-main.h (COP0_BADVADDR): Define. 
-	(SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
-	(SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
-	(_sim_cpu): Add exc_* fields to store register value snapshots.	
-	* mips.igen (*): Replace memory-related SignalException* calls
-	with references to SIM_CORE_SIGNAL hook.
-	
-	* dv-tx3904irc.c (tx3904irc_port_event): printf format warning
-	fix.
-	* sim-main.c (*): Minor warning cleanups.
-	
-1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* m16.igen (DADDIU5): Correct type-o.
-
-Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
-
-	* mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
- 	variables.
-
-Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
-
-	* Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
- 	to include path.
-	(interp.o): Add dependency on itable.h
-	(oengine.c, gencode): Delete remaining references.
-	(BUILT_SRC_FROM_GEN): Clean up.
-	
-1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
-	
-	* vr4run.c: New.
-	* Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
-	tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
-	tmp-run-hack) : New.
-	* m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
-	DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): 
-	Drop the "64" qualifier to get the HACK generator working.
-	Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
-	* mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
-	qualifier to get the hack generator working.
-	(do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
-	(DSLL): Use do_dsll.
-	(DSLLV): Use do_dsllv.
-	(DSRA): Use do_dsra.
-	(DSRL): Use do_dsrl.
-	(DSRLV): Use do_dsrlv.
-	(BC1): Move *vr4100 to get the HACK generator working.
-	(CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to 
-	get the HACK generator working.
-	(MACC) Rename to get the HACK generator working.
-	(DMACC,MACCS,DMACCS): Add the 64.
-	
-1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
-
-	* mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
-	* sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
-	
-1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
-
-    * mips/interp.c (DEBUG): Cleanups.
-
-1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
-	(tx3904sio_tickle): fflush after a stdout character output.
-	
-1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* interp.c (sim_close): Uninstall modules.
-
-Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h, interp.c (sim_monitor): Change to global
- 	function.
-
-Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (vr4100): Only include vr4100 instructions in
- 	simulator.
-	* configure: Re-generate.
-	* m16.igen (*): Tag all mips16 instructions as also being vr4100.
-
-Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
-	* sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
- 	true alternative.
-
-	* configure.in (sim_default_gen, sim_use_gen): Replace with
- 	sim_gen.
-	(--enable-sim-igen): Delete config option. Always using IGEN.
-	* configure: Re-generate.
-	
-	* Makefile.in (gencode): Kill, kill, kill.
-	* gencode.c: Ditto.
-	
-Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
- 	bit mips16 igen simulator.
-	* configure: Re-generate.
-
-	* mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
- 	as part of vr4100 ISA.
-	* vr.igen: Mark all instructions as 64 bit only.
-
-Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
- 	Pacify GCC.
-
-Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in: Configure mips-lsi-elf nee mips*lsi* as a
- 	mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
-	* configure: Re-generate.
-
-	* m16.igen (BREAK): Define breakpoint instruction.
-	(JALX32): Mark instruction as mips16 and not r3900.
-	* mips.igen (C.cond.fmt): Fix typo in instruction format.
-
-	* sim-main.h (PENDING_FILL): Wrap C statements in do/while.
-
-Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
- 	insn as a debug breakpoint.
-
-	* sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
- 	pending.slot_size.
-	(PENDING_SCHED): Clean up trace statement.
-	(PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
-	(PENDING_FILL): Delay write by only one cycle.
-	(PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
-
-	* sim-main.c (pending_tick): Clean up trace statements. Add trace
- 	of pending writes.
-	(pending_tick): Fix sizes in switch statements, 4 & 8 instead of
- 	32 & 64.
-	(pending_tick): Move incrementing of index to FOR statement.
-	(pending_tick): Only update PENDING_OUT after a write has occured.
-	
-	* configure.in: Add explicit mips-lsi-* target.  Use gencode to
- 	build simulator.
-	* configure: Re-generate.
-	
-	* interp.c (sim_engine_run OLD): Delete explicit call to
- 	PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
-	
-Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
-	interrupt level number to match changed SignalExceptionInterrupt
-	macro.
-
-Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* interp.c: #include "itable.h" if WITH_IGEN.
-	(get_insn_name): New function.
-	(sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
-	* sim-main.h (MAX_INSNS,INSN_NAME): Delete.
-
-Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* configure: Rebuilt to inhale new common/aclocal.m4.
-
-Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904sio.c: Include sim-assert.h.
-
-Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904sio.c: New file: tx3904 serial I/O module.
-	* configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
-	Reorganize target-specific sim-hardware checks.
-	* configure: rebuilt.
-	* interp.c (sim_open): For tx39 target boards, set
-	OPERATING_ENVIRONMENT, add tx3904sio devices.
-	* tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
-	ROM executables.  Install dv-sockser into sim-modules list.
-	
-	* dv-tx3904irc.c: Compiler warning clean-up.
-	* dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
-	frequent hw-trace messages.
-
-Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* vr.igen (MulAcc): Identify as a vr4100 specific function.
-
-Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (IGEN_INCLUDE): Add vr.igen.
-
-	* vr.igen: New file.
-	(MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
-	* mips.igen: Define vr4100 model. Include vr.igen.
-Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* mips.igen (check_mf_hilo): Correct check.
-
-Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (interrupt_event): Add prototype.
-
-	* dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
- 	register_ptr, register_value.
-	(deliver_tx3904tmr_tick): Fix types passed to printf fmt.
-
-	* sim-main.h (tracefh): Make extern.
-
-Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904tmr.c: Deschedule timer event after dispatching.
-	Reduce unnecessarily high timer event frequency.  
-	* dv-tx3904cpu.c: Ditto for interrupt event.
-	
-Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* interp.c (decode_coproc): For TX39, add stub COP0 register #7,
- 	to allay warnings.
-	(interrupt_event): Made non-static.
-	
-	* dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
- 	interchange of configuration values for external vs. internal
- 	clock dividers.
-	
-Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
-
-	* mips.igen (BREAK): Moved code to here for 
-	simulator-reserved break instructions.
-	* gencode.c (build_instruction): Ditto.
-	* interp.c (signal_exception): Code moved from here.  Non-
-	reserved instructions now use exception vector, rather 
-	than halting sim.
-	* sim-main.h: Moved magic constants to here.
-
-Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
- 	register upon non-zero interrupt event level, clear upon zero
- 	event value.
-	* dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
-	by passing zero event value.
-	(*_io_{read,write}_buffer): Endianness fixes.
-	* dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
-	(deliver_*_tick): Reduce sim event interval to 75% of count interval.
-
-	* interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
-	serial I/O and timer module at base address 0xFFFF0000.
-	
-Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* mips.igen (SWC1) : Correct the handling of ReverseEndian 
-	and BigEndianCPU.
-
-Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
-	parts.
-	* configure: Update.
-
-Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* dv-tx3904tmr.c: New file - implements tx3904 timer.
-	* dv-tx3904{irc,cpu}.c: Mild reformatting.
-	* configure.in: Include tx3904tmr in hw_device list.
-	* configure: Rebuilt.
-	* interp.c (sim_open): Instantiate three timer instances.
-	Fix address typo of tx3904irc instance.
-
-Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
-
-	* interp.c (signal_exception): SystemCall exception now uses
-	the exception vector.
-
-Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* interp.c (decode_coproc): For TX39, add stub COP0 register #3,
-	to allay warnings.
-
-Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
-
-Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
-
-	* dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
- 	sim-main.h. Declare a struct hw_descriptor instead of struct
- 	hw_device_descriptor.
-
-Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (do_store_left, do_load_left): Compute nr of left and
- 	right bits and then re-align left hand bytes to correct byte
- 	lanes.  Fix incorrect computation in do_store_left when loading
- 	bytes from second word.
-
-Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
-	* interp.c (sim_open): Only create a device tree when HW is
- 	enabled.
-
-	* dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
-	* interp.c (signal_exception): Ditto.
-
-Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c: Mark BEGEZALL as LIKELY.
-
-Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (ALU32_END): Sign extend 32 bit results.
-	* mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
-	
-Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
- 	modules.  Recognize TX39 target with "mips*tx39" pattern.
-	* configure: Rebuilt.
-	* sim-main.h (*): Added many macros defining bits in
- 	TX39 control registers.
-	(SignalInterrupt): Send actual PC instead of NULL.
-	(SignalNMIReset): New exception type.
-	* interp.c (board): New variable for future use to identify
-	a particular board being simulated.
-	(mips_option_handler,mips_options): Added "--board" option.
-	(interrupt_event): Send actual PC.
-	(sim_open): Make memory layout conditional on board setting.
-	(signal_exception): Initial implementation of hardware interrupt
- 	handling.  Accept another break instruction variant for simulator
- 	exit.
-	(decode_coproc): Implement RFE instruction for TX39.
-	(mips.igen): Decode RFE instruction as such.
-	* configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
-	* interp.c: Define "jmr3904" and "jmr3904debug" board types and
-	bbegin to implement memory map.
-	* dv-tx3904cpu.c: New file.
-	* dv-tx3904irc.c: New file.
-
-Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* mips.igen (check_mt_hilo): Create a separate r3900 version.
-
-Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* tx.igen (madd,maddu):  Replace calls to check_op_hilo
-	with calls to check_div_hilo.
-
-Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
-	Replace check_op_hilo with check_mult_hilo and check_div_hilo.
-	Add special r3900 version of do_mult_hilo.  
-	(do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
-	with calls to check_mult_hilo.
-	(do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
-	with calls to check_div_hilo.
-
-Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (SUBTARGET_R3900): Define for mipstx39 target.
-  	Document a replacement.
-
-Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
-
-	* interp.c (sim_monitor): Make mon_printf work.
-
-Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* sim-main.h (INSN_NAME): New arg `cpu'.
-
-Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
-
-        * configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* acconfig.h: New file.
-	* configure.in: Reverted change of Apr 24; use sinclude again.
-
-Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
-
-	* configure.in: Don't call sinclude.
-
-Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
-
-	* mips.igen (do_store_left): Pass 0 not NULL to store_memory.
-
-Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (ERET): Implement.
-
-	* interp.c (decode_coproc): Return sign-extended EPC.
-
-	* mips.igen (ANDI, LUI, MFC0): Add tracing code.
-
-	* interp.c (signal_exception): Do not ignore Trap.
-	(signal_exception): On TRAP, restart at exception address.
-	(HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
-	(signal_exception): Update.
-	(sim_open): Patch V_COMMON interrupt vector with an abort sequence
- 	so that TRAP instructions are caught.
-
-Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (struct hilo_access, struct hilo_history): Define,
- 	contains HI/LO access history.
-	(struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
-	(HIACCESS, LOACCESS): Delete, replace with
-	(HIHISTORY, LOHISTORY): New macros.
-	(CHECKHILO): Delete all, moved to mips.igen
-	
-	* gencode.c (build_instruction): Do not generate checks for
- 	correct HI/LO register usage.
-
-	* interp.c (old_engine_run): Delete checks for correct HI/LO
- 	register usage.
-
-	* mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
- 	check_mf_cycles): New functions.
-	(do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
- 	do_divu, domultx, do_mult, do_multu): Use.
-
-	* tx.igen ("madd", "maddu"): Use.
-	
-Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (DSRAV): Use function do_dsrav.
-	(SRAV): Use new function do_srav.
-
-	* m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
-	(B): Sign extend 11 bit immediate.
-	(EXT-B*): Shift 16 bit immediate left by 1.
-	(ADDIU*): Don't sign extend immediate value.
-
-Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* m16run.c (sim_engine_run): Restore CIA after handling an event.
-
-	* sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
- 	functions.
-
-	* mips.igen (delayslot32, nullify_next_insn): New functions.
-	(m16.igen): Always include.
-	(do_*): Add more tracing.
-
-	* m16.igen (delayslot16): Add NIA argument, could be called by a
- 	32 bit MIPS16 instruction.
-	
-	* interp.c (ifetch16): Move function from here.
-	* sim-main.c (ifetch16): To here.
-	
-	* sim-main.c (ifetch16, ifetch32): Update to match current
- 	implementations of LH, LW.
-	(signal_exception): Don't print out incorrect hex value of illegal
- 	instruction.
-
-Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
- 	instruction.
-
-	* m16.igen: Implement MIPS16 instructions.
-	
-	* mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
- 	do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
- 	do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
- 	do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
- 	do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
- 	bodies of corresponding code from 32 bit insn to these.  Also used
- 	by MIPS16 versions of functions.
-	
-	* sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
-	(IMEM16): Drop NR argument from macro.
-
-Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-main.o.
-
-	* sim-main.h (address_translation, load_memory, store_memory,
- 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
- 	as INLINE_SIM_MAIN.
-	(pr_addr, pr_uword64): Declare.
-	(sim-main.c): Include when H_REVEALS_MODULE_P.
-	
-	* interp.c (address_translation, load_memory, store_memory,
- 	cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
- 	from here.
-	* sim-main.c: To here. Fix compilation problems.
-	
-	* configure.in: Enable inlining.
-	* configure: Re-config.
-
-Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen: Include tx.igen.
-	* Makefile.in (IGEN_INCLUDE): Add tx.igen.
-	* tx.igen: New file, contains MADD and MADDU.
-
-	* interp.c (load_memory): When shifting bytes, use LOADDRMASK not
- 	the hardwired constant `7'.
-	(store_memory): Ditto.
-	(LOADDRMASK): Move definition to sim-main.h.
-
-	mips.igen (MTC0): Enable for r3900.
-	(ADDU): Add trace.
-
-	mips.igen (do_load_byte): Delete.
-	(do_load, do_store, do_load_left, do_load_write, do_store_left,
- 	do_store_right): New functions.
-	(SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
-
-	configure.in: Let the tx39 use igen again.
-	configure: Update.
-	
-Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
- 	not an address sized quantity.  Return zero for cache sizes.
-
-Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (r3900): r3900 does not support 64 bit integer
- 	operations.
-
-Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* configure.in (mipstx39*-*-*): Use gencode simulator rather
-	than igen one.
-	* configure : Rebuild.
-	
-Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
-
-Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (Max, Min): Comment out functions. Not yet used.
-
-Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
-
-	* Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
- 	configurable settings for stand-alone simulator.
-	
-	* configure.in: Added X11 search, just in case.
-	
-	* configure: Regenerated.
-
-Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_write, sim_read, load_memory, store_memory):
- 	Replace sim_core_*_map with read_map, write_map, exec_map resp.
-
-Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (GETFCC): Return an unsigned value.
-
-Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (DIV): Fix check for -1 / MIN_INT.
-	(DADD): Result destination is RD not RT.
-
-Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (HIACCESS, LOACCESS): Always define.
-
-	* mdmx.igen (Maxi, Mini): Rename Max, Min.
-
-	* interp.c (sim_info): Delete.
-
-Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
-
-	* interp.c (DECLARE_OPTION_HANDLER): Use it.
-	(mips_option_handler): New argument `cpu'.
-	(sim_open): Update call to sim_add_option_table.
-
-Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (CxC1): Add tracing.
-
-Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (Max, Min): Declare.
-
-	* interp.c (Max, Min): New functions.
-
-	* mips.igen (BC1): Add tracing.
-	
-Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
-	
-	* interp.c Added memory map for stack in vr4100
-	
-Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
-
-	* interp.c (load_memory): Add missing "break"'s.
-
-Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_store_register, sim_fetch_register): Pass in
- 	length parameter.  Return -1.
-
-Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
-
-	* interp.c: Added hardware init hook, fixed warnings.
-
-Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
-
-Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (ifetch16): New function.
-
-	* sim-main.h (IMEM32): Rename IMEM.
-	(IMEM16_IMMED): Define.
-	(IMEM16): Define.
-	(DELAY_SLOT): Update.
-	
-	* m16run.c (sim_engine_run): New file.
-	
-	* m16.igen: All instructions except LB.
-	(LB): Call do_load_byte.
-	* mips.igen (do_load_byte): New function.
-	(LB): Call do_load_byte.
-
-	* mips.igen: Move spec for insn bit size and high bit from here.
-	* Makefile.in (tmp-igen, tmp-m16): To here.
-
-	* m16.dc: New file, decode mips16 instructions.
-
-	* Makefile.in (SIM_NO_ALL): Define.
-	(tmp-m16): Generate both 16 bit and 32 bit simulator engines.
-
-Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (mips_fpu_bitsize): For tx39, restrict floating
- 	point unit to 32 bit registers.
-	* configure: Re-generate.
-
-Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (sim_use_gen): Make IGEN the default simulator
- 	generator for generic 32 and 64 bit mips targets.
-	* configure: Re-generate.
-
-Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (SizeFGR): Determine from floating-point and not gpr
- 	bitsize.
-
-	* interp.c (sim_fetch_register, sim_store_register): Read/write
- 	FGR from correct location.
-	(sim_open): Set size of FGR's according to
- 	WITH_TARGET_FLOATING_POINT_BITSIZE.
-	
-	* sim-main.h (FGR): Store floating point registers in a separate
- 	array.
-
-Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (ColdReset): Call PENDING_INVALIDATE.
-
-	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
-
-	* interp.c (pending_tick): New function.  Deliver pending writes.
-
-	* sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
- 	PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
- 	it can handle mixed sized quantites and single bits.
-	
-Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (oengine.h): Do not include when building with IGEN.
-	(sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
-	(sim_info): Ditto for PROCESSOR_64BIT.
-	(sim_monitor): Replace ut_reg with unsigned_word.
-	(*): Ditto for t_reg.
-	(LOADDRMASK): Define.
-	(sim_open): Remove defunct check that host FP is IEEE compliant,
- 	using software to emulate floating point.
-	(value_fpr, ...): Always compile, was conditional on HASFPU.
-
-Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
- 	size.
-
-	* interp.c (SD, CPU): Define.
-	(mips_option_handler): Set flags in each CPU.
-	(interrupt_event): Assume CPU 0 is the one being iterrupted.
-	(sim_close): Do not clear STATE, deleted anyway.
-	(sim_write, sim_read): Assume CPU zero's vm should be used for
- 	data transfers.
-	(sim_create_inferior): Set the PC for all processors.
-	(sim_monitor, store_word, load_word, mips16_entry): Add cpu
- 	argument.
-	(mips16_entry): Pass correct nr of args to store_word, load_word.
-	(ColdReset): Cold reset all cpu's.
-	(signal_exception): Pass cpu to sim_monitor & mips16_entry.
-	(sim_monitor, load_memory, store_memory, signal_exception): Use
- 	`CPU' instead of STATE_CPU.
-
-
-	* sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
- 	SD or CPU_.
-	
-	* sim-main.h (signal_exception): Add sim_cpu arg.
-	(SignalException*): Pass both SD and CPU to signal_exception.
-	* interp.c (signal_exception): Update.
-	
-	* sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
- 	Ditto
-	(sync_operation, prefetch, cache_op, store_memory, load_memory,
- 	address_translation): Ditto
-	(decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
-	
-Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_engine_run): Add `nr_cpus' argument.
-
-	* mips.igen (model): Map processor names onto BFD name.	
-
-	* sim-main.h (CPU_CIA): Delete.
- 	(SET_CIA, GET_CIA): Define
-
-Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (GPR_SET): Define, used by igen when zeroing a
- 	regiser.
-
-	* configure.in (default_endian): Configure a big-endian simulator
- 	by default.
-	* configure: Re-generate.
-	
-Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c (sim_monitor): Handle Densan monitor outbyte
-	and inbyte functions.
-
-1997-12-29  Felix Lee  <flee@cygnus.com>
-
-	* interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
-
-Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* Makefile.in (tmp-igen): Arrange for $zero to always be
-	reset to zero after every instruction.
-
-Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* mips.igen (MSUB): Fix to work like MADD.
-	* gencode.c (MSUB): Similarly.
-
-Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen (LWC1): Correct assembler - lwc1 not swc1.
-
-Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (sim-fpu.h): Include.
-
-	* interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
- 	Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
- 	using host independant sim_fpu module.
-
-Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (signal_exception): Report internal errors with SIGABRT
- 	not SIGQUIT.
-
-	* sim-main.h (C0_CONFIG): New register.
-	(signal.h): No longer include.
-
-	* interp.c (decode_coproc): Allow access C0_CONFIG to register.
-
-Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
-
-Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen: Tag vr5000 instructions.
-	(ANDI): Was missing mipsIV model, fix assembler syntax.
-	(do_c_cond_fmt): New function.
-	(C.cond.fmt): Handle mips I-III which do not support CC field
- 	separatly.
-	(bc1): Handle mips IV which do not have a delaed FCC separatly.
-	(SDR): Mask paddr when BigEndianMem, not the converse as specified
- 	in IV3.2 spec.
-	(DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
- 	vr5000 which saves LO in a GPR separatly.
-	
-	* configure.in (enable-sim-igen): For vr5000, select vr5000
- 	specific instructions.
-	* configure: Re-generate.
-	
-Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-fpu module.
-
-	* interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
- 	fmt_uninterpreted_64 bit cases to switch.  Convert to
- 	fmt_formatted,
-
-	* sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
-
-	* mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
- 	as specified in IV3.2 spec.
-	(MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
-
-Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen: Delay slot branches add OFFSET to NIA not CIA.
- 	(MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
-	(MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
- 	PENDING_FILL versions of instructions.  Simplify.
-	(X): New function.
-	(MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
- 	instructions.
-	(BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
- 	a signed value.
-	(MTHI, MFHI): Disable code checking HI-LO.
-	
-	* sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
- 	global.
-	(NULLIFY_NEXT_INSTRUCTION): Call dotrace.
-
-Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (build_mips16_operands): Replace IPC with cia.
-
-	* interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
- 	value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
- 	IPC to `cia'.
-	(UndefinedResult): Replace function with macro/function
- 	combination.
-	(sim_engine_run): Don't save PC in IPC.
-
-	* sim-main.h (IPC): Delete.
-
-
-	* interp.c (signal_exception, store_word, load_word,
- 	address_translation, load_memory, store_memory, cache_op,
- 	prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
- 	cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
- 	current instruction address - cia - argument.
-	(sim_read, sim_write): Call address_translation directly.
-	(sim_engine_run): Rename variable vaddr to cia.
-	(signal_exception): Pass cia to sim_monitor
-	
-	* sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
- 	Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
- 	COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
-
-	* sim-main.h (SignalExceptionSimulatorFault): Delete definition.
-  	* interp.c (sim_open): Replace SignalExceptionSimulatorFault with
- 	SIM_ASSERT.
-	
-	* interp.c (signal_exception): Pass restart address to
- 	sim_engine_restart.
-
-	* Makefile.in (semantics.o, engine.o, support.o, itable.o,
- 	idecode.o): Add dependency.
-
-	* sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
- 	Delete definitions
-	(DELAY_SLOT): Update NIA not PC with branch address.
-	(NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
-
-	* mips.igen: Use CIA not PC in branch calculations.
-	(illegal): Call SignalException.
- 	(BEQ, ADDIU): Fix assembler.
-
-Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* m16.igen (JALX): Was missing.
-
-	* configure.in (enable-sim-igen): New configuration option.
-	* configure: Re-generate.
-	
-	* sim-main.h (MAX_INSNS, INSN_NAME): Define.
-
-	* interp.c (load_memory, store_memory): Delete parameter RAW.
-	(sim_read, sim_write): Use sim_core_{read,write}_buffer directly
- 	bypassing {load,store}_memory.
-
-	* sim-main.h (ByteSwapMem): Delete definition.
-
-	* Makefile.in (SIM_OBJS): Add sim-memopt module.
-
-	* interp.c (sim_do_command, sim_commands): Delete mips specific
- 	commands.  Handled by module sim-options.
-		
-	* sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
-	(WITH_MODULO_MEMORY): Define.
-
-	* interp.c (sim_info): Delete code printing memory size.
-
-	* interp.c (mips_size): Nee sim_size, delete function.
-	(power2): Delete.
-	(monitor, monitor_base, monitor_size): Delete global variables.
-	(sim_open, sim_close): Delete code creating monitor and other
- 	memory regions.  Use sim-memopts module, via sim_do_commandf, to
- 	manage memory regions.
-	(load_memory, store_memory): Use sim-core for memory model.
-	
-	* interp.c (address_translation): Delete all memory map code
- 	except line forcing 32 bit addresses.
-
-Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (WITH_TRACE): Delete definition.  Enables common
- 	trace options.
-
-	* interp.c (logfh, logfile): Delete globals.
-	(sim_open, sim_close): Delete code opening & closing log file.
-	(mips_option_handler): Delete -l and -n options.
-	(OPTION mips_options): Ditto.
-
-	* interp.c (OPTION mips_options): Rename option trace to dinero.
-	(mips_option_handler): Update.
-
-Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (fetch_str): New function.
-	(sim_monitor): Rewrite using sim_read & sim_write.
-	(sim_open): Check magic number.
-	(sim_open): Write monitor vectors into memory using sim_write.
-	(MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
-	(sim_read, sim_write): Simplify - transfer data one byte at a
- 	time.
-	(load_memory, store_memory): Clarify meaning of parameter RAW.
-
-	* sim-main.h (isHOST): Defete definition.
-	(isTARGET): Mark as depreciated.
-	(address_translation): Delete parameter HOST.
-
-	* interp.c (address_translation): Delete parameter HOST.
-
-Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen: 
-
-	* Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
-	(tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
-
-Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* mips.igen: Add model filter field to records.
-
-Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
-	
-	interp.c (sim_engine_run): Do not compile function sim_engine_run
- 	when WITH_IGEN == 1.
-
-	* configure.in (sim_igen_flags, sim_m16_flags): Set according to
- 	target architecture.
-
-	Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
- 	igen. Replace with configuration variables sim_igen_flags /
- 	sim_m16_flags.
-
-	* m16.igen: New file.  Copy mips16 insns here.
-	* mips.igen: From here.
-
-Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
- 	to top.
-	(tmp-igen, tmp-m16): Pass -I srcdir to igen.
-
-Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c (build_instruction): Follow sim_write's lead in using
-	BigEndianMem instead of !ByteSwapMem.
-
-Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in (sim_gen): Dependent on target, select type of
- 	generator.  Always select old style generator.
-
-	configure: Re-generate.
-
-	Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
- 	targets.
-	(SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
- 	SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
- 	IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
-	(SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
- 	SIM_@sim_gen@_*, set by autoconf.
-	
-Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
-
-	* interp.c (ColdReset): Remove #ifdef HASFPU, check
- 	CURRENT_FLOATING_POINT instead.
-
-	* interp.c (ifetch32): New function. Fetch 32 bit instruction.
-	(address_translation): Raise exception InstructionFetch when
- 	translation fails and isINSTRUCTION.
-	
-	* interp.c (sim_open, sim_write, sim_monitor, store_word,
- 	sim_engine_run): Change type of of vaddr and paddr to
- 	address_word.
-	(address_translation, prefetch, load_memory, store_memory,
- 	cache_op): Change type of vAddr and pAddr to address_word.
-
-	* gencode.c (build_instruction): Change type of vaddr and paddr to
- 	address_word.
-
-Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
- 	macro to obtain result of ALU op.
-
-Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_info): Call profile_print.
-
-Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-profile.o module.
-
-	* sim-main.h (WITH_PROFILE): Do not define, defined in
- 	common/sim-config.h.  Use sim-profile module.
-	(simPROFILE): Delete defintion.
-
-	* interp.c (PROFILE): Delete definition.
-	(mips_option_handler): Delete 'p', 'y' and 'x' profile options.
-	(sim_close): Delete code writing profile histogram.
-	(mips_set_profile, mips_set_profile_size, writeout16, writeout32):
- 	Delete.
-	(sim_engine_run): Delete code profiling the PC.
-
-Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
-
-	* interp.c (sim_monitor): Make register pointers of type
- 	unsigned_word*.
-
-	* sim-main.h: Make registers of type unsigned_word not
- 	signed_word.
-
-Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sync_operation): Rename from SyncOperation, make
- 	global, add SD argument.
-	(prefetch): Rename from Prefetch, make global, add SD argument.
-	(decode_coproc): Make global.
-
-	* sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
-
-	* gencode.c (build_instruction): Generate DecodeCoproc not
- 	decode_coproc calls.
-
-	* interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
-	(SizeFGR): Move to sim-main.h
-	(simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
- 	simSIGINT, simJALDELAYSLOT): Move to sim-main.h
-	(FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
- 	sim-main.h.
-	(FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
- 	FP_RM_TOMINF, GETRM): Move to sim-main.h.
-	(Uncached, CachedNoncoherent, CachedCoherent, Cached,
- 	isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
-	(UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
- 	BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
-	
-	* sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
- 	exception.
-	(sim-alu.h): Include.
-	(NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
- 	(sim_cia): Typedef to instruction_address.
-	
-Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (interp.o): Rename generated file engine.c to
-	oengine.c.
-  	
-	* interp.c: Update.
-	
-Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (build_instruction): Use FPR_STATE not fpr_state.
-	
-Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (build_instruction): For "FPSQRT", output correct
- 	number of arguments to Recip.
-	
-Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (interp.o): Depends on sim-main.h
-
-	* interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
-
-	* sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
- 	ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
- 	(REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
- 	STATE, DSSTATE): Define
-	(GPR, FGRIDX, ..): Define.
-
-	* interp.c (registers, register_widths, fpr_state, ipc, dspc,
- 	pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
-	(GPR, FGRIDX, ...): Delete macros.
-	
-	* interp.c: Update names to match defines from sim-main.h
-	
-Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_monitor): Add SD argument.
-	(sim_warning): Delete.  Replace calls with calls to
- 	sim_io_eprintf.
-	(sim_error): Delete. Replace calls with sim_io_error.
-	(open_trace, writeout32, writeout16, getnum): Add SD argument.
-	(mips_set_profile): Rename from sim_set_profile. Add SD argument.
-	(mips_set_profile_size): Rename from sim_set_profile_size. Add SD
- 	argument.
-	(mips_size): Rename from sim_size. Add SD argument.
-
-	* interp.c (simulator): Delete global variable.
-	(callback): Delete global variable.
-	(mips_option_handler, sim_open, sim_write, sim_read,
- 	sim_store_register, sim_fetch_register, sim_info, sim_do_command,
- 	sim_size,sim_monitor): Use sim_io_* not callback->*.
-	(sim_open): ZALLOC simulator struct.
-	(PROFILE): Do not define.
-
-Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_open), support.h: Replace CHECKSIM macro found in
- 	support.h with corresponding code.
-
-	* sim-main.h (word64, uword64), support.h: Move definition to
- 	sim-main.h.
-	(WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
-
-	* support.h: Delete
-	* Makefile.in: Update dependencies
-	* interp.c: Do not include.
-	
-Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (address_translation, load_memory, store_memory,
- 	cache_op): Rename to from AddressTranslation et.al., make global,
- 	add SD argument
-	
-	* sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
- 	CacheOp): Define.
-	
-	* interp.c (SignalException): Rename to signal_exception, make
- 	global.
-
-	* interp.c (Interrupt, ...): Move definitions to sim-main.h.
-	
-	* sim-main.h (SignalException, SignalExceptionInterrupt,
- 	SignalExceptionInstructionFetch, SignalExceptionAddressStore,
- 	SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
- 	SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
- 	Define.
-  	
-	* interp.c, support.h: Use.
-	
-Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
- 	to value_fpr / store_fpr. Add SD argument.
-	(NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
- 	Multiply, Divide, Recip, SquareRoot, Convert): Make global.
-
-	* sim-main.h (ValueFPR, StoreFPR): Define.
-	
-Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_engine_run): Check consistency between configure
- 	WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
- 	and HASFPU.
-
-	* configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
-        (mips_fpu): Configure WITH_FLOATING_POINT.
-	(mips_endian): Configure WITH_TARGET_ENDIAN.
-	* configure: Update.
-
-Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
-
-	* configure: Regenerated.
-
-Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
-
-Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (print_igen_insn_models): Assume certain architectures
- 	include all mips* instructions.
-	(print_igen_insn_format): Use data_size==-1 as marker for MIPS16
- 	instruction.
-
-	* Makefile.in (tmp.igen): Add target. Generate igen input from
- 	gencode file.
-
-	* gencode.c (FEATURE_IGEN): Define.
-	(main): Add --igen option.  Generate output in igen format.
-	(process_instructions): Format output according to igen option.
-	(print_igen_insn_format): New function.
-	(print_igen_insn_models): New function.
-	(process_instructions): Only issue warnings and ignore
- 	instructions when no FEATURE_IGEN.
-
-Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
- 	MIPS targets.
-
-Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
- 	SIM_RESERVED_BITS): Delete, moved to common.
-	(SIM_EXTRA_CFLAGS): Update.
-	
-Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure.in: Configure non-strict memory alignment.
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c (SDBBP,DERET): Added (3900) insns.
-	(RFE): Turn on for 3900.
-	* interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
-	(dsstate): Made global.
-	(SUBTARGET_R3900): Added.
-	(CANCELDELAYSLOT): New.
-	(SignalException): Ignore SystemCall rather than ignore and
-	terminate.  Add DebugBreakPoint handling.
-	(decode_coproc): New insns RFE, DERET; and new registers Debug
-	and DEPC protected by SUBTARGET_R3900.
-	(sim_engine_run): Use CANCELDELAYSLOT rather than clearing
-	bits explicitly.
-	* Makefile.in,configure.in: Add mips subtarget option.
-	* configure: Update.	
-
-Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c: Add r3900 (tx39).
-	
-
-Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c (build_instruction): Don't need to subtract 4 for
-	JALR, just 2.
-
-Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* interp.c: Correct some HASFPU problems.
-
-Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (mips_options): Fix samples option short form, should
- 	be `x'.
-
-Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_info): Enable info code.  Was just returning.
-
-Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (decode_coproc): Clarify warning about unsuported MTC0,
- 	MFC0.
-
-Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* gencode.c (build_instruction): Use SIGNED64 for 64 bit
- 	constants.
-	(build_instruction): Ditto for LL.
-
-Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_open): Add call to sim_analyze_program, update
- 	call to sim_config.
-
-Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_kill): Delete.
-	(sim_create_inferior): Add ABFD argument. Set PC from same.
-	(sim_load): Move code initializing trap handlers from here.
-	(sim_open): To here.
-	(sim_load): Delete, use sim-hload.c.
-
-	* Makefile.in (SIM_OBJS): Add sim-hload.o module.
-
-Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_open): Add ABFD argument.
-	(sim_load): Move call to sim_config from here.
-	(sim_open): To here.  Check return status.
-
-Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
- 
- 	* gencode.c (build_instruction): Two arg MADD should
- 	not assign result to $0.
- 
-Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
-
-	* sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
-	* sim/mips/configure.in: Regenerate.
-
-Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
-
-	* interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
- 	signed8, unsigned8 et.al. types.
-
-	* interp.c (SUB_REG_FETCH): Handle both little and big endian
- 	hosts when selecting subreg.
-
-Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
-
-	* interp.c (sim_engine_run): Reset the ZERO register to zero
-	regardless of FEATURE_WARN_ZERO.
-	* gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
-
-Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (decode_coproc): Implement MTC0 N, CAUSE.
-	(SignalException): For BreakPoints ignore any mode bits and just
- 	save the PC.
-	(SignalException): Always set the CAUSE register.
-
-Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (SignalException): Clear the simDELAYSLOT flag when an
- 	exception has been taken.
-
-	* interp.c: Implement the ERET and mt/f sr instructions.
-
-Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (SignalException): Don't bother restarting an
- 	interrupt.
-
-Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (SignalException): Really take an interrupt.
-	(interrupt_event): Only deliver interrupts when enabled.
-
-Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_info): Only print info when verbose.
-	(sim_info) Use sim_io_printf for output.
-	
-Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (CoProcPresent): Add UNUSED attribute - not used by all
- 	mips architectures.
-
-Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_do_command): Check for common commands if a
- 	simulator specific command fails.
-
-Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
-	and simBE when DEBUG is defined.
-
-Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (interrupt_event): New function.  Pass exception event
- 	onto exception handler.
-
-	* configure.in: Check for stdlib.h.
-	* configure: Regenerate.
-
-	* gencode.c (build_instruction): Add UNUSED attribute to tempS
- 	variable declaration.
-	(build_instruction): Initialize memval1.
-	(build_instruction): Add UNUSED attribute to byte, bigend,
- 	reverse.
-	(build_operands): Ditto.
-
-	* interp.c: Fix GCC warnings.
-	(sim_get_quit_code): Delete.
-
-	* configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
-	* Makefile.in: Ditto.
-	* configure: Re-generate.
-	
-	* Makefile.in (SIM_OBJS): Add sim-watch.o module.
-
-Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (mips_option_handler): New function parse argumes using
- 	sim-options.
-	(myname): Replace with STATE_MY_NAME.
-	(sim_open): Delete check for host endianness - performed by
- 	sim_config.
-	(simHOSTBE, simBE): Delete, replaced by sim-endian flags.
-	(sim_open): Move much of the initialization from here.
-	(sim_load): To here.  After the image has been loaded and
- 	endianness set.
-	(sim_open): Move ColdReset from here.
-	(sim_create_inferior): To here.
-	(sim_open): Make FP check less dependant on host endianness.
-
-	* Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
- 	run.
-	* interp.c (sim_set_callbacks): Delete.
-
-	* interp.c (membank, membank_base, membank_size): Replace with
- 	STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
-	(sim_open): Remove call to callback->init. gdb/run do this.
-
-	* interp.c: Update
-
-	* sim-main.h (SIM_HAVE_FLATMEM): Define.
-
-	* interp.c (big_endian_p): Delete, replaced by
- 	current_target_byte_order.
-
-Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (host_read_long, host_read_word, host_swap_word,
- 	host_swap_long): Delete. Using common sim-endian.
-	(sim_fetch_register, sim_store_register): Use H2T.
-	(pipeline_ticks): Delete.  Handled by sim-events.
-	(sim_info): Update.
-	(sim_engine_run): Update.
-
-Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_stop_reason): Move code determining simEXCEPTION
- 	reason from here.
-	(SignalException): To here. Signal using sim_engine_halt.
-	(sim_stop_reason): Delete, moved to common.
-	
-Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
-
-	* interp.c (sim_open): Add callback argument.
-	(sim_set_callbacks): Delete SIM_DESC argument.
-	(sim_size): Ditto.
-
-Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add common modules.
-
-	* interp.c (sim_set_callbacks): Also set SD callback.
-	(set_endianness, xfer_*, swap_*): Delete.
-	(host_read_word, host_read_long, host_swap_word, host_swap_long):
- 	Change to functions using sim-endian macros.
-	(control_c, sim_stop): Delete, use common version.
-	(simulate): Convert into.
-	(sim_engine_run): This function.
-	(sim_resume): Delete.
-	
-	* interp.c (simulation): New variable - the simulator object.
-	(sim_kind): Delete global - merged into simulation.
-	(sim_load): Cleanup.  Move PC assignment from here.
-	(sim_create_inferior): To here.
-
-	* sim-main.h: New file.
-	* interp.c (sim-main.h): Include.
-	
-Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* tconfig.in (SIM_HAVE_BIENDIAN): Define.
-
-Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
-
-	* gencode.c (build_instruction): DIV instructions: check 
-	for division by zero and integer overflow before using 
-	host's division operation.
-
-Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* Makefile.in (SIM_OBJS): Add sim-load.o.
-	* interp.c: #include bfd.h.
-	(target_byte_order): Delete.
-	(sim_kind, myname, big_endian_p): New static locals.
-	(sim_open): Set sim_kind, myname.  Move call to set_endianness to
-	after argument parsing.  Recognize -E arg, set endianness accordingly.
-	(sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
-	load file into simulator.  Set PC from bfd.
-	(sim_create_inferior): Return SIM_RC.  Delete arg start_address.
-	(set_endianness): Use big_endian_p instead of target_byte_order.
-
-Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
-
-	* interp.c (sim_size): Delete prototype - conflicts with
- 	definition in remote-sim.h.  Correct definition.
-
-Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-	* config.in: Ditto.
-
-Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* interp.c (sim_open): New arg `kind'.
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* interp.c (sim_open): Set optind to 0 before calling getopt.
-
-Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
-
-	* configure: Regenerated to track ../common/aclocal.m4 changes.
-
-Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
-
-	* interp.c : Replace uses of pr_addr with pr_uword64
-	where the bit length is always 64 independent of SIM_ADDR.
-	(pr_uword64) : added.
-
-Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
-
-	* configure: Re-generate.
-
-Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
-
-	* configure: Regenerate to track ../common/aclocal.m4 changes.
-
-Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* interp.c (sim_open): New SIM_DESC result.  Argument is now
-	in argv form.
-	(other sim_*): New SIM_DESC argument.
-
-Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
-
-	* interp.c: Fix printing of addresses for non-64-bit targets.
-	(pr_addr): Add function to print address based on size.
-
-Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
-
-Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (build_mips16_operands): Correct computation of base
-	address for extended PC relative instruction.
-
-Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* interp.c (mips16_entry): Add support for floating point cases.
-	(SignalException): Pass floating point cases to mips16_entry.
-	(ValueFPR): Don't restrict fmt_single and fmt_word to even
-	registers.
-	(StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
-	or fmt_word.
-	(COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
-	and then set the state to fmt_uninterpreted.
-	(COP_SW): Temporarily set the state to fmt_word while calling
-	ValueFPR.
-
-Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (build_instruction): The high order may be set in the
-	comparison flags at any ISA level, not just ISA 4.
-
-Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
-
-	* Makefile.in (@COMMON_MAKEFILE_FRAG): Use
-	COMMON_{PRE,POST}_CONFIG_FRAG instead.
-	* configure.in: sinclude ../common/aclocal.m4.
-	* configure: Regenerated.
-
-Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Rebuild after change to aclocal.m4.
-
-Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* configure configure.in Makefile.in:  Update to new configure
-	scheme which is more compatible with WinGDB builds.
-	* configure.in:  Improve comment on how to run autoconf.
-	* configure:  Re-run autoconf to get new ../common/aclocal.m4.
-	* Makefile.in:  Use autoconf substitution to install common
-	makefile fragment.
-
-Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
-
-	* gencode.c (build_instruction): Use BigEndianCPU instead of
-	ByteSwapMem.
-
-Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c (sim_monitor): Make output to stdout visible in
-	wingdb's I/O log window.
-
-Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
-
-	* support.h: Undo previous change to SIGTRAP
-	and SIGQUIT values.
-
-Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* interp.c (store_word, load_word): New static functions.
-	(mips16_entry): New static function.
-	(SignalException): Look for mips16 entry and exit instructions.
-	(simulate): Use the correct index when setting fpr_state after
-	doing a pending move.
-
-Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c: Fix byte-swapping code throughout to work on
-	both little- and big-endian hosts.
-
-Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
-
-	* support.h: Make definitions of SIGTRAP and SIGQUIT consistent
-	with gdb/config/i386/xm-windows.h.
-
-Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
-
-	* gencode.c (build_instruction): Work around MSVC++ code gen bug
-	that messes up arithmetic shifts.
-
-Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
-	SIGTRAP and SIGQUIT for _WIN32.
-
-Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (build_instruction) [MUL]: Cast operands to word64, to
-	force a 64 bit multiplication.
-	(build_instruction) [OR]: In mips16 mode, don't do anything if the
-	destination register is 0, since that is the default mips16 nop
-	instruction.
-
-Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
-	(build_endian_shift): Don't check proc64.
-	(build_instruction): Always set memval to uword64.  Cast op2 to
-	uword64 when shifting it left in memory instructions.  Always use
-	the same code for stores--don't special case proc64.
-
-	* gencode.c (build_mips16_operands): Fix base PC value for PC
-	relative operands.
-	(build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
-	jal instruction.
-	* interp.c (simJALDELAYSLOT): Define.
- 	(JALDELAYSLOT): Define.
-	(INDELAYSLOT, INJALDELAYSLOT): Define.
-	(simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
-
-Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
-
-	* interp.c (sim_open): add flush_cache as a PMON routine
-	(sim_monitor): handle flush_cache by ignoring it
-
-Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
-
-	* gencode.c (build_instruction): Use !ByteSwapMem instead of
-	BigEndianMem.
-	* interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
-	(BigEndianMem): Rename to ByteSwapMem and change sense.
-	(BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
-	BigEndianMem references to !ByteSwapMem.
-	(set_endianness): New function, with prototype.
-	(sim_open): Call set_endianness.
-	(sim_info): Use simBE instead of BigEndianMem.
-	(xfer_direct_word, xfer_direct_long, swap_direct_word,
-	swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
-	xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
-	ifdefs, keeping the prototype declaration.
-	(swap_word): Rewrite correctly.
-	(ColdReset): Delete references to CONFIG.  Delete endianness related
-	code; moved to set_endianness.
-	
-Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
-
-	* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
-	* interp.c (CHECKHILO): Define away.
-	(simSIGINT): New macro.
-	(membank_size): Increase from 1MB to 2MB.
-	(control_c): New function.
-	(sim_resume): Rename parameter signal to signal_number.  Add local
-	variable prev.  Call signal before and after simulate.
-	(sim_stop_reason): Add simSIGINT support.
-	(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
-	functions always.
-	(sim_warning): Delete call to SignalException.  Do call printf_filtered
-	if logfh is NULL.
-	(AddressTranslation): Add #ifdef DEBUG around debugging message and
-	a call to sim_warning.
-
-Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
-	16 bit instructions.
-
-Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	Add support for mips16 (16 bit MIPS implementation):
-	* gencode.c (inst_type): Add mips16 instruction encoding types.
-	(GETDATASIZEINSN): Define.
-	(MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
-	jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
-	mtlo.
-	(MIPS16_DECODE): New table, for mips16 instructions.
-	(bitmap_val): New static function.
-	(struct mips16_op): Define.
-	(mips16_op_table): New table, for mips16 operands.
-	(build_mips16_operands): New static function.
-	(process_instructions): If PC is odd, decode a mips16
-	instruction.  Break out instruction handling into new
-	build_instruction function.
-	(build_instruction): New static function, broken out of
-	process_instructions.  Check modifiers rather than flags for SHIFT
-	bit count and m[ft]{hi,lo} direction.
-	(usage): Pass program name to fprintf.
-	(main): Remove unused variable this_option_optind.  Change
-	``*loptarg++'' to ``loptarg++''.
-	(my_strtoul): Parenthesize && within ||.
-	* interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
-	(simulate): If PC is odd, fetch a 16 bit instruction, and
-	increment PC by 2 rather than 4.
-	* configure.in: Add case for mips16*-*-*.
-	* configure: Rebuild.
-
-Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c: Allow -t to enable tracing in standalone simulator.
-	Fix garbage output in trace file and error messages.
-
-Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
-
-	* Makefile.in: Delete stuff moved to ../common/Make-common.in.
-	(SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
-	* configure.in: Simplify using macros in ../common/aclocal.m4.
-	* configure: Regenerated.
-	* tconfig.in: New file.
-
-Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
-
-	* interp.c: Fix bugs in 64-bit port.
-	Use ansi function declarations for msvc compiler.
-	Initialize and test file pointer in trace code.
-	Prevent duplicate definition of LAST_EMED_REGNUM.
-
-Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
-
-	* interp.c (xfer_big_long): Prevent unwanted sign extension.
-
-Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (SignalException): Check for explicit terminating
- 	breakpoint value.
-	* gencode.c: Pass instruction value through SignalException()
- 	calls for Trap, Breakpoint and Syscall.
-
-Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
- 	only used on those hosts that provide it.
-	* configure.in: Add sqrt() to list of functions to be checked for.
-	* config.in: Re-generated.
-	* configure: Re-generated.
-
-Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (process_instructions): Call build_endian_shift when
-	expanding STORE RIGHT, to fix swr.
-	* support.h (SIGNEXTEND): If the sign bit is not set, explicitly
-	clear the high bits.
-	* interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
-	Fix float to int conversions to produce signed values.
-
-Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
-	(process_instructions): Correct handling of nor instruction.
-	Correct shift count for 32 bit shift instructions. Correct sign
-	extension for arithmetic shifts to not shift the number of bits in
-	the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
-	unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
-	Fix madd.
-	* interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
-	It's OK to have a mult follow a mult.  What's not OK is to have a
-	mult follow an mfhi.
-	(Convert): Comment out incorrect rounding code.
-
-Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (sim_monitor): Improved monitor printf
- 	simulation. Tidied up simulator warnings, and added "--log" option
- 	for directing warning message output.
-	* gencode.c: Use sim_warning() rather than WARNING macro.
-
-Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
-	getopt1.o, rather than on gencode.c.  Link objects together.
-	Don't link against -liberty.
-	(gencode.o, getopt.o, getopt1.o): New targets.
-	* gencode.c: Include <ctype.h> and "ansidecl.h".
-	(AND): Undefine after including "ansidecl.h".
-	(ULONG_MAX): Define if not defined.
-	(OP_*): Don't define macros; now defined in opcode/mips.h.
-	(main): Call my_strtoul rather than strtoul.
-	(my_strtoul): New static function.
-
-Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
-
-	* gencode.c (process_instructions):  Generate word64 and uword64
-	instead of `long long' and `unsigned long long' data types.
-	* interp.c:  #include sysdep.h to get signals, and define default
-	for SIGBUS.
-	* (Convert):  Work around for Visual-C++ compiler bug with type
-	conversion.
-	* support.h:  Make things compile under Visual-C++ by using
-	__int64 instead of `long long'.  Change many refs to long long
-	into word64/uword64 typedefs.
-
-Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
-
-        * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
-        INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
-        (docdir): Removed.
-        * configure.in (AC_PREREQ): autoconf 2.5 or higher.
-        (AC_PROG_INSTALL): Added.
-	(AC_PROG_CC): Moved to before configure.host call.
-        * configure: Rebuilt.
-	
-Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* configure.in: Define @SIMCONF@ depending on mips target.
-	* configure: Rebuild.
-	* Makefile.in (run): Add @SIMCONF@ to control simulator
- 	construction.
-	* gencode.c: Change LOADDRMASK to 64bit memory model only.
-	* interp.c: Remove some debugging, provide more detailed error
- 	messages, update memory accesses to use LOADDRMASK.
-	
-Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
-	AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
-	stamp-h.
-	* configure: Rebuild.
-	* config.in: New file, generated by autoheader.
-	* interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
-	and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
-	HAVE_ANINT and HAVE_AINT, as appropriate.
-	* Makefile.in (run): Use @LIBS@ rather than -lm.
-	(interp.o): Depend upon config.h.
-	(Makefile): Just rebuild Makefile.
-	(clean): Remove stamp-h.
-	(mostlyclean): Make the same as clean, not as distclean.
-	(config.h, stamp-h): New targets.
-
-Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (ColdReset): Fix boolean test. Make all simulator
- 	globals static.
-
-Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (xfer_direct_word, xfer_direct_long,
-	swap_direct_word, swap_direct_long, xfer_big_word,
-	xfer_big_long, xfer_little_word, xfer_little_long,
-	swap_word,swap_long): Added.
-	* interp.c (ColdReset): Provide function indirection to
- 	host<->simulated_target transfer routines.
-	* interp.c (sim_store_register, sim_fetch_register): Updated to
- 	make use of indirected transfer routines.
-
-Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* gencode.c (process_instructions): Ensure FP ABS instruction
- 	recognised.
-	* interp.c (AbsoluteValue): Add routine. Also provide simple PMON
- 	system call support.
-
-Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (sim_do_command): Complain if callback structure not
- 	initialised.
-
-Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c (Convert): Provide round-to-nearest and round-to-zero
- 	support for Sun hosts.
-	* Makefile.in (gencode): Ensure the host compiler and libraries
- 	used for cross-hosted build.
-
-Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* interp.c, gencode.c: Some more (TODO) tidying.
-
-Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* gencode.c, interp.c: Replaced explicit long long references with
- 	WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
-	* support.h (SET64LO, SET64HI): Macros added.
-
-Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
-
-	* configure: Regenerate with autoconf 2.7.
-
-Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
-
-	* interp.c (LoadMemory): Enclose text following #endif in /* */.
-	* support.h: Remove superfluous "1" from #if.
-	* support.h (CHECKSIM): Remove stray 'a' at end of line.
-
-Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
-
-	* interp.c (StoreFPR): Control UndefinedResult() call on
- 	WARN_RESULT manifest.
-
-Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
-
-	* gencode.c: Tidied instruction decoding, and added FP instruction
- 	support.
-
-	* interp.c: Added dineroIII, and BSD profiling support. Also
- 	run-time FP handling.
-
-Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
-
-	* Changelog, Makefile.in, README.Cygnus, configure, configure.in,
- 	gencode.c, interp.c, support.h: created.
diff --git a/sim/mips/Makefile.in b/sim/mips/Makefile.in
deleted file mode 100644
index 9c3e838..0000000
--- a/sim/mips/Makefile.in
+++ /dev/null
@@ -1,400 +0,0 @@
-#    Makefile template for Configure for the MIPS simulator.
-#    Written by Cygnus Support.
-
-SHELL = @SHELL@
-
-## COMMON_PRE_CONFIG_FRAG
-
-srcdir=@srcdir@
-srcroot=$(srcdir)/../../
-
-# Object files created by various simulator generators.
-
-
-SIM_IGEN_OBJ = \
-	support.o \
-	itable.o \
-	semantics.o \
-	idecode.o \
-	icache.o \
-	@mips_igen_engine@ \
-	irun.o \
-
-
-SIM_M16_OBJ = \
-	m16_support.o \
-	m16_semantics.o \
-	m16_idecode.o \
-	m16_icache.o \
-	\
-	m32_support.o \
-	m32_semantics.o \
-	m32_idecode.o \
-	m32_icache.o \
-	\
-	itable.o \
-	m16run.o \
-
-SIM_MULTI_OBJ = itable.o @sim_multi_obj@
-
-MIPS_EXTRA_OBJS = @mips_extra_objs@
-MIPS_EXTRA_LIBS = @mips_extra_libs@
-
-SIM_OBJS = \
-	$(SIM_@sim_gen@_OBJ) \
-	$(SIM_NEW_COMMON_OBJS) \
-	$(MIPS_EXTRA_OBJS) \
-	cp1.o \
-	interp.o \
-	mdmx.o \
-	dsp.o \
-	sim-main.o \
-	sim-hload.o \
-	sim-engine.o \
-	sim-stop.o \
-	sim-resume.o \
-	sim-reason.o \
-
-
-# List of flags to always pass to $(CC).
-SIM_SUBTARGET=@SIM_SUBTARGET@
-SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
-
-SIM_EXTRA_CLEAN = clean-extra
-SIM_EXTRA_DISTCLEAN = distclean-extra
-
-SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
-
-SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)
-
-# List of main object files for `run'.
-SIM_RUN_OBJS = nrun.o
-
-
-
-## COMMON_POST_CONFIG_FRAG
-
-interp.o: $(srcdir)/interp.c config.h sim-main.h itable.h
-cp1.o: $(srcdir)/cp1.c config.h sim-main.h
-
-mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
-
-dsp.o: $(srcdir)/dsp.c $(srcdir)/sim-main.h
-
-multi-run.o: multi-include.h tmp-mach-multi
-
-../igen/igen:
-	cd ../igen && $(MAKE)
-
-IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
-IGEN_INSN=$(srcdir)/mips.igen
-IGEN_DC=$(srcdir)/mips.dc
-M16_DC=$(srcdir)/m16.dc
-IGEN_INCLUDE=\
-	$(srcdir)/m16.igen \
-	$(srcdir)/mdmx.igen \
-	$(srcdir)/mips3d.igen \
-	$(srcdir)/sb1.igen \
-	$(srcdir)/tx.igen \
-	$(srcdir)/vr.igen \
-	$(srcdir)/dsp.igen \
-
-# NB:	Since these can be built by a number of generators, care
-#	must be taken to ensure that they are only dependant on
-#	one of those generators.
-BUILT_SRC_FROM_GEN = \
-	itable.h \
-	itable.c \
-
-SIM_IGEN_ALL = tmp-igen
-SIM_M16_ALL = tmp-m16
-SIM_MULTI_ALL = tmp-multi
-
-$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
-
-
-
-BUILT_SRC_FROM_IGEN = \
-	icache.h \
-	icache.c \
-	idecode.h \
-	idecode.c \
-	semantics.h \
-	semantics.c \
-	model.h \
-	model.c \
-	support.h \
-	support.c \
-	engine.h \
-	engine.c \
-	irun.c \
-
-$(BUILT_SRC_FROM_IGEN): tmp-igen
-
-tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
-	cd ../igen && $(MAKE)
-	../igen/igen \
-		$(IGEN_TRACE) \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		@sim_igen_flags@ \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-B 32 \
-		-H 31 \
-		-i $(IGEN_INSN) \
-		-o $(IGEN_DC) \
-		-x \
-		-n icache.h    -hc tmp-icache.h \
-		-n icache.c    -c  tmp-icache.c \
-		-n semantics.h -hs tmp-semantics.h \
-		-n semantics.c -s  tmp-semantics.c \
-		-n idecode.h   -hd tmp-idecode.h \
-		-n idecode.c   -d  tmp-idecode.c \
-		-n model.h     -hm tmp-model.h \
-		-n model.c     -m  tmp-model.c \
-		-n support.h   -hf tmp-support.h \
-		-n support.c   -f  tmp-support.c \
-		-n itable.h    -ht tmp-itable.h \
-		-n itable.c    -t  tmp-itable.c \
-		-n engine.h    -he tmp-engine.h \
-		-n engine.c    -e  tmp-engine.c \
-		-n irun.c      -r  tmp-irun.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c
-	touch tmp-igen
-
-semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
-engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
-support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
-idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
-itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
-
-
-
-
-BUILT_SRC_FROM_M16 = \
-	m16_icache.h \
-	m16_icache.c \
-	m16_idecode.h \
-	m16_idecode.c \
-	m16_semantics.h \
-	m16_semantics.c \
-	m16_model.h \
-	m16_model.c \
-	m16_support.h \
-	m16_support.c \
-	\
-	m32_icache.h \
-	m32_icache.c \
-	m32_idecode.h \
-	m32_idecode.c \
-	m32_semantics.h \
-	m32_semantics.c \
-	m32_model.h \
-	m32_model.c \
-	m32_support.h \
-	m32_support.c \
-
-$(BUILT_SRC_FROM_M16): tmp-m16
-
-tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
-	cd ../igen && $(MAKE)
-	../igen/igen \
-		$(IGEN_TRACE) \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		@sim_m16_flags@ \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-B 16 \
-		-H 15 \
-		-i $(IGEN_INSN) \
-		-o $(M16_DC) \
-		-P m16_ \
-		-x \
-		-n m16_icache.h    -hc tmp-icache.h \
-		-n m16_icache.c    -c  tmp-icache.c \
-		-n m16_semantics.h -hs tmp-semantics.h \
-		-n m16_semantics.c -s  tmp-semantics.c \
-		-n m16_idecode.h   -hd tmp-idecode.h \
-		-n m16_idecode.c   -d  tmp-idecode.c \
-		-n m16_model.h     -hm tmp-model.h \
-		-n m16_model.c     -m  tmp-model.c \
-		-n m16_support.h   -hf tmp-support.h \
-		-n m16_support.c   -f  tmp-support.c \
-		#
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m16_model.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m16_model.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m16_support.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m16_support.c
-	../igen/igen \
-		$(IGEN_TRACE) \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		@sim_igen_flags@ \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-B 32 \
-		-H 31 \
-		-i $(IGEN_INSN) \
-		-o $(IGEN_DC) \
-		-P m32_ \
-		-x \
-		-n m32_icache.h    -hc tmp-icache.h \
-		-n m32_icache.c    -c  tmp-icache.c \
-		-n m32_semantics.h -hs tmp-semantics.h \
-		-n m32_semantics.c -s  tmp-semantics.c \
-		-n m32_idecode.h   -hd tmp-idecode.h \
-		-n m32_idecode.c   -d  tmp-idecode.c \
-		-n m32_model.h     -hm tmp-model.h \
-		-n m32_model.c     -m  tmp-model.c \
-		-n m32_support.h   -hf tmp-support.h \
-		-n m32_support.c   -f  tmp-support.c \
-		#
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.h m32_model.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-model.c m32_model.c
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.h m32_support.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-support.c m32_support.c
-	../igen/igen \
-		$(IGEN_TRACE) \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		-Wnowidth \
-		@sim_igen_flags@ @sim_m16_flags@ \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-i $(IGEN_INSN) \
-		-n itable.h    -ht tmp-itable.h \
-		-n itable.c    -t  tmp-itable.c \
-		#
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
-	touch tmp-m16
-
-
-BUILT_SRC_FROM_MULTI = @sim_multi_src@
-SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
-
-$(BUILT_SRC_FROM_MULTI): tmp-multi
-tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
-tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
-	for t in $(SIM_MULTI_IGEN_CONFIGS); do \
-	  p=`echo $${t} | sed -e 's/:.*//'` ; \
-	  m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
-	  f=`echo $${t} | sed -e 's/.*://'` ; \
-	  case $${p} in \
-	    m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
-	    *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
-	  esac; \
-	  ../igen/igen \
-		$(IGEN_TRACE) \
-		$${e} \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		-N 0 \
-		-M $${m} \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-i $(IGEN_INSN) \
-		-P $${p}_ \
-		-x \
-		-n $${p}_icache.h    -hc tmp-icache.h \
-		-n $${p}_icache.c    -c  tmp-icache.c \
-		-n $${p}_semantics.h -hs tmp-semantics.h \
-		-n $${p}_semantics.c -s  tmp-semantics.c \
-		-n $${p}_idecode.h   -hd tmp-idecode.h \
-		-n $${p}_idecode.c   -d  tmp-idecode.c \
-		-n $${p}_model.h     -hm tmp-model.h \
-		-n $${p}_model.c     -m  tmp-model.c \
-		-n $${p}_support.h   -hf tmp-support.h \
-		-n $${p}_support.c   -f  tmp-support.c \
-		-n $${p}_engine.h    -he tmp-engine.h \
-		-n $${p}_engine.c    -e  tmp-engine.c \
-		; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
-	  $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
-	done
-	touch tmp-mach-multi
-tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
-	../igen/igen \
-		$(IGEN_TRACE) \
-		-I $(srcdir) \
-		-Werror \
-		-Wnodiscard \
-		-Wnowidth \
-		-N 0 \
-		@sim_multi_flags@ \
-		-G gen-direct-access \
-		-G gen-zero-r0 \
-		-i $(IGEN_INSN) \
-		-n itable.h    -ht tmp-itable.h \
-		-n itable.c    -t  tmp-itable.c \
-		#
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h
-	$(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c
-	touch tmp-itable-multi
-tmp-run-multi: $(srcdir)/m16run.c
-	for t in $(SIM_MULTI_IGEN_CONFIGS); do \
-	  case $${t} in \
-	    m16*) \
-	      m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
-	      sed <  $(srcdir)/m16run.c > tmp-run \
-		    -e "s/^sim_/m16$${m}_/" \
-		    -e "s/m16_/m16$${m}_/" \
-		    -e "s/m32_/m32$${m}_/" ; \
-	      $(SHELL) $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
-	  esac \
-	done
-	touch tmp-run-multi
-
-clean-extra:
-	rm -f $(BUILT_SRC_FROM_GEN)
-	rm -f $(BUILT_SRC_FROM_IGEN)
-	rm -f $(BUILT_SRC_FROM_M16)
-	rm -f $(BUILT_SRC_FROM_MULTI)
-	rm -f tmp-*
-	rm -f m16*.o m32*.o itable*.o
-
-distclean-extra:
-	rm -f multi-include.h multi-run.c
diff --git a/sim/mips/acconfig.h b/sim/mips/acconfig.h
deleted file mode 100644
index f9b87a1..0000000
--- a/sim/mips/acconfig.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
-#undef HAVE_CATGETS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
diff --git a/sim/mips/config.in b/sim/mips/config.in
deleted file mode 100644
index dbd6508..0000000
--- a/sim/mips/config.in
+++ /dev/null
@@ -1,174 +0,0 @@
-/* config.in.  Generated automatically from configure.in by autoheader.  */
-
-/* Define if using alloca.c.  */
-#undef C_ALLOCA
-
-/* Define to empty if the keyword does not work.  */
-#undef const
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define if you have a working `mmap' system call.  */
-#undef HAVE_MMAP
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#undef inline
-
-/* Define to `long' if <sys/types.h> doesn't define.  */
-#undef off_t
-
-/* Define if you need to in order for stat and other things to work.  */
-#undef _POSIX_SOURCE
-
-/* Define as the return type of signal handlers (int or void).  */
-#undef RETSIGTYPE
-
-/* Define to `unsigned' if <sys/types.h> doesn't define.  */
-#undef size_t
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#undef STACK_DIRECTION
-
-/* Define if you have the ANSI C header files.  */
-#undef STDC_HEADERS
-
-/* Define if your processor stores words with the most significant
-   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
-#undef WORDS_BIGENDIAN
-
-/* Define to 1 if NLS is requested.  */
-#undef ENABLE_NLS
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
-#undef HAVE_GETTEXT
-
-/* Define as 1 if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if your locale.h file contains LC_MESSAGES.  */
-#undef HAVE_LC_MESSAGES
-
-/* Define if you have the __argz_count function.  */
-#undef HAVE___ARGZ_COUNT
-
-/* Define if you have the __argz_next function.  */
-#undef HAVE___ARGZ_NEXT
-
-/* Define if you have the __argz_stringify function.  */
-#undef HAVE___ARGZ_STRINGIFY
-
-/* Define if you have the __setfpucw function.  */
-#undef HAVE___SETFPUCW
-
-/* Define if you have the aint function.  */
-#undef HAVE_AINT
-
-/* Define if you have the anint function.  */
-#undef HAVE_ANINT
-
-/* Define if you have the dcgettext function.  */
-#undef HAVE_DCGETTEXT
-
-/* Define if you have the getcwd function.  */
-#undef HAVE_GETCWD
-
-/* Define if you have the getpagesize function.  */
-#undef HAVE_GETPAGESIZE
-
-/* Define if you have the getrusage function.  */
-#undef HAVE_GETRUSAGE
-
-/* Define if you have the munmap function.  */
-#undef HAVE_MUNMAP
-
-/* Define if you have the putenv function.  */
-#undef HAVE_PUTENV
-
-/* Define if you have the setenv function.  */
-#undef HAVE_SETENV
-
-/* Define if you have the setlocale function.  */
-#undef HAVE_SETLOCALE
-
-/* Define if you have the sigaction function.  */
-#undef HAVE_SIGACTION
-
-/* Define if you have the sqrt function.  */
-#undef HAVE_SQRT
-
-/* Define if you have the stpcpy function.  */
-#undef HAVE_STPCPY
-
-/* Define if you have the strcasecmp function.  */
-#undef HAVE_STRCASECMP
-
-/* Define if you have the strchr function.  */
-#undef HAVE_STRCHR
-
-/* Define if you have the time function.  */
-#undef HAVE_TIME
-
-/* Define if you have the <argz.h> header file.  */
-#undef HAVE_ARGZ_H
-
-/* Define if you have the <fcntl.h> header file.  */
-#undef HAVE_FCNTL_H
-
-/* Define if you have the <fpu_control.h> header file.  */
-#undef HAVE_FPU_CONTROL_H
-
-/* Define if you have the <limits.h> header file.  */
-#undef HAVE_LIMITS_H
-
-/* Define if you have the <locale.h> header file.  */
-#undef HAVE_LOCALE_H
-
-/* Define if you have the <malloc.h> header file.  */
-#undef HAVE_MALLOC_H
-
-/* Define if you have the <nl_types.h> header file.  */
-#undef HAVE_NL_TYPES_H
-
-/* Define if you have the <stdlib.h> header file.  */
-#undef HAVE_STDLIB_H
-
-/* Define if you have the <string.h> header file.  */
-#undef HAVE_STRING_H
-
-/* Define if you have the <strings.h> header file.  */
-#undef HAVE_STRINGS_H
-
-/* Define if you have the <sys/param.h> header file.  */
-#undef HAVE_SYS_PARAM_H
-
-/* Define if you have the <sys/resource.h> header file.  */
-#undef HAVE_SYS_RESOURCE_H
-
-/* Define if you have the <sys/time.h> header file.  */
-#undef HAVE_SYS_TIME_H
-
-/* Define if you have the <time.h> header file.  */
-#undef HAVE_TIME_H
-
-/* Define if you have the <unistd.h> header file.  */
-#undef HAVE_UNISTD_H
-
-/* Define if you have the <values.h> header file.  */
-#undef HAVE_VALUES_H
-
-/* Define if you have the m library (-lm).  */
-#undef HAVE_LIBM
diff --git a/sim/mips/configure b/sim/mips/configure
deleted file mode 100755
index 5185b89..0000000
--- a/sim/mips/configure
+++ /dev/null
@@ -1,7535 +0,0 @@
-#! /bin/sh
-# Guess values for system-dependent variables and create Makefiles.
-# Generated by GNU Autoconf 2.59.
-#
-# Copyright (C) 2003 Free Software Foundation, Inc.
-# This configure script is free software; the Free Software Foundation
-# gives unlimited permission to copy, distribute and modify it.
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
-	 /*)
-	   if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-	     $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-	     CONFIG_SHELL=$as_dir/$as_base
-	     export CONFIG_SHELL
-	     exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-	   fi;;
-	 esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
-  # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
-    ' >$as_me.lineno &&
-  chmod +x $as_me.lineno ||
-    { echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
-   { (exit 1); exit 1; }; }
-
-  # Don't try to exec as it changes $[0], causing all sort of problems
-  # (the dirname of $[0] is not the place where we might find the
-  # original and so on.  Autoconf is especially sensible to this).
-  . ./$as_me.lineno
-  # Exit status is that of the last command.
-  exit
-}
-
-
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
-  *c*,-n*) ECHO_N= ECHO_C='
-' ECHO_T='	' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
-esac
-
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-rm -f conf$$ conf$$.exe conf$$.file
-echo >conf$$.file
-if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
-    as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
-elif ln conf$$.file conf$$ 2>/dev/null; then
-  as_ln_s=ln
-else
-  as_ln_s='cp -p'
-fi
-rm -f conf$$ conf$$.exe conf$$.file
-
-if mkdir -p . 2>/dev/null; then
-  as_mkdir_p=:
-else
-  test -d ./-p && rmdir ./-p
-  as_mkdir_p=false
-fi
-
-as_executable_p="test -f"
-
-# Sed expression to map a string onto a valid CPP name.
-as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
-
-# Sed expression to map a string onto a valid variable name.
-as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
-
-
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS=" 	$as_nl"
-
-# CDPATH.
-$as_unset CDPATH
-
-
-# Name of the host.
-# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
-# so uname gets run too.
-ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
-
-exec 6>&1
-
-#
-# Initializations.
-#
-ac_default_prefix=/usr/local
-ac_config_libobj_dir=.
-cross_compiling=no
-subdirs=
-MFLAGS=
-MAKEFLAGS=
-SHELL=${CONFIG_SHELL-/bin/sh}
-
-# Maximum number of lines to put in a shell here document.
-# This variable seems obsolete.  It should probably be removed, and
-# only ac_max_sed_lines should be used.
-: ${ac_max_here_lines=38}
-
-# Identity of this package.
-PACKAGE_NAME=
-PACKAGE_TARNAME=
-PACKAGE_VERSION=
-PACKAGE_STRING=
-PACKAGE_BUGREPORT=
-
-ac_unique_file="Makefile.in"
-# Factoring default headers for most tests.
-ac_includes_default="\
-#include <stdio.h>
-#if HAVE_SYS_TYPES_H
-# include <sys/types.h>
-#endif
-#if HAVE_SYS_STAT_H
-# include <sys/stat.h>
-#endif
-#if STDC_HEADERS
-# include <stdlib.h>
-# include <stddef.h>
-#else
-# if HAVE_STDLIB_H
-#  include <stdlib.h>
-# endif
-#endif
-#if HAVE_STRING_H
-# if !STDC_HEADERS && HAVE_MEMORY_H
-#  include <memory.h>
-# endif
-# include <string.h>
-#endif
-#if HAVE_STRINGS_H
-# include <strings.h>
-#endif
-#if HAVE_INTTYPES_H
-# include <inttypes.h>
-#else
-# if HAVE_STDINT_H
-#  include <stdint.h>
-# endif
-#endif
-#if HAVE_UNISTD_H
-# include <unistd.h>
-#endif"
-
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS sim_environment sim_alignment sim_assert sim_bitsize sim_endian sim_hostendian sim_float sim_scache sim_default_model sim_hw_cflags sim_hw_objs sim_hw sim_inline sim_packages sim_regparm sim_reserved_bits sim_smp sim_stdcall sim_xor_endian WARN_CFLAGS WERROR_CFLAGS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CC_FOR_BUILD HDEFINES AR RANLIB ac_ct_RANLIB USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT CPP EGREP MAINT sim_bswap sim_cflags sim_debug sim_stdio sim_trace sim_profile SIM_SUBTARGET sim_igen_flags sim_m16_flags sim_gen sim_multi_flags sim_multi_igen_configs sim_multi_src sim_multi_obj mips_extra_objs mips_igen_engine mips_extra_libs cgen_breaks LIBOBJS LTLIBOBJS'
-ac_subst_files=''
-
-# Initialize some variables set by options.
-ac_init_help=
-ac_init_version=false
-# The variables have the same names as the options, with
-# dashes changed to underlines.
-cache_file=/dev/null
-exec_prefix=NONE
-no_create=
-no_recursion=
-prefix=NONE
-program_prefix=NONE
-program_suffix=NONE
-program_transform_name=s,x,x,
-silent=
-site=
-srcdir=
-verbose=
-x_includes=NONE
-x_libraries=NONE
-
-# Installation directory options.
-# These are left unexpanded so users can "make install exec_prefix=/foo"
-# and all the variables that are supposed to be based on exec_prefix
-# by default will actually change.
-# Use braces instead of parens because sh, perl, etc. also accept them.
-bindir='${exec_prefix}/bin'
-sbindir='${exec_prefix}/sbin'
-libexecdir='${exec_prefix}/libexec'
-datadir='${prefix}/share'
-sysconfdir='${prefix}/etc'
-sharedstatedir='${prefix}/com'
-localstatedir='${prefix}/var'
-libdir='${exec_prefix}/lib'
-includedir='${prefix}/include'
-oldincludedir='/usr/include'
-infodir='${prefix}/info'
-mandir='${prefix}/man'
-
-ac_prev=
-for ac_option
-do
-  # If the previous option needs an argument, assign it.
-  if test -n "$ac_prev"; then
-    eval "$ac_prev=\$ac_option"
-    ac_prev=
-    continue
-  fi
-
-  ac_optarg=`expr "x$ac_option" : 'x[^=]*=\(.*\)'`
-
-  # Accept the important Cygnus configure options, so we can diagnose typos.
-
-  case $ac_option in
-
-  -bindir | --bindir | --bindi | --bind | --bin | --bi)
-    ac_prev=bindir ;;
-  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
-    bindir=$ac_optarg ;;
-
-  -build | --build | --buil | --bui | --bu)
-    ac_prev=build_alias ;;
-  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
-    build_alias=$ac_optarg ;;
-
-  -cache-file | --cache-file | --cache-fil | --cache-fi \
-  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
-    ac_prev=cache_file ;;
-  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
-  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
-    cache_file=$ac_optarg ;;
-
-  --config-cache | -C)
-    cache_file=config.cache ;;
-
-  -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
-    ac_prev=datadir ;;
-  -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
-  | --da=*)
-    datadir=$ac_optarg ;;
-
-  -disable-* | --disable-*)
-    ac_feature=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid feature name: $ac_feature" >&2
-   { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    eval "enable_$ac_feature=no" ;;
-
-  -enable-* | --enable-*)
-    ac_feature=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid feature name: $ac_feature" >&2
-   { (exit 1); exit 1; }; }
-    ac_feature=`echo $ac_feature | sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "enable_$ac_feature='$ac_optarg'" ;;
-
-  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
-  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
-  | --exec | --exe | --ex)
-    ac_prev=exec_prefix ;;
-  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
-  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
-  | --exec=* | --exe=* | --ex=*)
-    exec_prefix=$ac_optarg ;;
-
-  -gas | --gas | --ga | --g)
-    # Obsolete; use --with-gas.
-    with_gas=yes ;;
-
-  -help | --help | --hel | --he | -h)
-    ac_init_help=long ;;
-  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
-    ac_init_help=recursive ;;
-  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
-    ac_init_help=short ;;
-
-  -host | --host | --hos | --ho)
-    ac_prev=host_alias ;;
-  -host=* | --host=* | --hos=* | --ho=*)
-    host_alias=$ac_optarg ;;
-
-  -includedir | --includedir | --includedi | --included | --include \
-  | --includ | --inclu | --incl | --inc)
-    ac_prev=includedir ;;
-  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
-  | --includ=* | --inclu=* | --incl=* | --inc=*)
-    includedir=$ac_optarg ;;
-
-  -infodir | --infodir | --infodi | --infod | --info | --inf)
-    ac_prev=infodir ;;
-  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
-    infodir=$ac_optarg ;;
-
-  -libdir | --libdir | --libdi | --libd)
-    ac_prev=libdir ;;
-  -libdir=* | --libdir=* | --libdi=* | --libd=*)
-    libdir=$ac_optarg ;;
-
-  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
-  | --libexe | --libex | --libe)
-    ac_prev=libexecdir ;;
-  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
-  | --libexe=* | --libex=* | --libe=*)
-    libexecdir=$ac_optarg ;;
-
-  -localstatedir | --localstatedir | --localstatedi | --localstated \
-  | --localstate | --localstat | --localsta | --localst \
-  | --locals | --local | --loca | --loc | --lo)
-    ac_prev=localstatedir ;;
-  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
-  | --localstate=* | --localstat=* | --localsta=* | --localst=* \
-  | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
-    localstatedir=$ac_optarg ;;
-
-  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
-    ac_prev=mandir ;;
-  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
-    mandir=$ac_optarg ;;
-
-  -nfp | --nfp | --nf)
-    # Obsolete; use --without-fp.
-    with_fp=no ;;
-
-  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
-  | --no-cr | --no-c | -n)
-    no_create=yes ;;
-
-  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
-  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
-    no_recursion=yes ;;
-
-  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
-  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
-  | --oldin | --oldi | --old | --ol | --o)
-    ac_prev=oldincludedir ;;
-  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
-  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
-  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
-    oldincludedir=$ac_optarg ;;
-
-  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
-    ac_prev=prefix ;;
-  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
-    prefix=$ac_optarg ;;
-
-  -program-prefix | --program-prefix | --program-prefi | --program-pref \
-  | --program-pre | --program-pr | --program-p)
-    ac_prev=program_prefix ;;
-  -program-prefix=* | --program-prefix=* | --program-prefi=* \
-  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
-    program_prefix=$ac_optarg ;;
-
-  -program-suffix | --program-suffix | --program-suffi | --program-suff \
-  | --program-suf | --program-su | --program-s)
-    ac_prev=program_suffix ;;
-  -program-suffix=* | --program-suffix=* | --program-suffi=* \
-  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
-    program_suffix=$ac_optarg ;;
-
-  -program-transform-name | --program-transform-name \
-  | --program-transform-nam | --program-transform-na \
-  | --program-transform-n | --program-transform- \
-  | --program-transform | --program-transfor \
-  | --program-transfo | --program-transf \
-  | --program-trans | --program-tran \
-  | --progr-tra | --program-tr | --program-t)
-    ac_prev=program_transform_name ;;
-  -program-transform-name=* | --program-transform-name=* \
-  | --program-transform-nam=* | --program-transform-na=* \
-  | --program-transform-n=* | --program-transform-=* \
-  | --program-transform=* | --program-transfor=* \
-  | --program-transfo=* | --program-transf=* \
-  | --program-trans=* | --program-tran=* \
-  | --progr-tra=* | --program-tr=* | --program-t=*)
-    program_transform_name=$ac_optarg ;;
-
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-  | -silent | --silent | --silen | --sile | --sil)
-    silent=yes ;;
-
-  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
-    ac_prev=sbindir ;;
-  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
-  | --sbi=* | --sb=*)
-    sbindir=$ac_optarg ;;
-
-  -sharedstatedir | --sharedstatedir | --sharedstatedi \
-  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
-  | --sharedst | --shareds | --shared | --share | --shar \
-  | --sha | --sh)
-    ac_prev=sharedstatedir ;;
-  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
-  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
-  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
-  | --sha=* | --sh=*)
-    sharedstatedir=$ac_optarg ;;
-
-  -site | --site | --sit)
-    ac_prev=site ;;
-  -site=* | --site=* | --sit=*)
-    site=$ac_optarg ;;
-
-  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
-    ac_prev=srcdir ;;
-  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
-    srcdir=$ac_optarg ;;
-
-  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
-  | --syscon | --sysco | --sysc | --sys | --sy)
-    ac_prev=sysconfdir ;;
-  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
-  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
-    sysconfdir=$ac_optarg ;;
-
-  -target | --target | --targe | --targ | --tar | --ta | --t)
-    ac_prev=target_alias ;;
-  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
-    target_alias=$ac_optarg ;;
-
-  -v | -verbose | --verbose | --verbos | --verbo | --verb)
-    verbose=yes ;;
-
-  -version | --version | --versio | --versi | --vers | -V)
-    ac_init_version=: ;;
-
-  -with-* | --with-*)
-    ac_package=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid package name: $ac_package" >&2
-   { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package| sed 's/-/_/g'`
-    case $ac_option in
-      *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
-      *) ac_optarg=yes ;;
-    esac
-    eval "with_$ac_package='$ac_optarg'" ;;
-
-  -without-* | --without-*)
-    ac_package=`expr "x$ac_option" : 'x-*without-\(.*\)'`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid package name: $ac_package" >&2
-   { (exit 1); exit 1; }; }
-    ac_package=`echo $ac_package | sed 's/-/_/g'`
-    eval "with_$ac_package=no" ;;
-
-  --x)
-    # Obsolete; use --with-x.
-    with_x=yes ;;
-
-  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
-  | --x-incl | --x-inc | --x-in | --x-i)
-    ac_prev=x_includes ;;
-  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
-  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
-    x_includes=$ac_optarg ;;
-
-  -x-libraries | --x-libraries | --x-librarie | --x-librari \
-  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
-    ac_prev=x_libraries ;;
-  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
-  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
-    x_libraries=$ac_optarg ;;
-
-  -*) { echo "$as_me: error: unrecognized option: $ac_option
-Try \`$0 --help' for more information." >&2
-   { (exit 1); exit 1; }; }
-    ;;
-
-  *=*)
-    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
-    # Reject names that are not valid shell variable names.
-    expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
-      { echo "$as_me: error: invalid variable name: $ac_envvar" >&2
-   { (exit 1); exit 1; }; }
-    ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`
-    eval "$ac_envvar='$ac_optarg'"
-    export $ac_envvar ;;
-
-  *)
-    # FIXME: should be removed in autoconf 3.0.
-    echo "$as_me: WARNING: you should use --build, --host, --target" >&2
-    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
-      echo "$as_me: WARNING: invalid host type: $ac_option" >&2
-    : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}
-    ;;
-
-  esac
-done
-
-if test -n "$ac_prev"; then
-  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
-  { echo "$as_me: error: missing argument to $ac_option" >&2
-   { (exit 1); exit 1; }; }
-fi
-
-# Be sure to have absolute paths.
-for ac_var in exec_prefix prefix
-do
-  eval ac_val=$`echo $ac_var`
-  case $ac_val in
-    [\\/$]* | ?:[\\/]* | NONE | '' ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# Be sure to have absolute paths.
-for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \
-	      localstatedir libdir includedir oldincludedir infodir mandir
-do
-  eval ac_val=$`echo $ac_var`
-  case $ac_val in
-    [\\/$]* | ?:[\\/]* ) ;;
-    *)  { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# There might be people who depend on the old broken behavior: `$host'
-# used to hold the argument of --host etc.
-# FIXME: To remove some day.
-build=$build_alias
-host=$host_alias
-target=$target_alias
-
-# FIXME: To remove some day.
-if test "x$host_alias" != x; then
-  if test "x$build_alias" = x; then
-    cross_compiling=maybe
-    echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
-    If a cross compiler is detected then cross compile mode will be used." >&2
-  elif test "x$build_alias" != "x$host_alias"; then
-    cross_compiling=yes
-  fi
-fi
-
-ac_tool_prefix=
-test -n "$host_alias" && ac_tool_prefix=$host_alias-
-
-test "$silent" = yes && exec 6>/dev/null
-
-
-# Find the source files, if location was not specified.
-if test -z "$srcdir"; then
-  ac_srcdir_defaulted=yes
-  # Try the directory containing this script, then its parent.
-  ac_confdir=`(dirname "$0") 2>/dev/null ||
-$as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$0" : 'X\(//\)[^/]' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$0" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  srcdir=$ac_confdir
-  if test ! -r $srcdir/$ac_unique_file; then
-    srcdir=..
-  fi
-else
-  ac_srcdir_defaulted=no
-fi
-if test ! -r $srcdir/$ac_unique_file; then
-  if test "$ac_srcdir_defaulted" = yes; then
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2
-   { (exit 1); exit 1; }; }
-  else
-    { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
-   { (exit 1); exit 1; }; }
-  fi
-fi
-(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null ||
-  { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2
-   { (exit 1); exit 1; }; }
-srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'`
-ac_env_build_alias_set=${build_alias+set}
-ac_env_build_alias_value=$build_alias
-ac_cv_env_build_alias_set=${build_alias+set}
-ac_cv_env_build_alias_value=$build_alias
-ac_env_host_alias_set=${host_alias+set}
-ac_env_host_alias_value=$host_alias
-ac_cv_env_host_alias_set=${host_alias+set}
-ac_cv_env_host_alias_value=$host_alias
-ac_env_target_alias_set=${target_alias+set}
-ac_env_target_alias_value=$target_alias
-ac_cv_env_target_alias_set=${target_alias+set}
-ac_cv_env_target_alias_value=$target_alias
-ac_env_CC_set=${CC+set}
-ac_env_CC_value=$CC
-ac_cv_env_CC_set=${CC+set}
-ac_cv_env_CC_value=$CC
-ac_env_CFLAGS_set=${CFLAGS+set}
-ac_env_CFLAGS_value=$CFLAGS
-ac_cv_env_CFLAGS_set=${CFLAGS+set}
-ac_cv_env_CFLAGS_value=$CFLAGS
-ac_env_LDFLAGS_set=${LDFLAGS+set}
-ac_env_LDFLAGS_value=$LDFLAGS
-ac_cv_env_LDFLAGS_set=${LDFLAGS+set}
-ac_cv_env_LDFLAGS_value=$LDFLAGS
-ac_env_CPPFLAGS_set=${CPPFLAGS+set}
-ac_env_CPPFLAGS_value=$CPPFLAGS
-ac_cv_env_CPPFLAGS_set=${CPPFLAGS+set}
-ac_cv_env_CPPFLAGS_value=$CPPFLAGS
-ac_env_CPP_set=${CPP+set}
-ac_env_CPP_value=$CPP
-ac_cv_env_CPP_set=${CPP+set}
-ac_cv_env_CPP_value=$CPP
-
-#
-# Report the --help message.
-#
-if test "$ac_init_help" = "long"; then
-  # Omit some internal or obsolete options to make the list less imposing.
-  # This message is too long to be a string in the A/UX 3.1 sh.
-  cat <<_ACEOF
-\`configure' configures this package to adapt to many kinds of systems.
-
-Usage: $0 [OPTION]... [VAR=VALUE]...
-
-To assign environment variables (e.g., CC, CFLAGS...), specify them as
-VAR=VALUE.  See below for descriptions of some of the useful variables.
-
-Defaults for the options are specified in brackets.
-
-Configuration:
-  -h, --help              display this help and exit
-      --help=short        display options specific to this package
-      --help=recursive    display the short help of all the included packages
-  -V, --version           display version information and exit
-  -q, --quiet, --silent   do not print \`checking...' messages
-      --cache-file=FILE   cache test results in FILE [disabled]
-  -C, --config-cache      alias for \`--cache-file=config.cache'
-  -n, --no-create         do not create output files
-      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
-
-_ACEOF
-
-  cat <<_ACEOF
-Installation directories:
-  --prefix=PREFIX         install architecture-independent files in PREFIX
-			  [$ac_default_prefix]
-  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
-			  [PREFIX]
-
-By default, \`make install' will install all the files in
-\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
-an installation prefix other than \`$ac_default_prefix' using \`--prefix',
-for instance \`--prefix=\$HOME'.
-
-For better control, use the options below.
-
-Fine tuning of the installation directories:
-  --bindir=DIR           user executables [EPREFIX/bin]
-  --sbindir=DIR          system admin executables [EPREFIX/sbin]
-  --libexecdir=DIR       program executables [EPREFIX/libexec]
-  --datadir=DIR          read-only architecture-independent data [PREFIX/share]
-  --sysconfdir=DIR       read-only single-machine data [PREFIX/etc]
-  --sharedstatedir=DIR   modifiable architecture-independent data [PREFIX/com]
-  --localstatedir=DIR    modifiable single-machine data [PREFIX/var]
-  --libdir=DIR           object code libraries [EPREFIX/lib]
-  --includedir=DIR       C header files [PREFIX/include]
-  --oldincludedir=DIR    C header files for non-gcc [/usr/include]
-  --infodir=DIR          info documentation [PREFIX/info]
-  --mandir=DIR           man documentation [PREFIX/man]
-_ACEOF
-
-  cat <<\_ACEOF
-
-Program names:
-  --program-prefix=PREFIX            prepend PREFIX to installed program names
-  --program-suffix=SUFFIX            append SUFFIX to installed program names
-  --program-transform-name=PROGRAM   run sed PROGRAM on installed program names
-
-X features:
-  --x-includes=DIR    X include files are in DIR
-  --x-libraries=DIR   X library files are in DIR
-
-System types:
-  --build=BUILD     configure for building on BUILD [guessed]
-  --host=HOST       cross-compile to build programs to run on HOST [BUILD]
-  --target=TARGET   configure for building compilers for TARGET [HOST]
-_ACEOF
-fi
-
-if test -n "$ac_init_help"; then
-
-  cat <<\_ACEOF
-
-Optional Features:
-  --disable-FEATURE       do not include FEATURE (same as --enable-FEATURE=no)
-  --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
-  --enable-maintainer-mode		Enable developer functionality.
-  --enable-sim-bswap			Use Host specific BSWAP instruction.
-  --enable-sim-cflags=opts		Extra CFLAGS for use in building simulator
-  --enable-sim-debug=opts		Enable debugging flags
-  --enable-sim-stdio			Specify whether to use stdio for console input/output.
-  --enable-sim-trace=opts		Enable tracing flags
-  --enable-sim-profile=opts		Enable profiling flags
-  --enable-sim-inline=inlines		Specify which functions should be inlined.
-  --enable-sim-alignment=align		Specify strict,  nonstrict or forced alignment of memory accesses.
-  --enable-sim-hostendian=end		Specify host byte endian orientation.
-  --enable-build-warnings Enable build-time compiler warnings if gcc is used
-  --enable-gdb-build-warnings Enable SIM specific build-time compiler warnings if gcc is used
-  --enable-sim-reserved-bits		Specify whether to check reserved bits in instruction.
-  --enable-sim-endian=endian		Specify target byte endian orientation.
-  --enable-sim-bitsize=N		Specify target bitsize (32 or 64).
-  --enable-sim-float			Specify that the target processor has floating point hardware.
-  --enable-sim-smp=n			Specify number of processors to configure for (default ${default_sim_smp}).
-  --enable-sim-hardware=LIST		Specify the hardware to be included in the build.
-
-Optional Packages:
-  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
-  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
-  --with-x                use the X Window System
-
-Some influential environment variables:
-  CC          C compiler command
-  CFLAGS      C compiler flags
-  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
-              nonstandard directory <lib dir>
-  CPPFLAGS    C/C++ preprocessor flags, e.g. -I<include dir> if you have
-              headers in a nonstandard directory <include dir>
-  CPP         C preprocessor
-
-Use these variables to override the choices made by `configure' or to help
-it to find libraries and programs with nonstandard names/locations.
-
-_ACEOF
-fi
-
-if test "$ac_init_help" = "recursive"; then
-  # If there are subdirs, report their specific --help.
-  ac_popdir=`pwd`
-  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
-    test -d $ac_dir || continue
-    ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-    cd $ac_dir
-    # Check for guested configure; otherwise get Cygnus style configure.
-    if test -f $ac_srcdir/configure.gnu; then
-      echo
-      $SHELL $ac_srcdir/configure.gnu  --help=recursive
-    elif test -f $ac_srcdir/configure; then
-      echo
-      $SHELL $ac_srcdir/configure  --help=recursive
-    elif test -f $ac_srcdir/configure.ac ||
-	   test -f $ac_srcdir/configure.in; then
-      echo
-      $ac_configure --help
-    else
-      echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
-    fi
-    cd $ac_popdir
-  done
-fi
-
-test -n "$ac_init_help" && exit 0
-if $ac_init_version; then
-  cat <<\_ACEOF
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This configure script is free software; the Free Software Foundation
-gives unlimited permission to copy, distribute and modify it.
-_ACEOF
-  exit 0
-fi
-exec 5>config.log
-cat >&5 <<_ACEOF
-This file contains any messages produced by compilers while
-running configure, to aid debugging if configure makes a mistake.
-
-It was created by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
-
-  $ $0 $@
-
-_ACEOF
-{
-cat <<_ASUNAME
-## --------- ##
-## Platform. ##
-## --------- ##
-
-hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
-uname -m = `(uname -m) 2>/dev/null || echo unknown`
-uname -r = `(uname -r) 2>/dev/null || echo unknown`
-uname -s = `(uname -s) 2>/dev/null || echo unknown`
-uname -v = `(uname -v) 2>/dev/null || echo unknown`
-
-/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
-/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
-
-/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
-/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
-/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
-hostinfo               = `(hostinfo) 2>/dev/null               || echo unknown`
-/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
-/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
-/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
-
-_ASUNAME
-
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  echo "PATH: $as_dir"
-done
-
-} >&5
-
-cat >&5 <<_ACEOF
-
-
-## ----------- ##
-## Core tests. ##
-## ----------- ##
-
-_ACEOF
-
-
-# Keep a trace of the command line.
-# Strip out --no-create and --no-recursion so they do not pile up.
-# Strip out --silent because we don't want to record it for future runs.
-# Also quote any args containing shell meta-characters.
-# Make two passes to allow for proper duplicate-argument suppression.
-ac_configure_args=
-ac_configure_args0=
-ac_configure_args1=
-ac_sep=
-ac_must_keep_next=false
-for ac_pass in 1 2
-do
-  for ac_arg
-  do
-    case $ac_arg in
-    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
-    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-    | -silent | --silent | --silen | --sile | --sil)
-      continue ;;
-    *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=`echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
-    esac
-    case $ac_pass in
-    1) ac_configure_args0="$ac_configure_args0 '$ac_arg'" ;;
-    2)
-      ac_configure_args1="$ac_configure_args1 '$ac_arg'"
-      if test $ac_must_keep_next = true; then
-	ac_must_keep_next=false # Got value, back to normal.
-      else
-	case $ac_arg in
-	  *=* | --config-cache | -C | -disable-* | --disable-* \
-	  | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
-	  | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
-	  | -with-* | --with-* | -without-* | --without-* | --x)
-	    case "$ac_configure_args0 " in
-	      "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
-	    esac
-	    ;;
-	  -* ) ac_must_keep_next=true ;;
-	esac
-      fi
-      ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'"
-      # Get rid of the leading space.
-      ac_sep=" "
-      ;;
-    esac
-  done
-done
-$as_unset ac_configure_args0 || test "${ac_configure_args0+set}" != set || { ac_configure_args0=; export ac_configure_args0; }
-$as_unset ac_configure_args1 || test "${ac_configure_args1+set}" != set || { ac_configure_args1=; export ac_configure_args1; }
-
-# When interrupted or exit'd, cleanup temporary files, and complete
-# config.log.  We remove comments because anyway the quotes in there
-# would cause problems or look ugly.
-# WARNING: Be sure not to use single quotes in there, as some shells,
-# such as our DU 5.0 friend, will then `close' the trap.
-trap 'exit_status=$?
-  # Save into config.log some information that might help in debugging.
-  {
-    echo
-
-    cat <<\_ASBOX
-## ---------------- ##
-## Cache variables. ##
-## ---------------- ##
-_ASBOX
-    echo
-    # The following way of writing the cache mishandles newlines in values,
-{
-  (set) 2>&1 |
-    case `(ac_space='"'"' '"'"'; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      sed -n \
-	"s/'"'"'/'"'"'\\\\'"'"''"'"'/g;
-	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p"
-      ;;
-    *)
-      sed -n \
-	"s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
-      ;;
-    esac;
-}
-    echo
-
-    cat <<\_ASBOX
-## ----------------- ##
-## Output variables. ##
-## ----------------- ##
-_ASBOX
-    echo
-    for ac_var in $ac_subst_vars
-    do
-      eval ac_val=$`echo $ac_var`
-      echo "$ac_var='"'"'$ac_val'"'"'"
-    done | sort
-    echo
-
-    if test -n "$ac_subst_files"; then
-      cat <<\_ASBOX
-## ------------- ##
-## Output files. ##
-## ------------- ##
-_ASBOX
-      echo
-      for ac_var in $ac_subst_files
-      do
-	eval ac_val=$`echo $ac_var`
-	echo "$ac_var='"'"'$ac_val'"'"'"
-      done | sort
-      echo
-    fi
-
-    if test -s confdefs.h; then
-      cat <<\_ASBOX
-## ----------- ##
-## confdefs.h. ##
-## ----------- ##
-_ASBOX
-      echo
-      sed "/^$/d" confdefs.h | sort
-      echo
-    fi
-    test "$ac_signal" != 0 &&
-      echo "$as_me: caught signal $ac_signal"
-    echo "$as_me: exit $exit_status"
-  } >&5
-  rm -f core *.core &&
-  rm -rf conftest* confdefs* conf$$* $ac_clean_files &&
-    exit $exit_status
-     ' 0
-for ac_signal in 1 2 13 15; do
-  trap 'ac_signal='$ac_signal'; { (exit 1); exit 1; }' $ac_signal
-done
-ac_signal=0
-
-# confdefs.h avoids OS command line length limits that DEFS can exceed.
-rm -rf conftest* confdefs.h
-# AIX cpp loses on an empty file, so make sure it contains at least a newline.
-echo >confdefs.h
-
-# Predefined preprocessor variables.
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_NAME "$PACKAGE_NAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_VERSION "$PACKAGE_VERSION"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_STRING "$PACKAGE_STRING"
-_ACEOF
-
-
-cat >>confdefs.h <<_ACEOF
-#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
-_ACEOF
-
-
-# Let the site file select an alternate cache file if it wants to.
-# Prefer explicitly selected file to automatically selected ones.
-if test -z "$CONFIG_SITE"; then
-  if test "x$prefix" != xNONE; then
-    CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
-  else
-    CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
-  fi
-fi
-for ac_site_file in $CONFIG_SITE; do
-  if test -r "$ac_site_file"; then
-    { echo "$as_me:$LINENO: loading site script $ac_site_file" >&5
-echo "$as_me: loading site script $ac_site_file" >&6;}
-    sed 's/^/| /' "$ac_site_file" >&5
-    . "$ac_site_file"
-  fi
-done
-
-if test -r "$cache_file"; then
-  # Some versions of bash will fail to source /dev/null (special
-  # files actually), so we avoid doing that.
-  if test -f "$cache_file"; then
-    { echo "$as_me:$LINENO: loading cache $cache_file" >&5
-echo "$as_me: loading cache $cache_file" >&6;}
-    case $cache_file in
-      [\\/]* | ?:[\\/]* ) . $cache_file;;
-      *)                      . ./$cache_file;;
-    esac
-  fi
-else
-  { echo "$as_me:$LINENO: creating cache $cache_file" >&5
-echo "$as_me: creating cache $cache_file" >&6;}
-  >$cache_file
-fi
-
-# Check that the precious variables saved in the cache have kept the same
-# value.
-ac_cache_corrupted=false
-for ac_var in `(set) 2>&1 |
-	       sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do
-  eval ac_old_set=\$ac_cv_env_${ac_var}_set
-  eval ac_new_set=\$ac_env_${ac_var}_set
-  eval ac_old_val="\$ac_cv_env_${ac_var}_value"
-  eval ac_new_val="\$ac_env_${ac_var}_value"
-  case $ac_old_set,$ac_new_set in
-    set,)
-      { echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
-echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
-      ac_cache_corrupted=: ;;
-    ,set)
-      { echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
-echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
-      ac_cache_corrupted=: ;;
-    ,);;
-    *)
-      if test "x$ac_old_val" != "x$ac_new_val"; then
-	{ echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
-echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
-	{ echo "$as_me:$LINENO:   former value:  $ac_old_val" >&5
-echo "$as_me:   former value:  $ac_old_val" >&2;}
-	{ echo "$as_me:$LINENO:   current value: $ac_new_val" >&5
-echo "$as_me:   current value: $ac_new_val" >&2;}
-	ac_cache_corrupted=:
-      fi;;
-  esac
-  # Pass precious variables to config.status.
-  if test "$ac_new_set" = set; then
-    case $ac_new_val in
-    *" "*|*"	"*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
-      ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
-    *) ac_arg=$ac_var=$ac_new_val ;;
-    esac
-    case " $ac_configure_args " in
-      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
-      *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
-    esac
-  fi
-done
-if $ac_cache_corrupted; then
-  { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
-echo "$as_me: error: changes in the environment can compromise the build" >&2;}
-  { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
-echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-          ac_config_headers="$ac_config_headers config.h:config.in"
-
-
-# This file contains common code used by all simulators.
-#
-# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be invoked before any target specific stuff.
-# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
-# It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# sinclude(../common/aclocal.m4)
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-#
-# SIM_AC_COMMON
-#
-# ... target specific stuff ...
-#
-# SIM_AC_OUTPUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-sim_inline="-DDEFAULT_INLINE=0"
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-# intl sister-directory configuration rules.
-#
-
-# The idea behind this macro is that there's no need to repeat all the
-# autoconf probes done by the intl directory - it's already done them
-# for us.  In fact, there's no need even to look at the cache for the
-# answers.  All we need to do is nab a few pieces of information.
-# The intl directory is set up to make this easy, by generating a
-# small file which can be sourced as a shell script; then we produce
-# the necessary substitutions and definitions for this directory.
-
-
-
-
-
-
-
-# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
-# it by inlining the macro's contents.
-# This file contains common code used by all simulators.
-#
-# common.m4 invokes AC macros used by all simulators and by the common
-# directory.  It is intended to be included before any target specific
-# stuff.  SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
-# the Makefile.  It is intended to be invoked last.
-#
-# The simulator's configure.in should look like:
-#
-# dnl Process this file with autoconf to produce a configure script.
-# AC_PREREQ(2.5)dnl
-# AC_INIT(Makefile.in)
-# AC_CONFIG_HEADER(config.h:config.in)
-#
-# sinclude(../common/aclocal.m4)
-# sinclude(../common/common.m4)
-#
-# ... target specific stuff ...
-
-ac_aux_dir=
-for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
-  if test -f $ac_dir/install-sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install-sh -c"
-    break
-  elif test -f $ac_dir/install.sh; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/install.sh -c"
-    break
-  elif test -f $ac_dir/shtool; then
-    ac_aux_dir=$ac_dir
-    ac_install_sh="$ac_aux_dir/shtool install -c"
-    break
-  fi
-done
-if test -z "$ac_aux_dir"; then
-  { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&5
-echo "$as_me: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-ac_config_guess="$SHELL $ac_aux_dir/config.guess"
-ac_config_sub="$SHELL $ac_aux_dir/config.sub"
-ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
-
-# Make sure we can run config.sub.
-$ac_config_sub sun4 >/dev/null 2>&1 ||
-  { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
-echo "$as_me: error: cannot run $ac_config_sub" >&2;}
-   { (exit 1); exit 1; }; }
-
-echo "$as_me:$LINENO: checking build system type" >&5
-echo $ECHO_N "checking build system type... $ECHO_C" >&6
-if test "${ac_cv_build+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_build_alias=$build_alias
-test -z "$ac_cv_build_alias" &&
-  ac_cv_build_alias=`$ac_config_guess`
-test -z "$ac_cv_build_alias" &&
-  { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
-echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
-   { (exit 1); exit 1; }; }
-ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_build" >&5
-echo "${ECHO_T}$ac_cv_build" >&6
-build=$ac_cv_build
-build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking host system type" >&5
-echo $ECHO_N "checking host system type... $ECHO_C" >&6
-if test "${ac_cv_host+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_host_alias=$host_alias
-test -z "$ac_cv_host_alias" &&
-  ac_cv_host_alias=$ac_cv_build_alias
-ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_host" >&5
-echo "${ECHO_T}$ac_cv_host" >&6
-host=$ac_cv_host
-host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-echo "$as_me:$LINENO: checking target system type" >&5
-echo $ECHO_N "checking target system type... $ECHO_C" >&6
-if test "${ac_cv_target+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_target_alias=$target_alias
-test "x$ac_cv_target_alias" = "x" &&
-  ac_cv_target_alias=$ac_cv_host_alias
-ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
-  { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
-echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
-   { (exit 1); exit 1; }; }
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_target" >&5
-echo "${ECHO_T}$ac_cv_target" >&6
-target=$ac_cv_target
-target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
-target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
-target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
-
-
-# The aliases save the names the user supplied, while $host etc.
-# will get canonicalized.
-test -n "$target_alias" &&
-  test "$program_prefix$program_suffix$program_transform_name" = \
-    NONENONEs,x,x, &&
-  program_prefix=${target_alias}-
-test "$program_prefix" != NONE &&
-  program_transform_name="s,^,$program_prefix,;$program_transform_name"
-# Use a double $ so make ignores it.
-test "$program_suffix" != NONE &&
-  program_transform_name="s,\$,$program_suffix,;$program_transform_name"
-# Double any \ or $.  echo might interpret backslashes.
-# By default was `s,x,x', remove it if useless.
-cat <<\_ACEOF >conftest.sed
-s/[\\$]/&&/g;s/;s,x,x,$//
-_ACEOF
-program_transform_name=`echo $program_transform_name | sed -f conftest.sed`
-rm conftest.sed
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "gcc", so it can be a program name with args.
-set dummy gcc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="gcc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
-set dummy ${ac_tool_prefix}cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="${ac_tool_prefix}cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_CC"; then
-  ac_ct_CC=$CC
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  CC=$ac_ct_CC
-else
-  CC="$ac_cv_prog_CC"
-fi
-
-fi
-if test -z "$CC"; then
-  # Extract the first word of "cc", so it can be a program name with args.
-set dummy cc; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-  ac_prog_rejected=no
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
-       ac_prog_rejected=yes
-       continue
-     fi
-    ac_cv_prog_CC="cc"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-if test $ac_prog_rejected = yes; then
-  # We found a bogon in the path, so make sure we never use it.
-  set dummy $ac_cv_prog_CC
-  shift
-  if test $# != 0; then
-    # We chose a different compiler from the bogus one.
-    # However, it has the same basename, so the bogon will be chosen
-    # first if we set CC to just the basename; use the full file name.
-    shift
-    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
-  fi
-fi
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$CC"; then
-  if test -n "$ac_tool_prefix"; then
-  for ac_prog in cl
-  do
-    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
-set dummy $ac_tool_prefix$ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$CC"; then
-  ac_cv_prog_CC="$CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-CC=$ac_cv_prog_CC
-if test -n "$CC"; then
-  echo "$as_me:$LINENO: result: $CC" >&5
-echo "${ECHO_T}$CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-    test -n "$CC" && break
-  done
-fi
-if test -z "$CC"; then
-  ac_ct_CC=$CC
-  for ac_prog in cl
-do
-  # Extract the first word of "$ac_prog", so it can be a program name with args.
-set dummy $ac_prog; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_CC"; then
-  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_CC="$ac_prog"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-ac_ct_CC=$ac_cv_prog_ac_ct_CC
-if test -n "$ac_ct_CC"; then
-  echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
-echo "${ECHO_T}$ac_ct_CC" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  test -n "$ac_ct_CC" && break
-done
-
-  CC=$ac_ct_CC
-fi
-
-fi
-
-
-test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&5
-echo "$as_me: error: no acceptable C compiler found in \$PATH
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-
-# Provide some information about the compiler.
-echo "$as_me:$LINENO:" \
-     "checking for C compiler version" >&5
-ac_compiler=`set X $ac_compile; echo $2`
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
-  (eval $ac_compiler --version </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5
-  (eval $ac_compiler -v </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5
-  (eval $ac_compiler -V </dev/null >&5) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }
-
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files a.out a.exe b.out"
-# Try to create an executable without -o first, disregard a.out.
-# It will help us diagnose broken compilers, and finding out an intuition
-# of exeext.
-echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
-echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6
-ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
-if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5
-  (eval $ac_link_default) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # Find the output, starting from the most likely.  This scheme is
-# not robust to junk in `.', hence go to wildcards (a.*) only as a last
-# resort.
-
-# Be careful to initialize this variable, since it used to be cached.
-# Otherwise an old cache value of `no' led to `EXEEXT = no' in a Makefile.
-ac_cv_exeext=
-# b.out is created by i960 compilers.
-for ac_file in a_out.exe a.exe conftest.exe a.out conftest a.* conftest.* b.out
-do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj )
-	;;
-    conftest.$ac_ext )
-	# This is the source file.
-	;;
-    [ab].out )
-	# We found the default executable, but exeext='' is most
-	# certainly right.
-	break;;
-    *.* )
-	ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	# FIXME: I believe we export ac_cv_exeext for Libtool,
-	# but it would be cool to find out if it's true.  Does anybody
-	# maintain Libtool? --akim.
-	export ac_cv_exeext
-	break;;
-    * )
-	break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: C compiler cannot create executables
-See \`config.log' for more details." >&5
-echo "$as_me: error: C compiler cannot create executables
-See \`config.log' for more details." >&2;}
-   { (exit 77); exit 77; }; }
-fi
-
-ac_exeext=$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_file" >&5
-echo "${ECHO_T}$ac_file" >&6
-
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether the C compiler works" >&5
-echo $ECHO_N "checking whether the C compiler works... $ECHO_C" >&6
-# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
-# If not cross compiling, check that we can run a simple program.
-if test "$cross_compiling" != yes; then
-  if { ac_try='./$ac_file'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-    cross_compiling=no
-  else
-    if test "$cross_compiling" = maybe; then
-	cross_compiling=yes
-    else
-	{ { echo "$as_me:$LINENO: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot run C compiled programs.
-If you meant to cross compile, use \`--host'.
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-    fi
-  fi
-fi
-echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-
-rm -f a.out a.exe conftest$ac_cv_exeext b.out
-ac_clean_files=$ac_clean_files_save
-# Check the compiler produces executables we can run.  If not, either
-# the compiler is broken, or we cross compile.
-echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
-echo $ECHO_N "checking whether we are cross compiling... $ECHO_C" >&6
-echo "$as_me:$LINENO: result: $cross_compiling" >&5
-echo "${ECHO_T}$cross_compiling" >&6
-
-echo "$as_me:$LINENO: checking for suffix of executables" >&5
-echo $ECHO_N "checking for suffix of executables... $ECHO_C" >&6
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  # If both `conftest.exe' and `conftest' are `present' (well, observable)
-# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
-# work properly (i.e., refer to `conftest.exe'), while it won't with
-# `rm'.
-for ac_file in conftest.exe conftest conftest.*; do
-  test -f "$ac_file" || continue
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;;
-    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
-	  export ac_cv_exeext
-	  break;;
-    * ) break;;
-  esac
-done
-else
-  { { echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest$ac_cv_exeext
-echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
-echo "${ECHO_T}$ac_cv_exeext" >&6
-
-rm -f conftest.$ac_ext
-EXEEXT=$ac_cv_exeext
-ac_exeext=$EXEEXT
-echo "$as_me:$LINENO: checking for suffix of object files" >&5
-echo $ECHO_N "checking for suffix of object files... $ECHO_C" >&6
-if test "${ac_cv_objext+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.o conftest.obj
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; then
-  for ac_file in `(ls conftest.o conftest.obj; ls conftest.*) 2>/dev/null`; do
-  case $ac_file in
-    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg ) ;;
-    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
-       break;;
-  esac
-done
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-{ { echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&5
-echo "$as_me: error: cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-rm -f conftest.$ac_cv_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
-echo "${ECHO_T}$ac_cv_objext" >&6
-OBJEXT=$ac_cv_objext
-ac_objext=$OBJEXT
-echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
-echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6
-if test "${ac_cv_c_compiler_gnu+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-#ifndef __GNUC__
-       choke me
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_compiler_gnu=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_compiler_gnu=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_cv_c_compiler_gnu=$ac_compiler_gnu
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
-echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6
-GCC=`test $ac_compiler_gnu = yes && echo yes`
-ac_test_CFLAGS=${CFLAGS+set}
-ac_save_CFLAGS=$CFLAGS
-CFLAGS="-g"
-echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
-echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_g+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_g=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_prog_cc_g=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_g" >&6
-if test "$ac_test_CFLAGS" = set; then
-  CFLAGS=$ac_save_CFLAGS
-elif test $ac_cv_prog_cc_g = yes; then
-  if test "$GCC" = yes; then
-    CFLAGS="-g -O2"
-  else
-    CFLAGS="-g"
-  fi
-else
-  if test "$GCC" = yes; then
-    CFLAGS="-O2"
-  else
-    CFLAGS=
-  fi
-fi
-echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5
-echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6
-if test "${ac_cv_prog_cc_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_prog_cc_stdc=no
-ac_save_CC=$CC
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdarg.h>
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
-struct buf { int x; };
-FILE * (*rcsopen) (struct buf *, struct stat *, int);
-static char *e (p, i)
-     char **p;
-     int i;
-{
-  return p[i];
-}
-static char *f (char * (*g) (char **, int), char **p, ...)
-{
-  char *s;
-  va_list v;
-  va_start (v,p);
-  s = g (p, va_arg (v,int));
-  va_end (v);
-  return s;
-}
-
-/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
-   function prototypes and stuff, but not '\xHH' hex character constants.
-   These don't provoke an error unfortunately, instead are silently treated
-   as 'x'.  The following induces an error, until -std1 is added to get
-   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
-   array size at least.  It's necessary to write '\x00'==0 to get something
-   that's true only with -std1.  */
-int osf4_cc_array ['\x00' == 0 ? 1 : -1];
-
-int test (int i, double x);
-struct s1 {int (*f) (int a);};
-struct s2 {int (*f) (double a);};
-int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
-int argc;
-char **argv;
-int
-main ()
-{
-return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
-  ;
-  return 0;
-}
-_ACEOF
-# Don't try gcc -ansi; that turns off useful extensions and
-# breaks some systems' header files.
-# AIX			-qlanglvl=ansi
-# Ultrix and OSF/1	-std1
-# HP-UX 10.20 and later	-Ae
-# HP-UX older versions	-Aa -D_HPUX_SOURCE
-# SVR4			-Xc -D__EXTENSIONS__
-for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
-do
-  CC="$ac_save_CC $ac_arg"
-  rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_prog_cc_stdc=$ac_arg
-break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext
-done
-rm -f conftest.$ac_ext conftest.$ac_objext
-CC=$ac_save_CC
-
-fi
-
-case "x$ac_cv_prog_cc_stdc" in
-  x|xno)
-    echo "$as_me:$LINENO: result: none needed" >&5
-echo "${ECHO_T}none needed" >&6 ;;
-  *)
-    echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5
-echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6
-    CC="$CC $ac_cv_prog_cc_stdc" ;;
-esac
-
-# Some people use a C++ compiler to compile C.  Since we use `exit',
-# in C++ we need to declare it.  In case someone uses the same compiler
-# for both compiling C and C++ we need to have the C++ compiler decide
-# the declaration of exit, since it's the most demanding environment.
-cat >conftest.$ac_ext <<_ACEOF
-#ifndef __cplusplus
-  choke me
-#endif
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  for ac_declaration in \
-   '' \
-   'extern "C" void std::exit (int) throw (); using std::exit;' \
-   'extern "C" void std::exit (int); using std::exit;' \
-   'extern "C" void exit (int) throw ();' \
-   'extern "C" void exit (int);' \
-   'void exit (int);'
-do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-#include <stdlib.h>
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-continue
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_declaration
-int
-main ()
-{
-exit (42);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
-rm -f conftest*
-if test -n "$ac_declaration"; then
-  echo '#ifdef __cplusplus' >>confdefs.h
-  echo $ac_declaration      >>confdefs.h
-  echo '#endif'             >>confdefs.h
-fi
-
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-# Find a good install program.  We prefer a C program (faster),
-# so one script is as good as another.  But avoid the broken or
-# incompatible versions:
-# SysV /etc/install, /usr/sbin/install
-# SunOS /usr/etc/install
-# IRIX /sbin/install
-# AIX /bin/install
-# AmigaOS /C/install, which installs bootblocks on floppy discs
-# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
-# AFS /usr/afsws/bin/install, which mishandles nonexistent args
-# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
-# OS/2's system install, which has a completely different semantic
-# ./install, which can be erroneously created by make from ./install.sh.
-echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
-echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6
-if test -z "$INSTALL"; then
-if test "${ac_cv_path_install+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  # Account for people who put trailing slashes in PATH elements.
-case $as_dir/ in
-  ./ | .// | /cC/* | \
-  /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
-  ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
-  /usr/ucb/* ) ;;
-  *)
-    # OSF1 and SCO ODT 3.0 have their own names for install.
-    # Don't use installbsd from OSF since it installs stuff as root
-    # by default.
-    for ac_prog in ginstall scoinst install; do
-      for ac_exec_ext in '' $ac_executable_extensions; do
-	if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
-	  if test $ac_prog = install &&
-	    grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # AIX install.  It has an incompatible calling convention.
-	    :
-	  elif test $ac_prog = install &&
-	    grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
-	    # program-specific install script used by HP pwplus--don't use.
-	    :
-	  else
-	    ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
-	    break 3
-	  fi
-	fi
-      done
-    done
-    ;;
-esac
-done
-
-
-fi
-  if test "${ac_cv_path_install+set}" = set; then
-    INSTALL=$ac_cv_path_install
-  else
-    # As a last resort, use the slow shell script.  We don't cache a
-    # path for INSTALL within a source directory, because that will
-    # break other packages using the cache if that directory is
-    # removed, or if the path is relative.
-    INSTALL=$ac_install_sh
-  fi
-fi
-echo "$as_me:$LINENO: result: $INSTALL" >&5
-echo "${ECHO_T}$INSTALL" >&6
-
-# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
-# It thinks the first close brace ends the variable substitution.
-test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
-
-test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
-
-test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
-
-
-# Put a plausible default for CC_FOR_BUILD in Makefile.
-if test "x$cross_compiling" = "xno"; then
-  CC_FOR_BUILD='$(CC)'
-else
-  CC_FOR_BUILD=gcc
-fi
-
-
-
-
-AR=${AR-ar}
-
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
-fi
-fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-  RANLIB=$ac_ct_RANLIB
-else
-  RANLIB="$ac_cv_prog_RANLIB"
-fi
-
-
-ALL_LINGUAS=
-# If we haven't got the data from the intl directory,
-# assume NLS is disabled.
-USE_NLS=no
-LIBINTL=
-LIBINTL_DEP=
-INCINTL=
-XGETTEXT=
-GMSGFMT=
-POSUB=
-
-if test -f  ../../intl/config.intl; then
-  .  ../../intl/config.intl
-fi
-echo "$as_me:$LINENO: checking whether NLS is requested" >&5
-echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
-if test x"$USE_NLS" != xyes; then
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-else
-  echo "$as_me:$LINENO: result: yes" >&5
-echo "${ECHO_T}yes" >&6
-
-cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
-
-  echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
-echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
-  # Look for .po and .gmo files in the source directory.
-  CATALOGS=
-  XLINGUAS=
-  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
-    # If there aren't any .gmo files the shell will give us the
-    # literal string "../path/to/srcdir/po/*.gmo" which has to be
-    # weeded out.
-    case "$cat" in *\**)
-      continue;;
-    esac
-    # The quadruple backslash is collapsed to a double backslash
-    # by the backticks, then collapsed again by the double quotes,
-    # leaving us with one backslash in the sed expression (right
-    # before the dot that mustn't act as a wildcard).
-    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
-    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
-    # The user is allowed to set LINGUAS to a list of languages to
-    # install catalogs for.  If it's empty that means "all of them."
-    if test "x$LINGUAS" = x; then
-      CATALOGS="$CATALOGS $cat"
-      XLINGUAS="$XLINGUAS $lang"
-    else
-      case "$LINGUAS" in *$lang*)
-        CATALOGS="$CATALOGS $cat"
-        XLINGUAS="$XLINGUAS $lang"
-        ;;
-      esac
-    fi
-  done
-  LINGUAS="$XLINGUAS"
-  echo "$as_me:$LINENO: result: $LINGUAS" >&5
-echo "${ECHO_T}$LINGUAS" >&6
-
-
-    DATADIRNAME=share
-
-  INSTOBJEXT=.mo
-
-  GENCAT=gencat
-
-  CATOBJEXT=.gmo
-
-fi
-
-# Check for common headers.
-# FIXME: Seems to me this can cause problems for i386-windows hosts.
-# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
-echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-  if test "${ac_cv_prog_CPP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-      # Double quotes because CPP needs to be expanded
-    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
-    do
-      ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  break
-fi
-
-    done
-    ac_cv_prog_CPP=$CPP
-
-fi
-  CPP=$ac_cv_prog_CPP
-else
-  ac_cv_prog_CPP=$CPP
-fi
-echo "$as_me:$LINENO: result: $CPP" >&5
-echo "${ECHO_T}$CPP" >&6
-ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  :
-else
-  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&5
-echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-echo "$as_me:$LINENO: checking for egrep" >&5
-echo $ECHO_N "checking for egrep... $ECHO_C" >&6
-if test "${ac_cv_prog_egrep+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
-    then ac_cv_prog_egrep='grep -E'
-    else ac_cv_prog_egrep='egrep'
-    fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
-echo "${ECHO_T}$ac_cv_prog_egrep" >&6
- EGREP=$ac_cv_prog_egrep
-
-
-echo "$as_me:$LINENO: checking for ANSI C header files" >&5
-echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
-if test "${ac_cv_header_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_header_stdc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_header_stdc=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <string.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "memchr" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "free" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-  if test "$cross_compiling" = yes; then
-  :
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ctype.h>
-#if ((' ' & 0x0FF) == 0x020)
-# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#else
-# define ISLOWER(c) \
-		   (('a' <= (c) && (c) <= 'i') \
-		     || ('j' <= (c) && (c) <= 'r') \
-		     || ('s' <= (c) && (c) <= 'z'))
-# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
-#endif
-
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int
-main ()
-{
-  int i;
-  for (i = 0; i < 256; i++)
-    if (XOR (islower (i), ISLOWER (i))
-	|| toupper (i) != TOUPPER (i))
-      exit(2);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_header_stdc=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
-echo "${ECHO_T}$ac_cv_header_stdc" >&6
-if test $ac_cv_header_stdc = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define STDC_HEADERS 1
-_ACEOF
-
-fi
-
-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-
-
-
-
-
-
-
-
-
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-		  inttypes.h stdint.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_Header=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_Header=no"
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-
-
-for ac_header in stdlib.h string.h strings.h unistd.h time.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in sys/time.h sys/resource.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-for ac_header in fcntl.h fpu_control.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-for ac_header in dlfcn.h errno.h sys/stat.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-for ac_func in getrusage time sigaction __setfpucw
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-# Check for socket libraries
-
-echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
-echo $ECHO_N "checking for bind in -lsocket... $ECHO_C" >&6
-if test "${ac_cv_lib_socket_bind+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lsocket  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bind ();
-int
-main ()
-{
-bind ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_socket_bind=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_socket_bind=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
-echo "${ECHO_T}$ac_cv_lib_socket_bind" >&6
-if test $ac_cv_lib_socket_bind = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBSOCKET 1
-_ACEOF
-
-  LIBS="-lsocket $LIBS"
-
-fi
-
-
-echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
-echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6
-if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lnsl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char gethostbyname ();
-int
-main ()
-{
-gethostbyname ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_nsl_gethostbyname=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_nsl_gethostbyname=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
-echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6
-if test $ac_cv_lib_nsl_gethostbyname = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBNSL 1
-_ACEOF
-
-  LIBS="-lnsl $LIBS"
-
-fi
-
-
-. ${srcdir}/../../bfd/configure.host
-
-
-
-USE_MAINTAINER_MODE=no
-# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
-if test "${enable_maintainer_mode+set}" = set; then
-  enableval="$enable_maintainer_mode"
-  case "${enableval}" in
-  yes)	MAINT="" USE_MAINTAINER_MODE=yes ;;
-  no)	MAINT="#" ;;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
-echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; MAINT="#" ;;
-esac
-if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
-  echo "Setting maintainer mode" 6>&1
-fi
-else
-  MAINT="#"
-fi;
-
-
-# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
-if test "${enable_sim_bswap+set}" = set; then
-  enableval="$enable_sim_bswap"
-  case "${enableval}" in
-  yes)	sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
-  no)	sim_bswap="-DWITH_BSWAP=0";;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
-echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_bswap="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
-  echo "Setting bswap flags = $sim_bswap" 6>&1
-fi
-else
-  sim_bswap=""
-fi;
-
-
-# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
-if test "${enable_sim_cflags+set}" = set; then
-  enableval="$enable_sim_cflags"
-  case "${enableval}" in
-  yes)	 sim_cflags="-O2 -fomit-frame-pointer";;
-  trace) { { echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
-echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_cflags="";;
-  no)	 sim_cflags="";;
-  *)	 sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
-  echo "Setting sim cflags = $sim_cflags" 6>&1
-fi
-else
-  sim_cflags=""
-fi;
-
-
-# Check whether --enable-sim-debug or --disable-sim-debug was given.
-if test "${enable_sim_debug+set}" = set; then
-  enableval="$enable_sim_debug"
-  case "${enableval}" in
-  yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
-  no)  sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
-  *)   sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
-  echo "Setting sim debug = $sim_debug" 6>&1
-fi
-else
-  sim_debug=""
-fi;
-
-
-# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
-if test "${enable_sim_stdio+set}" = set; then
-  enableval="$enable_sim_stdio"
-  case "${enableval}" in
-  yes)	sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
-  no)	sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
-  *)	{ { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_stdio="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
-  echo "Setting stdio flags = $sim_stdio" 6>&1
-fi
-else
-  sim_stdio=""
-fi;
-
-
-# Check whether --enable-sim-trace or --disable-sim-trace was given.
-if test "${enable_sim_trace+set}" = set; then
-  enableval="$enable_sim_trace"
-  case "${enableval}" in
-  yes)	sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
-  no)	sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
-  [-0-9]*)
-	sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
-  [a-z]*)
-	sim_trace=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_trace" = x; then
-	    sim_trace="-DWITH_TRACE='(TRACE_$x"
-	  else
-	    sim_trace="${sim_trace}|TRACE_$x"
-	  fi
-	done
-	sim_trace="$sim_trace)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
-  echo "Setting sim trace = $sim_trace" 6>&1
-fi
-else
-  sim_trace=""
-fi;
-
-
-# Check whether --enable-sim-profile or --disable-sim-profile was given.
-if test "${enable_sim_profile+set}" = set; then
-  enableval="$enable_sim_profile"
-  case "${enableval}" in
-  yes)	sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
-  no)	sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
-  [-0-9]*)
-	sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
-  [a-z]*)
-	sim_profile=""
-	for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-	  if test x"$sim_profile" = x; then
-	    sim_profile="-DWITH_PROFILE='(PROFILE_$x"
-	  else
-	    sim_profile="${sim_profile}|PROFILE_$x"
-	  fi
-	done
-	sim_profile="$sim_profile)'" ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
-  echo "Setting sim profile = $sim_profile" 6>&1
-fi
-else
-  sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
-fi;
-
-
-echo "$as_me:$LINENO: checking return type of signal handlers" >&5
-echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6
-if test "${ac_cv_type_signal+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <signal.h>
-#ifdef signal
-# undef signal
-#endif
-#ifdef __cplusplus
-extern "C" void (*signal (int, void (*)(int)))(int);
-#else
-void (*signal ()) ();
-#endif
-
-int
-main ()
-{
-int i;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_signal=void
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_signal=int
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
-echo "${ECHO_T}$ac_cv_type_signal" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define RETSIGTYPE $ac_cv_type_signal
-_ACEOF
-
-
-
-
-
-sim_link_files=
-sim_link_links=
-
-sim_link_links=tconfig.h
-if test -f ${srcdir}/tconfig.in
-then
-  sim_link_files=tconfig.in
-else
-  sim_link_files=../common/tconfig.in
-fi
-
-# targ-vals.def points to the libc macro description file.
-case "${target}" in
-*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
-esac
-sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
-sim_link_links="${sim_link_links} targ-vals.def"
-
-
-
-default_sim_inline=""
-# Check whether --enable-sim-inline or --disable-sim-inline was given.
-if test "${enable_sim_inline+set}" = set; then
-  enableval="$enable_sim_inline"
-  sim_inline=""
-case "$enableval" in
-  no)		sim_inline="-DDEFAULT_INLINE=0";;
-  0)		sim_inline="-DDEFAULT_INLINE=0";;
-  yes | 2)	sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
-  1)		sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
-  *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
-       new_flag=""
-       case "$x" in
-	 *_INLINE=*)	new_flag="-D$x";;
-	 *=*)		new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
-	 *_INLINE)	new_flag="-D$x=ALL_C_INLINE";;
-	 *)		new_flag="-D$x""_INLINE=ALL_C_INLINE";;
-       esac
-       if test x"$sim_inline" = x""; then
-	 sim_inline="$new_flag"
-       else
-	 sim_inline="$sim_inline $new_flag"
-       fi
-     done;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
-  echo "Setting inline flags = $sim_inline" 6>&1
-fi
-else
-
-if test "x$cross_compiling" = "xno"; then
-  if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
-    sim_inline="${default_sim_inline}"
-    if test x"$silent" != x"yes"; then
-      echo "Setting inline flags = $sim_inline" 6>&1
-    fi
-  else
-    sim_inline=""
-  fi
-else
-  sim_inline="-DDEFAULT_INLINE=0"
-fi
-fi;
-wire_alignment="NONSTRICT_ALIGNMENT"
-default_alignment=""
-
-# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
-if test "${enable_sim_alignment+set}" = set; then
-  enableval="$enable_sim_alignment"
-  case "${enableval}" in
-  strict | STRICT)       sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
-  nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
-  forced | FORCED)       sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
-  yes) if test x"$wire_alignment" != x; then
-	 sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-       else
-         if test x"$default_alignment" != x; then
-           sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
-         else
-	   echo "No hard-wired alignment for target $target" 1>&6
-	   sim_alignment="-DWITH_ALIGNMENT=0"
-         fi
-       fi;;
-  no)  if test x"$default_alignment" != x; then
-	 sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-       else
-         if test x"$wire_alignment" != x; then
-	   sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
-         else
-           echo "No default alignment for target $target" 1>&6
-           sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
-         fi
-       fi;;
-  *)   { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_alignment="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
-  echo "Setting alignment flags = $sim_alignment" 6>&1
-fi
-else
-  if test x"$default_alignment" != x; then
-  sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
-else
-  if test x"$wire_alignment" != x; then
-    sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
-  else
-    sim_alignment=
-  fi
-fi
-fi;
-
-# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
-if test "${enable_sim_hostendian+set}" = set; then
-  enableval="$enable_sim_hostendian"
-  case "${enableval}" in
-  no)	 sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
-  b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_hostendian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
-  echo "Setting hostendian flags = $sim_hostendian" 6>&1
-fi
-else
-
-if test "x$cross_compiling" = "xno"; then
-  echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
-echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
-if test "${ac_cv_c_bigendian+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  # See if sys/param.h defines the BYTE_ORDER macro.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
- bogus endian macros
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  # It does; now see whether it defined to BIG_ENDIAN or not.
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <sys/types.h>
-#include <sys/param.h>
-
-int
-main ()
-{
-#if BYTE_ORDER != BIG_ENDIAN
- not big endian
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_bigendian=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-# It does not; compile a test program.
-if test "$cross_compiling" = yes; then
-  # try to guess the endianness by grepping values into an object file
-  ac_cv_c_bigendian=unknown
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
-short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
-void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
-short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
-short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
-void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
-int
-main ()
-{
- _ascii (); _ebcdic ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
-  ac_cv_c_bigendian=yes
-fi
-if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
-  if test "$ac_cv_c_bigendian" = unknown; then
-    ac_cv_c_bigendian=no
-  else
-    # finding both strings is unlikely to happen, but who knows?
-    ac_cv_c_bigendian=unknown
-  fi
-fi
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-main ()
-{
-  /* Are we little or big endian?  From Harbison&Steele.  */
-  union
-  {
-    long l;
-    char c[sizeof (long)];
-  } u;
-  u.l = 1;
-  exit (u.c[sizeof (long) - 1] == 1);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_bigendian=no
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_bigendian=yes
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
-echo "${ECHO_T}$ac_cv_c_bigendian" >&6
-case $ac_cv_c_bigendian in
-  yes)
-
-cat >>confdefs.h <<\_ACEOF
-#define WORDS_BIGENDIAN 1
-_ACEOF
- ;;
-  no)
-     ;;
-  *)
-    { { echo "$as_me:$LINENO: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&5
-echo "$as_me: error: unknown endianness
-presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-
-  if test $ac_cv_c_bigendian = yes; then
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
-  else
-    sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
-  fi
-else
-  sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
-fi
-fi;
-
-# NOTE: Don't add -Wall or -Wunused, they both include
-# -Wunused-parameter which reports bogus warnings.
-# NOTE: If you add to this list, remember to update
-# gdb/doc/gdbint.texinfo.
-build_warnings="-Wimplicit -Wreturn-type -Wcomment -Wtrigraphs \
--Wformat -Wparentheses -Wpointer-arith"
-# GCC supports -Wuninitialized only with -O or -On, n != 0.
-if test x${CFLAGS+set} = xset; then
-  case "${CFLAGS}" in
-    *"-O0"* ) ;;
-    *"-O"* )
-      build_warnings="${build_warnings} -Wuninitialized"
-    ;;
-  esac
-else
-  build_warnings="${build_warnings} -Wuninitialized"
-fi
-# Up for debate: -Wswitch -Wcomment -trigraphs -Wtrigraphs
-# -Wunused-function -Wunused-label -Wunused-variable -Wunused-value
-# -Wchar-subscripts -Wtraditional -Wshadow -Wcast-qual
-# -Wcast-align -Wwrite-strings -Wconversion -Wstrict-prototypes
-# -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls
-# -Woverloaded-virtual -Winline -Werror"
-# Check whether --enable-build-warnings or --disable-build-warnings was given.
-if test "${enable_build_warnings+set}" = set; then
-  enableval="$enable_build_warnings"
-  case "${enableval}" in
-  yes)	;;
-  no)	build_warnings="-w";;
-  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${build_warnings} ${t}";;
-  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${t} ${build_warnings}";;
-  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
-  echo "Setting compiler warning flags = $build_warnings" 6>&1
-fi
-fi; # Check whether --enable-sim-build-warnings or --disable-sim-build-warnings was given.
-if test "${enable_sim_build_warnings+set}" = set; then
-  enableval="$enable_sim_build_warnings"
-  case "${enableval}" in
-  yes)	;;
-  no)	build_warnings="-w";;
-  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${build_warnings} ${t}";;
-  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${t} ${build_warnings}";;
-  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
-  echo "Setting GDB specific compiler warning flags = $build_warnings" 6>&1
-fi
-fi; WARN_CFLAGS=""
-WERROR_CFLAGS=""
-if test "x${build_warnings}" != x -a "x$GCC" = xyes
-then
-    echo "$as_me:$LINENO: checking compiler warning flags" >&5
-echo $ECHO_N "checking compiler warning flags... $ECHO_C" >&6
-    # Separate out the -Werror flag as some files just cannot be
-    # compiled with it enabled.
-    for w in ${build_warnings}; do
-	case $w in
-	-Werr*) WERROR_CFLAGS=-Werror ;;
-	*) # Check that GCC accepts it
-	    saved_CFLAGS="$CFLAGS"
-	    CFLAGS="$CFLAGS $w"
-	    cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  WARN_CFLAGS="${WARN_CFLAGS} $w"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-	    CFLAGS="$saved_CFLAGS"
-	esac
-    done
-    echo "$as_me:$LINENO: result: ${WARN_CFLAGS}${WERROR_CFLAGS}" >&5
-echo "${ECHO_T}${WARN_CFLAGS}${WERROR_CFLAGS}" >&6
-fi
-
-
-default_sim_reserved_bits="1"
-# Check whether --enable-sim-reserved-bits or --disable-sim-reserved-bits was given.
-if test "${enable_sim_reserved_bits+set}" = set; then
-  enableval="$enable_sim_reserved_bits"
-  case "${enableval}" in
-  yes)	sim_reserved_bits="-DWITH_RESERVED_BITS=1";;
-  no)	sim_reserved_bits="-DWITH_RESERVED_BITS=0";;
-  *)	{ { echo "$as_me:$LINENO: error: \"--enable-sim-reserved-bits does not take a value\"" >&5
-echo "$as_me: error: \"--enable-sim-reserved-bits does not take a value\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_reserved_bits="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_reserved_bits" != x""; then
-  echo "Setting reserved flags = $sim_reserved_bits" 6>&1
-fi
-else
-  sim_reserved_bits="-DWITH_RESERVED_BITS=${default_sim_reserved_bits}"
-fi;
-
-# DEPRECATED
-#
-# Instead of defining a `subtarget' macro, code should be checking
-# the value of {STATE,CPU}_ARCHITECTURE to identify the architecture
-# in question.
-#
-case "${target}" in
-  mips64vr*-*-*)	SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
-  mips*tx39*)           SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
-  mipsisa32*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
-  mipsisa64*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
-  *)                    SIM_SUBTARGET="";;
-esac
-
-
-
-
-#
-# Select the byte order of the target
-#
-mips_endian=
-default_endian=
-case "${target}" in
-  mips64el*-*-*)	mips_endian=LITTLE_ENDIAN ;;
-  mips64vr*el-*-*)      default_endian=LITTLE_ENDIAN ;;
-  mips64*-*-*)          default_endian=BIG_ENDIAN ;;
-  mips16*-*-*)          default_endian=BIG_ENDIAN ;;
-  mipsisa32*-*-*)       default_endian=BIG_ENDIAN ;;
-  mipsisa64*-*-*)       default_endian=BIG_ENDIAN ;;
-  mips*-*-*)            default_endian=BIG_ENDIAN ;;
-  *)                    default_endian=BIG_ENDIAN ;;
-esac
-
-wire_endian="$mips_endian"
-default_endian="$default_endian"
-# Check whether --enable-sim-endian or --disable-sim-endian was given.
-if test "${enable_sim_endian+set}" = set; then
-  enableval="$enable_sim_endian"
-  case "${enableval}" in
-  b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
-  l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
-  yes)	 if test x"$wire_endian" != x; then
-	   sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-	 else
-           if test x"$default_endian" != x; then
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
-	   else
-	     echo "No hard-wired endian for target $target" 1>&6
-	     sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  no)	 if test x"$default_endian" != x; then
-	   sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-	 else
-	   if test x"$wire_endian" != x; then
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
-	   else
-	     echo "No default endian for target $target" 1>&6
-	     sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
-	   fi
-	 fi;;
-  *)	 { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-endian\"" >&5
-echo "$as_me: error: \"Unknown value $enableval for --enable-sim-endian\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_endian="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
-  echo "Setting endian flags = $sim_endian" 6>&1
-fi
-else
-  if test x"$default_endian" != x; then
-  sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
-else
-  if test x"$wire_endian" != x; then
-    sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
-  else
-    sim_endian=
-  fi
-fi
-fi;
-
-
-
-#
-# Select the bitsize of the target
-#
-mips_addr_bitsize=
-case "${target}" in
-  mips64*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
-  mips16*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
-  mipsisa32*-*-*)       mips_bitsize=32 ; mips_msb=31 ;;
-  mipsisa64*-*-*)       mips_bitsize=64 ; mips_msb=63 ;;
-  mips*-*-*)            mips_bitsize=32 ; mips_msb=31 ;;
-  *)                    mips_bitsize=64 ; mips_msb=63 ;;
-esac
-wire_word_bitsize="$mips_bitsize"
-wire_word_msb="$mips_msb"
-wire_address_bitsize="$mips_addr_bitsize"
-wire_cell_bitsize=""
-# Check whether --enable-sim-bitsize or --disable-sim-bitsize was given.
-if test "${enable_sim_bitsize+set}" = set; then
-  enableval="$enable_sim_bitsize"
-  sim_bitsize=
-case "${enableval}" in
-  64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";;
-  32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";;
-  64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
-  32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";;
-  32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
-        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31"
-      else
-        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0"
-      fi ;;
-  64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then
-        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63"
-      else
-        sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0"
-      fi ;;
-  *)  { { echo "$as_me:$LINENO: error: \"--enable-sim-bitsize was given $enableval.  Expected 32 or 64\"" >&5
-echo "$as_me: error: \"--enable-sim-bitsize was given $enableval.  Expected 32 or 64\"" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-# address bitsize
-tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9]*,*//"`
-case x"${tmp}" in
-  x ) ;;
-  x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;;
-  x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;;
-  * ) { { echo "$as_me:$LINENO: error: \"--enable-sim-bitsize was given address size $enableval.  Expected 32 or 64\"" >&5
-echo "$as_me: error: \"--enable-sim-bitsize was given address size $enableval.  Expected 32 or 64\"" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-# cell bitsize
-tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9*]*,*[0-9]*,*//"`
-case x"${tmp}" in
-  x ) ;;
-  x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;;
-  x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;;
-  * ) { { echo "$as_me:$LINENO: error: \"--enable-sim-bitsize was given cell size $enableval.  Expected 32 or 64\"" >&5
-echo "$as_me: error: \"--enable-sim-bitsize was given cell size $enableval.  Expected 32 or 64\"" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then
-  echo "Setting bitsize flags = $sim_bitsize" 6>&1
-fi
-else
-  sim_bitsize=""
-if test x"$wire_word_bitsize" != x; then
-  sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize"
-fi
-if test x"$wire_word_msb" != x; then
-  sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb"
-fi
-if test x"$wire_address_bitsize" != x; then
-  sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize"
-fi
-if test x"$wire_cell_bitsize" != x; then
-  sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize"
-fi
-fi;
-
-
-
-#
-# Select the floating hardware support of the target
-#
-mips_fpu=HARDWARE_FLOATING_POINT
-mips_fpu_bitsize=
-case "${target}" in
-  mips*tx39*)		mips_fpu=HARD_FLOATING_POINT
-			mips_fpu_bitsize=32
-			;;
-  mips64*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
-  mips16*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
-  mipsisa32*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
-  mipsisa64*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
-  mips*-*-*)            mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
-  *)                    mips_fpu=HARD_FLOATING_POINT ;;
-esac
-
-default_sim_float="$mips_fpu"
-default_sim_float_bitsize="$mips_fpu_bitsize"
-# Check whether --enable-sim-float or --disable-sim-float was given.
-if test "${enable_sim_float+set}" = set; then
-  enableval="$enable_sim_float"
-  case "${enableval}" in
-  yes | hard)	sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT";;
-  no | soft)	sim_float="-DWITH_FLOATING_POINT=SOFT_FLOATING_POINT";;
-  32)           sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=32";;
-  64)           sim_float="-DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=64";;
-  *)		{ { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-float\"" >&5
-echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-float\"" >&2;}
-   { (exit 1); exit 1; }; }; sim_float="";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_float" != x""; then
-  echo "Setting float flags = $sim_float" 6>&1
-fi
-else
-
-sim_float=
-if test x"${default_sim_float}" != x""; then
-  sim_float="-DWITH_FLOATING_POINT=${default_sim_float}"
-fi
-if test x"${default_sim_float_bitsize}" != x""; then
-  sim_float="$sim_float -DWITH_TARGET_FLOATING_POINT_BITSIZE=${default_sim_float_bitsize}"
-fi
-
-fi;
-
-
-
-#
-# Select the level of SMP support
-#
-case "${target}" in
-  *)                    mips_smp=0 ;;
-esac
-
-default_sim_smp="$mips_smp"
-# Check whether --enable-sim-smp or --disable-sim-smp was given.
-if test "${enable_sim_smp+set}" = set; then
-  enableval="$enable_sim_smp"
-  case "${enableval}" in
-  yes)	sim_smp="-DWITH_SMP=5" ; sim_igen_smp="-N 5";;
-  no)	sim_smp="-DWITH_SMP=0" ; sim_igen_smp="-N 0";;
-  *)	sim_smp="-DWITH_SMP=$enableval" ; sim_igen_smp="-N $enableval";;
-esac
-if test x"$silent" != x"yes" && test x"$sim_smp" != x""; then
-  echo "Setting smp flags = $sim_smp" 6>&1
-fi
-else
-  sim_smp="-DWITH_SMP=${default_sim_smp}" ; sim_igen_smp="-N ${default_sim_smp}"
-if test x"$silent" != x"yes"; then
-  echo "Setting smp flags = $sim_smp" 6>&1
-fi
-fi;
-
-
-
-#
-# Select the IGEN architecture
-#
-sim_gen=IGEN
-sim_igen_machine="-M mipsIV"
-sim_m16_machine="-M mips16,mipsIII"
-sim_igen_filter="32,64,f"
-sim_m16_filter="16"
-sim_mach_default="mips8000"
-
-case "${target}" in
-  mips*tx39*)		sim_gen=IGEN
-			sim_igen_filter="32,f"
-			sim_igen_machine="-M r3900"
-			;;
-  mips64vr43*-*-*)	sim_gen=IGEN
-			sim_igen_machine="-M mipsIV"
-			sim_mach_default="mips8000"
-			;;
-  mips64vr5*-*-*)	sim_gen=IGEN
-			sim_igen_machine="-M vr5000"
-			sim_mach_default="mips5000"
-			;;
-  mips64vr41*)		sim_gen=M16
-			sim_igen_machine="-M vr4100"
-			sim_m16_machine="-M vr4100"
-			sim_igen_filter="32,64,f"
-			sim_m16_filter="16"
-			sim_mach_default="mips4100"
-                        ;;
-  mips64vr-*-* | mips64vrel-*-*)
-			sim_gen=MULTI
-			sim_multi_configs="\
-			  vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\
-			  vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
-			  vr5000:mipsIV:32,64,f:mips4300,mips5000\
-			  vr5400:mipsIV,vr5400:32,64,f:mips5400\
-			  vr5500:mipsIV,vr5500:32,64,f:mips5500"
-			sim_multi_default=mips5000
-			;;
-  mips64*-*-*)		sim_igen_filter="32,64,f"
-			sim_gen=IGEN
-			;;
-  mips16*-*-*)		sim_gen=M16
-			sim_igen_filter="32,64,f"
-			sim_m16_filter="16"
-			;;
-  mipsisa32r2*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips32r2,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips32r2"
-			sim_igen_filter="32,f"
-			sim_mach_default="mipsisa32r2"
-			;;
-  mipsisa32*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips32,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips32"
-			sim_igen_filter="32,f"
-			sim_mach_default="mipsisa32"
-			;;
-  mipsisa64r2*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips64r2"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mipsisa64r2"
-			;;
-  mipsisa64sb1*-*-*)	sim_gen=IGEN
-		        sim_igen_machine="-M mips64,mips3d,sb1"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mips_sb1"
-			;;
-  mipsisa64*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips64,mips3d,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips64"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mipsisa64"
-			;;
-  mips*lsi*)	        sim_gen=M16
-			sim_igen_machine="-M mipsIII,mips16"
-			sim_m16_machine="-M mips16,mipsIII"
-			sim_igen_filter="32,f"
-			sim_m16_filter="16"
-			sim_mach_default="mips4000"
-                        ;;
-  mips*-*-*)		sim_gen=IGEN
-			sim_igen_filter="32,f"
-			;;
-esac
-
-# The MULTI generator can combine several simulation engines into one.
-# executable.  A configuration which uses the MULTI should set two
-# variables: ${sim_multi_configs} and ${sim_multi_default}.
-#
-# ${sim_multi_configs} is the list of engines to build.  Each
-# space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS,
-# where:
-#
-# - NAME is a C-compatible prefix for the engine,
-# - MACHINE is a -M argument,
-# - FILTER is a -F argument, and
-# - BFDMACHS is a comma-separated list of bfd machines that the
-#     simulator can run.
-#
-# Each entry will have a separate simulation engine whose prefix is
-# m32<NAME>.  If the machine list includes "mips16", there will also
-# be a mips16 engine, prefix m16<NAME>.  The mips16 engine will be
-# generated using the same machine list as the 32-bit version,
-# but the filter will be "16" instead of FILTER.
-#
-# The simulator compares the bfd mach against BFDMACHS to decide
-# which engine to use.  Entries in BFDMACHS should be bfd_mach
-# values with "bfd_mach_" removed.  ${sim_multi_default} says
-# which entry should be the default.
-if test ${sim_gen} = MULTI; then
-
-  # Simple sanity check.
-  if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then
-    { { echo "$as_me:$LINENO: error: Error in configure.in: MULTI simulator not set up correctly" >&5
-echo "$as_me: error: Error in configure.in: MULTI simulator not set up correctly" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-
-  # Start in a known state.
-  rm -f multi-include.h multi-run.c
-  sim_multi_flags=
-  sim_multi_src=
-  sim_multi_obj=multi-run.o
-  sim_multi_igen_configs=
-  sim_seen_default=no
-
-  cat << __EOF__ > multi-run.c
-/* Main entry point for MULTI simulators.
-   Copyright (C) 2003 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-   --
-
-   This file was generated by sim/mips/configure.  */
-
-#include "sim-main.h"
-#include "multi-include.h"
-
-#define SD sd
-#define CPU cpu
-
-void
-sim_engine_run (SIM_DESC sd,
-		int next_cpu_nr,
-		int nr_cpus,
-		int signal) /* ignore */
-{
-  int mach;
-
-  if (STATE_ARCHITECTURE (sd) == NULL)
-    mach = bfd_mach_${sim_multi_default};
-  else
-    mach = STATE_ARCHITECTURE (SD)->mach;
-
-  switch (mach)
-    {
-__EOF__
-
-  for fc in ${sim_multi_configs}; do
-
-    # Split up the entry.  ${c} contains the first three elements.
-    # Note: outer sqaure brackets are m4 quotes.
-    c=`echo ${fc} | sed 's/:[^:]*$//'`
-    bfdmachs=`echo ${fc} | sed 's/.*://'`
-    name=`echo ${c} | sed 's/:.*//'`
-    machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
-    filter=`echo ${c} | sed 's/.*://'`
-
-    # Build the following lists:
-    #
-    #   sim_multi_flags: all -M and -F flags used by the simulator
-    #   sim_multi_src: all makefile-generated source files
-    #   sim_multi_obj: the objects for ${sim_multi_src}
-    #   sim_multi_igen_configs: igen configuration strings.
-    #
-    # Each entry in ${sim_multi_igen_configs} is a prefix (m32
-    # or m16) followed by the NAME, MACHINE and FILTER part of
-    # the ${sim_multi_configs} entry.
-    sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
-
-    # Check whether mips16 handling is needed.
-    case ${c} in
-      *:*mips16*:*)
-	# Run igen twice, once for normal mode and once for mips16.
-	ws="m32 m16"
-
-	# The top-level function for the mips16 simulator is
-	# in a file m16${name}_run.c, generated by the
-	# tmp-run-multi Makefile rule.
-	sim_multi_src="${sim_multi_src} m16${name}_run.c"
-	sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
-	sim_multi_flags="${sim_multi_flags} -F 16"
-	;;
-      *)
-	ws=m32
-	;;
-    esac
-
-    # Now add the list of igen-generated files to ${sim_multi_src}
-    # and ${sim_multi_obj}.
-    for w in ${ws}; do
-      for base in engine icache idecode model semantics support; do
-	sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
-	sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
-	sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
-      done
-      sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}"
-    done
-
-    # Add an include for the engine.h file.  This file declares the
-    # top-level foo_engine_run() function.
-    echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
-
-    # Add case statements for this engine to sim_engine_run().
-    for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
-      echo "    case bfd_mach_${mach}:" >> multi-run.c
-      if test ${mach} = ${sim_multi_default}; then
-	echo "    default:" >> multi-run.c
-	sim_seen_default=yes
-      fi
-    done
-    echo "      ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
-      >> multi-run.c
-    echo "      break;" >> multi-run.c
-  done
-
-  # Check whether we added a 'default:' label.
-  if test ${sim_seen_default} = no; then
-    { { echo "$as_me:$LINENO: error: Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default}" >&5
-echo "$as_me: error: Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default}" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-
-  cat << __EOF__ >> multi-run.c
-    }
-}
-
-int
-mips_mach_multi (SIM_DESC sd)
-{
-  if (STATE_ARCHITECTURE (sd) == NULL)
-    return bfd_mach_${sim_multi_default};
-
-  switch (STATE_ARCHITECTURE (SD)->mach)
-    {
-__EOF__
-
-  # Add case statements for this engine to mips_mach_multi().
-  for fc in ${sim_multi_configs}; do
-
-    # Split up the entry.  ${c} contains the first three elements.
-    # Note: outer sqaure brackets are m4 quotes.
-    c=`echo ${fc} | sed 's/:[^:]*$//'`
-    bfdmachs=`echo ${fc} | sed 's/.*://'`
-
-    for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
-      echo "    case bfd_mach_${mach}:" >> multi-run.c
-    done
-  done
-
-  cat << __EOF__ >> multi-run.c
-      return (STATE_ARCHITECTURE (SD)->mach);
-    default:
-      return bfd_mach_${sim_multi_default};
-    }
-}
-__EOF__
-
-  SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI"
-else
-  # For clean-extra
-  sim_multi_src=doesnt-exist.c
-
-  if test x"${sim_mach_default}" = x""; then
-    { { echo "$as_me:$LINENO: error: Error in configure.in: \${sim_mach_default} not defined" >&5
-echo "$as_me: error: Error in configure.in: \${sim_mach_default} not defined" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}"
-fi
-sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
-sim_m16_flags=" -F ${sim_m16_filter}  ${sim_m16_machine}  ${sim_igen_smp}"
-
-
-
-
-
-
-
-
-
-#
-# Add simulated hardware devices
-#
-hw_enabled=no
-case "${target}" in
-  mips*tx39*)
-	hw_enabled=yes
-	hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio"
-	mips_extra_objs="dv-sockser.o"
-	SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1"
-	;;
-  *)
-	mips_extra_objs=""
-	;;
-esac
-
-if test x"$hw_enabled" = x"yes"; then
-  sim_hw_p=yes
-else
-  sim_hw_p=no
-fi
-if test "$hw_devices"; then
-  hardware="core pal glue"
-else
-  hardware="core pal glue $hw_extra_devices"
-fi
-sim_hw_cflags="-DWITH_HW=1"
-sim_hw="$hardware"
-sim_hw_objs="\$(SIM_COMMON_HW_OBJS) `echo $sim_hw | sed -e 's/\([^ ][^ ]*\)/dv-\1.o/g'`"
-# Check whether --enable-sim-hardware or --disable-sim-hardware was given.
-if test "${enable_sim_hardware+set}" = set; then
-  enableval="$enable_sim_hardware"
-
-case "${enableval}" in
-  yes)	sim_hw_p=yes;;
-  no)	sim_hw_p=no;;
-  ,*)   sim_hw_p=yes; hardware="${hardware} `echo ${enableval} | sed -e 's/,/ /'`";;
-  *,)   sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'` ${hardware}";;
-  *)	sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'`"'';;
-esac
-if test "$sim_hw_p" != yes; then
-  sim_hw_objs=
-  sim_hw_cflags="-DWITH_HW=0"
-  sim_hw=
-else
-  sim_hw_cflags="-DWITH_HW=1"
-  # remove duplicates
-  sim_hw=""
-  sim_hw_objs="\$(SIM_COMMON_HW_OBJS)"
-  for i in $hardware ; do
-    case " $sim_hw " in
-      *" $i "*) ;;
-      *) sim_hw="$sim_hw $i" ; sim_hw_objs="$sim_hw_objs dv-$i.o";;
-    esac
-  done
-fi
-if test x"$silent" != x"yes" && test "$sim_hw_p" = "yes"; then
-  echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs"
-fi
-else
-
-if test "$sim_hw_p" != yes; then
-  sim_hw_objs=
-  sim_hw_cflags="-DWITH_HW=0"
-  sim_hw=
-fi
-if test x"$silent" != x"yes"; then
-  echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs"
-fi
-fi;
-
-
-
-# Choose simulator engine
-case "${target}" in
-  *)    mips_igen_engine="engine.o"
-	;;
-esac
-
-
-
-echo "$as_me:$LINENO: checking for X" >&5
-echo $ECHO_N "checking for X... $ECHO_C" >&6
-
-
-# Check whether --with-x or --without-x was given.
-if test "${with_x+set}" = set; then
-  withval="$with_x"
-
-fi;
-# $have_x is `yes', `no', `disabled', or empty when we do not yet know.
-if test "x$with_x" = xno; then
-  # The user explicitly disabled X.
-  have_x=disabled
-else
-  if test "x$x_includes" != xNONE && test "x$x_libraries" != xNONE; then
-    # Both variables are already set.
-    have_x=yes
-  else
-    if test "${ac_cv_have_x+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  # One or both of the vars are not set, and there is no cached value.
-ac_x_includes=no ac_x_libraries=no
-rm -fr conftest.dir
-if mkdir conftest.dir; then
-  cd conftest.dir
-  # Make sure to not put "make" in the Imakefile rules, since we grep it out.
-  cat >Imakefile <<'_ACEOF'
-acfindx:
-	@echo 'ac_im_incroot="${INCROOT}"; ac_im_usrlibdir="${USRLIBDIR}"; ac_im_libdir="${LIBDIR}"'
-_ACEOF
-  if (xmkmf) >/dev/null 2>/dev/null && test -f Makefile; then
-    # GNU make sometimes prints "make[1]: Entering...", which would confuse us.
-    eval `${MAKE-make} acfindx 2>/dev/null | grep -v make`
-    # Open Windows xmkmf reportedly sets LIBDIR instead of USRLIBDIR.
-    for ac_extension in a so sl; do
-      if test ! -f $ac_im_usrlibdir/libX11.$ac_extension &&
-	 test -f $ac_im_libdir/libX11.$ac_extension; then
-	ac_im_usrlibdir=$ac_im_libdir; break
-      fi
-    done
-    # Screen out bogus values from the imake configuration.  They are
-    # bogus both because they are the default anyway, and because
-    # using them would break gcc on systems where it needs fixed includes.
-    case $ac_im_incroot in
-	/usr/include) ;;
-	*) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;;
-    esac
-    case $ac_im_usrlibdir in
-	/usr/lib | /lib) ;;
-	*) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;;
-    esac
-  fi
-  cd ..
-  rm -fr conftest.dir
-fi
-
-# Standard set of common directories for X headers.
-# Check X11 before X11Rn because it is often a symlink to the current release.
-ac_x_header_dirs='
-/usr/X11/include
-/usr/X11R6/include
-/usr/X11R5/include
-/usr/X11R4/include
-
-/usr/include/X11
-/usr/include/X11R6
-/usr/include/X11R5
-/usr/include/X11R4
-
-/usr/local/X11/include
-/usr/local/X11R6/include
-/usr/local/X11R5/include
-/usr/local/X11R4/include
-
-/usr/local/include/X11
-/usr/local/include/X11R6
-/usr/local/include/X11R5
-/usr/local/include/X11R4
-
-/usr/X386/include
-/usr/x386/include
-/usr/XFree86/include/X11
-
-/usr/include
-/usr/local/include
-/usr/unsupported/include
-/usr/athena/include
-/usr/local/x11r5/include
-/usr/lpp/Xamples/include
-
-/usr/openwin/include
-/usr/openwin/share/include'
-
-if test "$ac_x_includes" = no; then
-  # Guess where to find include files, by looking for Intrinsic.h.
-  # First, try using that file with no special directory specified.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <X11/Intrinsic.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # We can compile using X headers with no special include directory.
-ac_x_includes=
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  for ac_dir in $ac_x_header_dirs; do
-  if test -r "$ac_dir/X11/Intrinsic.h"; then
-    ac_x_includes=$ac_dir
-    break
-  fi
-done
-fi
-rm -f conftest.err conftest.$ac_ext
-fi # $ac_x_includes = no
-
-if test "$ac_x_libraries" = no; then
-  # Check for the libraries.
-  # See if we find them without any special options.
-  # Don't add to $LIBS permanently.
-  ac_save_LIBS=$LIBS
-  LIBS="-lXt $LIBS"
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <X11/Intrinsic.h>
-int
-main ()
-{
-XtMalloc (0)
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  LIBS=$ac_save_LIBS
-# We can link X programs with no special library path.
-ac_x_libraries=
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-LIBS=$ac_save_LIBS
-for ac_dir in `echo "$ac_x_includes $ac_x_header_dirs" | sed s/include/lib/g`
-do
-  # Don't even attempt the hair of trying to link an X program!
-  for ac_extension in a so sl; do
-    if test -r $ac_dir/libXt.$ac_extension; then
-      ac_x_libraries=$ac_dir
-      break 2
-    fi
-  done
-done
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi # $ac_x_libraries = no
-
-if test "$ac_x_includes" = no || test "$ac_x_libraries" = no; then
-  # Didn't find X anywhere.  Cache the known absence of X.
-  ac_cv_have_x="have_x=no"
-else
-  # Record where we found X for the cache.
-  ac_cv_have_x="have_x=yes \
-		ac_x_includes=$ac_x_includes ac_x_libraries=$ac_x_libraries"
-fi
-fi
-
-  fi
-  eval "$ac_cv_have_x"
-fi # $with_x != no
-
-if test "$have_x" != yes; then
-  echo "$as_me:$LINENO: result: $have_x" >&5
-echo "${ECHO_T}$have_x" >&6
-  no_x=yes
-else
-  # If each of the values was on the command line, it overrides each guess.
-  test "x$x_includes" = xNONE && x_includes=$ac_x_includes
-  test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries
-  # Update the cache value to reflect the command line values.
-  ac_cv_have_x="have_x=yes \
-		ac_x_includes=$x_includes ac_x_libraries=$x_libraries"
-  echo "$as_me:$LINENO: result: libraries $x_libraries, headers $x_includes" >&5
-echo "${ECHO_T}libraries $x_libraries, headers $x_includes" >&6
-fi
-
-mips_extra_libs=""
-
-
-
-
-
-
-for ac_header in string.h strings.h stdlib.h stdlib.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-echo "$as_me:$LINENO: checking for fabs in -lm" >&5
-echo $ECHO_N "checking for fabs in -lm... $ECHO_C" >&6
-if test "${ac_cv_lib_m_fabs+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lm  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char fabs ();
-int
-main ()
-{
-fabs ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_m_fabs=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_m_fabs=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_m_fabs" >&5
-echo "${ECHO_T}$ac_cv_lib_m_fabs" >&6
-if test $ac_cv_lib_m_fabs = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBM 1
-_ACEOF
-
-  LIBS="-lm $LIBS"
-
-fi
-
-
-
-
-for ac_func in aint anint sqrt
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-
-ac_sources="$sim_link_files"
-ac_dests="$sim_link_links"
-while test -n "$ac_sources"; do
-  set $ac_dests; ac_dest=$1; shift; ac_dests=$*
-  set $ac_sources; ac_source=$1; shift; ac_sources=$*
-  ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
-done
-          ac_config_links="$ac_config_links $ac_config_links_1"
-
-cgen_breaks=""
-if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
-cgen_breaks="break cgen_rtx_error";
-fi
-
-          ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
-
-          ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
-
-          ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
-
-          ac_config_commands="$ac_config_commands Makefile"
-
-          ac_config_commands="$ac_config_commands stamp-h"
-
-cat >confcache <<\_ACEOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs, see configure's option --config-cache.
-# It is not useful on other systems.  If it contains results you don't
-# want to keep, you may remove or edit it.
-#
-# config.status only pays attention to the cache file if you give it
-# the --recheck option to rerun configure.
-#
-# `ac_cv_env_foo' variables (set or unset) will be overridden when
-# loading this file, other *unset* `ac_cv_foo' will be assigned the
-# following values.
-
-_ACEOF
-
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
-{
-  (set) 2>&1 |
-    case `(ac_space=' '; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      # `set' does not quote correctly, so add quotes (double-quote
-      # substitution turns \\\\ into \\, and sed turns \\ into \).
-      sed -n \
-	"s/'/'\\\\''/g;
-	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
-      ;;
-    *)
-      # `set' quotes correctly as required by POSIX, so do not add quotes.
-      sed -n \
-	"s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
-      ;;
-    esac;
-} |
-  sed '
-     t clear
-     : clear
-     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
-     t end
-     /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
-     : end' >>confcache
-if diff $cache_file confcache >/dev/null 2>&1; then :; else
-  if test -w $cache_file; then
-    test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
-    cat confcache >$cache_file
-  else
-    echo "not updating unwritable cache $cache_file"
-  fi
-fi
-rm -f confcache
-
-test "x$prefix" = xNONE && prefix=$ac_default_prefix
-# Let make expand exec_prefix.
-test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
-
-# VPATH may cause trouble with some makes, so we remove $(srcdir),
-# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
-# trailing colons and then remove the whole line if VPATH becomes empty
-# (actually we leave an empty line to preserve line numbers).
-if test "x$srcdir" = x.; then
-  ac_vpsub='/^[	 ]*VPATH[	 ]*=/{
-s/:*\$(srcdir):*/:/;
-s/:*\${srcdir}:*/:/;
-s/:*@srcdir@:*/:/;
-s/^\([^=]*=[	 ]*\):*/\1/;
-s/:*$//;
-s/^[^=]*=[	 ]*$//;
-}'
-fi
-
-DEFS=-DHAVE_CONFIG_H
-
-ac_libobjs=
-ac_ltlibobjs=
-for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
-  # 1. Remove the extension, and $U if already installed.
-  ac_i=`echo "$ac_i" |
-	 sed 's/\$U\././;s/\.o$//;s/\.obj$//'`
-  # 2. Add them.
-  ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext"
-  ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo'
-done
-LIBOBJS=$ac_libobjs
-
-LTLIBOBJS=$ac_ltlibobjs
-
-
-
-: ${CONFIG_STATUS=./config.status}
-ac_clean_files_save=$ac_clean_files
-ac_clean_files="$ac_clean_files $CONFIG_STATUS"
-{ echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
-echo "$as_me: creating $CONFIG_STATUS" >&6;}
-cat >$CONFIG_STATUS <<_ACEOF
-#! $SHELL
-# Generated by $as_me.
-# Run this file to recreate the current configuration.
-# Compiler output produced by configure, useful for debugging
-# configure, is in config.log if it exists.
-
-debug=false
-ac_cs_recheck=false
-ac_cs_silent=false
-SHELL=\${CONFIG_SHELL-$SHELL}
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-## --------------------- ##
-## M4sh Initialization.  ##
-## --------------------- ##
-
-# Be Bourne compatible
-if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
-  emulate sh
-  NULLCMD=:
-  # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
-  # is contrary to our usage.  Disable this feature.
-  alias -g '${1+"$@"}'='"$@"'
-elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
-  set -o posix
-fi
-DUALCASE=1; export DUALCASE # for MKS sh
-
-# Support unset when possible.
-if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
-  as_unset=unset
-else
-  as_unset=false
-fi
-
-
-# Work around bugs in pre-3.0 UWIN ksh.
-$as_unset ENV MAIL MAILPATH
-PS1='$ '
-PS2='> '
-PS4='+ '
-
-# NLS nuisances.
-for as_var in \
-  LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
-  LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
-  LC_TELEPHONE LC_TIME
-do
-  if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
-    eval $as_var=C; export $as_var
-  else
-    $as_unset $as_var
-  fi
-done
-
-# Required to use basename.
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
-  as_basename=basename
-else
-  as_basename=false
-fi
-
-
-# Name of the executable.
-as_me=`$as_basename "$0" ||
-$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
-	 X"$0" : 'X\(//\)$' \| \
-	 X"$0" : 'X\(/\)$' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X/"$0" |
-    sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
-  	  /^X\/\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\/\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-
-
-# PATH needs CR, and LINENO needs CR and PATH.
-# Avoid depending upon Character Ranges.
-as_cr_letters='abcdefghijklmnopqrstuvwxyz'
-as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
-as_cr_Letters=$as_cr_letters$as_cr_LETTERS
-as_cr_digits='0123456789'
-as_cr_alnum=$as_cr_Letters$as_cr_digits
-
-# The user is always right.
-if test "${PATH_SEPARATOR+set}" != set; then
-  echo "#! /bin/sh" >conf$$.sh
-  echo  "exit 0"   >>conf$$.sh
-  chmod +x conf$$.sh
-  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
-    PATH_SEPARATOR=';'
-  else
-    PATH_SEPARATOR=:
-  fi
-  rm -f conf$$.sh
-fi
-
-
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2"  || {
-  # Find who we are.  Look in the path if we contain no path at all
-  # relative or not.
-  case $0 in
-    *[\\/]* ) as_myself=$0 ;;
-    *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
-done
-
-       ;;
-  esac
-  # We did not find ourselves, most probably we were run as `sh COMMAND'
-  # in which case we are not to be found in the path.
-  if test "x$as_myself" = x; then
-    as_myself=$0
-  fi
-  if test ! -f "$as_myself"; then
-    { { echo "$as_me:$LINENO: error: cannot find myself; rerun with an absolute path" >&5
-echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  case $CONFIG_SHELL in
-  '')
-    as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for as_base in sh bash ksh sh5; do
-	 case $as_dir in
-	 /*)
-	   if ("$as_dir/$as_base" -c '
-  as_lineno_1=$LINENO
-  as_lineno_2=$LINENO
-  as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
-  test "x$as_lineno_1" != "x$as_lineno_2" &&
-  test "x$as_lineno_3"  = "x$as_lineno_2" ') 2>/dev/null; then
-	     $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
-	     $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
-	     CONFIG_SHELL=$as_dir/$as_base
-	     export CONFIG_SHELL
-	     exec "$CONFIG_SHELL" "$0" ${1+"$@"}
-	   fi;;
-	 esac
-       done
-done
-;;
-  esac
-
-  # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
-  # uniformly replaced by the line number.  The first 'sed' inserts a
-  # line-number line before each line; the second 'sed' does the real
-  # work.  The second script uses 'N' to pair each line-number line
-  # with the numbered line, and appends trailing '-' during
-  # substitution so that $LINENO is not a special case at line end.
-  # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
-  # second 'sed' script.  Blame Lee E. McMahon for sed's syntax.  :-)
-  sed '=' <$as_myself |
-    sed '
-      N
-      s,$,-,
-      : loop
-      s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
-      t loop
-      s,-$,,
-      s,^['$as_cr_digits']*\n,,
-    ' >$as_me.lineno &&
-  chmod +x $as_me.lineno ||
-    { { echo "$as_me:$LINENO: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&5
-echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2;}
-   { (exit 1); exit 1; }; }
-
-  # Don't try to exec as it changes $[0], causing all sort of problems
-  # (the dirname of $[0] is not the place where we might find the
-  # original and so on.  Autoconf is especially sensible to this).
-  . ./$as_me.lineno
-  # Exit status is that of the last command.
-  exit
-}
-
-
-case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
-  *c*,-n*) ECHO_N= ECHO_C='
-' ECHO_T='	' ;;
-  *c*,*  ) ECHO_N=-n ECHO_C= ECHO_T= ;;
-  *)       ECHO_N= ECHO_C='\c' ECHO_T= ;;
-esac
-
-if expr a : '\(a\)' >/dev/null 2>&1; then
-  as_expr=expr
-else
-  as_expr=false
-fi
-
-rm -f conf$$ conf$$.exe conf$$.file
-echo >conf$$.file
-if ln -s conf$$.file conf$$ 2>/dev/null; then
-  # We could just check for DJGPP; but this test a) works b) is more generic
-  # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
-  if test -f conf$$.exe; then
-    # Don't use ln at all; we don't have any links
-    as_ln_s='cp -p'
-  else
-    as_ln_s='ln -s'
-  fi
-elif ln conf$$.file conf$$ 2>/dev/null; then
-  as_ln_s=ln
-else
-  as_ln_s='cp -p'
-fi
-rm -f conf$$ conf$$.exe conf$$.file
-
-if mkdir -p . 2>/dev/null; then
-  as_mkdir_p=:
-else
-  test -d ./-p && rmdir ./-p
-  as_mkdir_p=false
-fi
-
-as_executable_p="test -f"
-
-# Sed expression to map a string onto a valid CPP name.
-as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
-
-# Sed expression to map a string onto a valid variable name.
-as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
-
-
-# IFS
-# We need space, tab and new line, in precisely that order.
-as_nl='
-'
-IFS=" 	$as_nl"
-
-# CDPATH.
-$as_unset CDPATH
-
-exec 6>&1
-
-# Open the log real soon, to keep \$[0] and so on meaningful, and to
-# report actual input values of CONFIG_FILES etc. instead of their
-# values after options handling.  Logging --version etc. is OK.
-exec 5>>config.log
-{
-  echo
-  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
-## Running $as_me. ##
-_ASBOX
-} >&5
-cat >&5 <<_CSEOF
-
-This file was extended by $as_me, which was
-generated by GNU Autoconf 2.59.  Invocation command line was
-
-  CONFIG_FILES    = $CONFIG_FILES
-  CONFIG_HEADERS  = $CONFIG_HEADERS
-  CONFIG_LINKS    = $CONFIG_LINKS
-  CONFIG_COMMANDS = $CONFIG_COMMANDS
-  $ $0 $@
-
-_CSEOF
-echo "on `(hostname || uname -n) 2>/dev/null | sed 1q`" >&5
-echo >&5
-_ACEOF
-
-# Files that config.status was made for.
-if test -n "$ac_config_files"; then
-  echo "config_files=\"$ac_config_files\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_headers"; then
-  echo "config_headers=\"$ac_config_headers\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_links"; then
-  echo "config_links=\"$ac_config_links\"" >>$CONFIG_STATUS
-fi
-
-if test -n "$ac_config_commands"; then
-  echo "config_commands=\"$ac_config_commands\"" >>$CONFIG_STATUS
-fi
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-ac_cs_usage="\
-\`$as_me' instantiates files from templates according to the
-current configuration.
-
-Usage: $0 [OPTIONS] [FILE]...
-
-  -h, --help       print this help, then exit
-  -V, --version    print version number, then exit
-  -q, --quiet      do not print progress messages
-  -d, --debug      don't remove temporary files
-      --recheck    update $as_me by reconfiguring in the same conditions
-  --file=FILE[:TEMPLATE]
-		   instantiate the configuration file FILE
-  --header=FILE[:TEMPLATE]
-		   instantiate the configuration header FILE
-
-Configuration files:
-$config_files
-
-Configuration headers:
-$config_headers
-
-Configuration links:
-$config_links
-
-Configuration commands:
-$config_commands
-
-Report bugs to <bug-autoconf@gnu.org>."
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-ac_cs_version="\\
-config.status
-configured by $0, generated by GNU Autoconf 2.59,
-  with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
-
-Copyright (C) 2003 Free Software Foundation, Inc.
-This config.status script is free software; the Free Software Foundation
-gives unlimited permission to copy, distribute and modify it."
-srcdir=$srcdir
-INSTALL="$INSTALL"
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-# If no file are specified by the user, then we need to provide default
-# value.  By we need to know if files were specified by the user.
-ac_need_defaults=:
-while test $# != 0
-do
-  case $1 in
-  --*=*)
-    ac_option=`expr "x$1" : 'x\([^=]*\)='`
-    ac_optarg=`expr "x$1" : 'x[^=]*=\(.*\)'`
-    ac_shift=:
-    ;;
-  -*)
-    ac_option=$1
-    ac_optarg=$2
-    ac_shift=shift
-    ;;
-  *) # This is not an option, so the user has probably given explicit
-     # arguments.
-     ac_option=$1
-     ac_need_defaults=false;;
-  esac
-
-  case $ac_option in
-  # Handling of the options.
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
-    ac_cs_recheck=: ;;
-  --version | --vers* | -V )
-    echo "$ac_cs_version"; exit 0 ;;
-  --he | --h)
-    # Conflict between --help and --header
-    { { echo "$as_me:$LINENO: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: ambiguous option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; };;
-  --help | --hel | -h )
-    echo "$ac_cs_usage"; exit 0 ;;
-  --debug | --d* | -d )
-    debug=: ;;
-  --file | --fil | --fi | --f )
-    $ac_shift
-    CONFIG_FILES="$CONFIG_FILES $ac_optarg"
-    ac_need_defaults=false;;
-  --header | --heade | --head | --hea )
-    $ac_shift
-    CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
-    ac_need_defaults=false;;
-  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
-  | -silent | --silent | --silen | --sile | --sil | --si | --s)
-    ac_cs_silent=: ;;
-
-  # This is an error.
-  -*) { { echo "$as_me:$LINENO: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&5
-echo "$as_me: error: unrecognized option: $1
-Try \`$0 --help' for more information." >&2;}
-   { (exit 1); exit 1; }; } ;;
-
-  *) ac_config_targets="$ac_config_targets $1" ;;
-
-  esac
-  shift
-done
-
-ac_configure_extra_args=
-
-if $ac_cs_silent; then
-  exec 6>/dev/null
-  ac_configure_extra_args="$ac_configure_extra_args --silent"
-fi
-
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-if \$ac_cs_recheck; then
-  echo "running $SHELL $0 " $ac_configure_args \$ac_configure_extra_args " --no-create --no-recursion" >&6
-  exec $SHELL $0 $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
-fi
-
-_ACEOF
-
-
-
-
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_config_target in $ac_config_targets
-do
-  case "$ac_config_target" in
-  # Handling of arguments.
-  "Makefile.sim" ) CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
-  "Make-common.sim" ) CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
-  ".gdbinit" ) CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
-  "$ac_config_links_1" ) CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
-  "Makefile" ) CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
-  "stamp-h" ) CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
-  "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
-  *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
-echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
-   { (exit 1); exit 1; }; };;
-  esac
-done
-
-# If the user did not use the arguments to specify the items to instantiate,
-# then the envvar interface is used.  Set only those that are not.
-# We use the long form for the default assignment because of an extremely
-# bizarre bug on SunOS 4.1.3.
-if $ac_need_defaults; then
-  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
-  test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
-  test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
-  test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
-fi
-
-# Have a temporary directory for convenience.  Make it in the build tree
-# simply because there is no reason to put it here, and in addition,
-# creating and moving files from /tmp can sometimes cause problems.
-# Create a temporary directory, and hook for its removal unless debugging.
-$debug ||
-{
-  trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
-  trap '{ (exit 1); exit 1; }' 1 2 13 15
-}
-
-# Create a (secure) tmp directory for tmp files.
-
-{
-  tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
-  test -n "$tmp" && test -d "$tmp"
-}  ||
-{
-  tmp=./confstat$$-$RANDOM
-  (umask 077 && mkdir $tmp)
-} ||
-{
-   echo "$me: cannot create a temporary directory in ." >&2
-   { (exit 1); exit 1; }
-}
-
-_ACEOF
-
-cat >>$CONFIG_STATUS <<_ACEOF
-
-#
-# CONFIG_FILES section.
-#
-
-# No need to generate the scripts if there are no CONFIG_FILES.
-# This happens for instance when ./config.status config.h
-if test -n "\$CONFIG_FILES"; then
-  # Protect against being on the right side of a sed subst in config.status.
-  sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g;
-   s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF
-s,@SHELL@,$SHELL,;t t
-s,@PATH_SEPARATOR@,$PATH_SEPARATOR,;t t
-s,@PACKAGE_NAME@,$PACKAGE_NAME,;t t
-s,@PACKAGE_TARNAME@,$PACKAGE_TARNAME,;t t
-s,@PACKAGE_VERSION@,$PACKAGE_VERSION,;t t
-s,@PACKAGE_STRING@,$PACKAGE_STRING,;t t
-s,@PACKAGE_BUGREPORT@,$PACKAGE_BUGREPORT,;t t
-s,@exec_prefix@,$exec_prefix,;t t
-s,@prefix@,$prefix,;t t
-s,@program_transform_name@,$program_transform_name,;t t
-s,@bindir@,$bindir,;t t
-s,@sbindir@,$sbindir,;t t
-s,@libexecdir@,$libexecdir,;t t
-s,@datadir@,$datadir,;t t
-s,@sysconfdir@,$sysconfdir,;t t
-s,@sharedstatedir@,$sharedstatedir,;t t
-s,@localstatedir@,$localstatedir,;t t
-s,@libdir@,$libdir,;t t
-s,@includedir@,$includedir,;t t
-s,@oldincludedir@,$oldincludedir,;t t
-s,@infodir@,$infodir,;t t
-s,@mandir@,$mandir,;t t
-s,@build_alias@,$build_alias,;t t
-s,@host_alias@,$host_alias,;t t
-s,@target_alias@,$target_alias,;t t
-s,@DEFS@,$DEFS,;t t
-s,@ECHO_C@,$ECHO_C,;t t
-s,@ECHO_N@,$ECHO_N,;t t
-s,@ECHO_T@,$ECHO_T,;t t
-s,@LIBS@,$LIBS,;t t
-s,@sim_environment@,$sim_environment,;t t
-s,@sim_alignment@,$sim_alignment,;t t
-s,@sim_assert@,$sim_assert,;t t
-s,@sim_bitsize@,$sim_bitsize,;t t
-s,@sim_endian@,$sim_endian,;t t
-s,@sim_hostendian@,$sim_hostendian,;t t
-s,@sim_float@,$sim_float,;t t
-s,@sim_scache@,$sim_scache,;t t
-s,@sim_default_model@,$sim_default_model,;t t
-s,@sim_hw_cflags@,$sim_hw_cflags,;t t
-s,@sim_hw_objs@,$sim_hw_objs,;t t
-s,@sim_hw@,$sim_hw,;t t
-s,@sim_inline@,$sim_inline,;t t
-s,@sim_packages@,$sim_packages,;t t
-s,@sim_regparm@,$sim_regparm,;t t
-s,@sim_reserved_bits@,$sim_reserved_bits,;t t
-s,@sim_smp@,$sim_smp,;t t
-s,@sim_stdcall@,$sim_stdcall,;t t
-s,@sim_xor_endian@,$sim_xor_endian,;t t
-s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
-s,@WERROR_CFLAGS@,$WERROR_CFLAGS,;t t
-s,@build@,$build,;t t
-s,@build_cpu@,$build_cpu,;t t
-s,@build_vendor@,$build_vendor,;t t
-s,@build_os@,$build_os,;t t
-s,@host@,$host,;t t
-s,@host_cpu@,$host_cpu,;t t
-s,@host_vendor@,$host_vendor,;t t
-s,@host_os@,$host_os,;t t
-s,@target@,$target,;t t
-s,@target_cpu@,$target_cpu,;t t
-s,@target_vendor@,$target_vendor,;t t
-s,@target_os@,$target_os,;t t
-s,@CC@,$CC,;t t
-s,@CFLAGS@,$CFLAGS,;t t
-s,@LDFLAGS@,$LDFLAGS,;t t
-s,@CPPFLAGS@,$CPPFLAGS,;t t
-s,@ac_ct_CC@,$ac_ct_CC,;t t
-s,@EXEEXT@,$EXEEXT,;t t
-s,@OBJEXT@,$OBJEXT,;t t
-s,@INSTALL_PROGRAM@,$INSTALL_PROGRAM,;t t
-s,@INSTALL_SCRIPT@,$INSTALL_SCRIPT,;t t
-s,@INSTALL_DATA@,$INSTALL_DATA,;t t
-s,@CC_FOR_BUILD@,$CC_FOR_BUILD,;t t
-s,@HDEFINES@,$HDEFINES,;t t
-s,@AR@,$AR,;t t
-s,@RANLIB@,$RANLIB,;t t
-s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
-s,@USE_NLS@,$USE_NLS,;t t
-s,@LIBINTL@,$LIBINTL,;t t
-s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t
-s,@INCINTL@,$INCINTL,;t t
-s,@XGETTEXT@,$XGETTEXT,;t t
-s,@GMSGFMT@,$GMSGFMT,;t t
-s,@POSUB@,$POSUB,;t t
-s,@CATALOGS@,$CATALOGS,;t t
-s,@DATADIRNAME@,$DATADIRNAME,;t t
-s,@INSTOBJEXT@,$INSTOBJEXT,;t t
-s,@GENCAT@,$GENCAT,;t t
-s,@CATOBJEXT@,$CATOBJEXT,;t t
-s,@CPP@,$CPP,;t t
-s,@EGREP@,$EGREP,;t t
-s,@MAINT@,$MAINT,;t t
-s,@sim_bswap@,$sim_bswap,;t t
-s,@sim_cflags@,$sim_cflags,;t t
-s,@sim_debug@,$sim_debug,;t t
-s,@sim_stdio@,$sim_stdio,;t t
-s,@sim_trace@,$sim_trace,;t t
-s,@sim_profile@,$sim_profile,;t t
-s,@SIM_SUBTARGET@,$SIM_SUBTARGET,;t t
-s,@sim_igen_flags@,$sim_igen_flags,;t t
-s,@sim_m16_flags@,$sim_m16_flags,;t t
-s,@sim_gen@,$sim_gen,;t t
-s,@sim_multi_flags@,$sim_multi_flags,;t t
-s,@sim_multi_igen_configs@,$sim_multi_igen_configs,;t t
-s,@sim_multi_src@,$sim_multi_src,;t t
-s,@sim_multi_obj@,$sim_multi_obj,;t t
-s,@mips_extra_objs@,$mips_extra_objs,;t t
-s,@mips_igen_engine@,$mips_igen_engine,;t t
-s,@mips_extra_libs@,$mips_extra_libs,;t t
-s,@cgen_breaks@,$cgen_breaks,;t t
-s,@LIBOBJS@,$LIBOBJS,;t t
-s,@LTLIBOBJS@,$LTLIBOBJS,;t t
-CEOF
-
-_ACEOF
-
-  cat >>$CONFIG_STATUS <<\_ACEOF
-  # Split the substitutions into bite-sized pieces for seds with
-  # small command number limits, like on Digital OSF/1 and HP-UX.
-  ac_max_sed_lines=48
-  ac_sed_frag=1 # Number of current file.
-  ac_beg=1 # First line for current file.
-  ac_end=$ac_max_sed_lines # Line after last line for current file.
-  ac_more_lines=:
-  ac_sed_cmds=
-  while $ac_more_lines; do
-    if test $ac_beg -gt 1; then
-      sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    else
-      sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
-    fi
-    if test ! -s $tmp/subs.frag; then
-      ac_more_lines=false
-    else
-      # The purpose of the label and of the branching condition is to
-      # speed up the sed processing (if there are no `@' at all, there
-      # is no need to browse any of the substitutions).
-      # These are the two extra sed commands mentioned above.
-      (echo ':t
-  /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
-      if test -z "$ac_sed_cmds"; then
-	ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
-      else
-	ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
-      fi
-      ac_sed_frag=`expr $ac_sed_frag + 1`
-      ac_beg=$ac_end
-      ac_end=`expr $ac_end + $ac_max_sed_lines`
-    fi
-  done
-  if test -z "$ac_sed_cmds"; then
-    ac_sed_cmds=cat
-  fi
-fi # test -n "$CONFIG_FILES"
-
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
-  ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_file" : 'X\(//\)[^/]' \| \
-	 X"$ac_file" : 'X\(//\)$' \| \
-	 X"$ac_file" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $INSTALL in
-  [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
-  *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
-  esac
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    configure_input=
-  else
-    configure_input="$ac_file.  "
-  fi
-  configure_input=$configure_input"Generated from `echo $ac_file_in |
-				     sed 's,.*/,,'` by configure."
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 echo "$f";;
-      *) # Relative
-	 if test -f "$f"; then
-	   # Build tree
-	   echo "$f"
-	 elif test -f "$srcdir/$f"; then
-	   # Source tree
-	   echo "$srcdir/$f"
-	 else
-	   # /dev/null tree
-	   { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-_ACEOF
-cat >>$CONFIG_STATUS <<_ACEOF
-  sed "$ac_vpsub
-$extrasub
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-:t
-/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
-s,@configure_input@,$configure_input,;t t
-s,@srcdir@,$ac_srcdir,;t t
-s,@abs_srcdir@,$ac_abs_srcdir,;t t
-s,@top_srcdir@,$ac_top_srcdir,;t t
-s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
-s,@builddir@,$ac_builddir,;t t
-s,@abs_builddir@,$ac_abs_builddir,;t t
-s,@top_builddir@,$ac_top_builddir,;t t
-s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
-s,@INSTALL@,$ac_INSTALL,;t t
-" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
-  rm -f $tmp/stdin
-  if test x"$ac_file" != x-; then
-    mv $tmp/out $ac_file
-  else
-    cat $tmp/out
-    rm -f $tmp/out
-  fi
-
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_HEADER section.
-#
-
-# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
-# NAME is the cpp macro being defined and VALUE is the value it is being given.
-#
-# ac_d sets the value in "#define NAME VALUE" lines.
-ac_dA='s,^\([	 ]*\)#\([	 ]*define[	 ][	 ]*\)'
-ac_dB='[	 ].*$,\1#\2'
-ac_dC=' '
-ac_dD=',;t'
-# ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
-ac_uA='s,^\([	 ]*\)#\([	 ]*\)undef\([	 ][	 ]*\)'
-ac_uB='$,\1#\2define\3'
-ac_uC=' '
-ac_uD=',;t'
-
-for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue
-  # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
-  case $ac_file in
-  - | *:- | *:-:* ) # input from stdin
-	cat >$tmp/stdin
-	ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
-	ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
-  * )   ac_file_in=$ac_file.in ;;
-  esac
-
-  test x"$ac_file" != x- && { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-
-  # First look for the input files in the build tree, otherwise in the
-  # src tree.
-  ac_file_inputs=`IFS=:
-    for f in $ac_file_in; do
-      case $f in
-      -) echo $tmp/stdin ;;
-      [\\/$]*)
-	 # Absolute (can't be DOS-style, as IFS=:)
-	 test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 # Do quote $f, to prevent DOS paths from being IFS'd.
-	 echo "$f";;
-      *) # Relative
-	 if test -f "$f"; then
-	   # Build tree
-	   echo "$f"
-	 elif test -f "$srcdir/$f"; then
-	   # Source tree
-	   echo "$srcdir/$f"
-	 else
-	   # /dev/null tree
-	   { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
-echo "$as_me: error: cannot find input file: $f" >&2;}
-   { (exit 1); exit 1; }; }
-	 fi;;
-      esac
-    done` || { (exit 1); exit 1; }
-  # Remove the trailing spaces.
-  sed 's/[	 ]*$//' $ac_file_inputs >$tmp/in
-
-_ACEOF
-
-# Transform confdefs.h into two sed scripts, `conftest.defines' and
-# `conftest.undefs', that substitutes the proper values into
-# config.h.in to produce config.h.  The first handles `#define'
-# templates, and the second `#undef' templates.
-# And first: Protect against being on the right side of a sed subst in
-# config.status.  Protect against being in an unquoted here document
-# in config.status.
-rm -f conftest.defines conftest.undefs
-# Using a here document instead of a string reduces the quoting nightmare.
-# Putting comments in sed scripts is not portable.
-#
-# `end' is used to avoid that the second main sed command (meant for
-# 0-ary CPP macros) applies to n-ary macro definitions.
-# See the Autoconf documentation for `clear'.
-cat >confdef2sed.sed <<\_ACEOF
-s/[\\&,]/\\&/g
-s,[\\$`],\\&,g
-t clear
-: clear
-s,^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 (][^	 (]*\)\(([^)]*)\)[	 ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp
-t end
-s,^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 ][^	 ]*\)[	 ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp
-: end
-_ACEOF
-# If some macros were called several times there might be several times
-# the same #defines, which is useless.  Nevertheless, we may not want to
-# sort them, since we want the *last* AC-DEFINE to be honored.
-uniq confdefs.h | sed -n -f confdef2sed.sed >conftest.defines
-sed 's/ac_d/ac_u/g' conftest.defines >conftest.undefs
-rm -f confdef2sed.sed
-
-# This sed command replaces #undef with comments.  This is necessary, for
-# example, in the case of _POSIX_SOURCE, which is predefined and required
-# on some systems where configure will not decide to define it.
-cat >>conftest.undefs <<\_ACEOF
-s,^[	 ]*#[	 ]*undef[	 ][	 ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */,
-_ACEOF
-
-# Break up conftest.defines because some shells have a limit on the size
-# of here documents, and old seds have small limits too (100 cmds).
-echo '  # Handle all the #define templates only if necessary.' >>$CONFIG_STATUS
-echo '  if grep "^[	 ]*#[	 ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS
-echo '  # If there are no defines, we may have an empty if/fi' >>$CONFIG_STATUS
-echo '  :' >>$CONFIG_STATUS
-rm -f conftest.tail
-while grep . conftest.defines >/dev/null
-do
-  # Write a limited-size here document to $tmp/defines.sed.
-  echo '  cat >$tmp/defines.sed <<CEOF' >>$CONFIG_STATUS
-  # Speed up: don't consider the non `#define' lines.
-  echo '/^[	 ]*#[	 ]*define/!b' >>$CONFIG_STATUS
-  # Work around the forget-to-reset-the-flag bug.
-  echo 't clr' >>$CONFIG_STATUS
-  echo ': clr' >>$CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.defines >>$CONFIG_STATUS
-  echo 'CEOF
-  sed -f $tmp/defines.sed $tmp/in >$tmp/out
-  rm -f $tmp/in
-  mv $tmp/out $tmp/in
-' >>$CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.defines >conftest.tail
-  rm -f conftest.defines
-  mv conftest.tail conftest.defines
-done
-rm -f conftest.defines
-echo '  fi # grep' >>$CONFIG_STATUS
-echo >>$CONFIG_STATUS
-
-# Break up conftest.undefs because some shells have a limit on the size
-# of here documents, and old seds have small limits too (100 cmds).
-echo '  # Handle all the #undef templates' >>$CONFIG_STATUS
-rm -f conftest.tail
-while grep . conftest.undefs >/dev/null
-do
-  # Write a limited-size here document to $tmp/undefs.sed.
-  echo '  cat >$tmp/undefs.sed <<CEOF' >>$CONFIG_STATUS
-  # Speed up: don't consider the non `#undef'
-  echo '/^[	 ]*#[	 ]*undef/!b' >>$CONFIG_STATUS
-  # Work around the forget-to-reset-the-flag bug.
-  echo 't clr' >>$CONFIG_STATUS
-  echo ': clr' >>$CONFIG_STATUS
-  sed ${ac_max_here_lines}q conftest.undefs >>$CONFIG_STATUS
-  echo 'CEOF
-  sed -f $tmp/undefs.sed $tmp/in >$tmp/out
-  rm -f $tmp/in
-  mv $tmp/out $tmp/in
-' >>$CONFIG_STATUS
-  sed 1,${ac_max_here_lines}d conftest.undefs >conftest.tail
-  rm -f conftest.undefs
-  mv conftest.tail conftest.undefs
-done
-rm -f conftest.undefs
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-  # Let's still pretend it is `configure' which instantiates (i.e., don't
-  # use $as_me), people would be surprised to read:
-  #    /* config.h.  Generated by config.status.  */
-  if test x"$ac_file" = x-; then
-    echo "/* Generated by configure.  */" >$tmp/config.h
-  else
-    echo "/* $ac_file.  Generated by configure.  */" >$tmp/config.h
-  fi
-  cat $tmp/in >>$tmp/config.h
-  rm -f $tmp/in
-  if test x"$ac_file" != x-; then
-    if diff $ac_file $tmp/config.h >/dev/null 2>&1; then
-      { echo "$as_me:$LINENO: $ac_file is unchanged" >&5
-echo "$as_me: $ac_file is unchanged" >&6;}
-    else
-      ac_dir=`(dirname "$ac_file") 2>/dev/null ||
-$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_file" : 'X\(//\)[^/]' \| \
-	 X"$ac_file" : 'X\(//\)$' \| \
-	 X"$ac_file" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_file" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-      { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-      rm -f $ac_file
-      mv $tmp/config.h $ac_file
-    fi
-  else
-    cat $tmp/config.h
-    rm -f $tmp/config.h
-  fi
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_LINKS section.
-#
-
-for ac_file in : $CONFIG_LINKS; do test "x$ac_file" = x: && continue
-  ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
-  ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
-
-  { echo "$as_me:$LINENO: linking $srcdir/$ac_source to $ac_dest" >&5
-echo "$as_me: linking $srcdir/$ac_source to $ac_dest" >&6;}
-
-  if test ! -r $srcdir/$ac_source; then
-    { { echo "$as_me:$LINENO: error: $srcdir/$ac_source: file not found" >&5
-echo "$as_me: error: $srcdir/$ac_source: file not found" >&2;}
-   { (exit 1); exit 1; }; }
-  fi
-  rm -f $ac_dest
-
-  # Make relative symlinks.
-  ac_dest_dir=`(dirname "$ac_dest") 2>/dev/null ||
-$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_dest" : 'X\(//\)[^/]' \| \
-	 X"$ac_dest" : 'X\(//\)$' \| \
-	 X"$ac_dest" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dest_dir"
-  else
-    as_dir="$ac_dest_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dest_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dest_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dest_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dest_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dest_dir";;
-*)
-  case "$ac_dest_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dest_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dest_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  case $srcdir in
-  [\\/$]* | ?:[\\/]* ) ac_rel_source=$srcdir/$ac_source ;;
-      *) ac_rel_source=$ac_top_builddir$srcdir/$ac_source ;;
-  esac
-
-  # Try a symlink, then a hard link, then a copy.
-  ln -s $ac_rel_source $ac_dest 2>/dev/null ||
-    ln $srcdir/$ac_source $ac_dest 2>/dev/null ||
-    cp -p $srcdir/$ac_source $ac_dest ||
-    { { echo "$as_me:$LINENO: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&5
-echo "$as_me: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&2;}
-   { (exit 1); exit 1; }; }
-done
-_ACEOF
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-#
-# CONFIG_COMMANDS section.
-#
-for ac_file in : $CONFIG_COMMANDS; do test "x$ac_file" = x: && continue
-  ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
-  ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
-  ac_dir=`(dirname "$ac_dest") 2>/dev/null ||
-$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$ac_dest" : 'X\(//\)[^/]' \| \
-	 X"$ac_dest" : 'X\(//\)$' \| \
-	 X"$ac_dest" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$ac_dest" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-  { if $as_mkdir_p; then
-    mkdir -p "$ac_dir"
-  else
-    as_dir="$ac_dir"
-    as_dirs=
-    while test ! -d "$as_dir"; do
-      as_dirs="$as_dir $as_dirs"
-      as_dir=`(dirname "$as_dir") 2>/dev/null ||
-$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
-	 X"$as_dir" : 'X\(//\)[^/]' \| \
-	 X"$as_dir" : 'X\(//\)$' \| \
-	 X"$as_dir" : 'X\(/\)' \| \
-	 .     : '\(.\)' 2>/dev/null ||
-echo X"$as_dir" |
-    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
-  	  /^X\(\/\/\)[^/].*/{ s//\1/; q; }
-  	  /^X\(\/\/\)$/{ s//\1/; q; }
-  	  /^X\(\/\).*/{ s//\1/; q; }
-  	  s/.*/./; q'`
-    done
-    test ! -n "$as_dirs" || mkdir $as_dirs
-  fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
-echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
-   { (exit 1); exit 1; }; }; }
-
-  ac_builddir=.
-
-if test "$ac_dir" != .; then
-  ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
-  # A "../" for each directory in $ac_dir_suffix.
-  ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
-else
-  ac_dir_suffix= ac_top_builddir=
-fi
-
-case $srcdir in
-  .)  # No --srcdir option.  We are building in place.
-    ac_srcdir=.
-    if test -z "$ac_top_builddir"; then
-       ac_top_srcdir=.
-    else
-       ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
-    fi ;;
-  [\\/]* | ?:[\\/]* )  # Absolute path.
-    ac_srcdir=$srcdir$ac_dir_suffix;
-    ac_top_srcdir=$srcdir ;;
-  *) # Relative path.
-    ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
-    ac_top_srcdir=$ac_top_builddir$srcdir ;;
-esac
-
-# Do not use `cd foo && pwd` to compute absolute paths, because
-# the directories may not exist.
-case `pwd` in
-.) ac_abs_builddir="$ac_dir";;
-*)
-  case "$ac_dir" in
-  .) ac_abs_builddir=`pwd`;;
-  [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
-  *) ac_abs_builddir=`pwd`/"$ac_dir";;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_builddir=${ac_top_builddir}.;;
-*)
-  case ${ac_top_builddir}. in
-  .) ac_abs_top_builddir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
-  *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_srcdir=$ac_srcdir;;
-*)
-  case $ac_srcdir in
-  .) ac_abs_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
-  *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
-  esac;;
-esac
-case $ac_abs_builddir in
-.) ac_abs_top_srcdir=$ac_top_srcdir;;
-*)
-  case $ac_top_srcdir in
-  .) ac_abs_top_srcdir=$ac_abs_builddir;;
-  [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
-  *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
-  esac;;
-esac
-
-
-  { echo "$as_me:$LINENO: executing $ac_dest commands" >&5
-echo "$as_me: executing $ac_dest commands" >&6;}
-  case $ac_dest in
-    Makefile ) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
- rm -f Makesim1.tmp Makesim2.tmp Makefile
- sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
- sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
- sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
-	-e '/^## COMMON_POST_/ r Makesim2.tmp' \
-	<Makefile.sim >Makefile
- rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
- ;;
-    stamp-h ) echo > stamp-h ;;
-  esac
-done
-_ACEOF
-
-cat >>$CONFIG_STATUS <<\_ACEOF
-
-{ (exit 0); exit 0; }
-_ACEOF
-chmod +x $CONFIG_STATUS
-ac_clean_files=$ac_clean_files_save
-
-
-# configure is writing to config.log, and then calls config.status.
-# config.status does its own redirection, appending to config.log.
-# Unfortunately, on DOS this fails, as config.log is still kept open
-# by configure, so config.status won't be able to write to it; its
-# output is simply discarded.  So we exec the FD to /dev/null,
-# effectively closing config.log, so it can be properly (re)opened and
-# appended to by config.status.  When coming back to configure, we
-# need to make the FD available again.
-if test "$no_create" != yes; then
-  ac_cs_success=:
-  ac_config_status_args=
-  test "$silent" = yes &&
-    ac_config_status_args="$ac_config_status_args --quiet"
-  exec 5>/dev/null
-  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
-  exec 5>>config.log
-  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
-  # would make configure fail if this is the last instruction.
-  $ac_cs_success || { (exit 1); exit 1; }
-fi
-
-
diff --git a/sim/mips/configure.ac b/sim/mips/configure.ac
deleted file mode 100644
index f81abbb..0000000
--- a/sim/mips/configure.ac
+++ /dev/null
@@ -1,437 +0,0 @@
-dnl Process this file with autoconf to produce a configure script.
-AC_PREREQ(2.59)dnl
-AC_INIT(Makefile.in)
-AC_CONFIG_HEADER(config.h:config.in)
-
-sinclude(../common/aclocal.m4)
-
-# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
-# it by inlining the macro's contents.
-sinclude(../common/common.m4)
-
-dnl Options available in this module
-SIM_AC_OPTION_INLINE()
-SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
-SIM_AC_OPTION_HOSTENDIAN
-SIM_AC_OPTION_WARNINGS
-SIM_AC_OPTION_RESERVED_BITS(1)
-
-# DEPRECATED
-#
-# Instead of defining a `subtarget' macro, code should be checking
-# the value of {STATE,CPU}_ARCHITECTURE to identify the architecture
-# in question.
-#
-case "${target}" in
-  mips64vr*-*-*)	SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
-  mips*tx39*)           SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
-  mipsisa32*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
-  mipsisa64*-*-*)       SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
-  *)                    SIM_SUBTARGET="";;
-esac
-AC_SUBST(SIM_SUBTARGET)
-
-
-
-#
-# Select the byte order of the target
-#
-mips_endian=
-default_endian=
-case "${target}" in
-  mips64el*-*-*)	mips_endian=LITTLE_ENDIAN ;;
-  mips64vr*el-*-*)      default_endian=LITTLE_ENDIAN ;;
-  mips64*-*-*)          default_endian=BIG_ENDIAN ;;
-  mips16*-*-*)          default_endian=BIG_ENDIAN ;;
-  mipsisa32*-*-*)       default_endian=BIG_ENDIAN ;;
-  mipsisa64*-*-*)       default_endian=BIG_ENDIAN ;;
-  mips*-*-*)            default_endian=BIG_ENDIAN ;;
-  *)                    default_endian=BIG_ENDIAN ;;
-esac
-SIM_AC_OPTION_ENDIAN($mips_endian,$default_endian)
-
-
-
-#
-# Select the bitsize of the target
-#
-mips_addr_bitsize=
-case "${target}" in
-  mips64*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
-  mips16*-*-*)          mips_bitsize=64 ; mips_msb=63 ;;
-  mipsisa32*-*-*)       mips_bitsize=32 ; mips_msb=31 ;;
-  mipsisa64*-*-*)       mips_bitsize=64 ; mips_msb=63 ;;
-  mips*-*-*)            mips_bitsize=32 ; mips_msb=31 ;;
-  *)                    mips_bitsize=64 ; mips_msb=63 ;;
-esac
-SIM_AC_OPTION_BITSIZE($mips_bitsize,$mips_msb,$mips_addr_bitsize)
-
-
-
-#
-# Select the floating hardware support of the target
-#
-mips_fpu=HARDWARE_FLOATING_POINT
-mips_fpu_bitsize=
-case "${target}" in
-  mips*tx39*)		mips_fpu=HARD_FLOATING_POINT
-			mips_fpu_bitsize=32
-			;;
-  mips64*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
-  mips16*-*-*)          mips_fpu=HARD_FLOATING_POINT ;;
-  mipsisa32*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
-  mipsisa64*-*-*)       mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=64 ;;
-  mips*-*-*)            mips_fpu=HARD_FLOATING_POINT ; mips_fpu_bitsize=32 ;;
-  *)                    mips_fpu=HARD_FLOATING_POINT ;;
-esac
-SIM_AC_OPTION_FLOAT($mips_fpu,$mips_fpu_bitsize)
-
-
-
-#
-# Select the level of SMP support
-#
-case "${target}" in
-  *)                    mips_smp=0 ;;
-esac
-SIM_AC_OPTION_SMP($mips_smp)
-
-
-
-#
-# Select the IGEN architecture
-#
-sim_gen=IGEN
-sim_igen_machine="-M mipsIV"
-sim_m16_machine="-M mips16,mipsIII"
-sim_igen_filter="32,64,f"
-sim_m16_filter="16"
-sim_mach_default="mips8000"
-
-case "${target}" in
-  mips*tx39*)		sim_gen=IGEN
-			sim_igen_filter="32,f"
-			sim_igen_machine="-M r3900"
-			;;
-  mips64vr43*-*-*)	sim_gen=IGEN
-			sim_igen_machine="-M mipsIV"
-			sim_mach_default="mips8000"
-			;;
-  mips64vr5*-*-*)	sim_gen=IGEN
-			sim_igen_machine="-M vr5000"
-			sim_mach_default="mips5000"
-			;;
-  mips64vr41*)		sim_gen=M16
-			sim_igen_machine="-M vr4100"
-			sim_m16_machine="-M vr4100"
-			sim_igen_filter="32,64,f"
-			sim_m16_filter="16"
-			sim_mach_default="mips4100"
-                        ;;
-  mips64vr-*-* | mips64vrel-*-*)
-			sim_gen=MULTI
-			sim_multi_configs="\
-			  vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\
-			  vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
-			  vr5000:mipsIV:32,64,f:mips4300,mips5000\
-			  vr5400:mipsIV,vr5400:32,64,f:mips5400\
-			  vr5500:mipsIV,vr5500:32,64,f:mips5500"
-			sim_multi_default=mips5000
-			;;
-  mips64*-*-*)		sim_igen_filter="32,64,f"
-			sim_gen=IGEN
-			;;
-  mips16*-*-*)		sim_gen=M16
-			sim_igen_filter="32,64,f"
-			sim_m16_filter="16"
-			;;
-  mipsisa32r2*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips32r2,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips32r2"
-			sim_igen_filter="32,f"
-			sim_mach_default="mipsisa32r2"
-			;;
-  mipsisa32*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips32,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips32"
-			sim_igen_filter="32,f"
-			sim_mach_default="mipsisa32"
-			;;
-  mipsisa64r2*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips64r2"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mipsisa64r2"
-			;;
-  mipsisa64sb1*-*-*)	sim_gen=IGEN
-		        sim_igen_machine="-M mips64,mips3d,sb1"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mips_sb1"
-			;;
-  mipsisa64*-*-*)	sim_gen=M16
-		        sim_igen_machine="-M mips64,mips3d,mips16,mips16e,dsp"
-			sim_m16_machine="-M mips16,mips16e,mips64"
-			sim_igen_filter="32,64,f"
-			sim_mach_default="mipsisa64"
-			;;
-  mips*lsi*)	        sim_gen=M16
-			sim_igen_machine="-M mipsIII,mips16"
-			sim_m16_machine="-M mips16,mipsIII"
-			sim_igen_filter="32,f"
-			sim_m16_filter="16"
-			sim_mach_default="mips4000"
-                        ;;
-  mips*-*-*)		sim_gen=IGEN
-			sim_igen_filter="32,f"
-			;;
-esac
-
-# The MULTI generator can combine several simulation engines into one.
-# executable.  A configuration which uses the MULTI should set two
-# variables: ${sim_multi_configs} and ${sim_multi_default}.
-#
-# ${sim_multi_configs} is the list of engines to build.  Each
-# space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS,
-# where:
-#
-# - NAME is a C-compatible prefix for the engine,
-# - MACHINE is a -M argument,
-# - FILTER is a -F argument, and
-# - BFDMACHS is a comma-separated list of bfd machines that the
-#     simulator can run.
-#
-# Each entry will have a separate simulation engine whose prefix is
-# m32<NAME>.  If the machine list includes "mips16", there will also
-# be a mips16 engine, prefix m16<NAME>.  The mips16 engine will be
-# generated using the same machine list as the 32-bit version,
-# but the filter will be "16" instead of FILTER.
-#
-# The simulator compares the bfd mach against BFDMACHS to decide
-# which engine to use.  Entries in BFDMACHS should be bfd_mach
-# values with "bfd_mach_" removed.  ${sim_multi_default} says
-# which entry should be the default.
-if test ${sim_gen} = MULTI; then
-
-  # Simple sanity check.
-  if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then
-    AC_MSG_ERROR(Error in configure.in: MULTI simulator not set up correctly)
-  fi
-
-  # Start in a known state.
-  rm -f multi-include.h multi-run.c
-  sim_multi_flags=
-  sim_multi_src=
-  sim_multi_obj=multi-run.o
-  sim_multi_igen_configs=
-  sim_seen_default=no
-
-  cat << __EOF__ > multi-run.c
-/* Main entry point for MULTI simulators.
-   Copyright (C) 2003 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-   --
-
-   This file was generated by sim/mips/configure.  */
-
-#include "sim-main.h"
-#include "multi-include.h"
-
-#define SD sd
-#define CPU cpu
-
-void
-sim_engine_run (SIM_DESC sd,
-		int next_cpu_nr,
-		int nr_cpus,
-		int signal) /* ignore */
-{
-  int mach;
-
-  if (STATE_ARCHITECTURE (sd) == NULL)
-    mach = bfd_mach_${sim_multi_default};
-  else
-    mach = STATE_ARCHITECTURE (SD)->mach;
-
-  switch (mach)
-    {
-__EOF__
-
-  for fc in ${sim_multi_configs}; do
-
-    # Split up the entry.  ${c} contains the first three elements.
-    # Note: outer sqaure brackets are m4 quotes.
-    c=`echo ${fc} | sed ['s/:[^:]*$//']`
-    bfdmachs=`echo ${fc} | sed 's/.*://'`
-    name=`echo ${c} | sed 's/:.*//'`
-    machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
-    filter=`echo ${c} | sed 's/.*://'`
-
-    # Build the following lists:
-    #
-    #   sim_multi_flags: all -M and -F flags used by the simulator
-    #   sim_multi_src: all makefile-generated source files
-    #   sim_multi_obj: the objects for ${sim_multi_src}
-    #   sim_multi_igen_configs: igen configuration strings.
-    #
-    # Each entry in ${sim_multi_igen_configs} is a prefix (m32
-    # or m16) followed by the NAME, MACHINE and FILTER part of
-    # the ${sim_multi_configs} entry.
-    sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
-
-    # Check whether mips16 handling is needed.
-    case ${c} in
-      *:*mips16*:*)
-	# Run igen twice, once for normal mode and once for mips16.
-	ws="m32 m16"
-
-	# The top-level function for the mips16 simulator is
-	# in a file m16${name}_run.c, generated by the
-	# tmp-run-multi Makefile rule.
-	sim_multi_src="${sim_multi_src} m16${name}_run.c"
-	sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
-	sim_multi_flags="${sim_multi_flags} -F 16"
-	;;
-      *)
-	ws=m32
-	;;
-    esac
-
-    # Now add the list of igen-generated files to ${sim_multi_src}
-    # and ${sim_multi_obj}.
-    for w in ${ws}; do
-      for base in engine icache idecode model semantics support; do
-	sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
-	sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
-	sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
-      done
-      sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}"
-    done
-
-    # Add an include for the engine.h file.  This file declares the
-    # top-level foo_engine_run() function.
-    echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
-
-    # Add case statements for this engine to sim_engine_run().
-    for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
-      echo "    case bfd_mach_${mach}:" >> multi-run.c
-      if test ${mach} = ${sim_multi_default}; then
-	echo "    default:" >> multi-run.c
-	sim_seen_default=yes
-      fi
-    done
-    echo "      ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
-      >> multi-run.c
-    echo "      break;" >> multi-run.c
-  done
-
-  # Check whether we added a 'default:' label.
-  if test ${sim_seen_default} = no; then
-    AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default})
-  fi
-
-  cat << __EOF__ >> multi-run.c
-    }
-}
-
-int
-mips_mach_multi (SIM_DESC sd)
-{
-  if (STATE_ARCHITECTURE (sd) == NULL)
-    return bfd_mach_${sim_multi_default};
-
-  switch (STATE_ARCHITECTURE (SD)->mach)
-    {
-__EOF__
-
-  # Add case statements for this engine to mips_mach_multi().
-  for fc in ${sim_multi_configs}; do
-
-    # Split up the entry.  ${c} contains the first three elements.
-    # Note: outer sqaure brackets are m4 quotes.
-    c=`echo ${fc} | sed ['s/:[^:]*$//']`
-    bfdmachs=`echo ${fc} | sed 's/.*://'`
-
-    for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
-      echo "    case bfd_mach_${mach}:" >> multi-run.c
-    done
-  done
-
-  cat << __EOF__ >> multi-run.c
-      return (STATE_ARCHITECTURE (SD)->mach);
-    default:
-      return bfd_mach_${sim_multi_default};
-    }
-}
-__EOF__
-
-  SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI"
-else
-  # For clean-extra
-  sim_multi_src=doesnt-exist.c
-
-  if test x"${sim_mach_default}" = x""; then
-    AC_MSG_ERROR(Error in configure.in: \${sim_mach_default} not defined)
-  fi
-  SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}"
-fi
-sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
-sim_m16_flags=" -F ${sim_m16_filter}  ${sim_m16_machine}  ${sim_igen_smp}"
-AC_SUBST(sim_igen_flags)
-AC_SUBST(sim_m16_flags)
-AC_SUBST(sim_gen)
-AC_SUBST(sim_multi_flags)
-AC_SUBST(sim_multi_igen_configs)
-AC_SUBST(sim_multi_src)
-AC_SUBST(sim_multi_obj)
-
-
-#
-# Add simulated hardware devices
-#
-hw_enabled=no
-case "${target}" in
-  mips*tx39*)
-	hw_enabled=yes
-	hw_extra_devices="tx3904cpu tx3904irc tx3904tmr tx3904sio" 
-	mips_extra_objs="dv-sockser.o"
-	SIM_SUBTARGET="$SIM_SUBTARGET -DTARGET_TX3904=1"
-	;;
-  *)
-	mips_extra_objs="" 
-	;;
-esac
-SIM_AC_OPTION_HARDWARE($hw_enabled,$hw_devices,$hw_extra_devices)
-AC_SUBST(mips_extra_objs)
-
-
-# Choose simulator engine
-case "${target}" in
-  *)    mips_igen_engine="engine.o"
-	;;
-esac
-AC_SUBST(mips_igen_engine)
-
-
-AC_PATH_X
-mips_extra_libs=""
-AC_SUBST(mips_extra_libs)
-
-AC_CHECK_HEADERS(string.h strings.h stdlib.h stdlib.h)
-AC_CHECK_LIB(m, fabs)
-AC_CHECK_FUNCS(aint anint sqrt)
-
-SIM_AC_OUTPUT
diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c
deleted file mode 100644
index 556af1a..0000000
--- a/sim/mips/cp1.c
+++ /dev/null
@@ -1,1584 +0,0 @@
-/*> cp1.c <*/
-/* MIPS Simulator FPU (CoProcessor 1) support.
-   Copyright (C) 2002 Free Software Foundation, Inc.
-   Originally created by Cygnus Solutions.  Extensive modifications,
-   including paired-single operation support and MIPS-3D support
-   contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
-   Corporation (SiByte).
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-/* XXX: The following notice should be removed as soon as is practical:  */
-/* Floating Point Support for gdb MIPS simulators
-
-   This file is part of the MIPS sim
-
-		THIS SOFTWARE IS NOT COPYRIGHTED
-   (by Cygnus.)
-
-   Cygnus offers the following for use in the public domain.  Cygnus
-   makes no warranty with regard to the software or it's performance
-   and the user accepts the software "AS IS" with all faults.
-
-   CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
-   THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-
-   (Originally, this code was in interp.c)
-*/
-
-#include "sim-main.h"
-
-/* Within cp1.c we refer to sim_cpu directly.  */
-#define CPU cpu
-#define SD CPU_STATE(cpu)
-
-/*-- FPU support routines ---------------------------------------------------*/
-
-/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
-   formats conform to ANSI/IEEE Std 754-1985.
-
-   SINGLE precision floating:
-      seeeeeeeefffffffffffffffffffffff
-        s =  1bit  = sign
-        e =  8bits = exponent
-        f = 23bits = fraction
-
-   SINGLE precision fixed:
-      siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
-        s =  1bit  = sign
-        i = 31bits = integer
-
-   DOUBLE precision floating:
-      seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
-        s =  1bit  = sign
-        e = 11bits = exponent
-        f = 52bits = fraction
-
-   DOUBLE precision fixed:
-      siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
-        s =  1bit  = sign
-        i = 63bits = integer
-
-   PAIRED SINGLE precision floating:
-      seeeeeeeefffffffffffffffffffffffseeeeeeeefffffffffffffffffffffff
-      |         upper                ||         lower                |
-        s =  1bit  = sign
-        e =  8bits = exponent
-        f = 23bits = fraction
-    Note: upper = [63..32], lower = [31..0]
- */
-
-/* Extract packed single values:  */
-#define FP_PS_upper(v) (((v) >> 32) & (unsigned)0xFFFFFFFF)
-#define FP_PS_lower(v) ((v) & (unsigned)0xFFFFFFFF)
-#define FP_PS_cat(u,l) (((unsigned64)((u) & (unsigned)0xFFFFFFFF) << 32) \
-                        | (unsigned64)((l) & 0xFFFFFFFF))
-
-/* Explicit QNaN values.  */
-#define FPQNaN_SINGLE   (0x7FBFFFFF)
-#define FPQNaN_WORD     (0x7FFFFFFF)
-#define FPQNaN_DOUBLE   (UNSIGNED64 (0x7FF7FFFFFFFFFFFF))
-#define FPQNaN_LONG     (UNSIGNED64 (0x7FFFFFFFFFFFFFFF))
-#define FPQNaN_PS       (FP_PS_cat (FPQNaN_SINGLE, FPQNaN_SINGLE))
-
-static const char *fpu_format_name (FP_formats fmt);
-#ifdef DEBUG
-static const char *fpu_rounding_mode_name (int rm);
-#endif
-
-uword64
-value_fpr (sim_cpu *cpu,
-	   address_word cia,
-	   int fpr,
-	   FP_formats fmt)
-{
-  uword64 value = 0;
-  int err = 0;
-
-  /* Treat unused register values, as fixed-point 64bit values.  */
-  if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
-    {
-#if 1
-      /* If request to read data as "uninterpreted", then use the current
-	 encoding:  */
-      fmt = FPR_STATE[fpr];
-#else
-      fmt = fmt_long;
-#endif
-    }
-
-  /* For values not yet accessed, set to the desired format.  */
-  if (FPR_STATE[fpr] == fmt_uninterpreted)
-    {
-      FPR_STATE[fpr] = fmt;
-#ifdef DEBUG
-      printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
-	      fpu_format_name (fmt));
-#endif /* DEBUG */
-    }
-  if (fmt != FPR_STATE[fpr])
-    {
-      sim_io_eprintf (SD, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
-		      fpr, fpu_format_name (FPR_STATE[fpr]),
-		      fpu_format_name (fmt), pr_addr (cia));
-      FPR_STATE[fpr] = fmt_unknown;
-    }
-
-  if (FPR_STATE[fpr] == fmt_unknown)
-    {
-      /* Set QNaN value:  */
-      switch (fmt)
-	{
-	case fmt_single:  value = FPQNaN_SINGLE;  break;
-	case fmt_double:  value = FPQNaN_DOUBLE;  break;
-	case fmt_word:    value = FPQNaN_WORD;    break;
-	case fmt_long:    value = FPQNaN_LONG;    break;
-	case fmt_ps:      value = FPQNaN_PS;      break;
-	default:          err = -1;               break;
-	}
-    }
-  else if (SizeFGR () == 64)
-    {
-      switch (fmt)
-	{
-	case fmt_single:
-	case fmt_word:
-	  value = (FGR[fpr] & 0xFFFFFFFF);
-	  break;
-
-	case fmt_uninterpreted:
-	case fmt_double:
-	case fmt_long:
-	case fmt_ps:
-	  value = FGR[fpr];
-	  break;
-
-	default:
-	  err = -1;
-	  break;
-	}
-    }
-  else
-    {
-      switch (fmt)
-	{
-	case fmt_single:
-	case fmt_word:
-	  value = (FGR[fpr] & 0xFFFFFFFF);
-	  break;
-
-	case fmt_uninterpreted:
-	case fmt_double:
-	case fmt_long:
-	  if ((fpr & 1) == 0)
-	    {
-	      /* Even register numbers only.  */
-#ifdef DEBUG
-	      printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
-		      fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
-		      fpr, pr_uword64 ((uword64) FGR[fpr]));
-#endif
-	      value = ((((uword64) FGR[fpr+1]) << 32)
-		       | (FGR[fpr] & 0xFFFFFFFF));
-	    }
-	  else
-	    {
-	      SignalException (ReservedInstruction, 0);
-	    }
-	  break;
-
-	case fmt_ps:
-	  SignalException (ReservedInstruction, 0);
-	  break;
-
-	default:
-	  err = -1;
-	  break;
-	}
-    }
-
-  if (err)
-    SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
-
-#ifdef DEBUG
-  printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
-	  fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
-	  SizeFGR ());
-#endif /* DEBUG */
-
-  return (value);
-}
-
-void
-store_fpr (sim_cpu *cpu,
-	   address_word cia,
-	   int fpr,
-	   FP_formats fmt,
-	   uword64 value)
-{
-  int err = 0;
-
-#ifdef DEBUG
-  printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
-	  fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
-	  SizeFGR ());
-#endif /* DEBUG */
-
-  if (SizeFGR () == 64)
-    {
-      switch (fmt)
-	{
-	case fmt_uninterpreted_32:
-	  fmt = fmt_uninterpreted;
-	case fmt_single:
-	case fmt_word:
-	  if (STATE_VERBOSE_P (SD))
-	    sim_io_eprintf (SD,
-			    "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
-			    pr_addr (cia));
-	  FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
-	  FPR_STATE[fpr] = fmt;
-	  break;
-
-	case fmt_uninterpreted_64:
-	  fmt = fmt_uninterpreted;
-	case fmt_uninterpreted:
-	case fmt_double:
-	case fmt_long:
-	case fmt_ps:
-	  FGR[fpr] = value;
-	  FPR_STATE[fpr] = fmt;
-	  break;
-
-	default:
-	  FPR_STATE[fpr] = fmt_unknown;
-	  err = -1;
-	  break;
-	}
-    }
-  else
-    {
-      switch (fmt)
-	{
-	case fmt_uninterpreted_32:
-	  fmt = fmt_uninterpreted;
-	case fmt_single:
-	case fmt_word:
-	  FGR[fpr] = (value & 0xFFFFFFFF);
-	  FPR_STATE[fpr] = fmt;
-	  break;
-
-	case fmt_uninterpreted_64:
-	  fmt = fmt_uninterpreted;
-	case fmt_uninterpreted:
-	case fmt_double:
-	case fmt_long:
-	  if ((fpr & 1) == 0)
-	    {
-	      /* Even register numbers only.  */
-	      FGR[fpr+1] = (value >> 32);
-	      FGR[fpr] = (value & 0xFFFFFFFF);
-	      FPR_STATE[fpr + 1] = fmt;
-	      FPR_STATE[fpr] = fmt;
-	    }
-	  else
-	    {
-	      FPR_STATE[fpr] = fmt_unknown;
-	      FPR_STATE[fpr + 1] = fmt_unknown;
-	      SignalException (ReservedInstruction, 0);
-	    }
-	  break;
-
-	case fmt_ps:
-	  FPR_STATE[fpr] = fmt_unknown;
-	  SignalException (ReservedInstruction, 0);
-	  break;
-
-	default:
-	  FPR_STATE[fpr] = fmt_unknown;
-	  err = -1;
-	  break;
-	}
-    }
-
-  if (err)
-    SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
-
-#ifdef DEBUG
-  printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
-	  fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt));
-#endif /* DEBUG */
-
-  return;
-}
-
-
-/* CP1 control/status register access functions.  */
-
-void
-test_fcsr (sim_cpu *cpu,
-	   address_word cia)
-{
-  unsigned int cause;
-
-  cause = (FCSR & fcsr_CAUSE_mask) >> fcsr_CAUSE_shift;
-  if ((cause & ((FCSR & fcsr_ENABLES_mask) >> fcsr_ENABLES_shift)) != 0
-      || (cause & (1 << UO)))
-    {
-      SignalExceptionFPE();
-    }
-}
-
-unsigned_word
-value_fcr(sim_cpu *cpu,
-	  address_word cia,
-	  int fcr)
-{
-  unsigned32 value = 0;
-
-  switch (fcr)
-    {
-    case 0:  /* FP Implementation and Revision Register.  */
-      value = FCR0;
-      break;
-    case 25:  /* FP Condition Codes Register (derived from FCSR).  */
-      value = (FCR31 & fcsr_FCC_mask) >> fcsr_FCC_shift;
-      value = (value & 0x1) | (value >> 1);   /* Close FCC gap.  */
-      break;
-    case 26:  /* FP Exceptions Register (derived from FCSR).  */
-      value = FCR31 & (fcsr_CAUSE_mask | fcsr_FLAGS_mask);
-      break;
-    case 28:  /* FP Enables Register (derived from FCSR).  */
-      value = FCR31 & (fcsr_ENABLES_mask | fcsr_RM_mask);
-      if ((FCR31 & fcsr_FS) != 0)
-	value |= fenr_FS;
-      break;
-    case 31:  /* FP Control/Status Register (FCSR).  */
-      value = FCR31 & ~fcsr_ZERO_mask;
-      break;
-    }
-
-  return (EXTEND32 (value));
-}
-
-void
-store_fcr(sim_cpu *cpu,
-	  address_word cia,
-	  int fcr,
-	  unsigned_word value)
-{
-  unsigned32 v;
-
-  v = VL4_8(value);
-  switch (fcr)
-    {
-    case 25:  /* FP Condition Codes Register (stored into FCSR).  */
-      v = (v << 1) | (v & 0x1);             /* Adjust for FCC gap.  */
-      FCR31 &= ~fcsr_FCC_mask;
-      FCR31 |= ((v << fcsr_FCC_shift) & fcsr_FCC_mask);
-      break;
-    case 26:  /* FP Exceptions Register (stored into FCSR).  */
-      FCR31 &= ~(fcsr_CAUSE_mask | fcsr_FLAGS_mask);
-      FCR31 |= (v & (fcsr_CAUSE_mask | fcsr_FLAGS_mask));
-      test_fcsr(cpu, cia);
-      break;
-    case 28:  /* FP Enables Register (stored into FCSR).  */
-      if ((v & fenr_FS) != 0)
-	v |= fcsr_FS;
-      else
-	v &= ~fcsr_FS;
-      FCR31 &= (fcsr_FCC_mask | fcsr_CAUSE_mask | fcsr_FLAGS_mask);
-      FCR31 |= (v & (fcsr_FS | fcsr_ENABLES_mask | fcsr_RM_mask));
-      test_fcsr(cpu, cia);
-      break;
-    case 31:  /* FP Control/Status Register (FCSR).  */
-      FCR31 = v & ~fcsr_ZERO_mask;
-      test_fcsr(cpu, cia);
-      break;
-    }
-}
-
-void
-update_fcsr (sim_cpu *cpu,
-	     address_word cia,
-	     sim_fpu_status status)
-{
-  FCSR &= ~fcsr_CAUSE_mask;
-
-  if (status != 0)
-    {
-      unsigned int cause = 0;
-
-      /* map between sim_fpu codes and MIPS FCSR */
-      if (status & (sim_fpu_status_invalid_snan
-		    | sim_fpu_status_invalid_isi
-		    | sim_fpu_status_invalid_idi
-		    | sim_fpu_status_invalid_zdz
-		    | sim_fpu_status_invalid_imz
-		    | sim_fpu_status_invalid_cmp
-		    | sim_fpu_status_invalid_sqrt
-		    | sim_fpu_status_invalid_cvi))
-	cause |= (1 << IO);
-      if (status & sim_fpu_status_invalid_div0)
-	cause |= (1 << DZ);
-      if (status & sim_fpu_status_overflow)
-	cause |= (1 << OF);
-      if (status & sim_fpu_status_underflow)
-	cause |= (1 << UF);
-      if (status & sim_fpu_status_inexact)
-	cause |= (1 << IR);
-#if 0 /* Not yet.  */
-      /* Implicit clearing of other bits by unimplemented done by callers.  */
-      if (status & sim_fpu_status_unimplemented)
-	cause |= (1 << UO);
-#endif
-
-      FCSR |= (cause << fcsr_CAUSE_shift);
-      test_fcsr (cpu, cia);
-      FCSR |= ((cause & ~(1 << UO)) << fcsr_FLAGS_shift);
-    }
-  return;
-}
-
-static sim_fpu_round
-rounding_mode(int rm)
-{
-  sim_fpu_round round;
-
-  switch (rm)
-    {
-    case FP_RM_NEAREST:
-      /* Round result to nearest representable value. When two
-	 representable values are equally near, round to the value
-	 that has a least significant bit of zero (i.e. is even).  */
-      round = sim_fpu_round_near;
-      break;
-    case FP_RM_TOZERO:
-      /* Round result to the value closest to, and not greater in
-	 magnitude than, the result.  */
-      round = sim_fpu_round_zero;
-      break;
-    case FP_RM_TOPINF:
-      /* Round result to the value closest to, and not less than,
-	 the result.  */
-      round = sim_fpu_round_up;
-      break;
-    case FP_RM_TOMINF:
-      /* Round result to the value closest to, and not greater than,
-	 the result.  */
-      round = sim_fpu_round_down;
-      break;
-    default:
-      round = 0;
-      fprintf (stderr, "Bad switch\n");
-      abort ();
-    }
-  return round;
-}
-
-/* When the FS bit is set, MIPS processors return zero for
-   denormalized results and optionally replace denormalized inputs
-   with zero.  When FS is clear, some implementation trap on input
-   and/or output, while other perform the operation in hardware.  */
-static sim_fpu_denorm
-denorm_mode(sim_cpu *cpu)
-{
-  sim_fpu_denorm denorm;
-
-  /* XXX: FIXME: Eventually should be CPU model dependent.  */
-  if (GETFS())
-    denorm = sim_fpu_denorm_zero;
-  else
-    denorm = 0;
-  return denorm;
-}
-
-
-/* Comparison operations.  */
-
-static sim_fpu_status
-fp_test(unsigned64 op1,
-	unsigned64 op2,
-	FP_formats fmt,
-	int abs,
-	int cond,
-	int *condition)
-{
-  sim_fpu wop1;
-  sim_fpu wop2;
-  sim_fpu_status status = 0;
-  int  less, equal, unordered;
-
-  /* The format type has already been checked:  */
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	sim_fpu_32to (&wop1, op1);
-	sim_fpu_32to (&wop2, op2);
-	break;
-      }
-    case fmt_double:
-      {
-	sim_fpu_64to (&wop1, op1);
-	sim_fpu_64to (&wop2, op2);
-	break;
-      }
-    default:
-      fprintf (stderr, "Bad switch\n");
-      abort ();
-    }
-
-  if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
-    {
-      if ((cond & (1 << 3)) ||
-	  sim_fpu_is_snan (&wop1) || sim_fpu_is_snan (&wop2))
-	status = sim_fpu_status_invalid_snan;
-      less = 0;
-      equal = 0;
-      unordered = 1;
-    }
-  else
-    {
-      if (abs)
-	{
-	  status |= sim_fpu_abs (&wop1, &wop1);
-	  status |= sim_fpu_abs (&wop2, &wop2);
-	}
-      equal = sim_fpu_is_eq (&wop1, &wop2);
-      less = !equal && sim_fpu_is_lt (&wop1, &wop2);
-      unordered = 0;
-    }
-  *condition = (((cond & (1 << 2)) && less)
-		|| ((cond & (1 << 1)) && equal)
-		|| ((cond & (1 << 0)) && unordered));
-  return status;
-}
-
-void
-fp_cmp(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op1,
-       unsigned64 op2,
-       FP_formats fmt,
-       int abs,
-       int cond,
-       int cc)
-{
-  sim_fpu_status status = 0;
-
-  /* The format type should already have been checked.  The FCSR is
-     updated before the condition codes so that any exceptions will
-     be signalled before the condition codes are changed.  */
-  switch (fmt)
-    {
-    case fmt_single:
-    case fmt_double:
-      {
-	int result;
-	status = fp_test(op1, op2, fmt, abs, cond, &result);
-	update_fcsr (cpu, cia, status);
-	SETFCC (cc, result);
-	break;
-      }
-    case fmt_ps:
-      {
-	int result0, result1;
-	status  = fp_test(FP_PS_lower (op1), FP_PS_lower (op2), fmt_single,
-			  abs, cond, &result0);
-	status |= fp_test(FP_PS_upper (op1), FP_PS_upper (op2), fmt_single,
-			  abs, cond, &result1);
-	update_fcsr (cpu, cia, status);
-	SETFCC (cc, result0);
-	SETFCC (cc+1, result1);
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-}
-
-
-/* Basic arithmetic operations.  */
-
-static unsigned64
-fp_unary(sim_cpu *cpu,
-	 address_word cia,
-	 int (*sim_fpu_op)(sim_fpu *, const sim_fpu *),
-	 unsigned64 op,
-	 FP_formats fmt)
-{
-  sim_fpu wop;
-  sim_fpu ans;
-  sim_fpu_round round = rounding_mode (GETRM());
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  sim_fpu_status status = 0;
-  unsigned64 result = 0;
-
-  /* The format type has already been checked: */
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	unsigned32 res;
-	sim_fpu_32to (&wop, op);
-	status |= (*sim_fpu_op) (&ans, &wop);
-	status |= sim_fpu_round_32 (&ans, round, denorm);
-	sim_fpu_to32 (&res, &ans);
-	result = res;
-	break;
-      }
-    case fmt_double:
-      {
-	unsigned64 res;
-	sim_fpu_64to (&wop, op);
-	status |= (*sim_fpu_op) (&ans, &wop);
-	status |= sim_fpu_round_64 (&ans, round, denorm);
-	sim_fpu_to64 (&res, &ans);
-	result = res;
-	break;
-      }
-    case fmt_ps:
-      {
-	int status_u = 0, status_l = 0;
-	unsigned32 res_u, res_l;
-	sim_fpu_32to (&wop, FP_PS_upper(op));
-	status_u |= (*sim_fpu_op) (&ans, &wop);
-	sim_fpu_to32 (&res_u, &ans);
-	sim_fpu_32to (&wop, FP_PS_lower(op));
-	status_l |= (*sim_fpu_op) (&ans, &wop);
-	sim_fpu_to32 (&res_l, &ans);
-	result = FP_PS_cat(res_u, res_l);
-	status = status_u | status_l;
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status);
-  return result;
-}
-
-static unsigned64
-fp_binary(sim_cpu *cpu,
-	  address_word cia,
-	  int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
-	  unsigned64 op1,
-	  unsigned64 op2,
-	  FP_formats fmt)
-{
-  sim_fpu wop1;
-  sim_fpu wop2;
-  sim_fpu ans;
-  sim_fpu_round round = rounding_mode (GETRM());
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  sim_fpu_status status = 0;
-  unsigned64 result = 0;
-
-  /* The format type has already been checked: */
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	unsigned32 res;
-	sim_fpu_32to (&wop1, op1);
-	sim_fpu_32to (&wop2, op2);
-	status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	status |= sim_fpu_round_32 (&ans, round, denorm);
-	sim_fpu_to32 (&res, &ans);
-	result = res;
-	break;
-      }
-    case fmt_double:
-      {
-	unsigned64 res;
-	sim_fpu_64to (&wop1, op1);
-	sim_fpu_64to (&wop2, op2);
-	status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	status |= sim_fpu_round_64 (&ans, round, denorm);
-	sim_fpu_to64 (&res, &ans);
-	result = res;
-	break;
-      }
-    case fmt_ps:
-      {
-	int status_u = 0, status_l = 0;
-	unsigned32 res_u, res_l;
-	sim_fpu_32to (&wop1, FP_PS_upper(op1));
-	sim_fpu_32to (&wop2, FP_PS_upper(op2));
-	status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	sim_fpu_to32 (&res_u, &ans);
-	sim_fpu_32to (&wop1, FP_PS_lower(op1));
-	sim_fpu_32to (&wop2, FP_PS_lower(op2));
-	status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	sim_fpu_to32 (&res_l, &ans);
-	result = FP_PS_cat(res_u, res_l);
-	status = status_u | status_l;
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status);
-  return result;
-}
-
-/* Common MAC code for single operands (.s or .d), defers setting FCSR.  */
-static sim_fpu_status
-inner_mac(int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
-	  unsigned64 op1,
-	  unsigned64 op2,
-	  unsigned64 op3,
-	  int scale,
-	  int negate,
-	  FP_formats fmt,
-	  sim_fpu_round round,
-	  sim_fpu_denorm denorm,
-	  unsigned64 *result)
-{
-  sim_fpu wop1;
-  sim_fpu wop2;
-  sim_fpu ans;
-  sim_fpu_status status = 0;
-  sim_fpu_status op_status;
-  unsigned64 temp = 0;
-
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	unsigned32 res;
-	sim_fpu_32to (&wop1, op1);
-	sim_fpu_32to (&wop2, op2);
-	status |= sim_fpu_mul (&ans, &wop1, &wop2);
-	if (scale != 0 && sim_fpu_is_number (&ans))  /* number or denorm */
-	  ans.normal_exp += scale;
-	status |= sim_fpu_round_32 (&ans, round, denorm);
-	wop1 = ans;
-        op_status = 0;
-	sim_fpu_32to (&wop2, op3);
-	op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	op_status |= sim_fpu_round_32 (&ans, round, denorm);
-	status |= op_status;
-	if (negate)
-	  {
-	    wop1 = ans;
-	    op_status = sim_fpu_neg (&ans, &wop1);
-	    op_status |= sim_fpu_round_32 (&ans, round, denorm);
-	    status |= op_status;
-	  }
-	sim_fpu_to32 (&res, &ans);
-	temp = res;
-	break;
-      }
-    case fmt_double:
-      {
-	unsigned64 res;
-	sim_fpu_64to (&wop1, op1);
-	sim_fpu_64to (&wop2, op2);
-	status |= sim_fpu_mul (&ans, &wop1, &wop2);
-	if (scale != 0 && sim_fpu_is_number (&ans))  /* number or denorm */
-	  ans.normal_exp += scale;
-	status |= sim_fpu_round_64 (&ans, round, denorm);
-	wop1 = ans;
-        op_status = 0;
-	sim_fpu_64to (&wop2, op3);
-	op_status |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-	op_status |= sim_fpu_round_64 (&ans, round, denorm);
-	status |= op_status;
-	if (negate)
-	  {
-	    wop1 = ans;
-	    op_status = sim_fpu_neg (&ans, &wop1);
-	    op_status |= sim_fpu_round_64 (&ans, round, denorm);
-	    status |= op_status;
-	  }
-	sim_fpu_to64 (&res, &ans);
-	temp = res;
-	break;
-      }
-    default:
-      fprintf (stderr, "Bad switch\n");
-      abort ();
-    }
-  *result = temp;
-  return status;
-}
-
-/* Common implementation of madd, nmadd, msub, nmsub that does
-   intermediate rounding per spec.  Also used for recip2 and rsqrt2,
-   which are transformed into equivalent nmsub operations.  The scale
-   argument is an adjustment to the exponent of the intermediate
-   product op1*op2.  It is currently non-zero for rsqrt2 (-1), which
-   requires an effective division by 2. */
-static unsigned64
-fp_mac(sim_cpu *cpu,
-       address_word cia,
-       int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
-       unsigned64 op1,
-       unsigned64 op2,
-       unsigned64 op3,
-       int scale,
-       int negate,
-       FP_formats fmt)
-{
-  sim_fpu_round round = rounding_mode (GETRM());
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  sim_fpu_status status = 0;
-  unsigned64 result = 0;
-
-  /* The format type has already been checked: */
-  switch (fmt)
-    {
-    case fmt_single:
-    case fmt_double:
-      status = inner_mac(sim_fpu_op, op1, op2, op3, scale,
-			 negate, fmt, round, denorm, &result);
-      break;
-    case fmt_ps:
-      {
-	int status_u, status_l;
-	unsigned64 result_u, result_l;
-	status_u = inner_mac(sim_fpu_op, FP_PS_upper(op1), FP_PS_upper(op2),
-			     FP_PS_upper(op3), scale, negate, fmt_single,
-			     round, denorm, &result_u);
-	status_l = inner_mac(sim_fpu_op, FP_PS_lower(op1), FP_PS_lower(op2),
-			     FP_PS_lower(op3), scale, negate, fmt_single,
-			     round, denorm, &result_l);
-	result = FP_PS_cat(result_u, result_l);
-	status = status_u | status_l;
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status);
-  return result;
-}
-
-/* Common rsqrt code for single operands (.s or .d), intermediate rounding.  */
-static sim_fpu_status
-inner_rsqrt(unsigned64 op1,
-	    FP_formats fmt,
-	    sim_fpu_round round,
-	    sim_fpu_denorm denorm,
-	    unsigned64 *result)
-{
-  sim_fpu wop1;
-  sim_fpu ans;
-  sim_fpu_status status = 0;
-  sim_fpu_status op_status;
-  unsigned64 temp = 0;
-
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	unsigned32 res;
-	sim_fpu_32to (&wop1, op1);
-	status |= sim_fpu_sqrt (&ans, &wop1);
-	status |= sim_fpu_round_32 (&ans, status, round);
-	wop1 = ans;
-	op_status = sim_fpu_inv (&ans, &wop1);
-	op_status |= sim_fpu_round_32 (&ans, round, denorm);
-	sim_fpu_to32 (&res, &ans);
-	temp = res;
-	status |= op_status;
-	break;
-      }
-    case fmt_double:
-      {
-	unsigned64 res;
-	sim_fpu_64to (&wop1, op1);
-	status |= sim_fpu_sqrt (&ans, &wop1);
-	status |= sim_fpu_round_64 (&ans, round, denorm);
-	wop1 = ans;
-	op_status = sim_fpu_inv (&ans, &wop1);
-	op_status |= sim_fpu_round_64 (&ans, round, denorm);
-	sim_fpu_to64 (&res, &ans);
-	temp = res;
-	status |= op_status;
-	break;
-      }
-    default:
-      fprintf (stderr, "Bad switch\n");
-      abort ();
-    }
-  *result = temp;
-  return status;
-}
-
-static unsigned64
-fp_inv_sqrt(sim_cpu *cpu,
-	    address_word cia,
-	    unsigned64 op1,
-	    FP_formats fmt)
-{
-  sim_fpu_round round = rounding_mode (GETRM());
-  sim_fpu_round denorm = denorm_mode (cpu);
-  sim_fpu_status status = 0;
-  unsigned64 result = 0;
-
-  /* The format type has already been checked: */
-  switch (fmt)
-    {
-    case fmt_single:
-    case fmt_double:
-      status = inner_rsqrt (op1, fmt, round, denorm, &result);
-      break;
-    case fmt_ps:
-      {
-	int status_u, status_l;
-	unsigned64 result_u, result_l;
-	status_u = inner_rsqrt (FP_PS_upper(op1), fmt_single, round, denorm,
-				&result_u);
-	status_l = inner_rsqrt (FP_PS_lower(op1), fmt_single, round, denorm,
-				&result_l);
-	result = FP_PS_cat(result_u, result_l);
-	status = status_u | status_l;
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status);
-  return result;
-}
-
-
-unsigned64
-fp_abs(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op,
-       FP_formats fmt)
-{
-  return fp_unary(cpu, cia, &sim_fpu_abs, op, fmt);
-}
-
-unsigned64
-fp_neg(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op,
-       FP_formats fmt)
-{
-  return fp_unary(cpu, cia, &sim_fpu_neg, op, fmt);
-}
-
-unsigned64
-fp_add(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op1,
-       unsigned64 op2,
-       FP_formats fmt)
-{
-  return fp_binary(cpu, cia, &sim_fpu_add, op1, op2, fmt);
-}
-
-unsigned64
-fp_sub(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op1,
-       unsigned64 op2,
-       FP_formats fmt)
-{
-  return fp_binary(cpu, cia, &sim_fpu_sub, op1, op2, fmt);
-}
-
-unsigned64
-fp_mul(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op1,
-       unsigned64 op2,
-       FP_formats fmt)
-{
-  return fp_binary(cpu, cia, &sim_fpu_mul, op1, op2, fmt);
-}
-
-unsigned64
-fp_div(sim_cpu *cpu,
-       address_word cia,
-       unsigned64 op1,
-       unsigned64 op2,
-       FP_formats fmt)
-{
-  return fp_binary(cpu, cia, &sim_fpu_div, op1, op2, fmt);
-}
-
-unsigned64
-fp_recip(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op,
-         FP_formats fmt)
-{
-  return fp_unary(cpu, cia, &sim_fpu_inv, op, fmt);
-}
-
-unsigned64
-fp_sqrt(sim_cpu *cpu,
-        address_word cia,
-        unsigned64 op,
-        FP_formats fmt)
-{
-  return fp_unary(cpu, cia, &sim_fpu_sqrt, op, fmt);
-}
-
-unsigned64
-fp_rsqrt(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op,
-         FP_formats fmt)
-{
-  return fp_inv_sqrt(cpu, cia, op, fmt);
-}
-
-unsigned64
-fp_madd(sim_cpu *cpu,
-        address_word cia,
-        unsigned64 op1,
-        unsigned64 op2,
-        unsigned64 op3,
-        FP_formats fmt)
-{
-  return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 0, fmt);
-}
-
-unsigned64
-fp_msub(sim_cpu *cpu,
-        address_word cia,
-        unsigned64 op1,
-        unsigned64 op2,
-        unsigned64 op3,
-        FP_formats fmt)
-{
-  return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 0, fmt);
-}
-
-unsigned64
-fp_nmadd(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op1,
-         unsigned64 op2,
-         unsigned64 op3,
-         FP_formats fmt)
-{
-  return fp_mac(cpu, cia, &sim_fpu_add, op1, op2, op3, 0, 1, fmt);
-}
-
-unsigned64
-fp_nmsub(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op1,
-         unsigned64 op2,
-         unsigned64 op3,
-         FP_formats fmt)
-{
-  return fp_mac(cpu, cia, &sim_fpu_sub, op1, op2, op3, 0, 1, fmt);
-}
-
-
-/* MIPS-3D ASE operations.  */
-
-/* Variant of fp_binary for *r.ps MIPS-3D operations. */
-static unsigned64
-fp_binary_r(sim_cpu *cpu,
-	    address_word cia,
-	    int (*sim_fpu_op)(sim_fpu *, const sim_fpu *, const sim_fpu *),
-	    unsigned64 op1,
-	    unsigned64 op2) 
-{
-  sim_fpu wop1;
-  sim_fpu wop2;
-  sim_fpu ans;
-  sim_fpu_round round = rounding_mode (GETRM ());
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  sim_fpu_status status_u, status_l;
-  unsigned64 result;
-  unsigned32 res_u, res_l;
-
-  /* The format must be fmt_ps.  */
-  status_u = 0;
-  sim_fpu_32to (&wop1, FP_PS_upper (op1));
-  sim_fpu_32to (&wop2, FP_PS_lower (op1));
-  status_u |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-  status_u |= sim_fpu_round_32 (&ans, round, denorm);
-  sim_fpu_to32 (&res_u, &ans);
-  status_l = 0;
-  sim_fpu_32to (&wop1, FP_PS_upper (op2));
-  sim_fpu_32to (&wop2, FP_PS_lower (op2));
-  status_l |= (*sim_fpu_op) (&ans, &wop1, &wop2);
-  status_l |= sim_fpu_round_32 (&ans, round, denorm);
-  sim_fpu_to32 (&res_l, &ans);
-  result = FP_PS_cat (res_u, res_l);
-
-  update_fcsr (cpu, cia, status_u | status_l);
-  return result;
-}
-
-unsigned64
-fp_add_r(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op1,
-         unsigned64 op2,
-         FP_formats fmt)
-{
-  return fp_binary_r (cpu, cia, &sim_fpu_add, op1, op2);
-}
-
-unsigned64
-fp_mul_r(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op1,
-         unsigned64 op2,
-         FP_formats fmt)
-{
-  return fp_binary_r (cpu, cia, &sim_fpu_mul, op1, op2);
-}
-
-#define NR_FRAC_GUARD   (60)
-#define IMPLICIT_1 LSBIT64 (NR_FRAC_GUARD)
-
-static int
-fpu_inv1(sim_fpu *f, const sim_fpu *l)
-{
-  static const sim_fpu sim_fpu_one = {
-    sim_fpu_class_number, 0, IMPLICIT_1, 0
-  };
-  int  status = 0;
-  sim_fpu t;
-
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_maxfp;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  if (sim_fpu_is_infinity (l))
-    {
-      *f = sim_fpu_zero;
-      f->sign = l->sign;
-      return status;
-    }
-  status |= sim_fpu_div (f, &sim_fpu_one, l);
-  return status;
-}
-
-static int
-fpu_inv1_32(sim_fpu *f, const sim_fpu *l)
-{
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_max32;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  return fpu_inv1 (f, l);
-}
-
-static int
-fpu_inv1_64(sim_fpu *f, const sim_fpu *l)
-{
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_max64;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  return fpu_inv1 (f, l);
-}
-
-unsigned64
-fp_recip1(sim_cpu *cpu,
-          address_word cia,
-          unsigned64 op,
-          FP_formats fmt)
-{
-  switch (fmt)
-    {
-    case fmt_single:
-    case fmt_ps:
-      return fp_unary (cpu, cia, &fpu_inv1_32, op, fmt);
-    case fmt_double:
-      return fp_unary (cpu, cia, &fpu_inv1_64, op, fmt);
-    }
-  return 0;
-}
-
-unsigned64
-fp_recip2(sim_cpu *cpu,
-          address_word cia,
-          unsigned64 op1,
-          unsigned64 op2,
-          FP_formats fmt)
-{
-  static const unsigned64 one_single = UNSIGNED64 (0x3F800000);
-  static const unsigned64 one_double = UNSIGNED64 (0x3FF0000000000000);
-  static const unsigned64 one_ps = (UNSIGNED64 (0x3F800000) << 32 | UNSIGNED64 (0x3F800000));
-  unsigned64 one;
-
-  /* Implemented as nmsub fd, 1, fs, ft.  */
-  switch (fmt)
-    {
-    case fmt_single:  one = one_single;  break;
-    case fmt_double:  one = one_double;  break;
-    case fmt_ps:      one = one_ps;      break;
-    default:          one = 0;           abort ();
-    }
-  return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, one, 0, 1, fmt);
-}
-
-static int
-fpu_inv_sqrt1(sim_fpu *f, const sim_fpu *l)
-{
-  static const sim_fpu sim_fpu_one = {
-    sim_fpu_class_number, 0, IMPLICIT_1, 0
-  };
-  int  status = 0;
-  sim_fpu t;
-
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_maxfp;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  if (sim_fpu_is_infinity (l))
-    {
-      if (!l->sign)
-	{
-	  f->class = sim_fpu_class_zero;
-	  f->sign = 0;
-	}
-      else
-	{
-	  *f = sim_fpu_qnan;
-	  status = sim_fpu_status_invalid_sqrt;
-	}
-      return status;
-    }
-  status |= sim_fpu_sqrt (&t, l);
-  status |= sim_fpu_div (f, &sim_fpu_one, &t);
-  return status;
-}
-
-static int
-fpu_inv_sqrt1_32(sim_fpu *f, const sim_fpu *l)
-{
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_max32;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  return fpu_inv_sqrt1 (f, l);
-}
-
-static int
-fpu_inv_sqrt1_64(sim_fpu *f, const sim_fpu *l)
-{
-  if (sim_fpu_is_zero (l))
-    {
-      *f = sim_fpu_max64;
-      f->sign = l->sign;
-      return sim_fpu_status_invalid_div0;
-    }
-  return fpu_inv_sqrt1 (f, l);
-}
-
-unsigned64
-fp_rsqrt1(sim_cpu *cpu,
-          address_word cia,
-          unsigned64 op,
-          FP_formats fmt)
-{
-  switch (fmt)
-    {
-    case fmt_single:
-    case fmt_ps:
-      return fp_unary (cpu, cia, &fpu_inv_sqrt1_32, op, fmt);
-    case fmt_double:
-      return fp_unary (cpu, cia, &fpu_inv_sqrt1_64, op, fmt);
-    }
-  return 0;
-}
-
-unsigned64
-fp_rsqrt2(sim_cpu *cpu,
-          address_word cia,
-          unsigned64 op1,
-          unsigned64 op2,
-          FP_formats fmt)
-{
-  static const unsigned64 half_single = UNSIGNED64 (0x3F000000);
-  static const unsigned64 half_double = UNSIGNED64 (0x3FE0000000000000);
-  static const unsigned64 half_ps = (UNSIGNED64 (0x3F000000) << 32 | UNSIGNED64 (0x3F000000));
-  unsigned64 half;
-
-  /* Implemented as (nmsub fd, 0.5, fs, ft)/2, where the divide is
-     done by scaling the exponent during multiply.  */
-  switch (fmt)
-    {
-    case fmt_single:  half = half_single;  break;
-    case fmt_double:  half = half_double;  break;
-    case fmt_ps:      half = half_ps;      break;
-    default:          half = 0;            abort ();
-    }
-  return fp_mac (cpu, cia, &sim_fpu_sub, op1, op2, half, -1, 1, fmt);
-}
-
-
-/* Conversion operations.  */
-
-uword64
-convert (sim_cpu *cpu,
-	 address_word cia,
-	 int rm,
-	 uword64 op,
-	 FP_formats from,
-	 FP_formats to)
-{
-  sim_fpu wop;
-  sim_fpu_round round = rounding_mode (rm);
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  unsigned32 result32;
-  unsigned64 result64;
-  sim_fpu_status status = 0;
-
-  /* Convert the input to sim_fpu internal format */
-  switch (from)
-    {
-    case fmt_double:
-      sim_fpu_64to (&wop, op);
-      break;
-    case fmt_single:
-      sim_fpu_32to (&wop, op);
-      break;
-    case fmt_word:
-      status = sim_fpu_i32to (&wop, op, round);
-      break;
-    case fmt_long:
-      status = sim_fpu_i64to (&wop, op, round);
-      break;
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  /* Convert sim_fpu format into the output */
-  /* The value WOP is converted to the destination format, rounding
-     using mode RM. When the destination is a fixed-point format, then
-     a source value of Infinity, NaN or one which would round to an
-     integer outside the fixed point range then an IEEE Invalid Operation
-     condition is raised.  Not used if destination format is PS.  */
-  switch (to)
-    {
-    case fmt_single:
-      status |= sim_fpu_round_32 (&wop, round, denorm);
-      /* For a NaN, normalize mantissa bits (cvt.s.d can't preserve them) */
-      if (sim_fpu_is_qnan (&wop))
-	wop = sim_fpu_qnan;
-      sim_fpu_to32 (&result32, &wop);
-      result64 = result32;
-      break;
-    case fmt_double:
-      status |= sim_fpu_round_64 (&wop, round, denorm);
-      /* For a NaN, normalize mantissa bits (make cvt.d.s consistent) */
-      if (sim_fpu_is_qnan (&wop))
-	wop = sim_fpu_qnan;
-      sim_fpu_to64 (&result64, &wop);
-      break;
-    case fmt_word:
-      status |= sim_fpu_to32i (&result32, &wop, round);
-      result64 = result32;
-      break;
-    case fmt_long:
-      status |= sim_fpu_to64i (&result64, &wop, round);
-      break;
-    default:
-      result64 = 0;
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status);
-  return result64;
-}
-
-unsigned64
-ps_lower(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op)
-{
-  return FP_PS_lower (op);
-}
-
-unsigned64
-ps_upper(sim_cpu *cpu,
-         address_word cia,
-         unsigned64 op)
-{
-  return FP_PS_upper(op);
-}
-
-unsigned64
-pack_ps(sim_cpu *cpu,
-        address_word cia,
-        unsigned64 op1,
-        unsigned64 op2,
-        FP_formats fmt)
-{
-  unsigned64 result = 0;
-
-  /* The registers must specify FPRs valid for operands of type
-     "fmt". If they are not valid, the result is undefined. */
-
-  /* The format type should already have been checked: */
-  switch (fmt)
-    {
-    case fmt_single:
-      {
-	sim_fpu wop;
-	unsigned32 res_u, res_l;
-	sim_fpu_32to (&wop, op1);
-	sim_fpu_to32 (&res_u, &wop);
-	sim_fpu_32to (&wop, op2);
-	sim_fpu_to32 (&res_l, &wop);
-	result = FP_PS_cat(res_u, res_l);
-	break;
-      }
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  return result;
-}
-
-unsigned64
-convert_ps (sim_cpu *cpu,
-            address_word cia,
-            int rm,
-            unsigned64 op,
-            FP_formats from,
-            FP_formats to)
-{
-  sim_fpu wop_u, wop_l;
-  sim_fpu_round round = rounding_mode (rm);
-  sim_fpu_denorm denorm = denorm_mode (cpu);
-  unsigned32 res_u, res_l;
-  unsigned64 result;
-  sim_fpu_status status_u = 0, status_l = 0;
-
-  /* As convert, but used only for paired values (formats PS, PW) */
-
-  /* Convert the input to sim_fpu internal format */
-  switch (from)
-    {
-    case fmt_word:   /* fmt_pw */
-      sim_fpu_i32to (&wop_u, (op >> 32) & (unsigned)0xFFFFFFFF, round);
-      sim_fpu_i32to (&wop_l, op & (unsigned)0xFFFFFFFF, round);
-      break;
-    case fmt_ps:
-      sim_fpu_32to (&wop_u, FP_PS_upper(op));
-      sim_fpu_32to (&wop_l, FP_PS_lower(op));
-      break;
-    default:
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  /* Convert sim_fpu format into the output */
-  switch (to)
-    {
-    case fmt_word:   /* fmt_pw */
-      status_u |= sim_fpu_to32i (&res_u, &wop_u, round);
-      status_l |= sim_fpu_to32i (&res_l, &wop_l, round);
-      result = (((unsigned64)res_u) << 32) | (unsigned64)res_l;
-      break;
-    case fmt_ps:
-      status_u |= sim_fpu_round_32 (&wop_u, 0, round);
-      status_l |= sim_fpu_round_32 (&wop_l, 0, round);
-      sim_fpu_to32 (&res_u, &wop_u);
-      sim_fpu_to32 (&res_l, &wop_l);
-      result = FP_PS_cat(res_u, res_l);
-      break;
-    default:
-      result = 0;
-      sim_io_eprintf (SD, "Bad switch\n");
-      abort ();
-    }
-
-  update_fcsr (cpu, cia, status_u | status_l);
-  return result;
-}
-
-static const char *
-fpu_format_name (FP_formats fmt)
-{
-  switch (fmt)
-    {
-    case fmt_single:
-      return "single";
-    case fmt_double:
-      return "double";
-    case fmt_word:
-      return "word";
-    case fmt_long:
-      return "long";
-    case fmt_ps:
-      return "ps";
-    case fmt_unknown:
-      return "<unknown>";
-    case fmt_uninterpreted:
-      return "<uninterpreted>";
-    case fmt_uninterpreted_32:
-      return "<uninterpreted_32>";
-    case fmt_uninterpreted_64:
-      return "<uninterpreted_64>";
-    default:
-      return "<format error>";
-    }
-}
-
-#ifdef DEBUG
-static const char *
-fpu_rounding_mode_name (int rm)
-{
-  switch (rm)
-    {
-    case FP_RM_NEAREST:
-      return "Round";
-    case FP_RM_TOZERO:
-      return "Trunc";
-    case FP_RM_TOPINF:
-      return "Ceil";
-    case FP_RM_TOMINF:
-      return "Floor";
-    default:
-      return "<rounding mode error>";
-    }
-}
-#endif /* DEBUG */
diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h
deleted file mode 100644
index 9a189a9..0000000
--- a/sim/mips/cp1.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*> cp1.h <*/
-/* MIPS Simulator FPU (CoProcessor 1) definitions.
-   Copyright (C) 1997, 1998, 2002 Free Software Foundation, Inc.
-   Derived from sim-main.h contributed by Cygnus Solutions,
-   modified substantially by Ed Satterthwaite of Broadcom Corporation
-   (SiByte).
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef CP1_H
-#define CP1_H
-
-/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR) 
-   in CPU state (struct sim_cpu), and for FPU functions.  */
-
-#define fcsr_FCC_mask      (0xFE800000)
-#define fcsr_FCC_shift     (23)
-#define	fcsr_FCC_bit(cc)   ((cc) == 0 ? 23 : (24 + (cc)))
-#define fcsr_FS            (1 << 24) /* MIPS III onwards : Flush to Zero */
-#define fcsr_ZERO_mask     (0x007C0000)
-#define fcsr_CAUSE_mask    (0x0003F000)
-#define fcsr_CAUSE_shift   (12)
-#define fcsr_ENABLES_mask  (0x00000F80)
-#define fcsr_ENABLES_shift (7)
-#define fcsr_FLAGS_mask    (0x0000007C)
-#define fcsr_FLAGS_shift   (2)
-#define fcsr_RM_mask       (0x00000003)
-#define fcsr_RM_shift      (0)
-
-#define fenr_FS            (0x00000004)
-
-/* Macros to update and retrieve the FCSR condition-code bits.  This
-   is complicated by the fact that there is a hole in the index range
-   of the bits within the FCSR register.  (Note that the number of bits
-   visible depends on the ISA in use, but that is handled elsewhere.)  */
-#define SETFCC(cc,v) \
-  do { \
-    (FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \
-  } while (0)
-#define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0)
-
-
-/* Read flush-to-zero bit (not right-justified).  */
-#define GETFS()            ((int)(FCSR & fcsr_FS))
-
-
-/* FCSR flag bits definitions and access macros.  */
-#define IR            0   /* I: Inexact Result */
-#define UF            1   /* U: UnderFlow */
-#define OF            2   /* O: OverFlow */
-#define DZ            3   /* Z: Division by Zero */
-#define IO            4   /* V: Invalid Operation */
-#define UO            5   /* E: Unimplemented Operation (CAUSE field only) */
-
-#define FP_FLAGS(b)   (1 << ((b) + fcsr_FLAGS_shift))
-#define FP_ENABLE(b)  (1 << ((b) + fcsr_ENABLES_shift))
-#define FP_CAUSE(b)   (1 << ((b) + fcsr_CAUSE_shift))
-
-
-/* Rounding mode bit definitions and access macros.  */
-#define FP_RM_NEAREST 0   /* Round to nearest (Round).  */
-#define FP_RM_TOZERO  1   /* Round to zero (Trunc).  */
-#define FP_RM_TOPINF  2   /* Round to Plus infinity (Ceil).  */
-#define FP_RM_TOMINF  3   /* Round to Minus infinity (Floor).  */
-
-#define GETRM()       ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask)
-
-
-#endif /* CP1_H */
diff --git a/sim/mips/dsp.c b/sim/mips/dsp.c
deleted file mode 100644
index b829d77..0000000
--- a/sim/mips/dsp.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Simulation code for the MIPS DSP ASE.
-   Copyright (C) 2005 Free Software Foundation, Inc.
-   Contributed by MIPS Technologies, Inc.  Written by Chao-ying Fu.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "sim-main.h"
-
-int DSPLO_REGNUM[4] =
-{
-  AC0LOIDX,
-  AC1LOIDX,
-  AC2LOIDX,
-  AC3LOIDX,
-};
-
-int DSPHI_REGNUM[4] =
-{
-  AC0HIIDX,
-  AC1HIIDX,
-  AC2HIIDX,
-  AC3HIIDX,
-};
diff --git a/sim/mips/dsp.igen b/sim/mips/dsp.igen
deleted file mode 100644
index 18aafcb..0000000
--- a/sim/mips/dsp.igen
+++ /dev/null
@@ -1,1820 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the MIPS DSP ASE.
-// Copyright (C) 2005 Free Software Foundation, Inc.
-// Contributed by MIPS Technologies, Inc.  Written by Chao-ying Fu.
-//
-// This file is part of GDB, the GNU debugger.
-//
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-
-// op: 0 = ADD, 1 = SUB
-// sat: 0 = no saturation, 1 = saturation
-:function:::void:do_ph_op:int rd, int rs, int rt, int op, int sat
-{
-  int i;
-  signed32 h0;
-  signed16 h1, h2;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned32 result = 0;
-  for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-      if (op == 0) // ADD
-	h0 = (signed32)h1 + (signed32)h2;
-      else // SUB
-        h0 = (signed32)h1 - (signed32)h2;
-      if (((h0 & 0x10000) >> 1) != (h0 & 0x8000))
-	{
-	  DSPCR |= DSPCR_OUFLAG4;
-	  if (sat == 1)
-	    {
-	      if (h0 & 0x10000)
-		h0 = 0x8000;
-	      else
-		h0 = 0x7fff;
-	    }
-	}
-      result |= ((unsigned32)((unsigned16)h0) << i);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-// op: 0 = ADD, 1 = SUB
-:function:::void:do_w_op:int rd, int rs, int rt, int op
-{
-  signed64 h0;
-  signed32 h1, h2;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned32 result = 0;
-  h1 = (signed32)v1;
-  h2 = (signed32)v2;
-  if (op == 0) // ADD
-    h0 = (signed64)h1 + (signed64)h2;
-  else // SUB
-    h0 = (signed64)h1 - (signed64)h2;
-  if (((h0 & 0x100000000) >> 1) != (h0 & 0x80000000))
-    {
-      DSPCR |= DSPCR_OUFLAG4;
-      if (h0 & 0x100000000)
-	h0 = 0x80000000;
-      else
-	h0 = 0x7fffffff;
-    }
-  GPR[rd] = EXTEND32 (h0);
-}
-
-// op: 0 = ADD, 1 = SUB
-// sat: 0 = no saturation, 1 = saturation
-:function:::void:do_qb_op:int rd, int rs, int rt, int op, int sat
-{
-  int i;
-  unsigned32 h0;
-  unsigned8 h1, h2;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned32 result = 0;
-  for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8)
-    {
-      h1 = (unsigned8)(v1 & 0xff);
-      h2 = (unsigned8)(v2 & 0xff);
-      if (op == 0) // ADD
-	h0 = (unsigned32)h1 + (unsigned32)h2;
-      else // SUB
-	h0 = (unsigned32)h1 - (unsigned32)h2;
-      if (h0 & 0x100)
-	{
-	  DSPCR |= DSPCR_OUFLAG4;
-	  if (sat == 1)
-	    {
-	      if (op == 0) // ADD
-		h0 = 0xff;
-	      else // SUB
-		h0 = 0;
-	    }
-	}
-      result |= ((unsigned32)((unsigned8)h0) << i);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-// op: 0 = left, 1 = right
-:function:::void:do_qb_shift:int rd, int rt, int shift, int op
-{
-  int i, j;
-  unsigned8 h0;
-  unsigned32 v1 = GPR[rt];
-  unsigned32 result = 0;
-  for (i = 0; i < 32; i += 8, v1 >>= 8)
-    {
-      h0 = (unsigned8)(v1 & 0xff);
-      if (op == 0) // left
-	{
-	  for (j = 7; j >= 8 - shift; j--)
-	    {
-	      if (h0 & (1<<j))
-		{
-		  DSPCR |= DSPCR_OUFLAG6;
-		  break;
-		}
-	    }
-          h0 = h0 << shift;
-	}
-      else // right
-        h0 = h0 >> shift;
-      result |= ((unsigned32)h0 << i);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-// op: 0 = left, 1 = right
-// sat: 0 = no saturation/rounding, 1 = saturation/rounding
-:function:::void:do_ph_shift:int rd, int rt, int shift, int op, int sat
-{
-  int i, j;
-  signed16 h0;
-  unsigned32 v1 = GPR[rt];
-  unsigned32 result = 0;
-  int setcond;
-  for (i = 0; i < 32; i += 16, v1 >>= 16)
-    {
-      h0 = (signed16)(v1 & 0xffff);
-      if (op == 0) // left
-	{
-	  setcond = 0;
-	  if (h0 & (1<<15))
-	    {
-	      for (j = 14; j >= 15 - shift; j--)
-		{
-		  if (!(h0 & (1 << j)))
-		    {
-		      DSPCR |= DSPCR_OUFLAG6;
-		      setcond = 1;
-		      break;
-		    }
-		}
-	    }
-	  else
-	    {
-	      for (j = 14; j >= 15 - shift; j--)
-		{
-		  if (h0 & (1 << j))
-		    {
-		      DSPCR |= DSPCR_OUFLAG6;
-		      setcond = 2;
-		      break;
-		    }
-		}
-	    }
-	  h0 = h0 << shift;
-	  if (sat == 1)
-	    {
-	      if (setcond == 2)
-		h0 = 0x7fff; 
-	      else if (setcond == 1)
-		h0 = 0x8000;
-	    }
-	}
-      else // right
-	{
-	  if (sat == 1 && shift != 0 && (h0 & (1 << (shift-1))))
-	    h0 = (h0 >> shift) + 1;
-	  else
-	    h0 = h0 >> shift;
-	}
-
-      result |= ((unsigned32)((unsigned16)h0) << i);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-:function:::void:do_w_shll:int rd, int rt, int shift
-{
-  int i;
-  unsigned32 v1 = GPR[rt];
-  unsigned32 result = 0;
-  int setcond = 0;
-  if (v1 & (1 << 31))
-    {
-      for (i = 30; i >= 31 - shift; i--)
-	{
-	  if (!(v1 & (1 << i)))
-	    {
-	      DSPCR |= DSPCR_OUFLAG6;
-	      setcond = 1;
-	      break;
-	    }
-	}
-    }
-  else
-    {
-      for (i = 30; i >= 31 - shift; i--)
-	{
-	  if (v1 & (1 << i))
-	    {
-	      DSPCR |= DSPCR_OUFLAG6;
-	      setcond = 2;
-	      break;
-	    }
-	}
-    }
-  if (setcond == 2)
-    result = 0x7fffffff; 
-  else if (setcond == 1)
-    result = 0x80000000;
-  else
-    result = v1 << shift; 
-  GPR[rd] = EXTEND32 (result);
-}
-
-:function:::void:do_w_shra:int rd, int rt, int shift
-{
-  unsigned32 result = GPR[rt];
-  signed32 h0 = (signed32)result;
-  if (shift != 0 && (h0 & (1 << (shift-1))))
-    h0 = (h0 >> shift) + 1;
-  else
-    h0 = h0 >> shift;
-  GPR[rd] = EXTEND32 (h0);
-}
-
-011111,5.RS,5.RT,5.RD,01010,010000:SPECIAL3:32::ADDQ.PH
-"addq.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_op (SD_, RD, RS, RT, 0, 0);
-}
-
-011111,5.RS,5.RT,5.RD,01110,010000:SPECIAL3:32::ADDQ_S.PH
-"addq_s.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_op (SD_, RD, RS, RT, 0, 1);
-}
-
-011111,5.RS,5.RT,5.RD,10110,010000:SPECIAL3:32::ADDQ_S.W
-"addq_s.w r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_w_op (SD_, RD, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00000,010000:SPECIAL3:32::ADDU.QB
-"addu.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_op (SD_, RD, RS, RT, 0, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00100,010000:SPECIAL3:32::ADDU_S.QB
-"addu_s.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_op (SD_, RD, RS, RT, 0, 1);
-}
-
-011111,5.RS,5.RT,5.RD,01011,010000:SPECIAL3:32::SUBQ.PH
-"subq.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_op (SD_, RD, RS, RT, 1, 0);
-}
-
-011111,5.RS,5.RT,5.RD,01111,010000:SPECIAL3:32::SUBQ_S.PH
-"subq_s.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_op (SD_, RD, RS, RT, 1, 1);
-}
-
-011111,5.RS,5.RT,5.RD,10111,010000:SPECIAL3:32::SUBQ_S.W
-"subq_s.w r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_w_op (SD_, RD, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,5.RD,00001,010000:SPECIAL3:32::SUBU.QB
-"subu.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_op (SD_, RD, RS, RT, 1, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00101,010000:SPECIAL3:32::SUBU_S.QB
-"subu_s.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_op (SD_, RD, RS, RT, 1, 1);
-}
-
-011111,5.RS,5.RT,5.RD,10000,010000:SPECIAL3:32::ADDSC
-"addsc r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned64 h0;
-  h0 = (unsigned64)v1 + (unsigned64)v2;
-  if (h0 & 0x100000000LL)
-    DSPCR |= DSPCR_CARRY;
-  GPR[RD] = EXTEND32 (h0);
-}
-
-011111,5.RS,5.RT,5.RD,10001,010000:SPECIAL3:32::ADDWC
-"addwc r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned64 h0;
-  signed32 h1 = (signed32) v1;
-  signed32 h2 = (signed32) v2;
-  h0 = (signed64)h1 + (signed64)h2
-       + (signed64)((DSPCR >> DSPCR_CARRY_SHIFT) & DSPCR_CARRY_MASK);
-  if (((h0 & 0x100000000LL) >> 1) != (h0 & 0x80000000))
-    DSPCR |= DSPCR_OUFLAG4;
-  GPR[RD] = EXTEND32 (h0);
-}
-
-011111,5.RS,5.RT,5.RD,10010,010000:SPECIAL3:32::MODSUB
-"modsub r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 result = 0;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned32 decr = v2 & 0xff;
-  unsigned32 lastindex = (v2 & 0xffff00) >> 8;
-  if (v1 == 0)
-    result = lastindex;
-  else
-    result =  v1 - decr;
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,5.RS,00000,5.RD,10100,010000:SPECIAL3:32::RADDU.W.QB
-"raddu.w.qb r<RD>, r<RS>"
-*dsp:
-{
-  int i;
-  unsigned8 h0;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 result = 0;
-  for (i = 0; i < 32; i += 8, v1 >>= 8)
-    {
-      h0 = (unsigned8)(v1 & 0xff);
-      result += (unsigned32)h0;
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,00000,5.RT,5.RD,01001,010010:SPECIAL3:32::ABSQ_S.PH
-"absq_s.ph r<RD>, r<RT>"
-*dsp:
-{
-  int i;
-  signed16 h0;
-  unsigned32 v1 = GPR[RT];
-  unsigned32 result = 0;
-  for (i = 0; i < 32; i += 16, v1 >>= 16)
-    {
-      h0 = (signed16)(v1 & 0xffff);
-      if (h0 == (signed16)0x8000)
-	{
-	  DSPCR |= DSPCR_OUFLAG4;
-	  h0 = 0x7fff;
-	}
-      else if (h0 & 0x8000)
-	h0 = -h0; 
-      result |= ((unsigned32)((unsigned16)h0) << i);
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,00000,5.RT,5.RD,10001,010010:SPECIAL3:32::ABSQ_S.W
-"absq_s.w r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  signed32 h0 = (signed32)v1;
-  if (h0 == (signed32)0x80000000)
-    {
-      DSPCR |= DSPCR_OUFLAG4;
-      h0 = 0x7fffffff;
-    }
-  else if (h0 & 0x80000000)
-    h0 = -h0; 
-  GPR[RD] = EXTEND32 (h0);
-}
-
-011111,5.RS,5.RT,5.RD,01100,010001:SPECIAL3:32::PRECRQ.QB.PH
-"precrq.qb.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned32 tempu = (v1 & 0xff000000) >> 24;
-  unsigned32 tempv = (v1 & 0xff00) >> 8;
-  unsigned32 tempw = (v2 & 0xff000000) >> 24;
-  unsigned32 tempx = (v2 & 0xff00) >> 8;
-  GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
-}
-
-011111,5.RS,5.RT,5.RD,10100,010001:SPECIAL3:32::PRECRQ.PH.W
-"precrq.ph.w r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned32 tempu = (v1 & 0xffff0000) >> 16;
-  unsigned32 tempv = (v2 & 0xffff0000) >> 16;
-  GPR[RD] = EXTEND32 ((tempu << 16) | tempv);
-}
-
-011111,5.RS,5.RT,5.RD,10101,010001:SPECIAL3:32::PRECRQ_RS.PH.W
-"precrq_rs.ph.w r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  signed32 h1 = (signed32)v1;
-  signed32 h2 = (signed32)v2;
-  signed64 temp1 = (signed64)h1 + (signed64)0x8000;
-  signed32 temp2;
-  signed64 temp3 = (signed64)h2 + (signed64)0x8000;
-  signed32 temp4;
-  if (((temp1 & 0x100000000LL) >> 1) != (temp1 & 0x80000000))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      temp2 = 0x7fff;
-    }
-  else
-    temp2 = (signed32)((temp1 & 0xffff0000) >> 16);
-  if (((temp3 & 0x100000000LL) >> 1) != (temp3 & 0x80000000))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      temp4 = 0x7fff;
-    }
-  else
-    temp4 = (signed32)((temp3 & 0xffff0000) >> 16);
-  GPR[RD] = EXTEND32 ((temp2 << 16) | temp4);
-}
-
-011111,5.RS,5.RT,5.RD,01111,010001:SPECIAL3:32::PRECRQU_S.QB.PH
-"precrqu_s.qb.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned32 tempu, tempv, tempw, tempx;
-  if (v1 & 0x80000000)
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempu = 0;
-    }
-  else if (!(v1 & 0x80000000) && ((v1 >> 16) > (unsigned32)0x7f80))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempu = 0xff;
-    }
-  else
-    tempu = (v1 & 0x7f800000) >> 23;
-  if (v1 & 0x8000)
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempv = 0;
-    }
-  else if (!(v1 & 0x8000) && ((v1 & 0xffff) > (unsigned32)0x7f80))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempv = 0xff;
-    }
-  else
-    tempv = (v1 & 0x7f80) >> 7;
-  if (v2 & 0x80000000)
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempw = 0;
-    }
-  else if (!(v2 & 0x80000000) && ((v2 >> 16) > (unsigned32)0x7f80))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempw = 0xff;
-    }
-  else
-    tempw = (v2 & 0x7f800000) >> 23;
-  if (v2 & 0x8000)
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempx = 0;
-    }
-  else if (!(v2 & 0x8000) && ((v2 & 0xffff) > (unsigned32)0x7f80))
-    {
-      DSPCR |= DSPCR_OUFLAG6;
-      tempx = 0xff;
-    }
-  else
-    tempx = (v2 & 0x7f80) >> 7;
-  GPR[RD] = EXTEND32 ((tempu << 24) | (tempv << 16) | (tempw << 8) | tempx);
-}
-
-011111,00000,5.RT,5.RD,01100,010010:SPECIAL3:32::PRECEQ.W.PHL
-"preceq.w.phl r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 (v1 & 0xffff0000);
-}
-
-011111,00000,5.RT,5.RD,01101,010010:SPECIAL3:32::PRECEQ.W.PHR
-"preceq.w.phr r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xffff) << 16);
-}
-
-011111,00000,5.RT,5.RD,00100,010010:SPECIAL3:32::PRECEQU.PH.QBL
-"precequ.ph.qbl r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff0000) >> 9);
-}
-
-011111,00000,5.RT,5.RD,00101,010010:SPECIAL3:32::PRECEQU.PH.QBR
-"precequ.ph.qbr r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff00) << 15) | ((v1 & 0xff) << 7);
-}
-
-011111,00000,5.RT,5.RD,00110,010010:SPECIAL3:32::PRECEQU.PH.QBLA
-"precequ.ph.qbla r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 1) | ((v1 & 0xff00) >> 1);
-}
-
-011111,00000,5.RT,5.RD,00111,010010:SPECIAL3:32::PRECEQU.PH.QBRA
-"precequ.ph.qbra r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff0000) << 7) | ((v1 & 0xff) << 7);
-}
-
-011111,00000,5.RT,5.RD,11100,010010:SPECIAL3:32::PRECEU.PH.QBL
-"preceu.ph.qbl r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff0000) >> 16);
-}
-
-011111,00000,5.RT,5.RD,11101,010010:SPECIAL3:32::PRECEU.PH.QBR
-"preceu.ph.qbr r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff00) << 8) | (v1 & 0xff);
-}
-
-011111,00000,5.RT,5.RD,11110,010010:SPECIAL3:32::PRECEU.PH.QBLA
-"preceu.ph.qbla r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff000000) >> 8) | ((v1 & 0xff00) >> 8);
-}
-
-011111,00000,5.RT,5.RD,11111,010010:SPECIAL3:32::PRECEU.PH.QBRA
-"preceu.ph.qbra r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 & 0xff0000) | (v1 & 0xff));
-}
-
-011111,00,3.SHIFT3,5.RT,5.RD,00000,010011:SPECIAL3:32::SHLL.QB
-"shll.qb r<RD>, r<RT>, <SHIFT3>"
-*dsp:
-{
-  do_qb_shift (SD_, RD, RT, SHIFT3, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00010,010011:SPECIAL3:32::SHLLV.QB
-"shllv.qb r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x7;
-  do_qb_shift (SD_, RD, RT, shift, 0);
-}
-
-011111,0,4.SHIFT4,5.RT,5.RD,01000,010011:SPECIAL3:32::SHLL.PH
-"shll.ph r<RD>, r<RT>, <SHIFT4>"
-*dsp:
-{
-  do_ph_shift (SD_, RD, RT, SHIFT4, 0, 0);
-}
-
-011111,5.RS,5.RT,5.RD,01010,010011:SPECIAL3:32::SHLLV.PH
-"shllv.ph r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0xf;
-  do_ph_shift (SD_, RD, RT, shift, 0, 0);
-}
-
-011111,0,4.SHIFT4,5.RT,5.RD,01100,010011:SPECIAL3:32::SHLL_S.PH
-"shll_s.ph r<RD>, r<RT>, <SHIFT4>"
-*dsp:
-{
-  do_ph_shift (SD_, RD, RT, SHIFT4, 0, 1);
-}
-
-011111,5.RS,5.RT,5.RD,01110,010011:SPECIAL3:32::SHLLV_S.PH
-"shllv_s.ph r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0xf;
-  do_ph_shift (SD_, RD, RT, shift, 0, 1);
-}
-
-011111,5.SHIFT5,5.RT,5.RD,10100,010011:SPECIAL3:32::SHLL_S.W
-"shll_s.w r<RD>, r<RT>, <SHIFT5>"
-*dsp:
-{
-  do_w_shll (SD_, RD, RT, SHIFT5);
-}
-
-011111,5.RS,5.RT,5.RD,10110,010011:SPECIAL3:32::SHLLV_S.W
-"shllv_s.w r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_w_shll (SD_, RD, RT, shift);
-}
-
-011111,00,3.SHIFT3,5.RT,5.RD,00001,010011:SPECIAL3:32::SHRL.QB
-"shrl.qb r<RD>, r<RT>, <SHIFT3>"
-*dsp:
-{
-  do_qb_shift (SD_, RD, RT, SHIFT3, 1);
-}
-
-011111,5.RS,5.RT,5.RD,00011,010011:SPECIAL3:32::SHRLV.QB
-"shrlv.qb r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x7;
-  do_qb_shift (SD_, RD, RT, shift, 1);
-}
-
-011111,0,4.SHIFT4,5.RT,5.RD,01001,010011:SPECIAL3:32::SHRA.PH
-"shra.ph r<RD>, r<RT>, <SHIFT4>"
-*dsp:
-{
-  do_ph_shift (SD_, RD, RT, SHIFT4, 1, 0);
-}
-
-011111,5.RS,5.RT,5.RD,01011,010011:SPECIAL3:32::SHRAV.PH
-"shrav.ph r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0xf;
-  do_ph_shift (SD_, RD, RT, shift, 1, 0);
-}
-
-011111,0,4.SHIFT4,5.RT,5.RD,01101,010011:SPECIAL3:32::SHRA_R.PH
-"shra_r.ph r<RD>, r<RT>, <SHIFT4>"
-*dsp:
-{
-  do_ph_shift (SD_, RD, RT, SHIFT4, 1, 1);
-}
-
-011111,5.RS,5.RT,5.RD,01111,010011:SPECIAL3:32::SHRAV_R.PH
-"shrav_r.ph r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0xf;
-  do_ph_shift (SD_, RD, RT, shift, 1, 1);
-}
-
-011111,5.SHIFT5,5.RT,5.RD,10101,010011:SPECIAL3:32::SHRA_R.W
-"shra_r.w r<RD>, r<RT>, <SHIFT5>"
-*dsp:
-{
-  do_w_shra (SD_, RD, RT, SHIFT5);
-}
-
-011111,5.RS,5.RT,5.RD,10111,010011:SPECIAL3:32::SHRAV_R.W
-"shrav_r.w r<RD>, r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_w_shra (SD_, RD, RT, shift);
-}
-
-// loc: 0 = qhl, 1 = qhr
-:function:::void:do_qb_muleu:int rd, int rs, int rt, int loc
-{
-  int i;
-  unsigned32 result = 0;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned16 h1, h2;
-  unsigned32 prod;
-  if (loc == 0)
-    v1 >>= 16;
-  for (i = 0; i < 32; i += 16, v1 >>= 8, v2 >>= 16)
-    {
-      h1 = (unsigned16)(v1 & 0xff);
-      h2 = (unsigned16)(v2 & 0xffff);
-      prod = (unsigned32)h1 * (unsigned32)h2;
-      if (prod > 0xffff)
-	{
-	  DSPCR |= DSPCR_OUFLAG5;
-	  prod = 0xffff;
-	}
-      result |= ((unsigned32)prod << i);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-011111,5.RS,5.RT,5.RD,00110,010000:SPECIAL3:32::MULEU_S.PH.QBL
-"muleu_s.ph.qbl r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_muleu (SD_, RD, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00111,010000:SPECIAL3:32::MULEU_S.PH.QBR
-"muleu_s.ph.qbr r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_muleu (SD_, RD, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,5.RD,11111,010000:SPECIAL3:32::MULQ_RS.PH
-"mulq_rs.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  int i;
-  unsigned32 result = 0;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  signed16 h1, h2;
-  signed32 prod;
-  for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-      if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
-	{
-	  DSPCR |= DSPCR_OUFLAG5;
-	  prod = 0x7fffffff;
-	}
-      else
-	prod = (((signed32)h1 * (signed32)h2) << 1) + (signed32)0x8000;
-
-      result |= (((unsigned32)prod >> 16) << i);
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-// loc: 0 = phl, 1 = phr
-:function:::void:do_ph_muleq:int rd, int rs, int rt, int loc
-{
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  signed16 h1, h2;
-  signed32 prod;
-  if (loc == 0)
-    {
-      h1 = (signed16)(v1 >> 16);
-      h2 = (signed16)(v2 >> 16);
-    }
-  else
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-    }
-  if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
-    {
-      DSPCR |= DSPCR_OUFLAG5;
-      prod = 0x7fffffff;
-    }
-  else
-    prod = ((signed32)h1 * (signed32)h2) << 1;
-  GPR[rd] = EXTEND32 (prod);
-}
-
-011111,5.RS,5.RT,5.RD,11100,010000:SPECIAL3:32::MULEQ_S.W.PHL
-"muleq_s.w.phl r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_muleq (SD_, RD, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,5.RD,11101,010000:SPECIAL3:32::MULEQ_S.W.PHR
-"muleq_s.w.phr r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_muleq (SD_, RD, RS, RT, 1);
-}
-
-// op: 0 = DPAU 1 = DPSU
-// loc: 0 = qbl, 1 = qbr
-:function:::void:do_qb_dot_product:int ac, int rs, int rt, int op, int loc
-{
-  int i;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned8 h1, h2;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
-  if (loc == 0)
-    {
-      v1 >>= 16;
-      v2 >>= 16;
-    }
-  for (i = 0; i < 16; i += 8, v1 >>= 8, v2 >>= 8)
-    {
-      h1 = (unsigned8)(v1 & 0xff);
-      h2 = (unsigned8)(v2 & 0xff);
-      if (op == 0) // DPAU
-	prod += (unsigned64)h1 * (unsigned64)h2;
-      else // DPSU
-	prod -= (unsigned64)h1 * (unsigned64)h2;
-    }
-  DSPLO(ac) = EXTEND32 (prod);
-  DSPHI(ac) = EXTEND32 (prod >> 32);
-}
-
-011111,5.RS,5.RT,000,2.AC,00011,110000:SPECIAL3:32::DPAU.H.QBL
-"dpau.h.qbl ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_dot_product (SD_, AC, RS, RT, 0, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,00111,110000:SPECIAL3:32::DPAU.H.QBR
-"dpau.h.qbr ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_dot_product (SD_, AC, RS, RT, 0, 1);
-}
-
-011111,5.RS,5.RT,000,2.AC,01011,110000:SPECIAL3:32::DPSU.H.QBL
-"dpsu.h.qbl ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_dot_product (SD_, AC, RS, RT, 1, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,01111,110000:SPECIAL3:32::DPSU.H.QBR
-"dpsu.h.qbr ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_dot_product (SD_, AC, RS, RT, 1, 1);
-}
-
-// op: 0 = DPAQ 1 = DPSQ
-:function:::void:do_ph_dot_product:int ac, int rs, int rt, int op
-{
-  int i;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  signed16 h1, h2;
-  signed32 result;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
-  for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-      if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
-	{
-	  DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-	  result = (signed32)0x7fffffff;
-	}
-      else
-	result = ((signed32)h1 * (signed32)h2) << 1;
-
-      if (op == 0) // DPAQ
-	prod += (signed64)result;
-      else // DPSQ
-	prod -= (signed64)result;
-    }
-  DSPLO(ac) = EXTEND32 (prod);
-  DSPHI(ac) = EXTEND32 (prod >> 32);
-}
-
-011111,5.RS,5.RT,000,2.AC,00100,110000:SPECIAL3:32::DPAQ_S.W.PH
-"dpaq_s.w.ph ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_dot_product (SD_, AC, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,00101,110000:SPECIAL3:32::DPSQ_S.W.PH
-"dpsq_s.w.ph ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_dot_product (SD_, AC, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,000,2.AC,00110,110000:SPECIAL3:32::MULSAQ_S.W.PH
-"mulsaq_s.w.ph ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  int i;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  signed16 h1, h2;
-  signed32 result;
-  unsigned32 lo = DSPLO(AC);
-  unsigned32 hi = DSPHI(AC);
-  signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
-  for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-      if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
-	{
-	  DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + AC));
-	  result = (signed32) 0x7fffffff;
-	}
-      else
-	result = ((signed32)h1 * (signed32)h2) << 1;
-
-      if (i == 0)
-	prod -= (signed64) result;
-      else
-	prod += (signed64) result;
-    }
-  DSPLO(AC) = EXTEND32 (prod);
-  DSPHI(AC) = EXTEND32 (prod >> 32);
-}
-
-// op: 0 = DPAQ 1 = DPSQ
-:function:::void:do_w_dot_product:int ac, int rs, int rt, int op
-{
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  signed32 h1, h2;
-  signed64 result;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned32 resultlo;
-  unsigned32 resulthi;
-  unsigned32 carry;
-  unsigned64 temp1;
-  signed64 temp2;
-  h1 = (signed32) v1;
-  h2 = (signed32) v2;
-  if (h1 == 0x80000000 && h2 == 0x80000000)
-    {
-      DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-      result = (signed64) 0x7fffffffffffffffLL;
-    }
-  else
-    result = ((signed64)h1 * (signed64)h2) << 1;
-  resultlo = (unsigned32)(result);
-  resulthi = (unsigned32)(result >> 32);
-  if (op ==0) // DPAQ
-    {
-      temp1 = (unsigned64)lo + (unsigned64)resultlo;
-      carry = (unsigned32)((temp1 >> 32) & 1);
-      temp2 = (signed64)((signed32)hi) + (signed64)((signed32)resulthi) +
-	      (signed64)((signed32)carry);
-    }
-  else // DPSQ
-    {
-      temp1 = (unsigned64)lo - (unsigned64)resultlo;
-      carry = (unsigned32)((temp1 >> 32) & 1);
-      temp2 = (signed64)((signed32)hi) - (signed64)((signed32)resulthi) -
-	      (signed64)((signed32)carry);
-    }
-  if (((temp2 & 0x100000000LL) >> 1) != (temp2 & 0x80000000LL))
-    {
-      DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-      if (temp2 & 0x100000000LL)
-	{
-	  DSPLO(ac) = EXTEND32 (0x00000000);
-	  DSPHI(ac) = EXTEND32 (0x80000000);
-	}
-      else
-	{
-	  DSPLO(ac) = EXTEND32 (0xffffffff);
-	  DSPHI(ac) = EXTEND32 (0x7fffffff);
-	}
-    }
-  else
-    {
-      DSPLO(ac) = EXTEND32 (temp1);
-      DSPHI(ac) = EXTEND32 (temp2);
-    }
-}
-
-011111,5.RS,5.RT,000,2.AC,01100,110000:SPECIAL3:32::DPAQ_SA.L.W
-"dpaq_sa.l.w ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_w_dot_product (SD_, AC, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,01101,110000:SPECIAL3:32::DPSQ_SA.L.W
-"dpsq_sa.l.w ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_w_dot_product (SD_, AC, RS, RT, 1);
-}
-
-// op: 0 = MAQ_S 1 = MAQ_SA
-// loc: 0 = phl, 1 = phr
-:function:::void:do_ph_maq:int ac, int rs, int rt, int op, int loc
-{
-  int i;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  signed16 h1, h2;
-  signed32 result;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  signed64 prod = (signed64)((((unsigned64)hi) << 32) + (unsigned64)lo);
-  if (loc == 0)
-    {
-      h1 = (signed16)(v1 >> 16);
-      h2 = (signed16)(v2 >> 16);
-    }
-  else
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-    }
-  if (h1 == (signed16)0x8000 && h2 == (signed16)0x8000)
-    {
-      DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-      result = (signed32)0x7fffffff;
-    }
-  else
-    result = ((signed32)h1 * (signed32)h2) << 1;
-  prod += (signed64)result;
-  if (op == 1) // MAQ_SA
-    {
-      if (prod & 0x8000000000000000LL)
-	{
-	  for (i = 62; i >= 31; i--)
-	    {
-	      if (!(prod & ((signed64)1 << i)))
-		{
-		  DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-		  prod = 0xffffffff80000000LL;
-		  break;
-		}
-	    }
-	}
-      else
-	{
-	  for (i = 62; i >= 31; i--)
-	    {
-	      if (prod & ((signed64)1 << i))
-		{
-		  DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac));
-		  prod = 0x7fffffff;
-		  break;
-		}
-	    }
-	}
-    }
-  DSPLO(ac) = EXTEND32 (prod);
-  DSPHI(ac) = EXTEND32 (prod >> 32);
-}
-
-011111,5.RS,5.RT,000,2.AC,10100,110000:SPECIAL3:32::MAQ_S.W.PHL
-"maq_s.w.phl ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_maq (SD_, AC, RS, RT, 0, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,10110,110000:SPECIAL3:32::MAQ_S.W.PHR
-"maq_s.w.phr ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_maq (SD_, AC, RS, RT, 0, 1);
-}
-
-011111,5.RS,5.RT,000,2.AC,10000,110000:SPECIAL3:32::MAQ_SA.W.PHL
-"maq_sa.w.phl ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_maq (SD_, AC, RS, RT, 1, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,10010,110000:SPECIAL3:32::MAQ_SA.W.PHR
-"maq_sa.w.phr ac<AC>, r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_maq (SD_, AC, RS, RT, 1, 1);
-}
-
-011111,00000,5.RT,5.RD,11011,010010:SPECIAL3:32::BITREV
-"bitrev r<RD>, r<RT>"
-*dsp:
-{
-  int i;
-  unsigned32 v1 = GPR[RT];
-  unsigned32 h1 = 0;
-  for (i = 0; i < 16; i++)
-    {
-      if (v1 & (1 << i))
-	h1 |= (1 << (15 - i));
-    }
-  GPR[RD] = EXTEND32 (h1);
-}
-
-011111,5.RS,5.RT,00000,00000,001100:SPECIAL3:32::INSV
-"insv r<RT>, r<RS>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
-  unsigned32 size = (DSPCR >> DSPCR_SCOUNT_SHIFT) & DSPCR_SCOUNT_MASK;
-  unsigned32 mask1, mask2, mask3, result;
-  if (size < 32)
-    mask1 = (1 << size) - 1;
-  else
-    mask1 = 0xffffffff;
-  mask2 = (1 << pos) - 1;
-  if (pos + size < 32)
-    mask3 = ~((1 << (pos + size)) - 1);
-  else
-    mask3 = 0;
-  result = (v2 & mask3) | ((v1 & mask1) << pos) | (v2 & mask2);
-  GPR[RT] = EXTEND32 (result);
-}
-
-011111,00,8.IMM8,5.RD,00010,010010:SPECIAL3:32::REPL.QB
-"repl.qb r<RD>, <IMM8>"
-*dsp:
-{
-  GPR[RD] = EXTEND32 ((IMM8 << 24) | (IMM8 << 16) | (IMM8 << 8) | IMM8);
-}
-
-011111,00000,5.RT,5.RD,00011,010010:SPECIAL3:32::REPLV.QB
-"replv.qb r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  v1 = v1 & 0xff;
-  GPR[RD] = EXTEND32 ((v1 << 24) | (v1 << 16) | (v1 << 8) | v1);
-}
-
-011111,10.IMM10,5.RD,01010,010010:SPECIAL3:32::REPL.PH
-"repl.ph r<RD>, <IMM10>"
-*dsp:
-{
-  signed32 v1 = IMM10;
-  if (v1 & 0x200)
-    v1 |= 0xfffffc00;
-  GPR[RD] = EXTEND32 ((v1 << 16) | (v1 & 0xffff));
-}
-
-011111,00000,5.RT,5.RD,01011,010010:SPECIAL3:32::REPLV.PH
-"replv.ph r<RD>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RT];
-  v1 = v1 & 0xffff;
-  GPR[RD] = EXTEND32 ((v1 << 16) | v1);
-}
-
-// op: 0 = EQ, 1 = LT, 2 = LE
-:function:::void:do_qb_cmpu:int rs, int rt, int op
-{
-  int i, j;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned8 h1, h2;
-  unsigned32 mask;
-  for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
-    {
-      h1 = (unsigned8)(v1 & 0xff);
-      h2 = (unsigned8)(v2 & 0xff);
-      mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
-      DSPCR &= mask;
-      if (op == 0) // EQ
-	DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
-      else if (op == 1) // LT
-	DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
-      else // LE
-	DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
-    }
-}
-
-011111,5.RS,5.RT,00000,00000,010001:SPECIAL3:32::CMPU.EQ.QB
-"cmpu.eq.qb r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpu (SD_, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,00000,00001,010001:SPECIAL3:32::CMPU.LT.QB
-"cmpu.lt.qb r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpu (SD_, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,00000,00010,010001:SPECIAL3:32::CMPU.LE.QB
-"cmpu.le.qb r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpu (SD_, RS, RT, 2);
-}
-
-// op: 0 = EQ, 1 = LT, 2 = LE
-:function:::void:do_qb_cmpgu:int rd, int rs, int rt, int op
-{
-  int i, j;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  unsigned8 h1, h2;
-  unsigned32 result = 0;
-  for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
-    {
-      h1 = (unsigned8)(v1 & 0xff);
-      h2 = (unsigned8)(v2 & 0xff);
-      if (op == 0) // EQ
-	result |= ((h1 == h2) << j);
-      else if (op == 1) // LT
-	result |= ((h1 < h2) << j);
-      else // LE
-	result |= ((h1 <= h2) << j);
-    }
-  GPR[rd] = EXTEND32 (result);
-}
-
-011111,5.RS,5.RT,5.RD,00100,010001:SPECIAL3:32::CMPGU.EQ.QB
-"cmpgu.eq.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpgu (SD_, RD, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,5.RD,00101,010001:SPECIAL3:32::CMPGU.LT.QB
-"cmpgu.lt.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpgu (SD_, RD, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,5.RD,00110,010001:SPECIAL3:32::CMPGU.LE.QB
-"cmpgu.le.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  do_qb_cmpgu (SD_, RD, RS, RT, 2);
-}
-
-// op: 0 = EQ, 1 = LT, 2 = LE
-:function:::void:do_ph_cmpu:int rs, int rt, int op
-{
-  int i, j;
-  unsigned32 v1 = GPR[rs];
-  unsigned32 v2 = GPR[rt];
-  signed16 h1, h2;
-  unsigned32 mask;
-  for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (signed16)(v1 & 0xffff);
-      h2 = (signed16)(v2 & 0xffff);
-      mask = ~(1 << (DSPCR_CCOND_SHIFT + j));
-      DSPCR &= mask;
-      if (op == 0) // EQ
-	DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j));
-      else if (op == 1) // LT
-	DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j));
-      else // LE
-	DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j));
-    }
-}
-
-011111,5.RS,5.RT,00000,01000,010001:SPECIAL3:32::CMP.EQ.PH
-"cmp.eq.ph r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_cmpu (SD_, RS, RT, 0);
-}
-
-011111,5.RS,5.RT,00000,01001,010001:SPECIAL3:32::CMP.LT.PH
-"cmp.lt.ph r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_cmpu (SD_, RS, RT, 1);
-}
-
-011111,5.RS,5.RT,00000,01010,010001:SPECIAL3:32::CMP.LE.PH
-"cmp.le.ph r<RS>, r<RT>"
-*dsp:
-{
-  do_ph_cmpu (SD_, RS, RT, 2);
-}
-
-011111,5.RS,5.RT,5.RD,00011,010001:SPECIAL3:32::PICK.QB
-"pick.qb r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  int i, j;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned8 h1, h2;
-  unsigned32 result = 0;
-  for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8)
-    {
-      h1 = (unsigned8)(v1 & 0xff);
-      h2 = (unsigned8)(v2 & 0xff);
-      if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
-	result |= (unsigned32)(h1 << i);
-      else
-	result |= (unsigned32)(h2 << i);
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,5.RS,5.RT,5.RD,01011,010001:SPECIAL3:32::PICK.PH
-"pick.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  int i, j;
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  unsigned16 h1, h2;
-  unsigned32 result = 0;
-  for (i = 0, j = 0; i < 32; i += 16, j++, v1 >>= 16, v2 >>= 16)
-    {
-      h1 = (unsigned16)(v1 & 0xffff);
-      h2 = (unsigned16)(v2 & 0xffff);
-      if (DSPCR & (1 << (DSPCR_CCOND_SHIFT + j)))
-	result |= (unsigned32)(h1 << i);
-      else
-	result |= (unsigned32)(h2 << i);
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,5.RS,5.RT,5.RD,01110,010001:SPECIAL3:32::PACKRL.PH
-"packrl.ph r<RD>, r<RS>, r<RT>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  unsigned32 v2 = GPR[RT];
-  GPR[RD] = EXTEND32 ((v1 << 16) + (v2 >> 16));
-}
-
-// op: 0 = EXTR, 1 = EXTR_R, 2 = EXTR_RS
-:function:::void:do_w_extr:int rt, int ac, int shift, int op
-{
-  int i;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
-  signed64 result = (signed64)prod;
-  int setcond = 0;
-  if (!(prod & 0x8000000000000000LL))
-    {
-      for (i = 62; i >= (shift + 31); i--)
-	{
-	  if (prod & ((unsigned64)1 << i))
-	    {
-	      DSPCR |= DSPCR_OUFLAG7;
-	      setcond = 1;
-	      break;
-	    }
-	}
-      if (((prod >> (shift - 1)) & 0xffffffffLL) == 0xffffffffLL)
-	{
-	  DSPCR |= DSPCR_OUFLAG7;
-	  setcond = 1;
-	}
-    }
-  else
-    {
-      for (i = 62; i >= (shift + 31); i--)
-	{
-	  if (!(prod & ((unsigned64)1 << i)))
-	    {
-	      DSPCR |= DSPCR_OUFLAG7;
-	      setcond = 2;
-	      break;
-	    }
-	}
-    }
-  if (op == 0) // EXTR
-    result = result >> shift;
-  else if (op == 1) // EXTR_R
-    {
-      if (shift != 0)
-        result = ((result >> (shift - 1)) + 1) >> 1;
-      else
-	result = result >> shift;
-    }
-  else // EXTR_RS
-    {
-      if (setcond == 1)
-	result = 0x7fffffff;
-      else if (setcond == 2)
-	result = 0x80000000;
-      else 
-	{
-	  if (shift != 0)
-	    result = ((result >> (shift - 1)) + 1) >> 1;
-	  else
-	    result = result >> shift;
-	}
-    }
-  GPR[rt] = EXTEND32 (result);
-}
-
-011111,5.SHIFT,5.RT,000,2.AC,00000,111000:SPECIAL3:32::EXTR.W
-"extr.w r<RT>, ac<AC>, <SHIFT>"
-*dsp:
-{
-  do_w_extr (SD_, RT, AC, SHIFT, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,00001,111000:SPECIAL3:32::EXTRV.W
-"extrv.w r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_w_extr (SD_, RT, AC, shift, 0);
-}
-
-011111,5.SHIFT,5.RT,000,2.AC,00100,111000:SPECIAL3:32::EXTR_R.W
-"extr_r.w r<RT>, ac<AC>, <SHIFT>"
-*dsp:
-{
-  do_w_extr (SD_, RT, AC, SHIFT, 1);
-}
-
-011111,5.RS,5.RT,000,2.AC,00101,111000:SPECIAL3:32::EXTRV_R.W
-"extrv_r.w r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_w_extr (SD_, RT, AC, shift, 1);
-}
-
-011111,5.SHIFT,5.RT,000,2.AC,00110,111000:SPECIAL3:32::EXTR_RS.W
-"extr_rs.w r<RT>, ac<AC>, <SHIFT>"
-*dsp:
-{
-  do_w_extr (SD_, RT, AC, SHIFT, 2);
-}
-
-011111,5.RS,5.RT,000,2.AC,00111,111000:SPECIAL3:32::EXTRV_RS.W
-"extrv_rs.w r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_w_extr (SD_, RT, AC, shift, 2);
-}
-
-:function:::void:do_h_extr:int rt, int ac, int shift
-{
-  int i;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
-  signed64 result = (signed64)prod;
-  signed64 value = 0xffffffffffff8000LL;
-  result >>= shift;
-  if (result > 0x7fff)
-    {
-      result = 0x7fff;
-      DSPCR |= DSPCR_OUFLAG7;
-    }
-  else if (result < value)
-    {
-      result = value;
-      DSPCR |= DSPCR_OUFLAG7;
-    }
-  GPR[rt] = EXTEND32 (result);
-}
-
-011111,5.SHIFT,5.RT,000,2.AC,01110,111000:SPECIAL3:32::EXTR_S.H
-"extr_s.h r<RT>, ac<AC>, <SHIFT>"
-*dsp:
-{
-  do_h_extr (SD_, RT, AC, SHIFT);
-}
-
-011111,5.RS,5.RT,000,2.AC,01111,111000:SPECIAL3:32::EXTRV_S.H
-"extrv_s.h r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 shift = GPR[RS] & 0x1f;
-  do_h_extr (SD_, RT, AC, shift);
-}
-
-// op: 0 = EXTP, 1 = EXTPDP
-:function:::void:do_extp:int rt, int ac, int size, int op
-{
-  signed32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
-  unsigned64 result = 0;
-  if (pos - (size + 1) >= -1)
-    {
-      prod >>= (pos - size);
-      result = prod & (((unsigned64)1 << (size + 1)) - 1);
-      DSPCR &= (~DSPCR_EFI_SMASK);
-      if (op == 1) // EXTPDP
-	{
-	  if (pos - (size + 1) >= 0)
-	    {
-	      DSPCR &= (~DSPCR_POS_SMASK);
-	      DSPCR |= ((pos - (size + 1)) & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
-	    }
-	  else if (pos - (size + 1) == -1)
-	    {
-	      DSPCR |= DSPCR_POS_SMASK;
-	    }
-	}
-    }
-  else
-    {
-      DSPCR |= DSPCR_EFI;
-      Unpredictable ();
-    }
-  GPR[rt] = EXTEND32 (result);
-}
-
-011111,5.SIZE,5.RT,000,2.AC,00010,111000:SPECIAL3:32::EXTP
-"extp r<RT>, ac<AC>, <SIZE>"
-*dsp:
-{
-  do_extp (SD_, RT, AC, SIZE, 0);
-}
-
-011111,5.RS,5.RT,000,2.AC,00011,111000:SPECIAL3:32::EXTPV
-"extpv r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 size = GPR[RS] & 0x1f;
-  do_extp (SD_, RT, AC, size, 0);
-}
-
-011111,5.SIZE,5.RT,000,2.AC,01010,111000:SPECIAL3:32::EXTPDP
-"extpdp r<RT>, ac<AC>, <SIZE>"
-*dsp:
-{
-  do_extp (SD_, RT, AC, SIZE, 1);
-}
-
-011111,5.RS,5.RT,000,2.AC,01011,111000:SPECIAL3:32::EXTPDPV
-"extpdpv r<RT>, ac<AC>, r<RS>"
-*dsp:
-{
-  unsigned32 size = GPR[RS] & 0x1f;
-  do_extp (SD_, RT, AC, size, 1);
-}
-
-:function:::void:do_shilo:int ac, int shift
-{
-  unsigned32 lo = DSPLO(ac);
-  unsigned32 hi = DSPHI(ac);
-  unsigned64 prod = (((unsigned64)hi) << 32) + (unsigned64)lo;
-  if (shift > 31)
-    shift = shift - 64;
-  if (shift >= 0)
-    prod >>= shift;
-  else
-    prod <<= (-shift);
-  DSPLO(ac) = EXTEND32 (prod);
-  DSPHI(ac) = EXTEND32 (prod >> 32);
-}
-
-011111,6.SHIFT6,0000,000,2.AC,11010,111000:SPECIAL3:32::SHILO
-"shilo ac<AC>, <SHIFT6>"
-*dsp:
-{
-  do_shilo (SD_, AC, SHIFT6);
-}
-
-011111,5.RS,00000,000,2.AC,11011,111000:SPECIAL3:32::SHILOV
-"shilov ac<AC>, r<RS>"
-*dsp:
-{
-  signed32 shift = GPR[RS] & 0x3f;
-  do_shilo (SD_, AC, shift);
-}
-
-011111,5.RS,00000,000,2.AC,11111,111000:SPECIAL3:32::MTHLIP
-"mthlip r<RS>, ac<AC>"
-*dsp:
-{
-  unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
-  DSPHI(AC) = DSPLO(AC);
-  DSPLO(AC) = GPR[RS];
-  if (pos >= 32)
-    Unpredictable ();
-  else
-    pos += 32;
-  DSPCR &= (~DSPCR_POS_SMASK);
-  DSPCR |= (pos & DSPCR_POS_MASK) << DSPCR_POS_SHIFT;
-}
-
-000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHIdsp
-"mfhi r<RD>":AC == 0
-"mfhi r<RD>, ac<AC>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*dsp:
-{
-  if (AC == 0)
-    do_mfhi (SD_, RD);
-  else
-    GPR[RD] = DSPHI(AC);
-}
-
-000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLOdsp
-"mflo r<RD>":AC == 0
-"mflo r<RD>, ac<AC>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*dsp:
-{
-  if (AC == 0)
-    do_mflo (SD_, RD);
-  else
-    GPR[RD] = DSPLO(AC);
-}
-
-000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHIdsp
-"mthi r<RS>":AC == 0
-"mthi r<RS>, ac<AC>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*dsp:
-{
-  if (AC == 0)
-    check_mt_hilo (SD_, HIHISTORY);
-  DSPHI(AC) = GPR[RS];
-}
-
-000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLOdsp
-"mtlo r<RS>":AC == 0
-"mtlo r<RS>, ac<AC>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*dsp:
-{
-  if (AC == 0)
-    check_mt_hilo (SD_, LOHISTORY);
-  DSPLO(AC) = GPR[RS];
-}
-
-011111,5.RS,10.MASK10,10011,111000:SPECIAL3:32::WRDSP
-"wrdsp r<RS>":MASK10 == 1111111111
-"wrdsp r<RS>, <MASK10>"
-*dsp:
-{
-  unsigned32 v1 = GPR[RS];
-  if (MASK10 & 0x1)
-    {
-      DSPCR &= (~DSPCR_POS_SMASK);
-      DSPCR |= (v1 & DSPCR_POS_SMASK);
-    }
-  if (MASK10 & 0x2)
-    {
-      DSPCR &= (~DSPCR_SCOUNT_SMASK);
-      DSPCR |= (v1 & DSPCR_SCOUNT_SMASK);
-    }
-  if (MASK10 & 0x4)
-    {
-      DSPCR &= (~DSPCR_CARRY_SMASK);
-      DSPCR |= (v1 & DSPCR_CARRY_SMASK);
-    }
-  if (MASK10 & 0x8)
-    {
-      DSPCR &= (~DSPCR_OUFLAG_SMASK);
-      DSPCR |= (v1 & DSPCR_OUFLAG_SMASK);
-    }
-  if (MASK10 & 0x10)
-    {
-      DSPCR &= (~DSPCR_CCOND_SMASK);
-      DSPCR |= (v1 & DSPCR_CCOND_SMASK);
-    }
-  if (MASK10 & 0x20)
-    {
-      DSPCR &= (~DSPCR_EFI_SMASK);
-      DSPCR |= (v1 & DSPCR_EFI_SMASK);
-    }
-}
-
-011111,10.MASK10,5.RD,10010,111000:SPECIAL3:32::RDDSP
-"rddsp r<RD>":MASK10 == 1111111111
-"rddsp r<RD>, <MASK10>"
-*dsp:
-{
-  unsigned32 result = 0;
-  if (MASK10 & 0x1)
-    {
-      result &= (~DSPCR_POS_SMASK);
-      result |= (DSPCR & DSPCR_POS_SMASK);
-    }
-  if (MASK10 & 0x2)
-    {
-      result &= (~DSPCR_SCOUNT_SMASK);
-      result |= (DSPCR & DSPCR_SCOUNT_SMASK);
-    }
-  if (MASK10 & 0x4)
-    {
-      result &= (~DSPCR_CARRY_SMASK);
-      result |= (DSPCR & DSPCR_CARRY_SMASK);
-    }
-  if (MASK10 & 0x8)
-    {
-      result &= (~DSPCR_OUFLAG_SMASK);
-      result |= (DSPCR & DSPCR_OUFLAG_SMASK);
-    }
-  if (MASK10 & 0x10)
-    {
-      result &= (~DSPCR_CCOND_SMASK);
-      result |= (DSPCR & DSPCR_CCOND_SMASK);
-    }
-  if (MASK10 & 0x20)
-    {
-      result &= (~DSPCR_EFI_SMASK);
-      result |= (DSPCR & DSPCR_EFI_SMASK);
-    }
-  GPR[RD] = EXTEND32 (result);
-}
-
-011111,5.BASE,5.INDEX,5.RD,00110,001010:SPECIAL3:32::LBUX
-"lbux r<RD>, r<INDEX>(r<BASE>)"
-*dsp:
-{
-  GPR[RD] = do_load (SD_, AccessLength_BYTE, GPR[BASE], GPR[INDEX]);
-}
-
-011111,5.BASE,5.INDEX,5.RD,00100,001010:SPECIAL3:32::LHX
-"lhx r<RD>, r<INDEX>(r<BASE>)"
-*dsp:
-{
-  GPR[RD] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], GPR[INDEX]));
-}
-
-011111,5.BASE,5.INDEX,5.RD,00000,001010:SPECIAL3:32::LWX
-"lwx r<RD>, r<INDEX>(r<BASE>)"
-*dsp:
-{
-  GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
-}
-
-000001,00000,11100,16.OFFSET:REGIMM:32::BPOSGE32
-"bposge32 <OFFSET>"
-*dsp:
-{
-  unsigned32 pos = (DSPCR >> DSPCR_POS_SHIFT) & DSPCR_POS_MASK;
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if (pos >= 32)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
diff --git a/sim/mips/dv-tx3904cpu.c b/sim/mips/dv-tx3904cpu.c
deleted file mode 100644
index 07b8521..0000000
--- a/sim/mips/dv-tx3904cpu.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*  This file is part of the program GDB, the GNU debugger.
-    
-    Copyright (C) 1998 Free Software Foundation, Inc.
-    Contributed by Cygnus Solutions.
-    
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-    
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-    
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-    
-    */
-
-
-#include "sim-main.h"
-#include "hw-main.h"
-
-/* DEVICE
-
-   
-   tx3904cpu - tx3904 cpu virtual device
-
-   
-   DESCRIPTION
-
-   
-   Implements the external tx3904 functionality.  This includes the
-   delivery of of interrupts generated from other devices and the
-   handling of device specific registers.
-
-
-   PROPERTIES
-   
-   none
-
-
-   PORTS
-
-
-   reset (input)
-
-   Currently ignored.
-
-
-   nmi (input)
-
-   Deliver a non-maskable interrupt to the processor.
-
-
-   level (input)
-
-   Deliver a maskable interrupt of given level, corresponding to
-   IP[5:0], to processor.
-
-
-
-   BUGS
-
-
-   When delivering an interrupt, this code assumes that there is only
-   one processor (number 0).
-
-   This code does not attempt to be efficient at handling pending
-   interrupts.  It simply schedules the interrupt delivery handler
-   every instruction cycle until all pending interrupts go away.  An
-   alternative implementation might modify instructions that change
-   the PSW and have them check to see if the change makes an interrupt
-   delivery possible.
-
-   */
-
-
-
-struct tx3904cpu {
-  /* Pending interrupts for delivery by event handler */
-  int pending_reset, pending_nmi, pending_level;
-  struct hw_event* event;
-};
-
-
-
-/* input port ID's */ 
-
-enum {
-  RESET_PORT,
-  NMI_PORT,
-  LEVEL_PORT,
-};
-
-
-static const struct hw_port_descriptor tx3904cpu_ports[] = {
-
-  /* interrupt inputs */
-  { "reset", RESET_PORT, 0, input_port, },
-  { "nmi", NMI_PORT, 0, input_port, },
-  { "level", LEVEL_PORT, 0, input_port, },
-
-  { NULL, },
-};
-
-
-/* Finish off the partially created hw device.  Attach our local
-   callbacks.  Wire up our port names etc */
-
-static hw_port_event_method tx3904cpu_port_event;
-
-
-
-static void
-tx3904cpu_finish (struct hw *me)
-{
-  struct tx3904cpu *controller;
-
-  controller = HW_ZALLOC (me, struct tx3904cpu);
-  set_hw_data (me, controller);
-  set_hw_ports (me, tx3904cpu_ports);
-  set_hw_port_event (me, tx3904cpu_port_event);
-
-  /* Initialize the pending interrupt flags */
-  controller->pending_level = 0;
-  controller->pending_reset = 0;
-  controller->pending_nmi = 0;
-  controller->event = NULL;
-}
-
-
-
-/* An event arrives on an interrupt port */
-
-static void
-deliver_tx3904cpu_interrupt (struct hw *me,
-			    void *data)
-{
-  struct tx3904cpu *controller = hw_data (me);
-  SIM_DESC sd = hw_system (me);
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */
-  address_word cia = CIA_GET (cpu);
-
-#define CPU cpu
-#define SD current_state
-
-  if (controller->pending_reset)
-    {
-      controller->pending_reset = 0;
-      HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu)));
-      SignalExceptionNMIReset();
-    }
-  else if (controller->pending_nmi)
-    {
-      controller->pending_nmi = 0;
-      HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu)));
-      SignalExceptionNMIReset();
-    }
-  else if (controller->pending_level)
-    {
-      HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx",
-		 controller->pending_level,
-		 (long) CIA_GET (cpu), (long) SR));
-
-      /* Clear CAUSE register.  It may stay this way if the interrupt
-	 was cleared with a negative pending_level. */
-      CAUSE &= ~ (cause_IP_mask << cause_IP_shift);
-
-      if(controller->pending_level > 0) /* interrupt set */
-	{
-	  /* set hardware-interrupt subfields of CAUSE register */
-	  CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift;
-
-	  /* check for enabled / unmasked interrupts */
-	  if((SR & status_IEc) &&
-	     (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask)))
-	    {
-	      controller->pending_level = 0;
-	      SignalExceptionInterrupt(0 /* dummy value */);
-	    }
-	  else
-	    {
-	      /* reschedule soon */
-	      if(controller->event != NULL)
-		hw_event_queue_deschedule(me, controller->event);
-	      controller->event =
-		hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL);
-	    }
-	} /* interrupt set */
-    }
-#undef CPU cpu
-#undef SD current_state
-}
-
-
-static void
-tx3904cpu_port_event (struct hw *me,
-		     int my_port,
-		     struct hw *source,
-		     int source_port,
-		     int level)
-{
-  struct tx3904cpu *controller = hw_data (me);
-
-  switch (my_port)
-    {      
-    case RESET_PORT:
-      controller->pending_reset = 1;
-      HW_TRACE ((me, "port-in reset"));
-      break;
-      
-    case NMI_PORT:
-      controller->pending_nmi = 1;
-      HW_TRACE ((me, "port-in nmi"));
-      break;
-      
-    case LEVEL_PORT:
-      /* level == 0 means that the interrupt was cleared */
-      if(level == 0)
-	controller->pending_level = -1; /* signal end of interrupt */
-      else
-	controller->pending_level = level;
-      HW_TRACE ((me, "port-in level=%d", level));
-      break;
-      
-    default:
-      hw_abort (me, "bad switch");
-      break;
-    }
-
-  /* Schedule an event to be delivered immediately after current
-     instruction. */
-  if(controller->event != NULL)
-    hw_event_queue_deschedule(me, controller->event);
-  controller->event =
-    hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL);
-}
-
-
-const struct hw_descriptor dv_tx3904cpu_descriptor[] = {
-  { "tx3904cpu", tx3904cpu_finish, },
-  { NULL },
-};
diff --git a/sim/mips/dv-tx3904irc.c b/sim/mips/dv-tx3904irc.c
deleted file mode 100644
index 8b84e5c..0000000
--- a/sim/mips/dv-tx3904irc.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*  This file is part of the program GDB, the GNU debugger.
-    
-    Copyright (C) 1998 Free Software Foundation, Inc.
-    Contributed by Cygnus Solutions.
-    
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-    
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-    
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-    
-    */
-
-
-#include "sim-main.h"
-#include "hw-main.h"
-
-
-/* DEVICE
-
-   
-   tx3904irc - tx3904 interrupt controller
-
-   
-   DESCRIPTION
-
-   
-   Implements the tx3904 interrupt controller described in the tx3904
-   user guide.  It does not include the interrupt detection circuit
-   that preprocesses the eight external interrupts, so assumes that
-   each event on an input interrupt port signals a new interrupt.
-   That is, it implements edge- rather than level-triggered
-   interrupts.
-
-   This implementation does not support multiple concurrent
-   interrupts.
-
-
-   PROPERTIES
-
-
-   reg <base> <length>
-
-   Base of IRC control register bank.  <length> must equal 0x20.
-   Registers offsets:       0: ISR: interrupt status register
-                            4: IMR: interrupt mask register
-                           16: ILR0: interrupt level register 3..0
-                           20: ILR1: interrupt level register 7..4
-                           24: ILR2: interrupt level register 11..8
-                           28: ILR3: interrupt level register 15..12
-
-
-
-   PORTS
-
-
-   ip (output)
-
-   Interrupt priority port.  An event is generated when an interrupt
-   of a sufficient priority is passed through the IRC.  The value
-   associated with the event is the interrupt level (16-31), as given
-   for bits IP[5:0] in the book TMPR3904F Rev. 2.0, pg. 11-3.  Note
-   that even though INT[0] is tied externally to IP[5], we simulate
-   it as passing through the controller.
-
-   An output level of zero signals the clearing of a level interrupt.
-
-
-   int0-7 (input)
-
-   External interrupts.  Level = 0 -> level interrupt cleared.
-
-   
-   dmac0-3 (input)
-
-   DMA internal interrupts, correspond to DMA channels 0-3.  Level = 0 -> level interrupt cleared.
-
-
-   sio0-1 (input)
-
-   SIO internal interrupts.  Level = 0 -> level interrupt cleared.
-
-
-   tmr0-2 (input)
-
-   Timer internal interrupts.  Level = 0 -> level interrupt cleared.
-
-   */
-
-
-
-
-
-/* register numbers; each is one word long */
-enum
-{
-  ISR_REG = 0,
-  IMR_REG = 1,
-  ILR0_REG = 4,
-  ILR1_REG = 5,
-  ILR2_REG = 6,
-  ILR3_REG = 7,
-};
-
-
-/* port ID's */
-
-enum
-{
-  /* inputs, ordered to correspond to interrupt sources 0..15 */
-  INT1_PORT = 0, INT2_PORT, INT3_PORT, INT4_PORT, INT5_PORT, INT6_PORT, INT7_PORT,
-  DMAC3_PORT, DMAC2_PORT, DMAC1_PORT, DMAC0_PORT, SIO0_PORT, SIO1_PORT,
-  TMR0_PORT, TMR1_PORT, TMR2_PORT,
-
-  /* special INT[0] port */
-  INT0_PORT,
-
-  /* reset */
-  RESET_PORT,
-
-  /* output */
-  IP_PORT
-};
-
-
-static const struct hw_port_descriptor tx3904irc_ports[] = {
-
-  /* interrupt output */
-
-  { "ip", IP_PORT, 0, output_port, },
-
-  /* interrupt inputs (as names) */
-  /* in increasing order of level number */
-
-  { "int1", INT1_PORT, 0, input_port, },
-  { "int2", INT2_PORT, 0, input_port, },
-  { "int3", INT3_PORT, 0, input_port, },
-  { "int4", INT4_PORT, 0, input_port, },
-  { "int5", INT5_PORT, 0, input_port, },
-  { "int6", INT6_PORT, 0, input_port, },
-  { "int7", INT7_PORT, 0, input_port, },
-
-  { "dmac3", DMAC3_PORT, 0, input_port, },
-  { "dmac2", DMAC2_PORT, 0, input_port, },
-  { "dmac1", DMAC1_PORT, 0, input_port, },
-  { "dmac0", DMAC0_PORT, 0, input_port, },
-
-  { "sio0", SIO0_PORT, 0, input_port, },
-  { "sio1", SIO1_PORT, 0, input_port, },
-
-  { "tmr0", TMR0_PORT, 0, input_port, },
-  { "tmr1", TMR1_PORT, 0, input_port, },
-  { "tmr2", TMR2_PORT, 0, input_port, },
-
-  { "reset", RESET_PORT, 0, input_port, },
-  { "int0", INT0_PORT, 0, input_port, },
-
-  { NULL, },
-};
-
-
-#define NR_SOURCES (TMR3_PORT - INT1_PORT + 1) /* 16: number of interrupt sources */
-
-
-/* The interrupt controller register internal state.  Note that we
-   store state using the control register images, in host endian
-   order. */
-
-struct tx3904irc {
-  address_word base_address; /* control register base */
-  unsigned_4 isr;
-#define ISR_SET(c,s) ((c)->isr &= ~ (1 << (s)))
-  unsigned_4 imr;
-#define IMR_GET(c) ((c)->imr)
-  unsigned_4 ilr[4];
-#define ILR_GET(c,s) LSEXTRACTED32((c)->ilr[(s)/4], (s) % 4 * 8 + 2, (s) % 4 * 8)
-};
-
-
-
-/* Finish off the partially created hw device.  Attach our local
-   callbacks.  Wire up our port names etc */
-
-static hw_io_read_buffer_method tx3904irc_io_read_buffer;
-static hw_io_write_buffer_method tx3904irc_io_write_buffer;
-static hw_port_event_method tx3904irc_port_event;
-
-static void
-attach_tx3904irc_regs (struct hw *me,
-		      struct tx3904irc *controller)
-{
-  unsigned_word attach_address;
-  int attach_space;
-  unsigned attach_size;
-  reg_property_spec reg;
-
-  if (hw_find_property (me, "reg") == NULL)
-    hw_abort (me, "Missing \"reg\" property");
-
-  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
-    hw_abort (me, "\"reg\" property must contain one addr/size entry");
-
-  hw_unit_address_to_attach_address (hw_parent (me),
-				     &reg.address,
-				     &attach_space,
-				     &attach_address,
-				     me);
-  hw_unit_size_to_attach_size (hw_parent (me),
-			       &reg.size,
-			       &attach_size, me);
-
-  hw_attach_address (hw_parent (me), 0,
-		     attach_space, attach_address, attach_size,
-		     me);
-
-  controller->base_address = attach_address;
-}
-
-
-static void
-tx3904irc_finish (struct hw *me)
-{
-  struct tx3904irc *controller;
-
-  controller = HW_ZALLOC (me, struct tx3904irc);
-  set_hw_data (me, controller);
-  set_hw_io_read_buffer (me, tx3904irc_io_read_buffer);
-  set_hw_io_write_buffer (me, tx3904irc_io_write_buffer);
-  set_hw_ports (me, tx3904irc_ports);
-  set_hw_port_event (me, tx3904irc_port_event);
-
-  /* Attach ourself to our parent bus */
-  attach_tx3904irc_regs (me, controller);
-
-  /* Initialize to reset state */
-  controller->isr = 0x0000ffff;
-  controller->imr = 0;
-  controller->ilr[0] =
-    controller->ilr[1] =
-    controller->ilr[2] =
-    controller->ilr[3] = 0;
-}
-
-
-
-/* An event arrives on an interrupt port */
-
-static void
-tx3904irc_port_event (struct hw *me,
-		     int my_port,
-		     struct hw *source_dev,
-		     int source_port,
-		     int level)
-{
-  struct tx3904irc *controller = hw_data (me);
-
-  /* handle deactivated interrupt */
-  if(level == 0)
-    {
-      HW_TRACE ((me, "interrupt cleared on port %d", my_port));
-      hw_port_event(me, IP_PORT, 0);
-      return;
-    }
-
-  switch (my_port)
-    {
-    case INT0_PORT: 
-      {
-	int ip_number = 32; /* compute IP[5:0] */
-	HW_TRACE ((me, "port-event INT[0]"));
-	hw_port_event(me, IP_PORT, ip_number);
-	break;
-      }
-
-    case INT1_PORT: case INT2_PORT: case INT3_PORT: case INT4_PORT:
-    case INT5_PORT: case INT6_PORT: case INT7_PORT: case DMAC3_PORT:
-    case DMAC2_PORT: case DMAC1_PORT: case DMAC0_PORT: case SIO0_PORT:
-    case SIO1_PORT: case TMR0_PORT: case TMR1_PORT: case TMR2_PORT:
-      {
-	int source = my_port - INT1_PORT;
-
-	HW_TRACE ((me, "interrupt asserted on port %d", source));
-	ISR_SET(controller, source);
-	if(ILR_GET(controller, source) > IMR_GET(controller))
-	  {
-	    int ip_number = 16 + source; /* compute IP[4:0] */
-	    HW_TRACE ((me, "interrupt level %d", ILR_GET(controller,source)));
-	    hw_port_event(me, IP_PORT, ip_number);
-	  }
-	break;
-      }
-
-    case RESET_PORT:
-      {
-	HW_TRACE ((me, "reset"));
-	controller->isr = 0x0000ffff;
-	controller->imr = 0;
-	controller->ilr[0] =
-	  controller->ilr[1] =
-	  controller->ilr[2] =
-	  controller->ilr[3] = 0;
-	break;
-      }
-
-    case IP_PORT:
-      hw_abort (me, "Event on output port %d", my_port);
-      break;
-
-    default:
-      hw_abort (me, "Event on unknown port %d", my_port);
-      break;
-    }
-}
-
-
-/* generic read/write */
-
-static unsigned
-tx3904irc_io_read_buffer (struct hw *me,
-			 void *dest,
-			 int space,
-			 unsigned_word base,
-			 unsigned nr_bytes)
-{
-  struct tx3904irc *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = (address - controller->base_address) % 4;
-      unsigned_4 register_value; /* in target byte order */
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case ISR_REG: register_value = controller->isr; break;
-	case IMR_REG: register_value = controller->imr; break;
-	case ILR0_REG: register_value = controller->ilr[0]; break;
-	case ILR1_REG: register_value = controller->ilr[1]; break;
-	case ILR2_REG: register_value = controller->ilr[2]; break;
-	case ILR3_REG: register_value = controller->ilr[3]; break;
-	default: register_value = 0;
-	}
-
-      /* write requested byte out */
-      register_value = H2T_4(register_value);
-      memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
-    }
-
-  return nr_bytes;
-}     
-
-
-
-static unsigned
-tx3904irc_io_write_buffer (struct hw *me,
-			  const void *source,
-			  int space,
-			  unsigned_word base,
-			  unsigned nr_bytes)
-{
-  struct tx3904irc *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = (address - controller->base_address) % 4;
-      unsigned_4* register_ptr;
-      unsigned_4 register_value;
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case ISR_REG: register_ptr = & controller->isr; break;
-	case IMR_REG: register_ptr = & controller->imr; break;
-	case ILR0_REG: register_ptr = & controller->ilr[0]; break;
-	case ILR1_REG: register_ptr = & controller->ilr[1]; break;
-	case ILR2_REG: register_ptr = & controller->ilr[2]; break;
-	case ILR3_REG: register_ptr = & controller->ilr[3]; break;
-	default: register_ptr = & register_value; /* used as a dummy */
-	}
-
-      /* HW_TRACE ((me, "reg %d pre: %08lx", reg_number, (long) *register_ptr)); */
-
-      /* overwrite requested byte */
-      register_value = H2T_4(* register_ptr);
-      memcpy (((char*)&register_value)+reg_offset, (const char*)source + byte, 1);
-      * register_ptr = T2H_4(register_value);
-
-      /* HW_TRACE ((me, "post: %08lx", (long) *register_ptr)); */
-    }
-  return nr_bytes;
-}     
-
-
-const struct hw_descriptor dv_tx3904irc_descriptor[] = {
-  { "tx3904irc", tx3904irc_finish, },
-  { NULL },
-};
diff --git a/sim/mips/dv-tx3904sio.c b/sim/mips/dv-tx3904sio.c
deleted file mode 100644
index 5ba8e37..0000000
--- a/sim/mips/dv-tx3904sio.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/*  This file is part of the program GDB, the GNU debugger.
-    
-    Copyright (C) 1998, 1999 Free Software Foundation, Inc.
-    Contributed by Cygnus Solutions.
-    
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-    
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-    
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-    
-    */
-
-
-#include "sim-main.h"
-#include "hw-main.h"
-#include "dv-sockser.h"
-#include "sim-assert.h"
-
-
-/* DEVICE
-
-   
-   tx3904sio - tx3904 serial I/O
-
-   
-   DESCRIPTION
-
-   
-   Implements one tx3904 serial I/O controller described in the tx3904
-   user guide.  Three instances are required for SIO0 and SIO1 within
-   the tx3904, at different base addresses.
-
-   Both internal and system clocks are synthesized as divided versions
-   of the simulator clock.
-   
-   There is no support for:
-    - CTS/RTS flow control
-    - baud rate emulation - use infinite speed instead
-    - general frame format - use 8N1
-    - multi-controller system
-    - DMA - use interrupt-driven or polled-I/O instead
-
-
-   PROPERTIES
-
-
-   reg <base> <length>
-
-   Base of SIO control register bank.  <length> must equal 0x100.
-   Register offsets:       0: SLCR: line control register
-                           4: SLSR: line status register
-                           8: SDICR: DMA/interrupt control register
-                          12: SDISR: DMA/interrupt status register
-                          16: SFCR: FIFO control register
-			  20: SBGR: baud rate control register
-			  32: transfer FIFO buffer
-			  48: transfer FIFO buffer
-
-   backend {tcp | stdio}
-
-   Use dv-sockser TCP-port backend or stdio for backend.  Default: stdio.
-
-
-
-   PORTS
-
-
-   int (output)
-
-   Interrupt port.  An event is generated when a timer interrupt
-   occurs.
-
-
-   reset (input)
-
-   Reset port.
-
-   */
-
-
-
-/* static functions */
-
-struct tx3904sio_fifo;
-
-static void tx3904sio_tickle(struct hw*);
-static int tx3904sio_fifo_nonempty(struct hw*, struct tx3904sio_fifo*);
-static char tx3904sio_fifo_pop(struct hw*, struct tx3904sio_fifo*);
-static void tx3904sio_fifo_push(struct hw*, struct tx3904sio_fifo*, char);
-static void tx3904sio_fifo_reset(struct hw*, struct tx3904sio_fifo*);
-static void tx3904sio_poll(struct hw*, void* data);
-
-
-/* register numbers; each is one word long */
-enum 
-{
-  SLCR_REG = 0,
-  SLSR_REG = 1,
-  SDICR_REG = 2,
-  SDISR_REG = 3,
-  SFCR_REG = 4,
-  SBGR_REG = 5,
-  TFIFO_REG = 8,
-  SFIFO_REG = 12,
-};
-
-
-
-/* port ID's */
-
-enum
- {
-  RESET_PORT,
-  INT_PORT,
-};
-
-
-static const struct hw_port_descriptor tx3904sio_ports[] = 
-{
-  { "int", INT_PORT, 0, output_port, },
-  { "reset", RESET_PORT, 0, input_port, },
-  { NULL, },
-};
-
-
-
-/* Generic FIFO */
-struct tx3904sio_fifo 
-{
-  int size, used;
-  unsigned_1 *buffer;
-};
-
-
-
-/* The timer/counter register internal state.  Note that we store
-   state using the control register images, in host endian order. */
-
-struct tx3904sio 
-{
-  address_word base_address; /* control register base */
-  enum {sio_tcp, sio_stdio} backend; /* backend */
-
-  struct tx3904sio_fifo rx_fifo, tx_fifo; /* FIFOs */
-
-  unsigned_4 slcr;
-#define SLCR_WR_MASK        0xe17f0000U
-#define SLCR_SET_BYTE(c,o,b) ((c)->slcr = SLCR_WR_MASK & (((c)->slcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
-  unsigned_4 slsr;
-#define SLSR_WR_MASK        0x00000000 /* UFER/UPER/UOER unimplemented */
-  unsigned_4 sdicr;
-#define SDICR_WR_MASK       0x000f0000U
-#define SDICR_SET_BYTE(c,o,b) ((c)->sdicr = SDICR_WR_MASK & (((c)->sdicr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
-#define SDICR_GET_SDMAE(c)  ((c)->sdicr & 0x00080000)
-#define SDICR_GET_ERIE(c)   ((c)->sdicr & 0x00040000)
-#define SDICR_GET_TDIE(c)   ((c)->sdicr & 0x00020000)
-#define SDICR_GET_RDIE(c)   ((c)->sdicr & 0x00010000)
-  unsigned_4 sdisr;
-#define SDISR_WR_MASK       0x00070000U
-#define SDISR_SET_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
-#define SDISR_CLEAR_FLAG_BYTE(c,o,b) ((c)->sdisr = SDISR_WR_MASK & (((c)->sdisr & ~LSMASK32((o)*8+7,(o)*8)) & ((b)<< (o)*8)))
-#define SDISR_GET_TDIS(c)   ((c)->sdisr & 0x00020000)
-#define SDISR_SET_TDIS(c)   ((c)->sdisr |= 0x00020000)
-#define SDISR_GET_RDIS(c)   ((c)->sdisr & 0x00010000)
-#define SDISR_SET_RDIS(c)   ((c)->sdisr |= 0x00010000)
-  unsigned_4 sfcr;
-#define SFCR_WR_MASK       0x001f0000U
-#define SFCR_SET_BYTE(c,o,b) ((c)->sfcr = SFCR_WR_MASK & (((c)->sfcr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
-#define SFCR_GET_TFRST(c)   ((c)->sfcr & 0x00040000)
-#define SFCR_GET_RFRST(c)   ((c)->sfcr & 0x00020000)
-#define SFCR_GET_FRSTE(c)   ((c)->sfcr & 0x00010000)
-  unsigned_4 sbgr;
-#define SBGR_WR_MASK       0x03ff0000U
-#define SBGR_SET_BYTE(c,o,b) ((c)->sbgr = SBGR_WR_MASK & (((c)->sbgr & ~LSMASK32((o)*8+7,(o)*8)) | ((b)<< (o)*8)))
-
-  /* Periodic I/O polling */
-  struct hw_event* poll_event;
-};
-
-
-
-/* Finish off the partially created hw device.  Attach our local
-   callbacks.  Wire up our port names etc */
-
-static hw_io_read_buffer_method tx3904sio_io_read_buffer;
-static hw_io_write_buffer_method tx3904sio_io_write_buffer;
-static hw_port_event_method tx3904sio_port_event;
-
-
-static void
-attach_tx3904sio_regs (struct hw *me,
-		      struct tx3904sio *controller)
-{
-  unsigned_word attach_address;
-  int attach_space;
-  unsigned attach_size;
-  reg_property_spec reg;
-
-  if (hw_find_property (me, "reg") == NULL)
-    hw_abort (me, "Missing \"reg\" property");
-
-  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
-    hw_abort (me, "\"reg\" property must contain one addr/size entry");
-
-  hw_unit_address_to_attach_address (hw_parent (me),
-				     &reg.address,
-				     &attach_space,
-				     &attach_address,
-				     me);
-  hw_unit_size_to_attach_size (hw_parent (me),
-			       &reg.size,
-			       &attach_size, me);
-
-  hw_attach_address (hw_parent (me), 0,
-		     attach_space, attach_address, attach_size,
-		     me);
-
-  if(hw_find_property(me, "backend") != NULL)
-    {
-      const char* value = hw_find_string_property(me, "backend");
-      if(! strcmp(value, "tcp"))
-	controller->backend = sio_tcp;
-      else if(! strcmp(value, "stdio"))
-	controller->backend = sio_stdio;
-      else
-	hw_abort(me, "illegal value for backend parameter `%s': use tcp or stdio", value);
-    }
-
-  controller->base_address = attach_address;
-}
-
-
-static void
-tx3904sio_finish (struct hw *me)
-{
-  struct tx3904sio *controller;
-
-  controller = HW_ZALLOC (me, struct tx3904sio);
-  set_hw_data (me, controller);
-  set_hw_io_read_buffer (me, tx3904sio_io_read_buffer);
-  set_hw_io_write_buffer (me, tx3904sio_io_write_buffer);
-  set_hw_ports (me, tx3904sio_ports);
-  set_hw_port_event (me, tx3904sio_port_event);
-
-  /* Preset defaults */
-  controller->backend = sio_stdio;
-
-  /* Attach ourself to our parent bus */
-  attach_tx3904sio_regs (me, controller);
-
-  /* Initialize to reset state */
-  tx3904sio_fifo_reset(me, & controller->rx_fifo);
-  tx3904sio_fifo_reset(me, & controller->tx_fifo);
-  controller->slsr = controller->sdicr
-    = controller->sdisr = controller->sfcr
-    = controller->sbgr = 0;
-  controller->slcr = 0x40000000; /* set TWUB */
-  controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
-  controller->poll_event = NULL;
-}
-
-
-
-/* An event arrives on an interrupt port */
-
-static void
-tx3904sio_port_event (struct hw *me,
-		     int my_port,
-		     struct hw *source,
-		     int source_port,
-		     int level)
-{
-  struct tx3904sio *controller = hw_data (me);
-
-  switch (my_port)
-    {
-    case RESET_PORT:
-      {
-	HW_TRACE ((me, "reset"));
-
-	tx3904sio_fifo_reset(me, & controller->rx_fifo);
-	tx3904sio_fifo_reset(me, & controller->tx_fifo);
-	controller->slsr = controller->sdicr
-	  = controller->sdisr = controller->sfcr
-	  = controller->sbgr = 0;
-	controller->slcr = 0x40000000; /* set TWUB */
-	controller->sbgr = 0x03ff0000; /* set BCLK=3, BRD=FF */
-	/* Don't interfere with I/O poller. */
-	break;
-      }
-
-    default:
-      hw_abort (me, "Event on unknown port %d", my_port);
-      break;
-    }
-}
-
-
-/* generic read/write */
-
-static unsigned
-tx3904sio_io_read_buffer (struct hw *me,
-			 void *dest,
-			 int space,
-			 unsigned_word base,
-			 unsigned nr_bytes)
-{
-  struct tx3904sio *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
-
-  /* tickle fifos */
-  tx3904sio_tickle(me);
-
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = (address - controller->base_address) % 4;
-      unsigned_4 register_value; /* in target byte order */
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case SLCR_REG: register_value = controller->slcr; break;
-	case SLSR_REG: register_value = controller->slsr; break;
-	case SDICR_REG: register_value = controller->sdicr; break;
-	case SDISR_REG: register_value = controller->sdisr; break;
-	case SFCR_REG: register_value = controller->sfcr; break;
-	case SBGR_REG: register_value = controller->sbgr; break;
-	case TFIFO_REG: register_value = 0; break;
-	case SFIFO_REG:
-	  /* consume rx fifo for MS byte */
-	  if(reg_offset == 0 && tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
-	    register_value = (tx3904sio_fifo_pop(me, & controller->rx_fifo) << 24);
-	  else
-	    register_value = 0;
-	  break;
-	default: register_value = 0;
-	}
-
-      /* write requested byte out */
-      register_value = H2T_4(register_value);
-      /* HW_TRACE ((me, "byte %d %02x", reg_offset, ((char*)& register_value)[reg_offset])); */
-      memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
-    }
-
-  return nr_bytes;
-}     
-
-
-
-static unsigned
-tx3904sio_io_write_buffer (struct hw *me,
-			  const void *source,
-			  int space,
-			  unsigned_word base,
-			  unsigned nr_bytes)
-{
-  struct tx3904sio *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      unsigned_1 write_byte = ((const unsigned char*) source)[byte];
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = 3 - (address - controller->base_address) % 4;
-
-      /* HW_TRACE ((me, "byte %d %02x", reg_offset, write_byte)); */
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case SLCR_REG:
-	  SLCR_SET_BYTE(controller, reg_offset, write_byte);
-	  break;
-
-	case SLSR_REG: /* unwriteable */ break;
-
-	case SDICR_REG:
-	  {
-	    unsigned_4 last_int, next_int;
-	    
-	    /* deassert interrupt upon clear */
-	    last_int = controller->sdisr & controller->sdicr;
-	    /* HW_TRACE ((me, "sdicr - sdisr %08x sdicr %08x",
-	       controller->sdisr, controller->sdicr)); */
-	    SDICR_SET_BYTE(controller, reg_offset, write_byte);
-	    /* HW_TRACE ((me, "sdicr + sdisr %08x sdicr %08x",
-	       controller->sdisr, controller->sdicr)); */
-	    next_int = controller->sdisr & controller->sdicr;
-	    
-	    if(SDICR_GET_SDMAE(controller))
-	      hw_abort(me, "Cannot support DMA-driven sio.");
-
-	    if(~last_int & next_int) /* any bits set? */
-	      hw_port_event(me, INT_PORT, 1);
-	    if(last_int & ~next_int) /* any bits cleared? */
-	      hw_port_event(me, INT_PORT, 0);
-	  }
-	break;
-
-	case SDISR_REG:
-	  {
-	    unsigned_4 last_int, next_int;
-
-	    /* deassert interrupt upon clear */
-	    last_int = controller->sdisr & controller->sdicr;
-	    /* HW_TRACE ((me, "sdisr - sdisr %08x sdicr %08x", 
-	       controller->sdisr, controller->sdicr)); */
-	    SDISR_CLEAR_FLAG_BYTE(controller, reg_offset, write_byte);
-	    /* HW_TRACE ((me, "sdisr + sdisr %08x sdicr %08x", 
-	       controller->sdisr, controller->sdicr)); */
-	    next_int = controller->sdisr & controller->sdicr;
-
-	    if(~last_int & next_int) /* any bits set? */
-	      hw_port_event(me, INT_PORT, 1);
-	    if(last_int & ~next_int) /* any bits cleared? */
-	      hw_port_event(me, INT_PORT, 0);
-	  }
-	break;
-	
-	case SFCR_REG:
-	  SFCR_SET_BYTE(controller, reg_offset, write_byte);
-	  if(SFCR_GET_FRSTE(controller))
-	    {
-	      if(SFCR_GET_TFRST(controller)) tx3904sio_fifo_reset(me, & controller->tx_fifo);
-	      if(SFCR_GET_RFRST(controller)) tx3904sio_fifo_reset(me, & controller->rx_fifo);
-	    }
-	  break;
-	  
-	case SBGR_REG:
-	  SBGR_SET_BYTE(controller, reg_offset, write_byte);
-	  break;
-	  
-	case SFIFO_REG: /* unwriteable */ break;
-	  
-	case TFIFO_REG: 
-	  if(reg_offset == 3) /* first byte */
-	    tx3904sio_fifo_push(me, & controller->tx_fifo, write_byte);
-	  break;
-
-	default: 
-	  HW_TRACE ((me, "write to illegal register %d", reg_number));
-	}
-    } /* loop over bytes */
-
-  /* tickle fifos */
-  tx3904sio_tickle(me);
-
-  return nr_bytes;
-}     
-
-
-
-
-
-
-/* Send enqueued characters from tx_fifo and trigger TX interrupt.
-Receive characters into rx_fifo and trigger RX interrupt. */
-void
-tx3904sio_tickle(struct hw *me)
-{
-  struct tx3904sio* controller = hw_data(me);
-  int c;
-  char cc;
-  unsigned_4 last_int, next_int;
-
-  /* HW_TRACE ((me, "tickle backend: %02x", controller->backend)); */
-  switch(controller->backend) 
-    {
-    case sio_tcp:
-
-      while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
-	{
-	  cc = tx3904sio_fifo_pop(me, & controller->tx_fifo);
-	  dv_sockser_write(hw_system(me), cc);
-	  HW_TRACE ((me, "tcp output: %02x", cc));
-	}
-
-      c = dv_sockser_read(hw_system(me));
-      while(c != -1)
-	{
-	  cc = (char) c;
-	  HW_TRACE ((me, "tcp input: %02x", cc));
-	  tx3904sio_fifo_push(me, & controller->rx_fifo, cc);
-	  c = dv_sockser_read(hw_system(me));
-	}
-      break;
-
-    case sio_stdio:
-
-      while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
-	{
-	  cc = tx3904sio_fifo_pop(me, & controller->tx_fifo);
-	  sim_io_write_stdout(hw_system(me), & cc, 1);
-	  sim_io_flush_stdout(hw_system(me));
-	  HW_TRACE ((me, "stdio output: %02x", cc));
-	}
-
-      c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1);
-      while(c == 1)
-	{
-	  HW_TRACE ((me, "stdio input: %02x", cc));
-	  tx3904sio_fifo_push(me, & controller->rx_fifo, cc);
-	  c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1);
-	}
-
-      break;
-
-    default:
-      hw_abort(me, "Illegal backend mode: %d", controller->backend);
-    }
-
-  /* Update RDIS / TDIS flags */
-  last_int = controller->sdisr & controller->sdicr;
-  /* HW_TRACE ((me, "tickle - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
-  if(tx3904sio_fifo_nonempty(me, & controller->rx_fifo))
-    SDISR_SET_RDIS(controller);
-  if(! tx3904sio_fifo_nonempty(me, & controller->tx_fifo))
-    SDISR_SET_TDIS(controller);
-  next_int = controller->sdisr & controller->sdicr;
-  /* HW_TRACE ((me, "tickle + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */
-
-  if(~last_int & next_int) /* any bits set? */
-    hw_port_event(me, INT_PORT, 1);
-  if(last_int & ~next_int) /* any bits cleared? */
-    hw_port_event(me, INT_PORT, 0);
-
-  /* Add periodic polling for this port, if it's not already going. */
-  if(controller->poll_event == NULL)
-    {
-      controller->poll_event = hw_event_queue_schedule (me, 1000,
-							tx3904sio_poll, NULL);
-
-    }
-}
-
-
-
-
-int
-tx3904sio_fifo_nonempty(struct hw* me, struct tx3904sio_fifo* fifo)
-{
-  /* HW_TRACE ((me, "fifo used: %d", fifo->used)); */
-  return(fifo->used > 0);
-}
-
-
-char
-tx3904sio_fifo_pop(struct hw* me, struct tx3904sio_fifo* fifo)
-{
-  char it;
-  ASSERT(fifo->used > 0);
-  ASSERT(fifo->buffer != NULL);
-  it = fifo->buffer[0];
-  memcpy(& fifo->buffer[0], & fifo->buffer[1], fifo->used - 1);
-  fifo->used --;
-  /* HW_TRACE ((me, "pop fifo -> %02x", it)); */
-  return it;
-}
-
-
-void
-tx3904sio_fifo_push(struct hw* me, struct tx3904sio_fifo* fifo, char it)
-{
-  /* HW_TRACE ((me, "push %02x -> fifo", it)); */
-  if(fifo->size == fifo->used) /* full */
-    {
-      int next_size = fifo->size * 2 + 16;
-      char* next_buf = zalloc(next_size);
-      memcpy(next_buf, fifo->buffer, fifo->used);
-
-      if(fifo->buffer != NULL) zfree(fifo->buffer);
-      fifo->buffer = next_buf;
-      fifo->size = next_size;
-    }
-
-  fifo->buffer[fifo->used] = it;
-  fifo->used ++;
-}
-
-
-void
-tx3904sio_fifo_reset(struct hw* me, struct tx3904sio_fifo* fifo)
-{
-  /* HW_TRACE ((me, "reset fifo")); */
-  fifo->used = 0;
-  fifo->size = 0;
-  zfree(fifo->buffer);
-  fifo->buffer = 0;
-}
-
-
-void
-tx3904sio_poll(struct hw* me, void* ignored)
-{
-  struct tx3904sio* controller = hw_data (me);
-  tx3904sio_tickle (me);
-  hw_event_queue_deschedule (me, controller->poll_event);
-  controller->poll_event = hw_event_queue_schedule (me, 1000,
-						    tx3904sio_poll, NULL);
-}
-
-
-
-const struct hw_descriptor dv_tx3904sio_descriptor[] = {
-  { "tx3904sio", tx3904sio_finish, },
-  { NULL },
-};
diff --git a/sim/mips/dv-tx3904tmr.c b/sim/mips/dv-tx3904tmr.c
deleted file mode 100644
index 89e0625..0000000
--- a/sim/mips/dv-tx3904tmr.c
+++ /dev/null
@@ -1,699 +0,0 @@
-/*  This file is part of the program GDB, the GNU debugger.
-    
-    Copyright (C) 1998 Free Software Foundation, Inc.
-    Contributed by Cygnus Solutions.
-    
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-    
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-    
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-    
-    */
-
-
-#include "sim-main.h"
-#include "hw-main.h"
-
-
-/* DEVICE
-
-   
-   tx3904tmr - tx3904 timer
-
-   
-   DESCRIPTION
-
-   
-   Implements one tx3904 timer/counter described in the tx3904
-   user guide.  Three instances are required for TMR0, TMR1, and
-   TMR3 within the tx3904, at different base addresses.  
-
-   Both internal and system clocks are synthesized as divided versions
-   of the simulator clock.
-   
-   There is no support for:
-    - edge sensitivity of external clock
-    - different mode restrictions for TMR0..2
-    - level interrupts (interrupts are treated as events that occur at edges)
-
-
-
-   PROPERTIES
-
-
-   reg <base> <length>
-
-   Base of TMR control register bank.  <length> must equal 0x100.
-   Register offsets:       0: TCR: timer control  register
-                           4: TISR: timer interrupt status register
-                           8: CPRA: compare register A
-                          12: CPRB: compare register B
-                          16: ITMR: interval timer mode register
-			  32: CCDR: divider register
-			  48: PMGR: pulse generator mode register
-			  64: WTMR: watchdog timer mode register
-			 240: TRR: timer read register
-
-
-   clock <ticks>
-
-   Rate of timer clock signal.  This number is the number of simulator
-   ticks per clock signal tick.  Default 1.
-
-   
-   ext <ticks>
-
-   Rate of "external input clock signal", the other clock input of the
-   timer.  It uses the same scale as above.  Default 100.
-
-
-
-   PORTS
-
-
-   int (output)
-
-   Interrupt port.  An event is generated when a timer interrupt
-   occurs.
-
-
-   ff (output)
-
-   Flip-flop output, corresponds to the TMFFOUT port.  An event is
-   generated when flip-flop changes value.  The integer associated
-   with the event is 1/0 according to flip-flop value.
-
-
-   reset (input)
-
-   Reset port.
-
-   */
-
-
-
-/* static functions */
-
-static void deliver_tx3904tmr_tick (struct hw *me, void *data);
-
-
-/* register numbers; each is one word long */
-enum 
-{
-  TCR_REG = 0,
-  TISR_REG = 1,
-  CPRA_REG = 2,
-  CPRB_REG = 3,
-  ITMR_REG = 4,
-  CCDR_REG = 8,
-  PMGR_REG = 12,
-  WTMR_REG = 16,
-  TRR_REG = 60
-};
-
-
-
-/* port ID's */
-
-enum
- {
-  RESET_PORT,
-  INT_PORT,
-  FF_PORT
-};
-
-
-static const struct hw_port_descriptor tx3904tmr_ports[] = 
-{
-  { "int", INT_PORT, 0, output_port, },
-  { "ff", FF_PORT, 0, output_port, },
-  { "reset", RESET_PORT, 0, input_port, },
-  { NULL, },
-};
-
-
-
-/* The timer/counter register internal state.  Note that we store
-   state using the control register images, in host endian order. */
-
-struct tx3904tmr {
-  address_word base_address; /* control register base */
-  unsigned_4 clock_ticks, ext_ticks; /* clock frequencies */
-  signed_8 last_ticks; /* time at last deliver_*_tick call */
-  signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */
-  int ff; /* pulse generator flip-flop value: 1/0 */
-  struct hw_event* event; /* last scheduled event */
-
-  unsigned_4 tcr;
-#define GET_TCR_TCE(c)      (((c)->tcr & 0x80) >> 7)
-#define GET_TCR_CCDE(c)     (((c)->tcr & 0x40) >> 6)
-#define GET_TCR_CRE(c)      (((c)->tcr & 0x20) >> 5)
-#define GET_TCR_CCS(c)      (((c)->tcr & 0x04) >> 2)
-#define GET_TCR_TMODE(c)    (((c)->tcr & 0x03) >> 0)
-  unsigned_4 tisr;
-#define SET_TISR_TWIS(c)    ((c)->tisr |= 0x08)
-#define SET_TISR_TPIBS(c)   ((c)->tisr |= 0x04)
-#define SET_TISR_TPIAS(c)   ((c)->tisr |= 0x02)
-#define SET_TISR_TIIS(c)    ((c)->tisr |= 0x01)
-  unsigned_4 cpra;
-  unsigned_4 cprb;
-  unsigned_4 itmr;
-#define GET_ITMR_TIIE(c)    (((c)->itmr & 0x8000) >> 15)
-#define SET_ITMR_TIIE(c,v)  BLIT32((c)->itmr, 15, (v) ? 1 : 0)
-#define GET_ITMR_TZCE(c)    (((c)->itmr & 0x0001) >> 0)
-#define SET_ITMR_TZCE(c,v)  BLIT32((c)->itmr, 0, (v) ? 1 : 0)
-  unsigned_4 ccdr;
-#define GET_CCDR_CDR(c)     (((c)->ccdr & 0x07) >> 0)
-  unsigned_4 pmgr;
-#define GET_PMGR_TPIBE(c)   (((c)->pmgr & 0x8000) >> 15)
-#define SET_PMGR_TPIBE(c,v) BLIT32((c)->pmgr, 15, (v) ? 1 : 0)
-#define GET_PMGR_TPIAE(c)   (((c)->pmgr & 0x4000) >> 14)
-#define SET_PMGR_TPIAE(c,v) BLIT32((c)->pmgr, 14, (v) ? 1 : 0)
-#define GET_PMGR_FFI(c)     (((c)->pmgr & 0x0001) >> 0)
-#define SET_PMGR_FFI(c,v)   BLIT32((c)->pmgr, 0, (v) ? 1 : 0)
-  unsigned_4 wtmr;
-#define GET_WTMR_TWIE(c)    (((c)->wtmr & 0x8000) >> 15)
-#define SET_WTMR_TWIE(c,v)  BLIT32((c)->wtmr, 15, (v) ? 1 : 0)
-#define GET_WTMR_WDIS(c)    (((c)->wtmr & 0x0080) >> 7)
-#define SET_WTMR_WDIS(c,v)  BLIT32((c)->wtmr, 7, (v) ? 1 : 0)
-#define GET_WTMR_TWC(c)     (((c)->wtmr & 0x0001) >> 0)
-#define SET_WTMR_TWC(c,v)   BLIT32((c)->wtmr, 0, (v) ? 1 : 0)
-  unsigned_4 trr;
-};
-
-
-
-/* Finish off the partially created hw device.  Attach our local
-   callbacks.  Wire up our port names etc */
-
-static hw_io_read_buffer_method tx3904tmr_io_read_buffer;
-static hw_io_write_buffer_method tx3904tmr_io_write_buffer;
-static hw_port_event_method tx3904tmr_port_event;
-
-static void
-attach_tx3904tmr_regs (struct hw *me,
-		      struct tx3904tmr *controller)
-{
-  unsigned_word attach_address;
-  int attach_space;
-  unsigned attach_size;
-  reg_property_spec reg;
-
-  if (hw_find_property (me, "reg") == NULL)
-    hw_abort (me, "Missing \"reg\" property");
-
-  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
-    hw_abort (me, "\"reg\" property must contain one addr/size entry");
-
-  hw_unit_address_to_attach_address (hw_parent (me),
-				     &reg.address,
-				     &attach_space,
-				     &attach_address,
-				     me);
-  hw_unit_size_to_attach_size (hw_parent (me),
-			       &reg.size,
-			       &attach_size, me);
-
-  hw_attach_address (hw_parent (me), 0,
-		     attach_space, attach_address, attach_size,
-		     me);
-
-  if(hw_find_property(me, "clock") != NULL)
-    controller->clock_ticks = (unsigned_4) hw_find_integer_property(me, "clock");
-
-  if(hw_find_property(me, "ext") != NULL)
-    controller->ext_ticks = (unsigned_4) hw_find_integer_property(me, "ext");
-
-  controller->base_address = attach_address;
-}
-
-
-static void
-tx3904tmr_finish (struct hw *me)
-{
-  struct tx3904tmr *controller;
-
-  controller = HW_ZALLOC (me, struct tx3904tmr);
-  set_hw_data (me, controller);
-  set_hw_io_read_buffer (me, tx3904tmr_io_read_buffer);
-  set_hw_io_write_buffer (me, tx3904tmr_io_write_buffer);
-  set_hw_ports (me, tx3904tmr_ports);
-  set_hw_port_event (me, tx3904tmr_port_event);
-
-  /* Preset clock dividers */
-  controller->clock_ticks = 1;
-  controller->ext_ticks = 100;
-
-  /* Attach ourself to our parent bus */
-  attach_tx3904tmr_regs (me, controller);
-
-  /* Initialize to reset state */
-  controller->tcr = 
-    controller->itmr =
-    controller->ccdr =
-    controller->pmgr = 
-    controller->wtmr =
-    controller->tisr = 
-    controller->trr = 0;
-  controller->cpra = controller->cprb = 0x00FFFFFF;
-  controller->ff = 0;
-  controller->last_ticks = controller->roundoff_ticks = 0;
-  controller->event = NULL;
-}
-
-
-
-/* An event arrives on an interrupt port */
-
-static void
-tx3904tmr_port_event (struct hw *me,
-		     int my_port,
-		     struct hw *source,
-		     int source_port,
-		     int level)
-{
-  struct tx3904tmr *controller = hw_data (me);
-
-  switch (my_port)
-    {
-    case RESET_PORT:
-      {
-	HW_TRACE ((me, "reset"));
-
-	/* preset flip-flop to FFI value */
-	controller->ff = GET_PMGR_FFI(controller);
-
-	controller->tcr = 
-	  controller->itmr =
-	  controller->ccdr =
-	  controller->pmgr = 
-	  controller->wtmr =
-	  controller->tisr = 
-	  controller->trr = 0;
-	controller->cpra = controller->cprb = 0x00FFFFFF;
-	controller->last_ticks = controller->roundoff_ticks = 0;
-	if(controller->event != NULL)
-	  hw_event_queue_deschedule(me, controller->event);
-	controller->event = NULL;
-	break;
-      }
-
-    default:
-      hw_abort (me, "Event on unknown port %d", my_port);
-      break;
-    }
-}
-
-
-/* generic read/write */
-
-static unsigned
-tx3904tmr_io_read_buffer (struct hw *me,
-			 void *dest,
-			 int space,
-			 unsigned_word base,
-			 unsigned nr_bytes)
-{
-  struct tx3904tmr *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = 3 - (address - controller->base_address) % 4;
-      unsigned_4 register_value; /* in target byte order */
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case TCR_REG: register_value = controller->tcr; break;
-	case TISR_REG: register_value = controller->tisr; break;
-	case CPRA_REG: register_value = controller->cpra; break;
-	case CPRB_REG: register_value = controller->cprb; break;
-	case ITMR_REG: register_value = controller->itmr; break;
-	case CCDR_REG: register_value = controller->ccdr; break;
-	case PMGR_REG: register_value = controller->pmgr; break;
-	case WTMR_REG: register_value = controller->wtmr; break;
-	case TRR_REG: register_value = controller->trr; break;
-	default: register_value = 0;
-	}
-
-      /* write requested byte out */
-      memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1);
-    }
-
-  return nr_bytes;
-}     
-
-
-
-static unsigned
-tx3904tmr_io_write_buffer (struct hw *me,
-			  const void *source,
-			  int space,
-			  unsigned_word base,
-			  unsigned nr_bytes)
-{
-  struct tx3904tmr *controller = hw_data (me);
-  unsigned byte;
-
-  HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
-  for (byte = 0; byte < nr_bytes; byte++)
-    {
-      address_word address = base + byte;
-      unsigned_1 write_byte = ((const char*) source)[byte];
-      int reg_number = (address - controller->base_address) / 4;
-      int reg_offset = 3 - (address - controller->base_address) % 4;
-
-      /* fill in entire register_value word */
-      switch (reg_number)
-	{
-	case TCR_REG:
-	  if(reg_offset == 0) /* first byte */
-	    {
-	      /* update register, but mask out NOP bits */
-	      controller->tcr = (unsigned_4) (write_byte & 0xef);
-
-	      /* Reset counter value if timer suspended and CRE is set. */
-	      if(GET_TCR_TCE(controller) == 0 &&
-		 GET_TCR_CRE(controller) == 1)
-		controller->trr = 0;
-	    }
-	  /* HW_TRACE ((me, "tcr: %08lx", (long) controller->tcr)); */
-	  break;
-
-	case ITMR_REG:
-	  if(reg_offset == 1) /* second byte */
-	    {
-	      SET_ITMR_TIIE(controller, write_byte & 0x80);
-	    }
-	  else if(reg_offset == 0) /* first byte */
-	    {
-	      SET_ITMR_TZCE(controller, write_byte & 0x01);
-	    }
-	  /* HW_TRACE ((me, "itmr: %08lx", (long) controller->itmr)); */
-	  break;
-
-	case CCDR_REG:
-	  if(reg_offset == 0) /* first byte */
-	    {
-	      controller->ccdr = write_byte & 0x07;
-	    }
-	  /* HW_TRACE ((me, "ccdr: %08lx", (long) controller->ccdr)); */
-	  break;
-
-	case PMGR_REG:
-	  if(reg_offset == 1) /* second byte */
-	    {
-	      SET_PMGR_TPIBE(controller, write_byte & 0x80);
-	      SET_PMGR_TPIAE(controller, write_byte & 0x40);
-	    }
-	  else if(reg_offset == 0) /* first byte */
-	    {
-	      SET_PMGR_FFI(controller, write_byte & 0x01);
-	    }
-	  /* HW_TRACE ((me, "pmgr: %08lx", (long) controller->pmgr)); */
-	  break;
-
-	case WTMR_REG:
-	  if(reg_offset == 1) /* second byte */
-	    {
-	      SET_WTMR_TWIE(controller, write_byte & 0x80);
-	    }
-	  else if(reg_offset == 0) /* first byte */
-	    {
-	      SET_WTMR_WDIS(controller, write_byte & 0x80);
-	      SET_WTMR_TWC(controller, write_byte & 0x01);
-	    }
-	  /* HW_TRACE ((me, "wtmr: %08lx", (long) controller->wtmr)); */
-	  break;
-
-	case TISR_REG:
-	  if(reg_offset == 0) /* first byte */
-	    {
-	      /* All bits must be zero in given byte, according to
-                 spec. */
-
-	      /* Send an "interrupt off" event on the interrupt port */
-	      if(controller->tisr != 0) /* any interrupts active? */
-		{
-		  hw_port_event(me, INT_PORT, 0);		  
-		}
-	      
-	      /* clear interrupt status register */
-	      controller->tisr = 0;
-	    }
-	  /* HW_TRACE ((me, "tisr: %08lx", (long) controller->tisr)); */
-	  break;
-
-	case CPRA_REG:
-	  if(reg_offset < 3) /* first, second, or third byte */
-	    {
-	      MBLIT32(controller->cpra, (reg_offset*8)+7, (reg_offset*8), write_byte);
-	    }
-	  /* HW_TRACE ((me, "cpra: %08lx", (long) controller->cpra)); */
-	  break;
-
-	case CPRB_REG:
-	  if(reg_offset < 3) /* first, second, or third byte */
-	    {
-	      MBLIT32(controller->cprb, (reg_offset*8)+7, (reg_offset*8), write_byte);
-	    }
-	  /* HW_TRACE ((me, "cprb: %08lx", (long) controller->cprb)); */
-	  break;
-
-	default: 
-	  HW_TRACE ((me, "write to illegal register %d", reg_number));
-	}
-    } /* loop over bytes */
-
-  /* Schedule a timer event in near future, so we can increment or
-     stop the counter, to respond to register updates. */
-  hw_event_queue_schedule(me, 1, deliver_tx3904tmr_tick, NULL);
-
-  return nr_bytes;
-}     
-
-
-
-/* Deliver a clock tick to the counter. */
-static void
-deliver_tx3904tmr_tick (struct hw *me,
-			void *data)
-{
-  struct tx3904tmr *controller = hw_data (me);
-  SIM_DESC sd = hw_system (me);
-  signed_8 this_ticks = sim_events_time(sd);
-
-  signed_8 warp;
-  signed_8 divisor;
-  signed_8 quotient, remainder;
-
-  /* compute simulation ticks between last tick and this tick */
-  if(controller->last_ticks != 0)
-    warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
-  else
-    {
-      controller->last_ticks = this_ticks; /* initialize */
-      warp = controller->roundoff_ticks;
-    }
-
-  if(controller->event != NULL)
-    hw_event_queue_deschedule(me, controller->event);
-  controller->event = NULL;
-
-  /* Check whether the timer ticking is enabled at this moment.  This
-     largely a function of the TCE bit, but is also slightly
-     mode-dependent. */
-  switch((int) GET_TCR_TMODE(controller))
-    {
-    case 0: /* interval */
-      /* do not advance counter if TCE = 0 or if holding at count = CPRA */
-      if(GET_TCR_TCE(controller) == 0 ||
-	 controller->trr == controller->cpra)
-	return;
-      break;
-
-    case 1: /* pulse generator */
-      /* do not advance counter if TCE = 0 */
-      if(GET_TCR_TCE(controller) == 0)
-	return;
-      break;
-
-    case 2: /* watchdog */
-      /* do not advance counter if TCE = 0 and WDIS = 1 */
-      if(GET_TCR_TCE(controller) == 0 &&
-	 GET_WTMR_WDIS(controller) == 1)
-	return;
-      break;
-
-    case 3: /* disabled */
-      /* regardless of TCE, do not advance counter */
-      return;
-    }
-
-  /* In any of the above cases that return, a subsequent register
-     write will be needed to restart the timer.  A tick event is
-     scheduled by any register write, so it is more efficient not to
-     reschedule dummy events here. */
-
-
-  /* find appropriate divisor etc. */ 
-  if(GET_TCR_CCS(controller) == 0) /* internal system clock */
-    {
-      /* apply internal clock divider */
-      if(GET_TCR_CCDE(controller)) /* divisor circuit enabled? */
-	divisor = controller->clock_ticks * (1 << (1 + GET_CCDR_CDR(controller)));
-      else
-	divisor = controller->clock_ticks;
-    }
-  else
-    {
-      divisor = controller->ext_ticks;
-    }
-
-  /* how many times to increase counter? */
-  quotient = warp / divisor;
-  remainder = warp % divisor;
-
-  /* NOTE: If the event rescheduling code works properly, the quotient
-     should never be larger than 1.  That is, we should receive events
-     here at least as frequently as the simulated counter is supposed
-     to decrement.  So the remainder (-> roundoff_ticks) will slowly
-     accumulate, with the quotient == 0.  Once in a while, quotient
-     will equal 1. */
-
-  controller->roundoff_ticks = remainder;
-  controller->last_ticks = this_ticks;
-  while(quotient > 0) /* Is it time to increment counter? */
-    {
-      /* next 24-bit counter value */
-      unsigned_4 next_trr = (controller->trr + 1) % (1 << 24);
-      quotient --;
-      
-      switch((int) GET_TCR_TMODE(controller))
-	{
-	case 0: /* interval timer mode */
-	  {
-	    /* Current or next counter value matches CPRA value?  The
-	       first case covers counter holding at maximum before
-	       reset.  The second case covers normal counting
-	       behavior. */
-	    if(controller->trr == controller->cpra ||
-	       next_trr == controller->cpra)
-	      {
-		/* likely hold CPRA value */
-		if(controller->trr == controller->cpra)
-		  next_trr = controller->cpra;
-
-		SET_TISR_TIIS(controller);
-
-		/* Signal an interrupt if it is enabled with TIIE,
-		   and if we just arrived at CPRA.  Don't repeatedly
-		   interrupt if holding due to TZCE=0 */
-		if(GET_ITMR_TIIE(controller) &&
-		   next_trr != controller->trr)
-		  {
-		    hw_port_event(me, INT_PORT, 1);
-		  }
-
-		/* Reset counter? */
-		if(GET_ITMR_TZCE(controller))
-		  {
-		    next_trr = 0;
-		  }
-	      }
-	  }
-	break;
-
-	case 1: /* pulse generator mode */
-	  {
-	    /* first trip point */
-	    if(next_trr == controller->cpra)
-	      {
-		/* flip flip-flop & report */
-		controller->ff ^= 1;
-		hw_port_event(me, FF_PORT, controller->ff);
-		SET_TISR_TPIAS(controller);
-
-		/* signal interrupt */
-		if(GET_PMGR_TPIAE(controller))
-		  {
-		    hw_port_event(me, INT_PORT, 1);
-		  }
-
-	      }
-	    /* second trip point */
-	    else if(next_trr == controller->cprb)
-	      {
-		/* flip flip-flop & report */
-		controller->ff ^= 1;
-		hw_port_event(me, FF_PORT, controller->ff);
-		SET_TISR_TPIBS(controller);
-
-		/* signal interrupt */
-		if(GET_PMGR_TPIBE(controller))
-		  {
-		    hw_port_event(me, INT_PORT, 1);
-		  }
-
-		/* clear counter */
-		next_trr = 0;
-	      }
-	  }
-	break;
-
-	case 2: /* watchdog timer mode */
-	  {
-	    /* watchdog timer expiry */
-	    if(next_trr == controller->cpra)
-	      {
-		SET_TISR_TWIS(controller);
-
-		/* signal interrupt */
-		if(GET_WTMR_TWIE(controller))
-		  {
-		    hw_port_event(me, INT_PORT, 1);
-		  }
-
-		/* clear counter */
-		next_trr = 0;
-	      }
-	  }
-	break;
-
-	case 3: /* disabled */
-	default:
-	  break;
-	}
-
-      /* update counter and report */
-      controller->trr = next_trr;
-      /* HW_TRACE ((me, "counter trr %ld tisr %lx",
-	 (long) controller->trr, (long) controller->tisr)); */
-    } /* end quotient loop */
-
-  /* Reschedule a timer event in near future, so we can increment the
-     counter again.  Set the event about 75% of divisor time away, so
-     we will experience roughly 1.3 events per counter increment. */
-  controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
-}
-
-
-
-
-const struct hw_descriptor dv_tx3904tmr_descriptor[] = {
-  { "tx3904tmr", tx3904tmr_finish, },
-  { NULL },
-};
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
deleted file mode 100644
index 043d76d..0000000
--- a/sim/mips/interp.c
+++ /dev/null
@@ -1,2404 +0,0 @@
-/*> interp.c <*/
-/* Simulator for the MIPS architecture.
-
-   This file is part of the MIPS sim
-
-		THIS SOFTWARE IS NOT COPYRIGHTED
-
-   Cygnus offers the following for use in the public domain.  Cygnus
-   makes no warranty with regard to the software or it's performance
-   and the user accepts the software "AS IS" with all faults.
-
-   CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
-   THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-
-NOTEs:
-
-The IDT monitor (found on the VR4300 board), seems to lie about
-register contents. It seems to treat the registers as sign-extended
-32-bit values. This cause *REAL* problems when single-stepping 64-bit
-code on the hardware.
-
-*/
-
-/* The TRACE manifests enable the provision of extra features. If they
-   are not defined then a simpler (quicker) simulator is constructed
-   without the required run-time checks, etc. */
-#if 1 /* 0 to allow user build selection, 1 to force inclusion */
-#define TRACE (1)
-#endif
-
-#include "bfd.h"
-#include "sim-main.h"
-#include "sim-utils.h"
-#include "sim-options.h"
-#include "sim-assert.h"
-#include "sim-hw.h"
-
-#include "itable.h"
-
-
-#include "config.h"
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <ansidecl.h>
-#include <ctype.h>
-#include <limits.h>
-#include <math.h>
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
-
-#include "getopt.h"
-#include "libiberty.h"
-#include "bfd.h"
-#include "gdb/callback.h"   /* GDB simulator callback interface */
-#include "gdb/remote-sim.h" /* GDB simulator interface */
-
-#include "sysdep.h"
-
-#ifndef PARAMS
-#define PARAMS(x) 
-#endif
-
-char* pr_addr PARAMS ((SIM_ADDR addr));
-char* pr_uword64 PARAMS ((uword64 addr));
-
-
-/* Within interp.c we refer to the sim_state and sim_cpu directly. */
-#define CPU cpu
-#define SD sd
-
-
-/* The following reserved instruction value is used when a simulator
-   trap is required. NOTE: Care must be taken, since this value may be
-   used in later revisions of the MIPS ISA. */
-
-#define RSVD_INSTRUCTION           (0x00000005)
-#define RSVD_INSTRUCTION_MASK      (0xFC00003F)
-
-#define RSVD_INSTRUCTION_ARG_SHIFT 6
-#define RSVD_INSTRUCTION_ARG_MASK  0xFFFFF  
-
-
-/* Bits in the Debug register */
-#define Debug_DBD 0x80000000   /* Debug Branch Delay */
-#define Debug_DM  0x40000000   /* Debug Mode         */
-#define Debug_DBp 0x00000002   /* Debug Breakpoint indicator */
-
-/*---------------------------------------------------------------------------*/
-/*-- GDB simulator interface ------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-static void ColdReset PARAMS((SIM_DESC sd));
-
-/*---------------------------------------------------------------------------*/
-
-
-
-#define DELAYSLOT()     {\
-                          if (STATE & simDELAYSLOT)\
-                            sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
-                          STATE |= simDELAYSLOT;\
-                        }
-
-#define JALDELAYSLOT()	{\
-			  DELAYSLOT ();\
-			  STATE |= simJALDELAYSLOT;\
-			}
-
-#define NULLIFY()       {\
-                          STATE &= ~simDELAYSLOT;\
-                          STATE |= simSKIPNEXT;\
-                        }
-
-#define CANCELDELAYSLOT() {\
-                            DSSTATE = 0;\
-                            STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
-                          }
-
-#define INDELAYSLOT()	((STATE & simDELAYSLOT) != 0)
-#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
-
-/* Note that the monitor code essentially assumes this layout of memory.
-   If you change these, change the monitor code, too.  */
-#define K0BASE  (0x80000000)
-#define K0SIZE  (0x20000000)
-#define K1BASE  (0xA0000000)
-#define K1SIZE  (0x20000000)
-
-/* Simple run-time monitor support.
-   
-   We emulate the monitor by placing magic reserved instructions at
-   the monitor's entry points; when we hit these instructions, instead
-   of raising an exception (as we would normally), we look at the
-   instruction and perform the appropriate monitory operation.
-   
-   `*_monitor_base' are the physical addresses at which the corresponding 
-        monitor vectors are located.  `0' means none.  By default,
-        install all three.
-    The RSVD_INSTRUCTION... macros specify the magic instructions we
-    use at the monitor entry points.  */
-static int firmware_option_p = 0;
-static SIM_ADDR idt_monitor_base =     0xBFC00000;
-static SIM_ADDR pmon_monitor_base =    0xBFC00500;
-static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
-
-static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
-
-
-#define MEM_SIZE (2 << 20)
-
-
-#if defined(TRACE)
-static char *tracefile = "trace.din"; /* default filename for trace log */
-FILE *tracefh = NULL;
-static void open_trace PARAMS((SIM_DESC sd));
-#endif /* TRACE */
-
-static const char * get_insn_name (sim_cpu *, int);
-
-/* simulation target board.  NULL=canonical */
-static char* board = NULL;
-
-
-static DECLARE_OPTION_HANDLER (mips_option_handler);
-
-enum {
-  OPTION_DINERO_TRACE = OPTION_START,
-  OPTION_DINERO_FILE,
-  OPTION_FIRMWARE,
-  OPTION_BOARD
-};
-
-
-static SIM_RC
-mips_option_handler (sd, cpu, opt, arg, is_command)
-     SIM_DESC sd;
-     sim_cpu *cpu;
-     int opt;
-     char *arg;
-     int is_command;
-{
-  int cpu_nr;
-  switch (opt)
-    {
-    case OPTION_DINERO_TRACE: /* ??? */
-#if defined(TRACE)
-      /* Eventually the simTRACE flag could be treated as a toggle, to
-	 allow external control of the program points being traced
-	 (i.e. only from main onwards, excluding the run-time setup,
-	 etc.). */
-      for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
-	{
-	  sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
-	  if (arg == NULL)
-	    STATE |= simTRACE;
-	  else if (strcmp (arg, "yes") == 0)
-	    STATE |= simTRACE;
-	  else if (strcmp (arg, "no") == 0)
-	    STATE &= ~simTRACE;
-	  else if (strcmp (arg, "on") == 0)
-	    STATE |= simTRACE;
-	  else if (strcmp (arg, "off") == 0)
-	    STATE &= ~simTRACE;
-	  else
-	    {
-	      fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
-	      return SIM_RC_FAIL;
-	    }
-	}
-      return SIM_RC_OK;
-#else /* !TRACE */
-      fprintf(stderr,"\
-Simulator constructed without dinero tracing support (for performance).\n\
-Re-compile simulator with \"-DTRACE\" to enable this option.\n");
-      return SIM_RC_FAIL;
-#endif /* !TRACE */
-
-    case OPTION_DINERO_FILE:
-#if defined(TRACE)
-      if (optarg != NULL) {
-	char *tmp;
-	tmp = (char *)malloc(strlen(optarg) + 1);
-	if (tmp == NULL)
-	  {
-	    sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
-	    return SIM_RC_FAIL;
-	  }
-	else {
-	  strcpy(tmp,optarg);
-	  tracefile = tmp;
-	  sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
-	}
-      }
-#endif /* TRACE */
-      return SIM_RC_OK;
-
-    case OPTION_FIRMWARE:
-      return sim_firmware_command (sd, arg);
-
-    case OPTION_BOARD:
-      {
-	if (arg)
-	  {
-	    board = zalloc(strlen(arg) + 1);
-	    strcpy(board, arg);
-	  }
-	return SIM_RC_OK;
-      }
-    }
-  
-  return SIM_RC_OK;
-}
-
-
-static const OPTION mips_options[] =
-{
-  { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
-      '\0', "on|off", "Enable dinero tracing",
-      mips_option_handler },
-  { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
-      '\0', "FILE", "Write dinero trace to FILE",
-      mips_option_handler },
-  { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
-    '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
-    mips_option_handler },
-  { {"board", required_argument, NULL, OPTION_BOARD},
-     '\0', "none" /* rely on compile-time string concatenation for other options */
-
-#define BOARD_JMR3904 "jmr3904"
-           "|" BOARD_JMR3904
-#define BOARD_JMR3904_PAL "jmr3904pal"
-           "|" BOARD_JMR3904_PAL
-#define BOARD_JMR3904_DEBUG "jmr3904debug"
-           "|" BOARD_JMR3904_DEBUG
-#define BOARD_BSP "bsp"
-           "|" BOARD_BSP
-
-    , "Customize simulation for a particular board.", mips_option_handler },
-
-  { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
-};
-
-
-int interrupt_pending;
-
-void
-interrupt_event (SIM_DESC sd, void *data)
-{
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-  address_word cia = CIA_GET (cpu);
-  if (SR & status_IE)
-    {
-      interrupt_pending = 0;
-      SignalExceptionInterrupt (1); /* interrupt "1" */
-    }
-  else if (!interrupt_pending)
-    sim_events_schedule (sd, 1, interrupt_event, data);
-}
-
-
-/*---------------------------------------------------------------------------*/
-/*-- Device registration hook -----------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-static void device_init(SIM_DESC sd) {
-#ifdef DEVICE_INIT
-  extern void register_devices(SIM_DESC);
-  register_devices(sd);
-#endif
-}
-
-/*---------------------------------------------------------------------------*/
-/*-- GDB simulator interface ------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-SIM_DESC
-sim_open (kind, cb, abfd, argv)
-     SIM_OPEN_KIND kind;
-     host_callback *cb;
-     struct bfd *abfd;
-     char **argv;
-{
-  SIM_DESC sd = sim_state_alloc (kind, cb);
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
-  SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
-
-  /* FIXME: watchpoints code shouldn't need this */
-  STATE_WATCHPOINTS (sd)->pc = &(PC);
-  STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
-  STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
-
-  /* Initialize the mechanism for doing insn profiling.  */
-  CPU_INSN_NAME (cpu) = get_insn_name;
-  CPU_MAX_INSNS (cpu) = nr_itable_entries;
-
-  STATE = 0;
-  
-  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
-    return 0;
-  sim_add_option_table (sd, NULL, mips_options);
-
-
-  /* getopt will print the error message so we just have to exit if this fails.
-     FIXME: Hmmm...  in the case of gdb we need getopt to call
-     print_filtered.  */
-  if (sim_parse_args (sd, argv) != SIM_RC_OK)
-    {
-      /* Uninstall the modules to avoid memory leaks,
-	 file descriptor leaks, etc.  */
-      sim_module_uninstall (sd);
-      return 0;
-    }
-
-  /* handle board-specific memory maps */
-  if (board == NULL)
-    {
-      /* Allocate core managed memory */
-      
-
-      /* For compatibility with the old code - under this (at level one)
-	 are the kernel spaces K0 & K1.  Both of these map to a single
-	 smaller sub region */
-      sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
-		       K1BASE, K0SIZE,
-		       MEM_SIZE, /* actual size */
-		       K0BASE);
-      
-      device_init(sd);
-    }
-  else if (board != NULL
-	   && (strcmp(board, BOARD_BSP) == 0))
-    {
-      int i;
-
-      STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
-
-      /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-		       0x9FC00000, 
-		       4 * 1024 * 1024, /* 4 MB */
-		       0xBFC00000);
-
-      /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-		       0x80000000, 
-		       4 * 1024 * 1024, /* 4 MB */
-		       0xA0000000);
-
-      /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
-      for (i=0; i<8; i++) /* 32 MB total */
-	{
-	  unsigned size = 4 * 1024 * 1024;  /* 4 MB */
-	  sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-			   0x88000000 + (i * size), 
-			   size, 
-			   0xA8000000 + (i * size));
-	}
-    }
-#if (WITH_HW)
-  else if (board != NULL
-	   && (strcmp(board, BOARD_JMR3904) == 0 ||
-	       strcmp(board, BOARD_JMR3904_PAL) == 0 ||
-	       strcmp(board, BOARD_JMR3904_DEBUG) == 0))
-    {
-      /* match VIRTUAL memory layout of JMR-TX3904 board */
-      int i;
-
-      /* --- disable monitor unless forced on by user --- */
-
-      if (! firmware_option_p)
-	{
-	  idt_monitor_base = 0;
-	  pmon_monitor_base = 0;
-	  lsipmon_monitor_base = 0;
-	}
-
-      /* --- environment --- */
-
-      STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
-
-      /* --- memory --- */
-
-      /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-		       0x9FC00000, 
-		       4 * 1024 * 1024, /* 4 MB */
-		       0xBFC00000);
-
-      /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-		       0x80000000, 
-		       4 * 1024 * 1024, /* 4 MB */
-		       0xA0000000);
-
-      /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
-      for (i=0; i<8; i++) /* 32 MB total */
-	{
-	  unsigned size = 4 * 1024 * 1024;  /* 4 MB */
-	  sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
-			   0x88000000 + (i * size), 
-			   size, 
-			   0xA8000000 + (i * size));
-	}
-
-      /* Dummy memory regions for unsimulated devices - sorted by address */
-
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
-      sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
-
-
-      /* --- simulated devices --- */
-      sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
-      sim_hw_parse (sd, "/tx3904cpu");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
-      sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
-      {
-	/* FIXME: poking at dv-sockser internals, use tcp backend if
-	 --sockser_addr option was given.*/
-	extern char* sockser_addr;
-	if(sockser_addr == NULL)
-	  sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
-	else
-	  sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
-      }
-      sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
-      sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
-
-      /* -- device connections --- */
-      sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
-      sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
-      sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
-      sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
-
-      /* add PAL timer & I/O module */
-      if(! strcmp(board, BOARD_JMR3904_PAL))
-	{
-	 /* the device */
-	 sim_hw_parse (sd, "/pal@0xffff0000");
-	 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
-
-	 /* wire up interrupt ports to irc */
-	 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
-	 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
-	 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
-	}
-
-      if(! strcmp(board, BOARD_JMR3904_DEBUG))
-	{
-	  /* -- DEBUG: glue interrupt generators --- */
-	  sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
-	  sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
-	}
-
-      device_init(sd);
-    }
-#endif
-
-
-  /* check for/establish the a reference program image */
-  if (sim_analyze_program (sd,
-			   (STATE_PROG_ARGV (sd) != NULL
-			    ? *STATE_PROG_ARGV (sd)
-			    : NULL),
-			   abfd) != SIM_RC_OK)
-    {
-      sim_module_uninstall (sd);
-      return 0;
-    }
-
-  /* Configure/verify the target byte order and other runtime
-     configuration options */
-  if (sim_config (sd) != SIM_RC_OK)
-    {
-      sim_module_uninstall (sd);
-      return 0;
-    }
-
-  if (sim_post_argv_init (sd) != SIM_RC_OK)
-    {
-      /* Uninstall the modules to avoid memory leaks,
-	 file descriptor leaks, etc.  */
-      sim_module_uninstall (sd);
-      return 0;
-    }
-
-  /* verify assumptions the simulator made about the host type system.
-     This macro does not return if there is a problem */
-  SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
-  SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
-
-  /* This is NASTY, in that we are assuming the size of specific
-     registers: */
-  {
-    int rn;
-    for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
-      {
-	if (rn < 32)
-	  cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
-	else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
-	  cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
-	else if ((rn >= 33) && (rn <= 37))
-	  cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
-	else if ((rn == SRIDX)
-		 || (rn == FCR0IDX)
-		 || (rn == FCR31IDX)
-		 || ((rn >= 72) && (rn <= 89)))
-	  cpu->register_widths[rn] = 32;
-	else
-	  cpu->register_widths[rn] = 0;
-      }
-
-
-  }
-
-#if defined(TRACE)
-  if (STATE & simTRACE)
-    open_trace(sd);
-#endif /* TRACE */
-
-  /*
-  sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n", 
-		  idt_monitor_base,
-		  pmon_monitor_base, 
-		  lsipmon_monitor_base);
-  */
-
-  /* Write the monitor trap address handlers into the monitor (eeprom)
-     address space.  This can only be done once the target endianness
-     has been determined. */
-  if (idt_monitor_base != 0)
-    {
-      unsigned loop;
-      unsigned idt_monitor_size = 1 << 11;
-
-      /* the default monitor region */
-      sim_do_commandf (sd, "memory region 0x%x,0x%x",
-		       idt_monitor_base, idt_monitor_size);
-
-      /* Entry into the IDT monitor is via fixed address vectors, and
-	 not using machine instructions. To avoid clashing with use of
-	 the MIPS TRAP system, we place our own (simulator specific)
-	 "undefined" instructions into the relevant vector slots. */
-      for (loop = 0; (loop < idt_monitor_size); loop += 4)
-	{
-	  address_word vaddr = (idt_monitor_base + loop);
-	  unsigned32 insn = (RSVD_INSTRUCTION |
-			     (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
-			      << RSVD_INSTRUCTION_ARG_SHIFT));
-	  H2T (insn);
-	  sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
-	}
-    }
-
-  if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
-    {
-    /* The PMON monitor uses the same address space, but rather than
-       branching into it the address of a routine is loaded. We can
-       cheat for the moment, and direct the PMON routine to IDT style
-       instructions within the monitor space. This relies on the IDT
-       monitor not using the locations from 0xBFC00500 onwards as its
-       entry points.*/
-      unsigned loop;
-      for (loop = 0; (loop < 24); loop++)
-	{
-	  unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
-	  switch (loop)
-	    {
-            case 0: /* read */
-              value = 7;
-              break;
-            case 1: /* write */
-              value = 8;
-              break;
-            case 2: /* open */
-              value = 6;
-              break;
-            case 3: /* close */
-              value = 10;
-              break;
-            case 5: /* printf */
-              value = ((0x500 - 16) / 8); /* not an IDT reason code */
-              break;
-            case 8: /* cliexit */
-              value = 17;
-              break;
-            case 11: /* flush_cache */
-              value = 28;
-              break;
-          }
-
-	SIM_ASSERT (idt_monitor_base != 0);
-        value = ((unsigned int) idt_monitor_base + (value * 8));
-	H2T (value);
-
-	if (pmon_monitor_base != 0)
-	  {
-	    address_word vaddr = (pmon_monitor_base + (loop * 4));
-	    sim_write (sd, vaddr, (char *)&value, sizeof (value));
-	  }
-
-	if (lsipmon_monitor_base != 0)
-	  {
-	    address_word vaddr = (lsipmon_monitor_base + (loop * 4));
-	    sim_write (sd, vaddr, (char *)&value, sizeof (value));
-	  }
-      }
-
-  /* Write an abort sequence into the TRAP (common) exception vector
-     addresses.  This is to catch code executing a TRAP (et.al.)
-     instruction without installing a trap handler. */
-  if ((idt_monitor_base != 0) || 
-      (pmon_monitor_base != 0) || 
-      (lsipmon_monitor_base != 0))
-    {
-      unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
-			     HALT_INSTRUCTION /* BREAK */ };
-      H2T (halt[0]);
-      H2T (halt[1]);
-      sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
-      sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
-      sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
-      /* XXX: Write here unconditionally? */
-      sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
-      sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
-      sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
-    }
-  }
-
-
-
-  return sd;
-}
-
-#if defined(TRACE)
-static void
-open_trace(sd)
-     SIM_DESC sd;
-{
-  tracefh = fopen(tracefile,"wb+");
-  if (tracefh == NULL)
-    {
-      sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
-      tracefh = stderr;
-  }
-}
-#endif /* TRACE */
-
-/* Return name of an insn, used by insn profiling.  */
-static const char *
-get_insn_name (sim_cpu *cpu, int i)
-{
-  return itable[i].name;
-}
-
-void
-sim_close (sd, quitting)
-     SIM_DESC sd;
-     int quitting;
-{
-#ifdef DEBUG
-  printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
-#endif
-
-
-  /* "quitting" is non-zero if we cannot hang on errors */
-
-  /* shut down modules */
-  sim_module_uninstall (sd);
-
-  /* Ensure that any resources allocated through the callback
-     mechanism are released: */
-  sim_io_shutdown (sd);
-
-#if defined(TRACE)
-  if (tracefh != NULL && tracefh != stderr)
-   fclose(tracefh);
-  tracefh = NULL;
-#endif /* TRACE */
-
-  /* FIXME - free SD */
-
-  return;
-}
-
-
-int
-sim_write (sd,addr,buffer,size)
-     SIM_DESC sd;
-     SIM_ADDR addr;
-     unsigned char *buffer;
-     int size;
-{
-  int index;
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
-  /* Return the number of bytes written, or zero if error. */
-#ifdef DEBUG
-  sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
-#endif
-
-  /* We use raw read and write routines, since we do not want to count
-     the GDB memory accesses in our statistics gathering. */
-
-  for (index = 0; index < size; index++)
-    {
-      address_word vaddr = (address_word)addr + index;
-      address_word paddr;
-      int cca;
-      if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
-	break;
-      if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
-	break;
-    }
-
-  return(index);
-}
-
-int
-sim_read (sd,addr,buffer,size)
-     SIM_DESC sd;
-     SIM_ADDR addr;
-     unsigned char *buffer;
-     int size;
-{
-  int index;
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
-  /* Return the number of bytes read, or zero if error. */
-#ifdef DEBUG
-  sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
-#endif /* DEBUG */
-
-  for (index = 0; (index < size); index++)
-    {
-      address_word vaddr = (address_word)addr + index;
-      address_word paddr;
-      int cca;
-      if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
-	break;
-      if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
-	break;
-    }
-
-  return(index);
-}
-
-int
-sim_store_register (sd,rn,memory,length)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *memory;
-     int length;
-{
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-  /* NOTE: gdb (the client) stores registers in target byte order
-     while the simulator uses host byte order */
-#ifdef DEBUG
-  sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
-#endif /* DEBUG */
-
-  /* Unfortunately this suffers from the same problem as the register
-     numbering one. We need to know what the width of each logical
-     register number is for the architecture being simulated. */
-
-  if (cpu->register_widths[rn] == 0)
-    {
-      sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
-      return 0;
-    }
-
-
-
-  if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
-    {
-      cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
-      if (cpu->register_widths[rn] == 32)
-	{
-	  if (length == 8)
-	    {
-	      cpu->fgr[rn - FGR_BASE] = 
-		(unsigned32) T2H_8 (*(unsigned64*)memory);
-	      return 8;
-	    }
-	  else
-	    {
-	      cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
-	      return 4;
-	    }
-	}
-      else
-	{
-	  cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
-	  return 8;
-	}
-    }
-
-  if (cpu->register_widths[rn] == 32)
-    {
-      if (length == 8)
-	{
-	  cpu->registers[rn] =
-	    (unsigned32) T2H_8 (*(unsigned64*)memory);
-	  return 8;
-	}
-      else
-	{
-	  cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
-	  return 4;
-	}
-    }
-  else
-    {
-      cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
-      return 8;
-    }
-
-  return 0;
-}
-
-int
-sim_fetch_register (sd,rn,memory,length)
-     SIM_DESC sd;
-     int rn;
-     unsigned char *memory;
-     int length;
-{
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-  /* NOTE: gdb (the client) stores registers in target byte order
-     while the simulator uses host byte order */
-#ifdef DEBUG
-#if 0  /* FIXME: doesn't compile */
-  sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
-#endif
-#endif /* DEBUG */
-
-  if (cpu->register_widths[rn] == 0)
-    {
-      sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
-      return 0;
-    }
-
-
-
-  /* Any floating point register */
-  if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
-    {
-      if (cpu->register_widths[rn] == 32)
-	{
-	  if (length == 8)
-	    {
-	      *(unsigned64*)memory =
-		H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
-	      return 8;
-	    }
-	  else
-	    {
-	      *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
-	      return 4;
-	    }
-	}
-      else
-	{
-	  *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
-	  return 8;
-	}
-    }
-
-  if (cpu->register_widths[rn] == 32)
-    {
-      if (length == 8)
-	{
-	  *(unsigned64*)memory =
-	    H2T_8 ((unsigned32) (cpu->registers[rn]));
-	  return 8;
-	}
-      else
-	{
-	  *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
-	  return 4;
-	}
-    }
-  else
-    {
-      *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
-      return 8;
-    }
-
-  return 0;
-}
-
-
-SIM_RC
-sim_create_inferior (sd, abfd, argv,env)
-     SIM_DESC sd;
-     struct bfd *abfd;
-     char **argv;
-     char **env;
-{
-
-#ifdef DEBUG
-#if 0 /* FIXME: doesn't compile */
-  printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
-	 pr_addr(PC));
-#endif
-#endif /* DEBUG */
-
-  ColdReset(sd);
-
-  if (abfd != NULL)
-    {
-      /* override PC value set by ColdReset () */
-      int cpu_nr;
-      for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
-	{
-	  sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
-	  CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
-	}
-    }
-
-#if 0 /* def DEBUG */
-  if (argv || env)
-    {
-      /* We should really place the argv slot values into the argument
-	 registers, and onto the stack as required. However, this
-	 assumes that we have a stack defined, which is not
-	 necessarily true at the moment. */
-      char **cptr;
-      sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
-      for (cptr = argv; (cptr && *cptr); cptr++)
-	printf("DBG: arg \"%s\"\n",*cptr);
-    }
-#endif /* DEBUG */
-
-  return SIM_RC_OK;
-}
-
-void
-sim_do_command (sd,cmd)
-     SIM_DESC sd;
-     char *cmd;
-{
-  if (sim_args_command (sd, cmd) != SIM_RC_OK)
-    sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
-		   cmd);
-}
-
-/*---------------------------------------------------------------------------*/
-/*-- Private simulator support interface ------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-/* Read a null terminated string from memory, return in a buffer */
-static char *
-fetch_str (SIM_DESC sd,
-	   address_word addr)
-{
-  char *buf;
-  int nr = 0;
-  char null;
-  while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
-    nr++;
-  buf = NZALLOC (char, nr + 1);
-  sim_read (sd, addr, buf, nr);
-  return buf;
-}
-
-
-/* Implements the "sim firmware" command:
-	sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
-		NAME can be idt, pmon, or lsipmon.  If omitted, ADDRESS
-		defaults to the normal address for that monitor.
-	sim firmware none --- don't emulate any ROM monitor.  Useful
-		if you need a clean address space.  */
-static SIM_RC
-sim_firmware_command (SIM_DESC sd, char *arg)
-{
-  int address_present = 0;
-  SIM_ADDR address;
-
-  /* Signal occurrence of this option. */
-  firmware_option_p = 1;
-
-  /* Parse out the address, if present.  */
-  {
-    char *p = strchr (arg, '@');
-    if (p)
-      {
-	char *q;
-	address_present = 1;
-	p ++; /* skip over @ */
-
-	address = strtoul (p, &q, 0);
-	if (*q != '\0') 
-	  {
-	    sim_io_printf (sd, "Invalid address given to the"
-			   "`sim firmware NAME@ADDRESS' command: %s\n",
-			   p);
-	    return SIM_RC_FAIL;
-	  }
-      }
-    else
-      {
-	address_present = 0;
-	address = -1; /* Dummy value.  */
-      }
-  }
-
-  if (! strncmp (arg, "idt", 3))
-    {
-      idt_monitor_base = address_present ? address : 0xBFC00000;
-      pmon_monitor_base = 0;
-      lsipmon_monitor_base = 0;
-    }
-  else if (! strncmp (arg, "pmon", 4))
-    {
-      /* pmon uses indirect calls.  Hook into implied idt. */
-      pmon_monitor_base = address_present ? address : 0xBFC00500;
-      idt_monitor_base = pmon_monitor_base - 0x500;
-      lsipmon_monitor_base = 0;
-    }
-  else if (! strncmp (arg, "lsipmon", 7))
-    {
-      /* lsipmon uses indirect calls.  Hook into implied idt. */
-      pmon_monitor_base = 0;
-      lsipmon_monitor_base = address_present ? address : 0xBFC00200;
-      idt_monitor_base = lsipmon_monitor_base - 0x200;
-    }
-  else if (! strncmp (arg, "none", 4))
-    {
-      if (address_present)
-	{
-	  sim_io_printf (sd,
-			 "The `sim firmware none' command does "
-			 "not take an `ADDRESS' argument.\n");
-	  return SIM_RC_FAIL;
-	}
-      idt_monitor_base = 0;
-      pmon_monitor_base = 0;
-      lsipmon_monitor_base = 0;
-    }
-  else
-    {
-      sim_io_printf (sd, "\
-Unrecognized name given to the `sim firmware NAME' command: %s\n\
-Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
-		     arg);
-      return SIM_RC_FAIL;
-    }
-  
-  return SIM_RC_OK;
-}
-
-
-
-/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
-int
-sim_monitor (SIM_DESC sd,
-	     sim_cpu *cpu,
-	     address_word cia,
-	     unsigned int reason)
-{
-#ifdef DEBUG
-  printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
-#endif /* DEBUG */
-
-  /* The IDT monitor actually allows two instructions per vector
-     slot. However, the simulator currently causes a trap on each
-     individual instruction. We cheat, and lose the bottom bit. */
-  reason >>= 1;
-
-  /* The following callback functions are available, however the
-     monitor we are simulating does not make use of them: get_errno,
-     isatty, lseek, rename, system, time and unlink */
-  switch (reason)
-    {
-
-    case 6: /* int open(char *path,int flags) */
-      {
-	char *path = fetch_str (sd, A0);
-	V0 = sim_io_open (sd, path, (int)A1);
-	zfree (path);
-	break;
-      }
-
-    case 7: /* int read(int file,char *ptr,int len) */
-      {
-	int fd = A0;
-	int nr = A2;
-	char *buf = zalloc (nr);
-	V0 = sim_io_read (sd, fd, buf, nr);
-	sim_write (sd, A1, buf, nr);
-	zfree (buf);
-      }
-      break;
-
-    case 8: /* int write(int file,char *ptr,int len) */
-      {
-	int fd = A0;
-	int nr = A2;
-	char *buf = zalloc (nr);
-	sim_read (sd, A1, buf, nr);
-	V0 = sim_io_write (sd, fd, buf, nr);
-	zfree (buf);
-	break;
-      }
-
-    case 10: /* int close(int file) */
-      {
-	V0 = sim_io_close (sd, (int)A0);
-	break;
-      }
-
-    case 2:  /* Densan monitor: char inbyte(int waitflag) */
-      {
-	if (A0 == 0)	/* waitflag == NOWAIT */
-	  V0 = (unsigned_word)-1;
-      }
-     /* Drop through to case 11 */
-
-    case 11: /* char inbyte(void) */
-      {
-        char tmp;
-	/* ensure that all output has gone... */
-	sim_io_flush_stdout (sd);
-        if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
-	  {
-	    sim_io_error(sd,"Invalid return from character read");
-	    V0 = (unsigned_word)-1;
-	  }
-        else
-	  V0 = (unsigned_word)tmp;
-	break;
-      }
-
-    case 3:  /* Densan monitor: void co(char chr) */
-    case 12: /* void outbyte(char chr) : write a byte to "stdout" */
-      {
-        char tmp = (char)(A0 & 0xFF);
-        sim_io_write_stdout (sd, &tmp, sizeof(char));
-	break;
-      }
-
-    case 17: /* void _exit() */
-      {
-	sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
-	sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
-			 (unsigned int)(A0 & 0xFFFFFFFF));
-	break;
-      }
-
-    case 28: /* PMON flush_cache */
-      break;
-
-    case 55: /* void get_mem_info(unsigned int *ptr) */
-      /* in:  A0 = pointer to three word memory location */
-      /* out: [A0 + 0] = size */
-      /*      [A0 + 4] = instruction cache size */
-      /*      [A0 + 8] = data cache size */
-      {
-	unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
-	unsigned_4 zero = 0;
-	H2T (value);
-	sim_write (sd, A0 + 0, (char *)&value, 4);
-	sim_write (sd, A0 + 4, (char *)&zero, 4);
-	sim_write (sd, A0 + 8, (char *)&zero, 4);
-	/* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
-	break;
-      }
-    
-    case 158: /* PMON printf */
-      /* in:  A0 = pointer to format string */
-      /*      A1 = optional argument 1 */
-      /*      A2 = optional argument 2 */
-      /*      A3 = optional argument 3 */
-      /* out: void */
-      /* The following is based on the PMON printf source */
-      {
-	address_word s = A0;
-	char c;
-	signed_word *ap = &A1; /* 1st argument */
-        /* This isn't the quickest way, since we call the host print
-           routine for every character almost. But it does avoid
-           having to allocate and manage a temporary string buffer. */
-	/* TODO: Include check that we only use three arguments (A1,
-           A2 and A3) */
-	while (sim_read (sd, s++, &c, 1) && c != '\0')
-	  {
-            if (c == '%')
-	      {
-		char tmp[40];
-		enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
-		int width = 0, trunc = 0, haddot = 0, longlong = 0;
-		while (sim_read (sd, s++, &c, 1) && c != '\0')
-		  {
-		    if (strchr ("dobxXulscefg%", c))
-		      break;
-		    else if (c == '-')
-		      fmt = FMT_LJUST;
-		    else if (c == '0')
-		      fmt = FMT_RJUST0;
-		    else if (c == '~')
-		      fmt = FMT_CENTER;
-		    else if (c == '*')
-		      {
-			if (haddot)
-			  trunc = (int)*ap++;
-			else
-			  width = (int)*ap++;
-		      }
-		    else if (c >= '1' && c <= '9')
-		      {
-			address_word t = s;
-			unsigned int n;
-			while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
-			  tmp[s - t] = c;
-			tmp[s - t] = '\0';
-			n = (unsigned int)strtol(tmp,NULL,10);
-			if (haddot)
-			  trunc = n;
-			else
-			  width = n;
-			s--;
-		      }
-		    else if (c == '.')
-		      haddot = 1;
-		  }
-		switch (c)
-		  {
-		  case '%':
-		    sim_io_printf (sd, "%%");
-		    break;
-		  case 's':
-		    if ((int)*ap != 0)
-		      {
-			address_word p = *ap++;
-			char ch;
-			while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
-			  sim_io_printf(sd, "%c", ch);
-		      }
-		    else
-		      sim_io_printf(sd,"(null)");
-		    break;
-		  case 'c':
-		    sim_io_printf (sd, "%c", (int)*ap++);
-		    break;
-		  default:
-		    if (c == 'l')
-		      {
-			sim_read (sd, s++, &c, 1);
-			if (c == 'l')
-			  {
-			    longlong = 1;
-			    sim_read (sd, s++, &c, 1);
-			  }
-		      }
-		    if (strchr ("dobxXu", c))
-		      {
-			word64 lv = (word64) *ap++;
-			if (c == 'b')
-			  sim_io_printf(sd,"<binary not supported>");
-			else
-			  {
-			    sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
-			    if (longlong)
-			      sim_io_printf(sd, tmp, lv);
-			    else
-			      sim_io_printf(sd, tmp, (int)lv);
-			  }
-		      }
-		    else if (strchr ("eEfgG", c))
-		      {
-			double dbl = *(double*)(ap++);
-			sprintf (tmp, "%%%d.%d%c", width, trunc, c);
-			sim_io_printf (sd, tmp, dbl);
-			trunc = 0;
-		      }
-		  }
-	      }
-	    else
-	      sim_io_printf(sd, "%c", c);
-	  }
-	break;
-      }
-
-    default:
-      /* Unknown reason.  */
-      return 0;
-  }
-  return 1;
-}
-
-/* Store a word into memory.  */
-
-static void
-store_word (SIM_DESC sd,
-	    sim_cpu *cpu,
-	    address_word cia,
-	    uword64 vaddr,
-	    signed_word val)
-{
-  address_word paddr;
-  int uncached;
-
-  if ((vaddr & 3) != 0)
-    SignalExceptionAddressStore ();
-  else
-    {
-      if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-			      isTARGET, isREAL))
-	{
-	  const uword64 mask = 7;
-	  uword64 memval;
-	  unsigned int byte;
-
-	  paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
-	  byte = (vaddr & mask) ^ (BigEndianCPU << 2);
-	  memval = ((uword64) val) << (8 * byte);
-	  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
-		       isREAL);
-	}
-    }
-}
-
-/* Load a word from memory.  */
-
-static signed_word
-load_word (SIM_DESC sd,
-	   sim_cpu *cpu,
-	   address_word cia,
-	   uword64 vaddr)
-{
-  if ((vaddr & 3) != 0)
-    {
-      SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
-    }
-  else
-    {
-      address_word paddr;
-      int uncached;
-
-      if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-			      isTARGET, isREAL))
-	{
-	  const uword64 mask = 0x7;
-	  const unsigned int reverse = ReverseEndian ? 1 : 0;
-	  const unsigned int bigend = BigEndianCPU ? 1 : 0;
-	  uword64 memval;
-	  unsigned int byte;
-
-	  paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
-	  LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
-			       isDATA, isREAL);
-	  byte = (vaddr & mask) ^ (bigend << 2);
-	  return EXTEND32 (memval >> (8 * byte));
-	}
-    }
-
-  return 0;
-}
-
-/* Simulate the mips16 entry and exit pseudo-instructions.  These
-   would normally be handled by the reserved instruction exception
-   code, but for ease of simulation we just handle them directly.  */
-
-static void
-mips16_entry (SIM_DESC sd,
-	      sim_cpu *cpu,
-	      address_word cia,
-	      unsigned int insn)
-{
-  int aregs, sregs, rreg;
-
-#ifdef DEBUG
-  printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
-#endif /* DEBUG */
-
-  aregs = (insn & 0x700) >> 8;
-  sregs = (insn & 0x0c0) >> 6;
-  rreg =  (insn & 0x020) >> 5;
-
-  /* This should be checked by the caller.  */
-  if (sregs == 3)
-    abort ();
-
-  if (aregs < 5)
-    {
-      int i;
-      signed_word tsp;
-
-      /* This is the entry pseudo-instruction.  */
-
-      for (i = 0; i < aregs; i++)
-	store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
-
-      tsp = SP;
-      SP -= 32;
-
-      if (rreg)
-	{
-	  tsp -= 4;
-	  store_word (SD, CPU, cia, (uword64) tsp, RA);
-	}
-
-      for (i = 0; i < sregs; i++)
-	{
-	  tsp -= 4;
-	  store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
-	}
-    }
-  else
-    {
-      int i;
-      signed_word tsp;
-
-      /* This is the exit pseudo-instruction.  */
-
-      tsp = SP + 32;
-
-      if (rreg)
-	{
-	  tsp -= 4;
-	  RA = load_word (SD, CPU, cia, (uword64) tsp);
-	}
-
-      for (i = 0; i < sregs; i++)
-	{
-	  tsp -= 4;
-	  GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
-	}
-
-      SP += 32;
-
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-	  if (aregs == 5)
-	    {
-	      FGR[0] = WORD64LO (GPR[4]);
-	      FPR_STATE[0] = fmt_uninterpreted;
-	    }
-	  else if (aregs == 6)
-	    {
-	      FGR[0] = WORD64LO (GPR[5]);
-	      FGR[1] = WORD64LO (GPR[4]);
-	      FPR_STATE[0] = fmt_uninterpreted;
-	      FPR_STATE[1] = fmt_uninterpreted;
-	    }
-	}	  
-
-      PC = RA;
-    }
-  
-}
-
-/*-- trace support ----------------------------------------------------------*/
-
-/* The TRACE support is provided (if required) in the memory accessing
-   routines. Since we are also providing the architecture specific
-   features, the architecture simulation code can also deal with
-   notifying the TRACE world of cache flushes, etc. Similarly we do
-   not need to provide profiling support in the simulator engine,
-   since we can sample in the instruction fetch control loop. By
-   defining the TRACE manifest, we add tracing as a run-time
-   option. */
-
-#if defined(TRACE)
-/* Tracing by default produces "din" format (as required by
-   dineroIII). Each line of such a trace file *MUST* have a din label
-   and address field. The rest of the line is ignored, so comments can
-   be included if desired. The first field is the label which must be
-   one of the following values:
-
-	0       read data
-        1       write data
-        2       instruction fetch
-        3       escape record (treated as unknown access type)
-        4       escape record (causes cache flush)
-
-   The address field is a 32bit (lower-case) hexadecimal address
-   value. The address should *NOT* be preceded by "0x".
-
-   The size of the memory transfer is not important when dealing with
-   cache lines (as long as no more than a cache line can be
-   transferred in a single operation :-), however more information
-   could be given following the dineroIII requirement to allow more
-   complete memory and cache simulators to provide better
-   results. i.e. the University of Pisa has a cache simulator that can
-   also take bus size and speed as (variable) inputs to calculate
-   complete system performance (a much more useful ability when trying
-   to construct an end product, rather than a processor). They
-   currently have an ARM version of their tool called ChARM. */
-
-
-void
-dotrace (SIM_DESC sd,
-	 sim_cpu *cpu,
-	 FILE *tracefh,
-	 int type,
-	 SIM_ADDR address,
-	 int width,
-	 char *comment,...)
-{
-  if (STATE & simTRACE) {
-    va_list ap;
-    fprintf(tracefh,"%d %s ; width %d ; ", 
-		type,
-		pr_addr(address),
-		width);
-    va_start(ap,comment);
-    vfprintf(tracefh,comment,ap);
-    va_end(ap);
-    fprintf(tracefh,"\n");
-  }
-  /* NOTE: Since the "din" format will only accept 32bit addresses, and
-     we may be generating 64bit ones, we should put the hi-32bits of the
-     address into the comment field. */
-
-  /* TODO: Provide a buffer for the trace lines. We can then avoid
-     performing writes until the buffer is filled, or the file is
-     being closed. */
-
-  /* NOTE: We could consider adding a comment field to the "din" file
-     produced using type 3 markers (unknown access). This would then
-     allow information about the program that the "din" is for, and
-     the MIPs world that was being simulated, to be placed into the
-     trace file. */
-
-  return;
-}
-#endif /* TRACE */
-
-/*---------------------------------------------------------------------------*/
-/*-- simulator engine -------------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-static void
-ColdReset (SIM_DESC sd)
-{
-  int cpu_nr;
-  for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
-    {
-      sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
-      /* RESET: Fixed PC address: */
-      PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
-      /* The reset vector address is in the unmapped, uncached memory space. */
-      
-      SR &= ~(status_SR | status_TS | status_RP);
-      SR |= (status_ERL | status_BEV);
-      
-      /* Cheat and allow access to the complete register set immediately */
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
-	  && WITH_TARGET_WORD_BITSIZE == 64)
-	SR |= status_FR; /* 64bit registers */
-      
-      /* Ensure that any instructions with pending register updates are
-	 cleared: */
-      PENDING_INVALIDATE();
-      
-      /* Initialise the FPU registers to the unknown state */
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-	  int rn;
-	  for (rn = 0; (rn < 32); rn++)
-	    FPR_STATE[rn] = fmt_uninterpreted;
-	}
-      
-    }
-}
-
-
-
-
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Signal an exception condition. This will result in an exception
-   that aborts the instruction. The instruction operation pseudocode
-   will never see a return from this function call. */
-
-void
-signal_exception (SIM_DESC sd,
-		  sim_cpu *cpu,
-		  address_word cia,
-		  int exception,...)
-{
-  /* int vector; */
-
-#ifdef DEBUG
-  sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
-#endif /* DEBUG */
-
-  /* Ensure that any active atomic read/modify/write operation will fail: */
-  LLBIT = 0;
-
-  /* Save registers before interrupt dispatching */
-#ifdef SIM_CPU_EXCEPTION_TRIGGER
-  SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
-#endif
-
-  switch (exception) {
-
-    case DebugBreakPoint:
-      if (! (Debug & Debug_DM))
-        {
-          if (INDELAYSLOT())
-            {
-              CANCELDELAYSLOT();
-              
-              Debug |= Debug_DBD;  /* signaled from within in delay slot */
-              DEPC = cia - 4;      /* reference the branch instruction */
-            }
-          else
-            {
-              Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
-              DEPC = cia;
-            }
-        
-          Debug |= Debug_DM;            /* in debugging mode */
-          Debug |= Debug_DBp;           /* raising a DBp exception */
-          PC = 0xBFC00200;
-          sim_engine_restart (SD, CPU, NULL, NULL_CIA);
-        }
-      break;
-
-    case ReservedInstruction:
-     {
-       va_list ap;
-       unsigned int instruction;
-       va_start(ap,exception);
-       instruction = va_arg(ap,unsigned int);
-       va_end(ap);
-       /* Provide simple monitor support using ReservedInstruction
-          exceptions. The following code simulates the fixed vector
-          entry points into the IDT monitor by causing a simulator
-          trap, performing the monitor operation, and returning to
-          the address held in the $ra register (standard PCS return
-          address). This means we only need to pre-load the vector
-          space with suitable instruction values. For systems were
-          actual trap instructions are used, we would not need to
-          perform this magic. */
-       if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
-	 {
-	   int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
-	   if (!sim_monitor (SD, CPU, cia, reason))
-	     sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
-
-	   /* NOTE: This assumes that a branch-and-link style
-	      instruction was used to enter the vector (which is the
-	      case with the current IDT monitor). */
-	   sim_engine_restart (SD, CPU, NULL, RA);
-	 }
-       /* Look for the mips16 entry and exit instructions, and
-          simulate a handler for them.  */
-       else if ((cia & 1) != 0
-		&& (instruction & 0xf81f) == 0xe809
-		&& (instruction & 0x0c0) != 0x0c0)
-	 {
-	   mips16_entry (SD, CPU, cia, instruction);
-	   sim_engine_restart (sd, NULL, NULL, NULL_CIA);
-	 }
-       /* else fall through to normal exception processing */
-       sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
-     }
-
-    default:
-     /* Store exception code into current exception id variable (used
-        by exit code): */
-
-     /* TODO: If not simulating exceptions then stop the simulator
-        execution. At the moment we always stop the simulation. */
-
-#ifdef SUBTARGET_R3900
-      /* update interrupt-related registers */
-
-      /* insert exception code in bits 6:2 */
-      CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
-      /* shift IE/KU history bits left */
-      SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
-
-      if (STATE & simDELAYSLOT)
-	{
-	  STATE &= ~simDELAYSLOT;
-	  CAUSE |= cause_BD;
-	  EPC = (cia - 4); /* reference the branch instruction */
-	}
-      else
-	EPC = cia;
-
-     if (SR & status_BEV)
-       PC = (signed)0xBFC00000 + 0x180;
-     else
-       PC = (signed)0x80000000 + 0x080;
-#else
-     /* See figure 5-17 for an outline of the code below */
-     if (! (SR & status_EXL))
-       {
-	 CAUSE = (exception << 2);
-	 if (STATE & simDELAYSLOT)
-	   {
-	     STATE &= ~simDELAYSLOT;
-	     CAUSE |= cause_BD;
-	     EPC = (cia - 4); /* reference the branch instruction */
-	   }
-	 else
-	   EPC = cia;
-	 /* FIXME: TLB et.al. */
-	 /* vector = 0x180; */
-       }
-     else
-       {
-	 CAUSE = (exception << 2);
-	 /* vector = 0x180; */
-       }
-     SR |= status_EXL;
-     /* Store exception code into current exception id variable (used
-        by exit code): */
-
-     if (SR & status_BEV)
-       PC = (signed)0xBFC00200 + 0x180;
-     else
-       PC = (signed)0x80000000 + 0x180;
-#endif
-
-     switch ((CAUSE >> 2) & 0x1F)
-       {
-       case Interrupt:
-	 /* Interrupts arrive during event processing, no need to
-            restart */
-	 return;
-
-       case NMIReset:
-	 /* Ditto */
-#ifdef SUBTARGET_3900
-	 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000  */
-	 PC = (signed)0xBFC00000;
-#endif /* SUBTARGET_3900 */
-	 return;
-
-       case TLBModification:
-       case TLBLoad:
-       case TLBStore:
-       case AddressLoad:
-       case AddressStore:
-       case InstructionFetch:
-       case DataReference:
-	 /* The following is so that the simulator will continue from the
-	    exception handler address. */
-	 sim_engine_halt (SD, CPU, NULL, PC,
-			  sim_stopped, SIM_SIGBUS);
-
-       case ReservedInstruction:
-       case CoProcessorUnusable:
-	 PC = EPC;
-	 sim_engine_halt (SD, CPU, NULL, PC,
-			  sim_stopped, SIM_SIGILL);
-
-       case IntegerOverflow:
-       case FPE:
-	 sim_engine_halt (SD, CPU, NULL, PC,
-			  sim_stopped, SIM_SIGFPE);
-	 
-       case BreakPoint:
-	 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
-	 break;
-
-       case SystemCall:
-       case Trap:
-	 sim_engine_restart (SD, CPU, NULL, PC);
-	 break;
-
-       case Watch:
-	 PC = EPC;
-	 sim_engine_halt (SD, CPU, NULL, PC,
-			  sim_stopped, SIM_SIGTRAP);
-
-       default: /* Unknown internal exception */
-	 PC = EPC;
-	 sim_engine_halt (SD, CPU, NULL, PC,
-			  sim_stopped, SIM_SIGABRT);
-
-       }
-
-    case SimulatorFault:
-     {
-       va_list ap;
-       char *msg;
-       va_start(ap,exception);
-       msg = va_arg(ap,char *);
-       va_end(ap);
-       sim_engine_abort (SD, CPU, NULL_CIA,
-			 "FATAL: Simulator error \"%s\"\n",msg);
-     }
-   }
-
-  return;
-}
-
-
-
-/* This function implements what the MIPS32 and MIPS64 ISAs define as
-   "UNPREDICTABLE" behaviour.
-
-   About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
-   may vary from processor implementation to processor implementation,
-   instruction to instruction, or as a function of time on the same
-   implementation or instruction.  Software can never depend on results
-   that are UNPREDICTABLE. ..."  (MIPS64 Architecture for Programmers
-   Volume II, The MIPS64 Instruction Set.  MIPS Document MD00087 revision
-   0.95, page 2.)
-  
-   For UNPREDICTABLE behaviour, we print a message, if possible print
-   the offending instructions mips.igen instruction name (provided by
-   the caller), and stop the simulator.
-
-   XXX FIXME: eventually, stopping the simulator should be made conditional
-   on a command-line option.  */
-void
-unpredictable_action(sim_cpu *cpu, address_word cia)
-{
-  SIM_DESC sd = CPU_STATE(cpu);
-
-  sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
-  sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
-}
-
-
-/*-- co-processor support routines ------------------------------------------*/
-
-static int UNUSED
-CoProcPresent(unsigned int coproc_number)
-{
-  /* Return TRUE if simulator provides a model for the given co-processor number */
-  return(0);
-}
-
-void
-cop_lw (SIM_DESC sd,
-	sim_cpu *cpu,
-	address_word cia,
-	int coproc_num,
-	int coproc_reg,
-	unsigned int memword)
-{
-  switch (coproc_num)
-    {
-    case 1:
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-#ifdef DEBUG
-	  printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
-#endif
-	  StoreFPR(coproc_reg,fmt_word,(uword64)memword);
-	  FPR_STATE[coproc_reg] = fmt_uninterpreted;
-	  break;
-	}
-
-    default:
-#if 0 /* this should be controlled by a configuration option */
-      sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
-#endif
-      break;
-    }
-
-  return;
-}
-
-void
-cop_ld (SIM_DESC sd,
-	sim_cpu *cpu,
-	address_word cia,
-	int coproc_num,
-	int coproc_reg,
-	uword64 memword)
-{
-
-#ifdef DEBUG
-  printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
-#endif
-
-  switch (coproc_num) {
-    case 1:
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-	  StoreFPR(coproc_reg,fmt_uninterpreted,memword);
-	  break;
-	}
-
-    default:
-#if 0 /* this message should be controlled by a configuration option */
-     sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
-#endif
-     break;
-  }
-
-  return;
-}
-
-
-
-
-unsigned int
-cop_sw (SIM_DESC sd,
-	sim_cpu *cpu,
-	address_word cia,
-	int coproc_num,
-	int coproc_reg)
-{
-  unsigned int value = 0;
-
-  switch (coproc_num)
-    {
-    case 1:
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-	  FP_formats hold;
-	  hold = FPR_STATE[coproc_reg];
-	  FPR_STATE[coproc_reg] = fmt_word;
-	  value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
-	  FPR_STATE[coproc_reg] = hold;
-	  break;
-	}
-
-    default:
-#if 0 /* should be controlled by configuration option */
-      sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
-#endif
-      break;
-    }
-
-  return(value);
-}
-
-uword64
-cop_sd (SIM_DESC sd,
-	sim_cpu *cpu,
-	address_word cia,
-	int coproc_num,
-	int coproc_reg)
-{
-  uword64 value = 0;
-  switch (coproc_num)
-    {
-    case 1:
-      if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
-	{
-	  value = ValueFPR(coproc_reg,fmt_uninterpreted);
-	  break;
-	}
-
-    default:
-#if 0 /* should be controlled by configuration option */
-      sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
-#endif
-      break;
-    }
-
-  return(value);
-}
-
-
-
-
-void
-decode_coproc (SIM_DESC sd,
-	       sim_cpu *cpu,
-	       address_word cia,
-	       unsigned int instruction)
-{
-  int coprocnum = ((instruction >> 26) & 3);
-
-  switch (coprocnum)
-    {
-    case 0: /* standard CPU control and cache registers */
-      {
-        int code = ((instruction >> 21) & 0x1F);
-	int rt = ((instruction >> 16) & 0x1F);
-	int rd = ((instruction >> 11) & 0x1F);
-	int tail = instruction & 0x3ff;
-        /* R4000 Users Manual (second edition) lists the following CP0
-           instructions:
-	                                                           CODE><-RT><RD-><--TAIL--->
-	   DMFC0   Doubleword Move From CP0        (VR4100 = 01000000001tttttddddd00000000000)
-	   DMTC0   Doubleword Move To CP0          (VR4100 = 01000000101tttttddddd00000000000)
-	   MFC0    word Move From CP0              (VR4100 = 01000000000tttttddddd00000000000)
-	   MTC0    word Move To CP0                (VR4100 = 01000000100tttttddddd00000000000)
-	   TLBR    Read Indexed TLB Entry          (VR4100 = 01000010000000000000000000000001)
-	   TLBWI   Write Indexed TLB Entry         (VR4100 = 01000010000000000000000000000010)
-	   TLBWR   Write Random TLB Entry          (VR4100 = 01000010000000000000000000000110)
-	   TLBP    Probe TLB for Matching Entry    (VR4100 = 01000010000000000000000000001000)
-	   CACHE   Cache operation                 (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
-	   ERET    Exception return                (VR4100 = 01000010000000000000000000011000)
-	   */
-        if (((code == 0x00) || (code == 0x04)      /* MFC0  /  MTC0  */        
-	     || (code == 0x01) || (code == 0x05))  /* DMFC0 / DMTC0  */        
-	    && tail == 0)
-	  {
-	    /* Clear double/single coprocessor move bit. */
-	    code &= ~1;
-
-	    /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
-	    
-	    switch (rd)  /* NOTEs: Standard CP0 registers */
-	      {
-		/* 0 = Index               R4000   VR4100  VR4300 */
-		/* 1 = Random              R4000   VR4100  VR4300 */
-		/* 2 = EntryLo0            R4000   VR4100  VR4300 */
-		/* 3 = EntryLo1            R4000   VR4100  VR4300 */
-		/* 4 = Context             R4000   VR4100  VR4300 */
-		/* 5 = PageMask            R4000   VR4100  VR4300 */
-		/* 6 = Wired               R4000   VR4100  VR4300 */
-		/* 8 = BadVAddr            R4000   VR4100  VR4300 */
-		/* 9 = Count               R4000   VR4100  VR4300 */
-		/* 10 = EntryHi            R4000   VR4100  VR4300 */
-		/* 11 = Compare            R4000   VR4100  VR4300 */
-		/* 12 = SR                 R4000   VR4100  VR4300 */
-#ifdef SUBTARGET_R3900
-	      case 3:
-		/* 3 = Config              R3900                  */
-	      case 7:
-		/* 7 = Cache               R3900                  */
-	      case 15:
-		/* 15 = PRID               R3900                  */
-
-		/* ignore */
-		break;
-
-	      case 8:
-		/* 8 = BadVAddr            R4000   VR4100  VR4300 */
-		if (code == 0x00)
-		  GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
-		else
-		  COP0_BADVADDR = GPR[rt];
-		break;
-
-#endif /* SUBTARGET_R3900 */
-	      case 12:
-		if (code == 0x00)
-		  GPR[rt] = SR;
-		else
-		  SR = GPR[rt];
-		break;
-		/* 13 = Cause              R4000   VR4100  VR4300 */
-	      case 13:
-		if (code == 0x00)
-		  GPR[rt] = CAUSE;
-		else
-		  CAUSE = GPR[rt];
-		break;
-		/* 14 = EPC                R4000   VR4100  VR4300 */
-	      case 14:
-		if (code == 0x00)
-		  GPR[rt] = (signed_word) (signed_address) EPC;
-		else
-		  EPC = GPR[rt];
-		break;
-		/* 15 = PRId               R4000   VR4100  VR4300 */
-#ifdef SUBTARGET_R3900
-                /* 16 = Debug */
-              case 16:
-                if (code == 0x00)
-                  GPR[rt] = Debug;
-                else
-                  Debug = GPR[rt];
-                break;
-#else
-		/* 16 = Config             R4000   VR4100  VR4300 */
-              case 16:
-                if (code == 0x00)
-                  GPR[rt] = C0_CONFIG;
-                else
-                  C0_CONFIG = GPR[rt];
-                break;
-#endif
-#ifdef SUBTARGET_R3900
-                /* 17 = Debug */
-              case 17:
-                if (code == 0x00)
-                  GPR[rt] = DEPC;
-                else
-                  DEPC = GPR[rt];
-                break;
-#else
-		/* 17 = LLAddr             R4000   VR4100  VR4300 */
-#endif
-		/* 18 = WatchLo            R4000   VR4100  VR4300 */
-		/* 19 = WatchHi            R4000   VR4100  VR4300 */
-		/* 20 = XContext           R4000   VR4100  VR4300 */
-		/* 26 = PErr or ECC        R4000   VR4100  VR4300 */
-		/* 27 = CacheErr           R4000   VR4100 */
-		/* 28 = TagLo              R4000   VR4100  VR4300 */
-		/* 29 = TagHi              R4000   VR4100  VR4300 */
-		/* 30 = ErrorEPC           R4000   VR4100  VR4300 */
-		if (STATE_VERBOSE_P(SD))
-		  sim_io_eprintf (SD, 
-				  "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
-				  (unsigned long)cia);
-		GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
-		/* CPR[0,rd] = GPR[rt]; */
-	      default:
-		if (code == 0x00)
-		  GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
-		else
-		  COP0_GPR[rd] = GPR[rt];
-#if 0
-		if (code == 0x00)
-		  sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
-		else
-		  sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
-#endif
-	      }
-	  }
-	else if (code == 0x10 && (tail & 0x3f) == 0x18)
-	  {
-	    /* ERET */
-	    if (SR & status_ERL)
-	      {
-		/* Oops, not yet available */
-		sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
-		PC = EPC;
-		SR &= ~status_ERL;
-	      }
-	    else
-	      {
-		PC = EPC;
-		SR &= ~status_EXL;
-	      }
-	  }
-        else if (code == 0x10 && (tail & 0x3f) == 0x10)
-          {
-            /* RFE */
-#ifdef SUBTARGET_R3900
-	    /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
-
-	    /* shift IE/KU history bits right */
-	    SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
-
-	    /* TODO: CACHE register */
-#endif /* SUBTARGET_R3900 */
-          }
-        else if (code == 0x10 && (tail & 0x3f) == 0x1F)
-          {
-            /* DERET */
-            Debug &= ~Debug_DM;
-            DELAYSLOT();
-            DSPC = DEPC;
-          }
-	else
-	  sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
-        /* TODO: When executing an ERET or RFE instruction we should
-           clear LLBIT, to ensure that any out-standing atomic
-           read/modify/write sequence fails. */
-      }
-    break;
-    
-    case 2: /* co-processor 2 */
-      {
-	int handle = 0;
-
-
-	if(! handle)
-	  {
-	    sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
-			   instruction,pr_addr(cia));
-	  }
-      }
-    break;
-    
-    case 1: /* should not occur (FPU co-processor) */
-    case 3: /* should not occur (FPU co-processor) */
-      SignalException(ReservedInstruction,instruction);
-      break;
-    }
-  
-  return;
-}
-
-
-/* This code copied from gdb's utils.c.  Would like to share this code,
-   but don't know of a common place where both could get to it. */
-
-/* Temporary storage using circular buffer */
-#define NUMCELLS 16
-#define CELLSIZE 32
-static char*
-get_cell (void)
-{
-  static char buf[NUMCELLS][CELLSIZE];
-  static int cell=0;
-  if (++cell>=NUMCELLS) cell=0;
-  return buf[cell];
-}     
-
-/* Print routines to handle variable size regs, etc */
-
-/* Eliminate warning from compiler on 32-bit systems */
-static int thirty_two = 32;	
-
-char* 
-pr_addr(addr)
-  SIM_ADDR addr;
-{
-  char *paddr_str=get_cell();
-  switch (sizeof(addr))
-    {
-      case 8:
-        sprintf(paddr_str,"%08lx%08lx",
-		(unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
-	break;
-      case 4:
-        sprintf(paddr_str,"%08lx",(unsigned long)addr);
-	break;
-      case 2:
-        sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
-	break;
-      default:
-        sprintf(paddr_str,"%x",addr);
-    }
-  return paddr_str;
-}
-
-char* 
-pr_uword64(addr)
-  uword64 addr;
-{
-  char *paddr_str=get_cell();
-  sprintf(paddr_str,"%08lx%08lx",
-          (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
-  return paddr_str;
-}
-
-
-void
-mips_core_signal (SIM_DESC sd,
-                 sim_cpu *cpu,
-                 sim_cia cia,
-                 unsigned map,
-                 int nr_bytes,
-                 address_word addr,
-                 transfer_type transfer,
-                 sim_core_signals sig)
-{
-  const char *copy = (transfer == read_transfer ? "read" : "write");
-  address_word ip = CIA_ADDR (cia);
-
-  switch (sig)
-    {
-    case sim_core_unmapped_signal:
-      sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
-                      nr_bytes, copy, 
-		      (unsigned long) addr, (unsigned long) ip);
-      COP0_BADVADDR = addr;
-      SignalExceptionDataReference();
-      break;
-
-    case sim_core_unaligned_signal:
-      sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
-                      nr_bytes, copy, 
-		      (unsigned long) addr, (unsigned long) ip);
-      COP0_BADVADDR = addr;
-      if(transfer == read_transfer) 
-	SignalExceptionAddressLoad();
-      else
-	SignalExceptionAddressStore();
-      break;
-
-    default:
-      sim_engine_abort (sd, cpu, cia,
-                        "mips_core_signal - internal error - bad switch");
-    }
-}
-
-
-void
-mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
-{
-  ASSERT(cpu != NULL);
-
-  if(cpu->exc_suspended > 0)
-    sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended); 
-
-  PC = cia;
-  memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
-  cpu->exc_suspended = 0;
-}
-
-void
-mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
-{
-  ASSERT(cpu != NULL);
-
-  if(cpu->exc_suspended > 0)
-    sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n", 
-		   cpu->exc_suspended, exception); 
-
-  memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
-  memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
-  cpu->exc_suspended = exception;
-}
-
-void
-mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
-{
-  ASSERT(cpu != NULL);
-
-  if(exception == 0 && cpu->exc_suspended > 0)
-    {
-      /* warn not for breakpoints */
-      if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
-	sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
-		       cpu->exc_suspended); 
-    }
-  else if(exception != 0 && cpu->exc_suspended > 0)
-    {
-      if(exception != cpu->exc_suspended) 
-	sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
-		       cpu->exc_suspended, exception); 
-      
-      memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers)); 
-    }
-  else if(exception != 0 && cpu->exc_suspended == 0)
-    {
-      sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); 
-    }
-  cpu->exc_suspended = 0; 
-}
-
-
-/*---------------------------------------------------------------------------*/
-/*> EOF interp.c <*/
diff --git a/sim/mips/m16.dc b/sim/mips/m16.dc
deleted file mode 100644
index 292587c..0000000
--- a/sim/mips/m16.dc
+++ /dev/null
@@ -1,25 +0,0 @@
-# most instructions
-# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
-# { : mask : value : word }
-
-# Top level - create a very big switch statement.
-
-  padded-switch,combine :  15 :  11 :    :    :    :      :             :
-
-  switch,combine        :  10 :   8 :    :    :    :      :             :
-
-  switch,combine        :   4 :   0 :    :    :    :      :             :
-
-  switch,combine        :   7 :   5 :    :    :    :      :             :
-
-
-# Extended instructions, decode the same way
-
-  padded-switch,combine :  15 :  11 :    :    :    :    1 :             :
-
-  switch,combine        :  10 :   8 :    :    :    :    1 :             :
-
-  switch,combine        :   4 :   0 :    :    :    :    1 :             :
-
-  switch,combine        :   7 :   5 :    :    :    :    1 :             :
-
diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen
deleted file mode 100644
index f87a863..0000000
--- a/sim/mips/m16.igen
+++ /dev/null
@@ -1,1236 +0,0 @@
-// -*- C -*-
-//
-//
-// MIPS Architecture:
-//
-//        CPU Instruction Set (mips16)
-//
-
-// The instructions in this section are ordered according
-// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
-
-
-// The MIPS16 codes registers in a special way, map from one to the other.
-// :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
-:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
-:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
-:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
-:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
-
-:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
-
-:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
-:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
-
-:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
-
-:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
-
-
-// Load and Store Instructions
-
-
-10000,3.RX,3.RY,5.IMMED:RRI:16::LB
-"lb r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
-"lb r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
-}
-
-
-
-10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
-"lbu r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
-"lbu r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
-}
-
-
-
-10001,3.RX,3.RY,5.IMMED:RRI:16::LH
-"lh r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
-"lh r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
-}
-
-
-
-10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
-"lhu r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
-"lhu r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
-}
-
-
-
-10011,3.RX,3.RY,5.IMMED:RRI:16::LW
-"lw r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
-"lw r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
-}
-
-
-
-10110,3.RX,8.IMMED:RI:16::LWPC
-"lw r<TRX>, <IMMED> (PC)"
-*mips16:
-*vr4100:
-{
-  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
-				basepc (SD_) & ~3, IMMED << 2));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
-"lw r<TRX>, <IMMEDIATE> (PC)"
-*mips16:
-*vr4100:
-{
-  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
-}
-
-
-
-10010,3.RX,8.IMMED:RI:16::LWSP
-"lw r<TRX>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
-"lw r<TRX>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
-}
-
-
-
-10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
-"lwu r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
-"lwu r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
-}
-
-
-
-00111,3.RX,3.RY,5.IMMED:RRI:16::LD
-"ld r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
-"ld r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
-}
-
-
-
-11111,100,3.RY,5.IMMED:RI64:16::LDPC
-"ld r<TRY>, <IMMED> (PC)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
-		      basepc (SD_) & ~7, IMMED << 3);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
-"ld r<TRY>, <IMMEDIATE> (PC)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
-}
-
-
-
-11111,000,3.RY,5.IMMED:RI64:16::LDSP
-"ld r<TRY>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
-"ld r<TRY>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
-}
-
-
-
-11000,3.RX,3.RY,5.IMMED:RRI:16::SB
-"sb r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
-"sb r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
-}
-
-
-
-11001,3.RX,3.RY,5.IMMED:RRI:16::SH
-"sh r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
-"sh r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
-}
-
-
-
-11011,3.RX,3.RY,5.IMMED:RRI:16::SW
-"sw r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
-"sw r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
-}
-
-
-
-11010,3.RX,8.IMMED:RI:16::SWSP
-"sw r<TRX>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
-"sw r<TRX>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
-}
-
-
-
-01100,010,8.IMMED:I8:16::SWRASP
-"sw r<RAIDX>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
-"sw r<RAIDX>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
-}
-
-
-
-01111,3.RX,3.RY,5.IMMED:RRI:16::SD
-"sd r<TRY>, <IMMED> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
-"sd r<TRY>, <IMMEDIATE> (r<TRX>)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
-}
-
-
-
-11111,001,3.RY,5.IMMED:RI64:16::SDSP
-"sd r<TRY>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
-"sd r<TRY>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
-}
-
-
-
-11111,010,8.IMMED:I64:16::SDRASP
-"sd r<RAIDX>, <IMMED> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
-"sd r<RAIDX>, <IMMEDIATE> (SP)"
-*mips16:
-*vr4100:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
-}
-
-
-
-// ALU Immediate Instructions
-
-
-01101,3.RX,8.IMMED:RI:16::LI
-"li r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_ori (SD_, 0, TRX, IMMED);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
-"li r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_ori (SD_, 0, TRX, IMMEDIATE);
-}
-
-
-
-01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
-"addiu r<TRY>, r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
-}
-
-11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
-"addiu r<TRY>, r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
-}
-
-
-
-01001,3.RX,8.IMMED:RI:16::ADDIU8
-"addiu r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
-"addiu r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
-}
-
-
-
-01100,011,8.IMMED:I8:16::ADJSP
-"addiu SP, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
-"addiu SP, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
-}
-
-
-
-00001,3.RX,8.IMMED:RI:16::ADDIUPC
-"addiu r<TRX>, PC, <IMMED>"
-*mips16:
-*vr4100:
-{
-  unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
-  GPR[TRX] = EXTEND32 (temp);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
-"addiu r<TRX>, PC, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
-  GPR[TRX] = EXTEND32 (temp);
-}
-
-
-
-00000,3.RX,8.IMMED:RI:16::ADDIUSP
-"addiu r<TRX>, SP, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, SPIDX, TRX, IMMED << 2);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
-"addiu r<TRX>, SP, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
-}
-
-
-
-01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
-"daddiu r<TRY>, r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
-}
-
-11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
-"daddiu r<TRY>, r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
-}
-
-
-
-11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
-"daddiu r<TRY>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
-"daddiu r<TRY>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
-}
-
-
-
-11111,011,8.IMMED:I64:16::DADJSP
-"daddiu SP, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
-"daddiu SP, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
-}
-
-
-
-11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
-"daddiu r<TRY>, PC, <IMMED>"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
-"daddiu r<TRY>, PC, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
-}
-
-
-
-11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
-"daddiu r<TRY>, SP, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
-"daddiu r<TRY>, SP, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
-}
-
-
-
-01010,3.RX,8.IMMED:RI:16::SLTI
-"slti r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_slti (SD_, TRX, T8IDX, IMMED);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
-"slti r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_slti (SD_, TRX, T8IDX, IMMEDIATE);
-}
-
-
-
-01011,3.RX,8.IMMED:RI:16::SLTIU
-"sltiu r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_sltiu (SD_, TRX, T8IDX, IMMED);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
-"sltiu r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
-}
-
-
-
-11101,3.RX,3.RY,01010:RR:16::CMP
-"cmp r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_xor (SD_, TRX, TRY, T8IDX);
-}
-
-
-01110,3.RX,8.IMMED:RI:16::CMPI
-"cmpi r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  do_xori (SD_, TRX, T8IDX, IMMED);
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
-"sltiu r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  do_xori (SD_, TRX, T8IDX, IMMEDIATE);
-}
-
-
-
-// Two/Three Operand, Register-Type
-
-
-
-11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
-"addu r<TRZ>, r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_addu (SD_, TRX, TRY, TRZ);
-}
-
-
-
-11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
-"subu r<TRZ>, r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_subu (SD_, TRX, TRY, TRZ);
-}
-
-11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
-"daddu r<TRZ>, r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_daddu (SD_, TRX, TRY, TRZ);
-}
-
-
-
-11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
-"dsubu r<TRZ>, r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_dsubu (SD_, TRX, TRY, TRZ);
-}
-
-
-
-11101,3.RX,3.RY,00010:RR:16::SLT
-"slt r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_slt (SD_, TRX, TRY, T8IDX);
-}
-
-
-
-11101,3.RX,3.RY,00011:RR:16::SLTU
-"sltu r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_sltu (SD_, TRX, TRY, T8IDX);
-}
-
-
-
-11101,3.RX,3.RY,01011:RR:16::NEG
-"neg r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_subu (SD_, 0, TRY, TRX);
-}
-
-
-
-11101,3.RX,3.RY,01100:RR:16::AND
-"and r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_and (SD_, TRX, TRY, TRX);
-}
-
-
-
-11101,3.RX,3.RY,01101:RR:16::OR
-"or r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_or (SD_, TRX, TRY, TRX);
-}
-
-
-
-11101,3.RX,3.RY,01110:RR:16::XOR
-"xor r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_xor (SD_, TRX, TRY, TRX);
-}
-
-
-
-11101,3.RX,3.RY,01111:RR:16::NOT
-"not r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_nor (SD_, 0, TRY, TRX);
-}
-
-
-
-01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
-"move r<TRY>, r<R32>"
-*mips16:
-*vr4100:
-{
-  do_or (SD_, R32, 0, TRY);
-}
-
-
-
-01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
-"move r<R32>, r<TRZ>"
-*mips16:
-*vr4100:
-{
-  do_or (SD_, TRZ, 0, R32);
-}
-
-
-
-00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
-"sll r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_sll (SD_, TRY, TRX, SHIFT);
-}
-
-11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
-"sll r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_sll (SD_, TRY, TRX, SHAMT);
-}
-
-
-
-00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
-"srl r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_srl (SD_, TRY, TRX, SHIFT);
-}
-
-11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
-"srl r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_srl (SD_, TRY, TRX, SHAMT);
-}
-
-
-
-00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
-"sra r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_sra (SD_, TRY, TRX, SHIFT);
-}
-
-11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
-"sra r<TRX>, r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_sra (SD_, TRY, TRX, SHAMT);
-}
-
-
-
-11101,3.RX,3.RY,00100:RR:16::SLLV
-"sllv r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_sllv (SD_, TRX, TRY, TRY);
-}
-
-
-11101,3.RX,3.RY,00110:RR:16::SRLV
-"srlv r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_srlv (SD_, TRX, TRY, TRY);
-}
-
-
-11101,3.RX,3.RY,00111:RR:16::SRAV
-"srav r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_srav (SD_, TRX, TRY, TRY);
-}
-
-
-00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
-"dsll r<TRY>, r<TRX>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_dsll (SD_, TRY, TRX, SHIFT);
-}
-  
-11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
-"dsll r<TRY>, r<TRX>, <SHAMT>"
-*mips16:
-*vr4100:
-{
-  do_dsll (SD_, TRY, TRX, SHAMT);
-}
-  
-  
-  
-11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
-"dsrl r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_dsrl (SD_, TRY, TRY, SHIFT);
-}
-
-11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
-"dsrl r<TRY>, <SHAMT>"
-*mips16:
-*vr4100:
-{
-  do_dsrl (SD_, TRY, TRY, SHAMT);
-}
-
-
-
-11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
-"dsra r<TRY>, <SHIFT>"
-*mips16:
-*vr4100:
-{
-  do_dsra (SD_, TRY, TRY, SHIFT);
-}
-
-11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
-"dsra r<TRY>, <SHAMT>"
-*mips16:
-*vr4100:
-{
-  do_dsra (SD_, TRY, TRY, SHAMT);
-}
-
-
-
-11101,3.RX,3.RY,10100:RR:16::DSLLV
-"dsllv r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_dsllv (SD_, TRX, TRY, TRY);
-}
-
-
-11101,3.RX,3.RY,10110:RR:16::DSRLV
-"dsrlv r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_dsrlv (SD_, TRX, TRY, TRY);
-}
-
-
-11101,3.RX,3.RY,10111:RR:16::DSRAV
-"dsrav r<TRY>, r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_dsrav (SD_, TRX, TRY, TRY);
-}
-
-
-// Multiply /Divide Instructions
-
-
-11101,3.RX,3.RY,11000:RR:16::MULT
-"mult r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_mult (SD_, TRX, TRY, 0);
-}
-
-
-11101,3.RX,3.RY,11001:RR:16::MULTU
-"multu r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_multu (SD_, TRX, TRY, 0);
-}
-
-
-11101,3.RX,3.RY,11010:RR:16::DIV
-"div r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_div (SD_, TRX, TRY);
-}
-
-
-11101,3.RX,3.RY,11011:RR:16::DIVU
-"divu r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_divu (SD_, TRX, TRY);
-}
-
-
-11101,3.RX,000,10000:RR:16::MFHI
-"mfhi r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_mfhi (SD_, TRX);
-}
-
-
-11101,3.RX,000,10010:RR:16::MFLO
-"mflo r<TRX>"
-*mips16:
-*vr4100:
-{
-  do_mflo (SD_, TRX);
-}
-
-
-11101,3.RX,3.RY,11100:RR:16::DMULT
-"dmult r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_dmult (SD_, TRX, TRY, 0);
-}
-
-
-11101,3.RX,3.RY,11101:RR:16::DMULTU
-"dmultu r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_dmultu (SD_, TRX, TRY, 0);
-}
-
-
-11101,3.RX,3.RY,11110:RR:16::DDIV
-"ddiv r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_ddiv (SD_, TRX, TRY);
-}
-
-
-11101,3.RX,3.RY,11111:RR:16::DDIVU
-"ddivu r<TRX>, r<TRY>"
-*mips16:
-*vr4100:
-{
-  do_ddivu (SD_, TRX, TRY);
-}
-
-
-// Jump and Branch Instructions
-
-
-
-// Issue instruction in delay slot of branch
-:function:::address_word:delayslot16:address_word nia, address_word target
-{
-  instruction_word delay_insn;
-  sim_events_slip (SD, 1);
-  DSPC = CIA; /* save current PC somewhere */
-  STATE |= simDELAYSLOT;
-  delay_insn = IMEM16 (nia); /* NOTE: mips16 */
-  idecode_issue (CPU_, delay_insn, (nia));
-  STATE &= ~simDELAYSLOT;
-  return target;
-}
-  
-// compute basepc dependant on us being in a delay slot
-:function:::address_word:basepc:
-{
-  if (STATE & simDELAYSLOT)
-    {
-      return DSPC; /* return saved address of preceeding jmp */
-    }
-  else
-    {
-      return CIA;
-    }
-}
-
-
-// JAL
-00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
-"jal <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  address_word region = (NIA & MASK (63, 28));
-  RA = NIA + 2; /* skip 16 bit delayslot insn */
-  NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
-}
-
-
-
-// JALX - 32 and 16 bit versions.
-
-011101,26.IMMED:JALX:32::JALX32
-"jalx <IMMED>"
-*mips16:
-*vr4100:
-{
-  address_word region = (NIA & MASK (63, 28));
-  RA = NIA + 4; /* skip 32 bit delayslot insn */
-  NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
-}
-
-00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
-"jalx <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  address_word region = (NIA & MASK (63, 28));
-  RA = NIA + 2; /* 16 bit INSN */
-  NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
-}
-
-
-
-11101,3.RX,000,00000:RR:16::JR
-"jr r<TRX>"
-*mips16:
-*vr4100:
-{
-  NIA = delayslot16 (SD_, NIA, GPR[TRX]);
-}
-
-
-11101,000,001,00000:RR:16::JRRA
-"jrra"
-*mips16:
-*vr4100:
-{
-  NIA = delayslot16 (SD_, NIA, RA);
-}
-
-
-
-11101,3.RX,010,00000:RR:16::JALR
-"jalr r<TRX>"
-*mips16:
-*vr4100:
-{
-  RA = NIA + 2;
-  NIA = delayslot16 (SD_, NIA, GPR[TRX]);
-}
-
-
-
-00100,3.RX,8.IMMED:RI:16::BEQZ
-"beqz r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  if (GPR[TRX] == 0)
-    NIA = (NIA + (EXTEND8 (IMMED) << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
-"beqz r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  if (GPR[TRX] == 0)
-    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
-}
-
-
-
-00101,3.RX,8.IMMED:RI:16::BNEZ
-"bnez r<TRX>, <IMMED>"
-*mips16:
-*vr4100:
-{
-  if (GPR[TRX] != 0)
-    NIA = (NIA + (EXTEND8 (IMMED) << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
-"bnez r<TRX>, <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  if (GPR[TRX] != 0)
-    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
-}
-
-
-
-01100,000,8.IMMED:I8:16::BTEQZ
-"bteqz <IMMED>"
-*mips16:
-*vr4100:
-{
-  if (T8 == 0)
-    NIA = (NIA + (EXTEND8 (IMMED) << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
-"bteqz <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  if (T8 == 0)
-    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
-}
-
-
-
-01100,001,8.IMMED:I8:16::BTNEZ
-"btnez <IMMED>"
-*mips16:
-*vr4100:
-{
-  if (T8 != 0)
-    NIA = (NIA + (EXTEND8 (IMMED) << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
-"btnez <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  if (T8 != 0)
-    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
-}
-
-
-
-00010,11.IMMED:I:16::B
-"b <IMMED>"
-*mips16:
-*vr4100:
-{
-  NIA = (NIA + (EXTEND11 (IMMED) << 1));
-}
-
-11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
-"b <IMMEDIATE>"
-*mips16:
-*vr4100:
-{
-  NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
-}
-
-
-
-11101,3.RX,3.RY,00101:RR:16::BREAK
-"break"
-*mips16:
-*vr4100:
-{
-  if (STATE & simDELAYSLOT)
-    PC = cia - 2; /* reference the branch instruction */
-  else
-    PC = cia;
-  SignalException (BreakPoint, instruction_0);
-}
diff --git a/sim/mips/m16e.igen b/sim/mips/m16e.igen
deleted file mode 100644
index 2d7a073..0000000
--- a/sim/mips/m16e.igen
+++ /dev/null
@@ -1,105 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the MIPS16e instructions.
-// Copyright (C) 2005 Free Software Foundation, Inc.
-// Contributed by Nigel Stephens (nigel@mips.com) and 
-//                David Ung (davidu@mips.com) of MIPS Technologies.
-//
-// This file is part of GDB, the GNU debugger.
-// 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-
-11101,3.RX,100,10001:RR:16::SEB
-"seb r<TRX>"
-*mips16e:
-{
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] = EXTEND8 (GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-
-11101,3.RX,101,10001:RR:16::SEH
-"seh r<TRX>"
-*mips16e:
-{
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] = EXTEND16 (GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-11101,3.RX,110,10001:RR:16::SEW
-"sew r<TRX>"
-*mips16e:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] = EXTEND32 (GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-11101,3.RX,000,10001:RR:16::ZEB
-"zeb r<TRX>"
-*mips16e:
-{
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] =  (unsigned_word)(unsigned8)(GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-11101,3.RX,001,10001:RR:16::ZEH
-"zeh r<TRX>"
-*mips16e:
-{
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] = (unsigned_word)(unsigned16)(GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-11101,3.RX,010,10001:RR:16::ZEW
-"zew r<TRX>"
-*mips16e:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT1 (GPR[TRX]);
-  GPR[TRX] = (unsigned_word)(unsigned32)(GPR[TRX]);
-  TRACE_ALU_RESULT (GPR[TRX]);
-}
-
-
-11101,3.RX,100,00000:RR:16::JRC
-"jrc r<TRX>"
-*mips16e:
-{
-  NIA = GPR[TRX];
-}
-
-
-11101,000,101,00000:RR:16::JRCRA
-"jrc ra"
-*mips16e:
-{
-  NIA = RA;
-}
-
-
-11101,3.RX,110,00000:RR:16::JALRC
-"jalrc r<TRX>"
-*mips16e:
-{
-  RA = NIA;
-  NIA = GPR[TRX];
-}
diff --git a/sim/mips/m16run.c b/sim/mips/m16run.c
deleted file mode 100644
index 8a5d607..0000000
--- a/sim/mips/m16run.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*  This file is part of the program psim.
-
-    Copyright (C) 1998, Andrew Cagney <cagney@highland.com.au>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
- 
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- 
-    */
-
-#include "sim-main.h"
-#include "m16_idecode.h"
-#include "m32_idecode.h"
-#include "bfd.h"
-
-
-#define SD sd
-#define CPU cpu
-
-void
-sim_engine_run (SIM_DESC sd,
-		int next_cpu_nr,
-		int nr_cpus, /* ignore */
-		int siggnal) /* ignore */
-{
-  sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr);
-  address_word cia = CIA_GET (cpu);
-
-  while (1)
-    {
-      address_word nia;
-
-#if defined (ENGINE_ISSUE_PREFIX_HOOK)
-      ENGINE_ISSUE_PREFIX_HOOK ();
-#endif
-
-      if ((cia & 1))
-	{
-	  m16_instruction_word instruction_0 = IMEM16 (cia);
-	  nia = m16_idecode_issue (sd, instruction_0, cia);
-	}
-      else
-	{
-	  m32_instruction_word instruction_0 = IMEM32 (cia);
-	  nia = m32_idecode_issue (sd, instruction_0, cia);
-	}
-
-#if defined (ENGINE_ISSUE_POSTFIX_HOOK)
-      ENGINE_ISSUE_POSTFIX_HOOK ();
-#endif
-
-      /* Update the instruction address */
-      cia = nia;
-
-      /* process any events */
-      if (sim_events_tick (sd))
-        {
-          CIA_SET (CPU, cia);
-          sim_events_process (sd);
-	  cia = CIA_GET (CPU);
-        }
-
-    }
-}
diff --git a/sim/mips/mdmx.c b/sim/mips/mdmx.c
deleted file mode 100644
index 3af59b0..0000000
--- a/sim/mips/mdmx.c
+++ /dev/null
@@ -1,1477 +0,0 @@
-/* Simulation code for the MIPS MDMX ASE.
-   Copyright (C) 2002 Free Software Foundation, Inc.
-   Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
-   Corporation (SiByte).
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include <stdio.h>
-
-#include "sim-main.h"
-
-/* Within mdmx.c we refer to the sim_cpu directly. */
-#define CPU cpu
-#define SD  (CPU_STATE(CPU))
-
-/* XXX FIXME: temporary hack while the impact of making unpredictable()
-   a "normal" (non-igen) function is evaluated.  */
-#undef Unpredictable
-#define Unpredictable() unpredictable_action (cpu, cia)
-
-/* MDMX Representations
-
-   An 8-bit packed byte element (OB) is always unsigned.
-   The 24-bit accumulators are signed and are represented as 32-bit
-   signed values, which are reduced to 24-bit signed values prior to
-   Round and Clamp operations.
-  
-   A 16-bit packed halfword element (QH) is always signed.
-   The 48-bit accumulators are signed and are represented as 64-bit
-   signed values, which are reduced to 48-bit signed values prior to
-   Round and Clamp operations.
-  
-   The code below assumes a 2's-complement representation of signed
-   quantities.  Care is required to clear extended sign bits when
-   repacking fields.
-  
-   The code (and the code for arithmetic shifts in mips.igen) also makes
-   the (not guaranteed portable) assumption that right shifts of signed
-   quantities in C do sign extension.  */
-
-typedef unsigned64 unsigned48;
-#define MASK48 (UNSIGNED64 (0xffffffffffff))
-
-typedef unsigned32 unsigned24;
-#define MASK24 (UNSIGNED32 (0xffffff))
-
-typedef enum {
-  mdmx_ob,          /* OB (octal byte) */
-  mdmx_qh           /* QH (quad half-word) */
-} MX_fmt;
-
-typedef enum {
-  sel_elem,         /* element select */
-  sel_vect,         /* vector select */
-  sel_imm           /* immediate select */
-} VT_select;
-
-#define OB_MAX  ((unsigned8)0xFF)
-#define QH_MIN  ((signed16)0x8000)
-#define QH_MAX  ((signed16)0x7FFF)
-
-#define OB_CLAMP(x)  ((unsigned8)((x) > OB_MAX ? OB_MAX : (x)))
-#define QH_CLAMP(x)  ((signed16)((x) < QH_MIN ? QH_MIN : \
-                                ((x) > QH_MAX ? QH_MAX : (x))))
-
-#define MX_FMT(fmtsel) (((fmtsel) & 0x1) == 0 ? mdmx_ob : mdmx_qh)
-#define MX_VT(fmtsel)  (((fmtsel) & 0x10) == 0 ?    sel_elem : \
-                       (((fmtsel) & 0x18) == 0x10 ? sel_vect : sel_imm))
-
-#define QH_ELEM(v,fmtsel) \
-        ((signed16)(((v) >> (((fmtsel) & 0xC) << 2)) & 0xFFFF))
-#define OB_ELEM(v,fmtsel) \
-        ((unsigned8)(((v) >> (((fmtsel) & 0xE) << 2)) & 0xFF))
-
-
-typedef signed16 (*QH_FUNC)(signed16, signed16);
-typedef unsigned8 (*OB_FUNC)(unsigned8, unsigned8);
-
-/* vectorized logical operators */
-
-static signed16
-AndQH(signed16 ts, signed16 tt)
-{
-  return (signed16)((unsigned16)ts & (unsigned16)tt);
-}
-
-static unsigned8
-AndOB(unsigned8 ts, unsigned8 tt)
-{
-  return ts & tt;
-}
-
-static signed16
-NorQH(signed16 ts, signed16 tt)
-{
-  return (signed16)(((unsigned16)ts | (unsigned16)tt) ^ 0xFFFF);
-}
-
-static unsigned8
-NorOB(unsigned8 ts, unsigned8 tt)
-{
-  return (ts | tt) ^ 0xFF;
-}
-
-static signed16
-OrQH(signed16 ts, signed16 tt)
-{
-  return (signed16)((unsigned16)ts | (unsigned16)tt);
-}
-
-static unsigned8
-OrOB(unsigned8 ts, unsigned8 tt)
-{
-  return ts | tt;
-}
-
-static signed16
-XorQH(signed16 ts, signed16 tt)
-{
-  return (signed16)((unsigned16)ts ^ (unsigned16)tt);
-}
-
-static unsigned8
-XorOB(unsigned8 ts, unsigned8 tt)
-{
-  return ts ^ tt;
-}
-
-static signed16
-SLLQH(signed16 ts, signed16 tt)
-{
-  unsigned32 s = (unsigned32)tt & 0xF;
-  return (signed16)(((unsigned32)ts << s) & 0xFFFF);
-}
-
-static unsigned8
-SLLOB(unsigned8 ts, unsigned8 tt)
-{
-  unsigned32 s = tt & 0x7;
-  return (ts << s) & 0xFF;
-}
-
-static signed16
-SRLQH(signed16 ts, signed16 tt)
-{
-  unsigned32 s = (unsigned32)tt & 0xF;
-  return (signed16)((unsigned16)ts >> s);
-}
-
-static unsigned8
-SRLOB(unsigned8 ts, unsigned8 tt)
-{
-  unsigned32 s = tt & 0x7;
-  return ts >> s;
-}
-
-
-/* Vectorized arithmetic operators.  */
-
-static signed16
-AddQH(signed16 ts, signed16 tt)
-{
-  signed32 t = (signed32)ts + (signed32)tt;
-  return QH_CLAMP(t);
-}
-
-static unsigned8
-AddOB(unsigned8 ts, unsigned8 tt)
-{
-  unsigned32 t = (unsigned32)ts + (unsigned32)tt;
-  return OB_CLAMP(t);
-}
-
-static signed16
-SubQH(signed16 ts, signed16 tt)
-{
-  signed32 t = (signed32)ts - (signed32)tt;
-  return QH_CLAMP(t);
-}
-
-static unsigned8
-SubOB(unsigned8 ts, unsigned8 tt)
-{
-  signed32 t;
-  t = (signed32)ts - (signed32)tt;
-  if (t < 0)
-    t = 0;
-  return (unsigned8)t;
-}
-
-static signed16
-MinQH(signed16 ts, signed16 tt)
-{
-  return (ts < tt ? ts : tt);
-}
-
-static unsigned8
-MinOB(unsigned8 ts, unsigned8 tt)
-{
-  return (ts < tt ? ts : tt);
-}
-
-static signed16
-MaxQH(signed16 ts, signed16 tt)
-{
-  return (ts > tt ? ts : tt);
-}
-
-static unsigned8
-MaxOB(unsigned8 ts, unsigned8 tt)
-{
-  return (ts > tt ? ts : tt);
-}
-
-static signed16
-MulQH(signed16 ts, signed16 tt)
-{
-  signed32 t = (signed32)ts * (signed32)tt;
-  return QH_CLAMP(t);
-}
-
-static unsigned8
-MulOB(unsigned8 ts, unsigned8 tt)
-{
-  unsigned32 t = (unsigned32)ts * (unsigned32)tt;
-  return OB_CLAMP(t);
-}
-
-/* "msgn" and "sra" are defined only for QH format.  */
-
-static signed16
-MsgnQH(signed16 ts, signed16 tt)
-{
-  signed16 t;
-  if (ts < 0)
-    t = (tt == QH_MIN ? QH_MAX : -tt);
-  else if (ts == 0)
-    t = 0;
-  else
-    t = tt;
-  return t;
-}
-
-static signed16
-SRAQH(signed16 ts, signed16 tt)
-{
-  unsigned32 s = (unsigned32)tt & 0xF;
-  return (signed16)((signed32)ts >> s);
-}
-
-
-/* "pabsdiff" and "pavg" are defined only for OB format.  */
-
-static unsigned8
-AbsDiffOB(unsigned8 ts, unsigned8 tt)
-{
-  return (ts >= tt ? ts - tt : tt - ts);
-}
-
-static unsigned8
-AvgOB(unsigned8 ts, unsigned8 tt)
-{
-  return ((unsigned32)ts + (unsigned32)tt + 1) >> 1;
-}
-
-
-/* Dispatch tables for operations that update a CPR.  */
-
-static const QH_FUNC qh_func[] = {
-  AndQH,  NorQH,  OrQH,   XorQH, SLLQH, SRLQH,
-  AddQH,  SubQH,  MinQH,  MaxQH,
-  MulQH,  MsgnQH, SRAQH,  NULL,  NULL
-};
-
-static const OB_FUNC ob_func[] = {
-  AndOB,  NorOB,  OrOB,   XorOB, SLLOB, SRLOB,
-  AddOB,  SubOB,  MinOB,  MaxOB,
-  MulOB,  NULL,   NULL,   AbsDiffOB, AvgOB
-};
-
-/* Auxiliary functions for CPR updates.  */
-
-/* Vector mapping for QH format.  */
-static unsigned64
-qh_vector_op(unsigned64 v1, unsigned64 v2, QH_FUNC func)
-{
-  unsigned64 result = 0;
-  int  i;
-  signed16 h, h1, h2;
-
-  for (i = 0; i < 64; i += 16)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      h2 = (signed16)(v2 & 0xFFFF);  v2 >>= 16;
-      h = (*func)(h1, h2);
-      result |= ((unsigned64)((unsigned16)h) << i);
-    }
-  return result;
-}
-
-static unsigned64
-qh_map_op(unsigned64 v1, signed16 h2, QH_FUNC func)
-{
-  unsigned64 result = 0;
-  int  i;
-  signed16 h, h1;
-
-  for (i = 0; i < 64; i += 16)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      h = (*func)(h1, h2);
-      result |= ((unsigned64)((unsigned16)h) << i);
-    }
-  return result;
-}
-
-
-/* Vector operations for OB format.  */
-
-static unsigned64
-ob_vector_op(unsigned64 v1, unsigned64 v2, OB_FUNC func)
-{
-  unsigned64 result = 0;
-  int  i;
-  unsigned8 b, b1, b2;
-
-  for (i = 0; i < 64; i += 8)
-    {
-      b1 = v1 & 0xFF;  v1 >>= 8;
-      b2 = v2 & 0xFF;  v2 >>= 8;
-      b = (*func)(b1, b2);
-      result |= ((unsigned64)b << i);
-    }
-  return result;
-}
-
-static unsigned64
-ob_map_op(unsigned64 v1, unsigned8 b2, OB_FUNC func)
-{
-  unsigned64 result = 0;
-  int  i;
-  unsigned8 b, b1;
-
-  for (i = 0; i < 64; i += 8)
-    {
-      b1 = v1 & 0xFF;  v1 >>= 8;
-      b = (*func)(b1, b2);
-      result |= ((unsigned64)b << i);
-    }
-  return result;
-}
-
-
-/* Primary entry for operations that update CPRs.  */
-unsigned64
-mdmx_cpr_op(sim_cpu *cpu,
-	    address_word cia,
-	    int op,
-	    unsigned64 op1,
-	    int vt,
-	    MX_fmtsel fmtsel) 
-{
-  unsigned64 op2;
-  unsigned64 result = 0;
-
-  switch (MX_FMT (fmtsel))
-    {
-    case mdmx_qh:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = qh_map_op(op1, QH_ELEM(op2, fmtsel), qh_func[op]);
-	  break;
-	case sel_vect:
-	  result = qh_vector_op(op1, ValueFPR(vt, fmt_mdmx), qh_func[op]);
-	  break;
-	case sel_imm:
-	  result = qh_map_op(op1, vt, qh_func[op]);
-	  break;
-	}
-      break;
-    case mdmx_ob:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = ob_map_op(op1, OB_ELEM(op2, fmtsel), ob_func[op]);
-	  break;
-	case sel_vect:
-	  result = ob_vector_op(op1, ValueFPR(vt, fmt_mdmx), ob_func[op]);
-	  break;
-	case sel_imm:
-	  result = ob_map_op(op1, vt, ob_func[op]);
-	  break;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-
-  return result;
-}
-
-
-/* Operations that update CCs */
-
-static void
-qh_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
-{
-  int  i;
-  signed16 h1, h2;
-  int  boolean;
-
-  for (i = 0; i < 4; i++)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      h2 = (signed16)(v2 & 0xFFFF);  v2 >>= 16;
-      boolean = ((cond & MX_C_EQ) && (h1 == h2)) ||
-	((cond & MX_C_LT) && (h1 < h2));
-      SETFCC(i, boolean);
-    }
-}
-
-static void
-qh_map_test(sim_cpu *cpu, unsigned64 v1, signed16 h2, int cond)
-{
-  int  i;
-  signed16 h1;
-  int  boolean;
-
-  for (i = 0; i < 4; i++)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      boolean = ((cond & MX_C_EQ) && (h1 == h2)) ||
-	((cond & MX_C_LT) && (h1 < h2));
-      SETFCC(i, boolean);
-    }
-}
-
-static void
-ob_vector_test(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int cond)
-{
-  int  i;
-  unsigned8 b1, b2;
-  int  boolean;
-
-  for (i = 0; i < 8; i++)
-    {
-      b1 = v1 & 0xFF;  v1 >>= 8;
-      b2 = v2 & 0xFF;  v2 >>= 8;
-      boolean = ((cond & MX_C_EQ) && (b1 == b2)) ||
-	((cond & MX_C_LT) && (b1 < b2));
-      SETFCC(i, boolean);
-    }
-}
-
-static void
-ob_map_test(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int cond)
-{
-  int  i;
-  unsigned8 b1;
-  int  boolean;
-
-  for (i = 0; i < 8; i++)
-    {
-      b1 = (unsigned8)(v1 & 0xFF);  v1 >>= 8;
-      boolean = ((cond & MX_C_EQ) && (b1 == b2)) ||
-	((cond & MX_C_LT) && (b1 < b2));
-      SETFCC(i, boolean);
-    }
-}
-
-
-void
-mdmx_cc_op(sim_cpu *cpu,
-	   address_word cia,
-	   int cond,
-	   unsigned64 v1,
-	   int vt,
-	   MX_fmtsel fmtsel)
-{
-  unsigned64 op2;
-
-  switch (MX_FMT (fmtsel))
-    {
-    case mdmx_qh:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  qh_map_test(cpu, v1, QH_ELEM(op2, fmtsel), cond);
-	  break;
-	case sel_vect:
-	  qh_vector_test(cpu, v1, ValueFPR(vt, fmt_mdmx), cond);
-	  break;
-	case sel_imm:
-	  qh_map_test(cpu, v1, vt, cond);
-	  break;
-	}
-      break;
-    case mdmx_ob:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  ob_map_test(cpu, v1, OB_ELEM(op2, fmtsel), cond);
-	  break;
-	case sel_vect:
-	  ob_vector_test(cpu, v1, ValueFPR(vt, fmt_mdmx), cond);
-	  break;
-	case sel_imm:
-	  ob_map_test(cpu, v1, vt, cond);
-	  break;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-}
-
-
-/* Pick operations.  */
-
-static unsigned64
-qh_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned16 h;
-
-  s = 0;
-  for (i = 0; i < 4; i++)
-    {
-      h = ((GETFCC(i) == tf) ? (v1 & 0xFFFF) : (v2 & 0xFFFF));
-      v1 >>= 16;  v2 >>= 16;
-      result |= ((unsigned64)h << s);
-      s += 16;
-    }
-  return result;
-}
-
-static unsigned64
-qh_map_pick(sim_cpu *cpu, unsigned64 v1, signed16 h2, int tf)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned16 h;
-
-  s = 0;
-  for (i = 0; i < 4; i++)
-    {
-      h = (GETFCC(i) == tf) ? (v1 & 0xFFFF) : (unsigned16)h2;
-      v1 >>= 16;
-      result |= ((unsigned64)h << s);
-      s += 16;
-    }
-  return result;
-}
-
-static unsigned64
-ob_vector_pick(sim_cpu *cpu, unsigned64 v1, unsigned64 v2, int tf)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned8 b;
-
-  s = 0;
-  for (i = 0; i < 8; i++)
-    {
-      b = (GETFCC(i) == tf) ? (v1 & 0xFF) : (v2 & 0xFF);
-      v1 >>= 8;  v2 >>= 8;
-      result |= ((unsigned64)b << s);
-      s += 8;
-    }
-  return result;
-}
-
-static unsigned64
-ob_map_pick(sim_cpu *cpu, unsigned64 v1, unsigned8 b2, int tf)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned8 b;
-
-  s = 0;
-  for (i = 0; i < 8; i++)
-    {
-      b = (GETFCC(i) == tf) ? (v1 & 0xFF) : b2;
-      v1 >>= 8;
-      result |= ((unsigned64)b << s);
-      s += 8;
-    }
-  return result;
-}
-
-
-unsigned64
-mdmx_pick_op(sim_cpu *cpu,
-	     address_word cia,
-	     int tf,
-	     unsigned64 v1,
-	     int vt,
-	     MX_fmtsel fmtsel)
-{
-  unsigned64 result = 0;
-  unsigned64 op2;
-
-  switch (MX_FMT (fmtsel))
-    {
-    case mdmx_qh:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = qh_map_pick(cpu, v1, QH_ELEM(op2, fmtsel), tf);
-	  break;
-	case sel_vect:
-	  result = qh_vector_pick(cpu, v1, ValueFPR(vt, fmt_mdmx), tf);
-	  break;
-	case sel_imm:
-	  result = qh_map_pick(cpu, v1, vt, tf);
-	  break;
-	}
-      break;
-    case mdmx_ob:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = ob_map_pick(cpu, v1, OB_ELEM(op2, fmtsel), tf);
-	  break;
-	case sel_vect:
-	  result = ob_vector_pick(cpu, v1, ValueFPR(vt, fmt_mdmx), tf);
-	  break;
-	case sel_imm:
-	  result = ob_map_pick(cpu, v1, vt, tf);
-	  break;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-  return result;
-}
-
-
-/* Accumulators.  */
-
-typedef void (*QH_ACC)(signed48 *a, signed16 ts, signed16 tt);
-
-static void
-AccAddAQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a += (signed48)ts + (signed48)tt;
-}
-
-static void
-AccAddLQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a = (signed48)ts + (signed48)tt;
-}
-
-static void
-AccMulAQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a += (signed48)ts * (signed48)tt;
-}
-
-static void
-AccMulLQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a = (signed48)ts * (signed48)tt;
-}
-
-static void
-SubMulAQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a -= (signed48)ts * (signed48)tt;
-}
-
-static void
-SubMulLQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a = -((signed48)ts * (signed48)tt);
-}
-
-static void
-AccSubAQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a += (signed48)ts - (signed48)tt;
-}
-
-static void
-AccSubLQH(signed48 *a, signed16 ts, signed16 tt)
-{
-  *a =  (signed48)ts - (signed48)tt;
-}
-
-
-typedef void (*OB_ACC)(signed24 *acc, unsigned8 ts, unsigned8 tt);
-
-static void
-AccAddAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a += (signed24)ts + (signed24)tt;
-}
-
-static void
-AccAddLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a = (signed24)ts + (signed24)tt;
-}
-
-static void
-AccMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a += (signed24)ts * (signed24)tt;
-}
-
-static void
-AccMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a = (signed24)ts * (signed24)tt;
-}
-
-static void
-SubMulAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a -= (signed24)ts * (signed24)tt;
-}
-
-static void
-SubMulLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a = -((signed24)ts * (signed24)tt);
-}
-
-static void
-AccSubAOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a += (signed24)ts - (signed24)tt;
-}
-
-static void
-AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  *a = (signed24)ts - (signed24)tt;
-}
-
-static void
-AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt)
-{
-  unsigned8 t = (ts >= tt ? ts - tt : tt - ts);
-  *a += (signed24)t;
-}
-
-
-/* Dispatch tables for operations that update a CPR.  */
-
-static const QH_ACC qh_acc[] = {
-  AccAddAQH, AccAddAQH, AccMulAQH, AccMulLQH,
-  SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH,
-  NULL
-};
-
-static const OB_ACC ob_acc[] = {
-  AccAddAOB, AccAddLOB, AccMulAOB, AccMulLOB,
-  SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB,
-  AccAbsDiffOB
-};
-
-
-static void
-qh_vector_acc(signed48 a[], unsigned64 v1, unsigned64 v2, QH_ACC acc)
-{
-  int  i;
-  signed16 h1, h2;
-
-  for (i = 0; i < 4; i++)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      h2 = (signed16)(v2 & 0xFFFF);  v2 >>= 16;
-      (*acc)(&a[i], h1, h2);
-    }
-}
-
-static void
-qh_map_acc(signed48 a[], unsigned64 v1, signed16 h2, QH_ACC acc)
-{
-  int  i;
-  signed16 h1;
-
-  for (i = 0; i < 4; i++)
-    {
-      h1 = (signed16)(v1 & 0xFFFF);  v1 >>= 16;
-      (*acc)(&a[i], h1, h2);
-    }
-}
-
-static void
-ob_vector_acc(signed24 a[], unsigned64 v1, unsigned64 v2, OB_ACC acc)
-{
-  int  i;
-  unsigned8  b1, b2;
-
-  for (i = 0; i < 8; i++)
-    {
-      b1 = v1 & 0xFF;  v1 >>= 8;
-      b2 = v2 & 0xFF;  v2 >>= 8;
-      (*acc)(&a[i], b1, b2);
-    }
-}
-
-static void
-ob_map_acc(signed24 a[], unsigned64 v1, unsigned8 b2, OB_ACC acc)
-{
-  int  i;
-  unsigned8 b1;
-
-  for (i = 0; i < 8; i++)
-    {
-      b1 = v1 & 0xFF;  v1 >>= 8;
-      (*acc)(&a[i], b1, b2);
-    }
-}
-
-
-/* Primary entry for operations that accumulate */
-void
-mdmx_acc_op(sim_cpu *cpu,
-	    address_word cia,
-	    int op,
-	    unsigned64 op1,
-	    int vt,
-	    MX_fmtsel fmtsel) 
-{
-  unsigned64 op2;
-
-  switch (MX_FMT (fmtsel))
-    {
-    case mdmx_qh:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  qh_map_acc(ACC.qh, op1, QH_ELEM(op2, fmtsel), qh_acc[op]);
-	  break;
-	case sel_vect:
-	  qh_vector_acc(ACC.qh, op1, ValueFPR(vt, fmt_mdmx), qh_acc[op]);
-	  break;
-	case sel_imm:
-	  qh_map_acc(ACC.qh, op1, vt, qh_acc[op]);
-	  break;
-	}
-      break;
-    case mdmx_ob:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  ob_map_acc(ACC.ob, op1, OB_ELEM(op2, fmtsel), ob_acc[op]);
-	  break;
-	case sel_vect:
-	  ob_vector_acc(ACC.ob, op1, ValueFPR(vt, fmt_mdmx), ob_acc[op]);
-	  break;
-	case sel_imm:
-	  ob_map_acc(ACC.ob, op1, vt, ob_acc[op]);
-	  break;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-}
-
-
-/* Reading and writing accumulator (no conversion).  */
-
-unsigned64
-mdmx_rac_op(sim_cpu *cpu,
-	    address_word cia,
-	    int op,
-	    int fmt) 
-{
-  unsigned64    result;
-  unsigned int  shift;
-  int           i;
-
-  shift = op;          /* L = 00, M = 01, H = 10.  */
-  result = 0;
-
-  switch (fmt)
-    {
-    case MX_FMT_QH:
-      shift <<= 4;              /* 16 bits per element.  */
-      for (i = 3; i >= 0; --i)
-	{
-	  result <<= 16;
-	  result |= ((ACC.qh[i] >> shift) & 0xFFFF);
-	}
-      break;
-    case MX_FMT_OB:
-      shift <<= 3;              /*  8 bits per element.  */
-      for (i = 7; i >= 0; --i)
-	{
-	  result <<= 8;
-	  result |= ((ACC.ob[i] >> shift) & 0xFF);
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-  return result;
-}
-
-void
-mdmx_wacl(sim_cpu *cpu,
-	  address_word cia,
-	  int fmt,
-	  unsigned64 vs,
-	  unsigned64 vt) 
-{
-  int           i;
-
-  switch (fmt)
-    {
-    case MX_FMT_QH:
-      for (i = 0; i < 4; i++)
-	{
-	  signed32  s = (signed16)(vs & 0xFFFF);
-	  ACC.qh[i] = ((signed48)s << 16) | (vt & 0xFFFF);
-	  vs >>= 16;  vt >>= 16;
-	}
-      break;
-    case MX_FMT_OB:
-      for (i = 0; i < 8; i++)
-	{
-	  signed16  s = (signed8)(vs & 0xFF);
-	  ACC.ob[i] = ((signed24)s << 8) | (vt & 0xFF);
-	  vs >>= 8;   vt >>= 8;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-}
-
-void
-mdmx_wach(sim_cpu *cpu,
-	  address_word cia,
-	  int fmt,
-	  unsigned64 vs)
-{
-  int           i;
-
-  switch (fmt)
-    {
-    case MX_FMT_QH:
-      for (i = 0; i < 4; i++)
-	{
-	  signed32  s = (signed16)(vs & 0xFFFF);
-	  ACC.qh[i] &= ~((signed48)0xFFFF << 32);
-	  ACC.qh[i] |=  ((signed48)s << 32);
-	  vs >>= 16;
-	}
-      break;
-    case MX_FMT_OB:
-      for (i = 0; i < 8; i++)
-	{
-	  ACC.ob[i] &= ~((signed24)0xFF << 16);
-	  ACC.ob[i] |=  ((signed24)(vs & 0xFF) << 16);
-	  vs >>= 8;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-}
-
-
-/* Reading and writing accumulator (rounding conversions).
-   Enumerating function guarantees s >= 0 for QH ops.  */
-
-typedef signed16 (*QH_ROUND)(signed48 a, signed16 s);
-
-#define QH_BIT(n)  ((unsigned48)1 << (n))
-#define QH_ONES(n) (((unsigned48)1 << (n))-1)
-
-static signed16
-RNASQH(signed48 a, signed16 s)
-{
-  signed48 t;
-  signed16 result = 0;
-
-  if (s > 48)
-    result = 0;
-  else
-    {
-      t = (a >> s);
-      if ((a & QH_BIT(47)) == 0)
-	{
-	  if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	    t++;
-	  if (t > QH_MAX)
-	    t = QH_MAX;
-	}
-      else
-	{
-	  if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	    {
-	      if (s > 1 && ((unsigned48)a & QH_ONES(s-1)) != 0)
-		t++;
-	    }
-	  if (t < QH_MIN)
-	    t = QH_MIN;
-	}
-      result = (signed16)t;
-    }
-  return result;
-}
-
-static signed16
-RNAUQH(signed48 a, signed16 s)
-{
-  unsigned48 t;
-  signed16 result;
-
-  if (s > 48)
-    result = 0;
-  else if (s == 48)
-    result = ((unsigned48)a & MASK48) >> 47;
-  else
-    {
-      t = ((unsigned48)a & MASK48) >> s;
-      if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	t++;
-      if (t > 0xFFFF)
-	t = 0xFFFF;
-      result = (signed16)t;
-    }
-  return result;
-}
-
-static signed16
-RNESQH(signed48 a, signed16 s)
-{
-  signed48 t;
-  signed16 result = 0;
-
-  if (s > 47)
-    result = 0;
-  else
-    {
-      t = (a >> s);
-      if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	{
-	  if (s == 1 || (a & QH_ONES(s-1)) == 0)
-	    t += t & 1;
-	  else
-	    t += 1;
-	}
-      if ((a & QH_BIT(47)) == 0)
-	{
-	  if (t > QH_MAX)
-	    t = QH_MAX;
-	}
-      else
-	{
-	  if (t < QH_MIN)
-	    t = QH_MIN;
-	}
-      result = (signed16)t;
-    }
-  return result;
-}
-
-static signed16
-RNEUQH(signed48 a, signed16 s)
-{
-  unsigned48 t;
-  signed16 result;
-
-  if (s > 48)
-    result = 0;
-  else if (s == 48)
-    result = ((unsigned48)a > QH_BIT(47) ? 1 : 0);
-  else
-    {
-      t = ((unsigned48)a & MASK48) >> s;
-      if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	{
-	  if (s > 1 && (a & QH_ONES(s-1)) != 0)
-	    t++;
-	  else
-	    t += t & 1;
-	}
-      if (t > 0xFFFF)
-	t = 0xFFFF;
-      result = (signed16)t;
-    }
-  return result;
-}
-
-static signed16
-RZSQH(signed48 a, signed16 s)
-{
-  signed48 t;
-  signed16 result = 0;
-
-  if (s > 47)
-    result = 0;
-  else
-    {
-      t = (a >> s);
-      if ((a & QH_BIT(47)) == 0)
-	{
-	  if (t > QH_MAX)
-	    t = QH_MAX;
-	}
-      else
-	{
-	  if (t < QH_MIN)
-	    t = QH_MIN;
-	}
-      result = (signed16)t;
-    }
-  return result;
-}
-
-static signed16
-RZUQH(signed48 a, signed16 s)
-{
-  unsigned48 t;
-  signed16 result = 0;
-
-  if (s > 48)
-    result = 0;
-  else if (s == 48)
-    result = ((unsigned48)a > QH_BIT(47) ? 1 : 0);
-  else
-    {
-      t = ((unsigned48)a & MASK48) >> s;
-      if (t > 0xFFFF)
-	t = 0xFFFF;
-      result = (signed16)t;
-    }
-  return result;
-}
-
-
-typedef unsigned8 (*OB_ROUND)(signed24 a, unsigned8 s);
-
-#define OB_BIT(n)  ((unsigned24)1 << (n))
-#define OB_ONES(n) (((unsigned24)1 << (n))-1)
-
-static unsigned8
-RNAUOB(signed24 a, unsigned8 s)
-{
-  unsigned8 result;
-  unsigned24 t;
-
-  if (s > 24)
-    result = 0;
-  else if (s == 24)
-    result = ((unsigned24)a & MASK24) >> 23;
-  else
-    {
-      t = ((unsigned24)a & MASK24) >> s;
-      if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	t ++;
-      result = OB_CLAMP(t);
-    }
-  return result;
-}
-
-static unsigned8
-RNEUOB(signed24 a, unsigned8 s)
-{
-  unsigned8 result;
-  unsigned24 t;
-
-  if (s > 24)
-    result = 0;
-  else if (s == 24)
-    result = (((unsigned24)a & MASK24) > OB_BIT(23) ? 1 : 0);
-  else
-    {
-      t = ((unsigned24)a & MASK24) >> s;
-      if (s > 0 && ((a >> (s-1)) & 1) == 1)
-	{
-	  if (s > 1 && (a & OB_ONES(s-1)) != 0)
-	    t++;
-	  else
-	    t += t & 1;
-	}
-      result = OB_CLAMP(t);
-    }
-  return result;
-}
-
-static unsigned8
-RZUOB(signed24 a, unsigned8 s)
-{
-  unsigned8 result;
-  unsigned24 t;
-
-  if (s >= 24)
-    result = 0;
-  else
-    {
-      t = ((unsigned24)a & MASK24) >> s;
-      result = OB_CLAMP(t);
-    }
-  return result;
-}
-
-
-static const QH_ROUND qh_round[] = {
-  RNASQH, RNAUQH, RNESQH, RNEUQH, RZSQH,  RZUQH
-};
-
-static const OB_ROUND ob_round[] = {
-  NULL,   RNAUOB, NULL,   RNEUOB, NULL,   RZUOB
-};
-
-
-static unsigned64
-qh_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, QH_ROUND round)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  signed16 h, h2;
-
-  s = 0;
-  for (i = 0; i < 4; i++)
-    {
-      h2 = (signed16)(v2 & 0xFFFF);
-      if (h2 >= 0)
-	h = (*round)(ACC.qh[i], h2);
-      else
-	{
-	  UnpredictableResult ();
-	  h = 0xdead;
-	}
-      v2 >>= 16;
-      result |= ((unsigned64)((unsigned16)h) << s);
-      s += 16;
-    }
-  return result;
-}
-
-static unsigned64
-qh_map_round(sim_cpu *cpu, address_word cia, signed16 h2, QH_ROUND round)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  signed16  h;
-
-  s = 0;
-  for (i = 0; i < 4; i++)
-    {
-      if (h2 >= 0)
-	h = (*round)(ACC.qh[i], h2);
-      else
-	{
-	  UnpredictableResult ();
-	  h = 0xdead;
-	}
-      result |= ((unsigned64)((unsigned16)h) << s);
-      s += 16;
-    }
-  return result;
-}
-
-static unsigned64
-ob_vector_round(sim_cpu *cpu, address_word cia, unsigned64 v2, OB_ROUND round)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned8 b, b2;
-
-  s = 0;
-  for (i = 0; i < 8; i++)
-    {
-      b2 = v2 & 0xFF;  v2 >>= 8;
-      b = (*round)(ACC.ob[i], b2);
-      result |= ((unsigned64)b << s);
-      s += 8;
-    }
-  return result;
-}
-
-static unsigned64
-ob_map_round(sim_cpu *cpu, address_word cia, unsigned8 b2, OB_ROUND round)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  unsigned8 b;
-
-  s = 0;
-  for (i = 0; i < 8; i++)
-    {
-      b = (*round)(ACC.ob[i], b2);
-      result |= ((unsigned64)b << s);
-      s += 8;
-    }
-  return result;
-}
-
-
-unsigned64
-mdmx_round_op(sim_cpu *cpu,
-	      address_word cia,
-	      int rm,
-	      int vt,
-	      MX_fmtsel fmtsel) 
-{
-  unsigned64 op2;
-  unsigned64 result = 0;
-
-  switch (MX_FMT (fmtsel))
-    {
-    case mdmx_qh:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = qh_map_round(cpu, cia, QH_ELEM(op2, fmtsel), qh_round[rm]);
-	  break;
-	case sel_vect:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = qh_vector_round(cpu, cia, op2, qh_round[rm]);
-	  break;
-	case sel_imm:
-	  result = qh_map_round(cpu, cia, vt, qh_round[rm]);
-	  break;
-	}
-      break;
-    case mdmx_ob:
-      switch (MX_VT (fmtsel))
-	{
-	case sel_elem:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = ob_map_round(cpu, cia, OB_ELEM(op2, fmtsel), ob_round[rm]);
-	  break;
-	case sel_vect:
-	  op2 = ValueFPR(vt, fmt_mdmx);
-	  result = ob_vector_round(cpu, cia, op2, ob_round[rm]);
-	  break;
-	case sel_imm:
-	  result = ob_map_round(cpu, cia, vt, ob_round[rm]);
-	  break;
-	}
-      break;
-    default:
-      Unpredictable ();
-    }
-
-  return result;
-}
-
-
-/* Shuffle operation.  */
-
-typedef struct {
-  enum {vs, ss, vt} source;
-  unsigned int      index;
-} sh_map;
-
-static const sh_map ob_shuffle[][8] = {
-  /* MDMX 2.0 encodings (3-4, 6-7).  */
-  /* vr5400   encoding  (5), otherwise.  */
-  {                                                              }, /* RSVD */
-  {{vt,4}, {vs,4}, {vt,5}, {vs,5}, {vt,6}, {vs,6}, {vt,7}, {vs,7}}, /* RSVD */
-  {{vt,0}, {vs,0}, {vt,1}, {vs,1}, {vt,2}, {vs,2}, {vt,3}, {vs,3}}, /* RSVD */
-  {{vs,0}, {ss,0}, {vs,1}, {ss,1}, {vs,2}, {ss,2}, {vs,3}, {ss,3}}, /* upsl */
-  {{vt,1}, {vt,3}, {vt,5}, {vt,7}, {vs,1}, {vs,3}, {vs,5}, {vs,7}}, /* pach */
-  {{vt,0}, {vt,2}, {vt,4}, {vt,6}, {vs,0}, {vs,2}, {vs,4}, {vs,6}}, /* pacl */
-  {{vt,4}, {vs,4}, {vt,5}, {vs,5}, {vt,6}, {vs,6}, {vt,7}, {vs,7}}, /* mixh */
-  {{vt,0}, {vs,0}, {vt,1}, {vs,1}, {vt,2}, {vs,2}, {vt,3}, {vs,3}}  /* mixl */
-};
-
-static const sh_map qh_shuffle[][4] = {
-  {{vt,2}, {vs,2}, {vt,3}, {vs,3}},  /* mixh */
-  {{vt,0}, {vs,0}, {vt,1}, {vs,1}},  /* mixl */
-  {{vt,1}, {vt,3}, {vs,1}, {vs,3}},  /* pach */
-  {                              },  /* RSVD */
-  {{vt,1}, {vs,0}, {vt,3}, {vs,2}},  /* bfla */
-  {                              },  /* RSVD */
-  {{vt,2}, {vt,3}, {vs,2}, {vs,3}},  /* repa */
-  {{vt,0}, {vt,1}, {vs,0}, {vs,1}}   /* repb */
-};
-
-
-unsigned64
-mdmx_shuffle(sim_cpu *cpu,
-	     address_word cia,
-	     int shop,
-	     unsigned64 op1,
-	     unsigned64 op2)
-{
-  unsigned64 result = 0;
-  int  i, s;
-  int  op;
-
-  if ((shop & 0x3) == 0x1)       /* QH format.  */
-    {
-      op = shop >> 2;
-      s = 0;
-      for (i = 0; i < 4; i++)
-	{
-	  unsigned64 v;
-
-	  switch (qh_shuffle[op][i].source)
-	    {
-	    case vs:
-	      v = op1;
-	      break;
-	    case vt:
-	      v = op2;
-	      break;
-	    default:
-	      Unpredictable ();
-	      v = 0;
-	    }
-	  result |= (((v >> 16*qh_shuffle[op][i].index) & 0xFFFF) << s);
-	  s += 16;
-	}
-    }
-  else if ((shop & 0x1) == 0x0)  /* OB format.  */
-    {
-      op = shop >> 1;
-      s = 0;
-      for (i = 0; i < 8; i++)
-	{
-	  unsigned8 b;
-	  unsigned int ishift = 8*ob_shuffle[op][i].index;
-
-	  switch (ob_shuffle[op][i].source)
-	    {
-	    case vs:
-	      b = (op1 >> ishift) & 0xFF;
-	      break;
-	    case ss:
-	      b = ((op1 >> ishift) & 0x80) ? 0xFF : 0;
-	      break;
-	    case vt:
-	      b = (op2 >> ishift) & 0xFF;
-	      break;
-	    default:
-	      Unpredictable ();
-	      b = 0;
-	    }
-	  result |= ((unsigned64)b << s);
-	  s += 8;
-	}
-    }
-  else
-    Unpredictable ();
-
-  return result;
-}
diff --git a/sim/mips/mdmx.igen b/sim/mips/mdmx.igen
deleted file mode 100644
index d8edcd7..0000000
--- a/sim/mips/mdmx.igen
+++ /dev/null
@@ -1,593 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the MIPS MDMX ASE.
-// Copyright (C) 2002 Free Software Foundation, Inc.
-// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
-// Corporation (SiByte).
-//
-// This file is part of GDB, the GNU debugger.
-// 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-//  Reference: MIPS64 Architecture Volume IV-b:
-//             The MDMX Application-Specific Extension
-
-//  Notes on "format selectors" (FMTSEL):
-//
-//   A selector with final bit 0 indicates OB format.
-//   A selector with final bits 01 indicates QH format.
-//   A selector with final bits 11 has UNPREDICTABLE result per the spec.
-//
-//  Similarly, for the single-bit fields which differentiate between
-//  formats (FMTOP), 0 is OB format and 1 is QH format.
-
-//  If you change this file to add instructions, please make sure that model
-//  "sb1" configurations still build, and that you've added no new
-//  instructions to the "sb1" model.
-
-
-// Helper:
-//
-// Check whether MDMX is usable, and if not signal an appropriate exception.
-//
-
-:function:::void:check_mdmx:instruction_word insn
-*mdmx:
-{
-  if (! COP_Usable (1))
-    SignalExceptionCoProcessorUnusable (1);
-  if ((SR & (status_MX|status_FR)) != (status_MX|status_FR))
-    SignalExceptionMDMX ();
-  check_u64 (SD_, insn);
-}
-
-
-// Helper:
-//
-// Check whether a given MDMX format selector indicates a valid and usable
-// format, and if not signal an appropriate exception.
-//
-
-:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
-*mdmx:
-{
-  switch (fmtsel & 0x03)
-    {
-    case 0x00:     /* ob */
-    case 0x02:
-    case 0x01:     /* qh */
-      return 1;
-    case 0x03:     /* UNPREDICTABLE */
-      SignalException (ReservedInstruction, insn);
-      return 0;
-    }
-  return 0;
-}
-
-
-// Helper:
-//
-// Check whether a given MDMX format bit indicates a valid and usable
-// format, and if not signal an appropriate exception.
-//
-
-:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
-*mdmx:
-{
-  switch (fmtop & 0x01)
-    {
-    case 0x00:     /* ob */
-    case 0x01:     /* qh */
-      return 1;
-    }
-  return 0;
-}
-
-
-:%s::::FMTSEL:int fmtsel
-*mdmx:
-*sb1:
-{
-  if ((fmtsel & 0x1) == 0)
-    return "ob";
-  else if ((fmtsel & 0x3) == 1)
-    return "qh";
-  else
-    return "?";
-}
-
-
-:%s::::FMTOP:int fmtop
-*mdmx:
-*sb1:
-{
-  switch (fmtop)
-    {
-    case 0: return "ob";
-    case 1: return "qh";
-    default: return "?";
-    }
-}
-
-
-:%s::::SHOP:int shop
-*mdmx:
-*sb1:
-{
-  if ((shop & 0x11) == 0x00)
-    switch ((shop >> 1) & 0x07)
-      {
-      case 3:  return "upsl.ob";
-      case 4:  return "pach.ob";
-      case 6:  return "mixh.ob";
-      case 7:  return "mixl.ob";
-      default: return "?";
-      }
-  else if ((shop & 0x03) == 0x01)
-    switch ((shop >> 2) & 0x07)
-      {
-      case 0:  return "mixh.qh";
-      case 1:  return "mixl.qh";
-      case 2:  return "pach.qh";
-      case 4:  return "bfla.qh";
-      case 6:  return "repa.qh";
-      case 7:  return "repb.qh";
-      default: return "?";
-      }
-  else
-    return "?";
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt
-"add.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Add(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt
-"adda.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_AddA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt
-"addl.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_AddL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt
-"alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>"
-*mdmx:
-*sb1:
-{
-  unsigned64 result;
-  int s;
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  s = (IMM << 3);
-  result = ValueFPR(VS,fmt_mdmx) << s;
-  if (s != 0)  // x86 gcc treats >> 64 as >> 0
-    result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
-  StoreFPR(VD,fmt_mdmx,result);
-}
-
-
-011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt
-"alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>"
-*mdmx:
-*sb1:
-{
-  unsigned64 result;
-  int s;
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  s = ((GPR[RS] & 0x7) << 3);
-  result = ValueFPR(VS,fmt_mdmx) << s;
-  if (s != 0)  // x86 gcc treats >> 64 as >> 0
-    result |= ValueFPR(VT,fmt_mdmx) >> (64 - s);
-  StoreFPR(VD,fmt_mdmx,result);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt
-"and.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_And(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt
-"c.eq.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_EQ,VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt
-"c.le.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT|MX_C_EQ,VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt
-"c.lt.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_Comp(ValueFPR(VS,fmt_mdmx),MX_C_LT,VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt
-"max.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Max(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt
-"min.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Min(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,3.SEL,01,5.VT,5.VS,5.VD,000000:MDMX:64::MSGN.QH
-"msgn.qh v<VD>, v<VS>, v<VT>"
-*mdmx:
-{
-  check_mdmx (SD_, instruction_0);
-  StoreFPR(VD,fmt_mdmx,MX_Msgn(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt
-"mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Mul(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt
-"mula.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_MulA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt
-"mull.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_MulL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt
-"muls.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_MulS(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt
-"mulsl.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_MulSL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt
-"nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Nor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt
-"or.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Or(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt
-"pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Pick(0,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt
-"pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Pick(1,ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt
-"rach.%s<FMTOP> v<VD>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_H,FMTOP));
-}
-
-
-011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt
-"racl.%s<FMTOP> v<VD>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_L,FMTOP));
-}
-
-
-011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt
-"racm.%s<FMTOP> v<VD>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  StoreFPR(VD,fmt_mdmx,MX_RAC(MX_RAC_M,FMTOP));
-}
-
-
-011110,3.SEL,01,5.VT,00000,5.VD,100101:MDMX:64::RNAS.QH
-"rnas.qh v<VD>, v<VT>"
-*mdmx:
-{
-  check_mdmx (SD_, instruction_0);
-  StoreFPR(VD,fmt_mdmx,MX_RNAS(VT,qh_fmtsel(SEL)));
-}
-
-
-011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt
-"rnau.%s<FMTSEL> v<VD>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_RNAU(VT,FMTSEL));
-}
-
-
-011110,3.SEL,01,5.VT,00000,5.VD,100110:MDMX:64::RNES.QH
-"rnes.qh v<VD>, v<VT>"
-*mdmx:
-{
-  check_mdmx (SD_, instruction_0);
-  StoreFPR(VD,fmt_mdmx,MX_RNES(VT,qh_fmtsel(SEL)));
-}
-
-
-011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt
-"rneu.%s<FMTSEL> v<VD>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_RNEU(VT,FMTSEL));
-}
-
-
-011110,3.SEL,01,5.VT,00000,5.VD,100100:MDMX:64::RZS.QH
-"rzs.qh v<VD>, v<VT>"
-*mdmx:
-{
-  check_mdmx (SD_, instruction_0);
-  StoreFPR(VD,fmt_mdmx,MX_RZS(VT,qh_fmtsel(SEL)));
-}
-
-
-011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt
-"rzu.%s<FMTSEL> v<VD>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_RZU(VT,FMTSEL));
-}
-
-
-011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt
-"shfl.%s<SHOP> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, SHOP))
-    StoreFPR(VD,fmt_mdmx,MX_SHFL(SHOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx)));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt
-"sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_ShiftLeftLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,3.SEL,01,5.VT,5.VS,5.VD,010011:MDMX:64::SRA.QH
-"sra.qh v<VD>, v<VS>, v<VT>"
-*mdmx:
-{
-  check_mdmx (SD_, instruction_0);
-  StoreFPR(VD,fmt_mdmx,MX_ShiftRightArith(ValueFPR(VS,fmt_mdmx),VT,qh_fmtsel(SEL)));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt
-"srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_ShiftRightLogical(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt
-"sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Sub(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt
-"suba.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_SubA(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt
-"subl.%s<FMTSEL> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    MX_SubL(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt
-"wach.%s<FMTOP> v<VS>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  MX_WACH(FMTOP,ValueFPR(VS,fmt_mdmx));
-}
-
-
-011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt
-"wacl.%s<FMTOP> v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  MX_WACL(FMTOP,ValueFPR(VS,fmt_mdmx),ValueFPR(VT,fmt_mdmx));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt
-"xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
-*mdmx:
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
-    StoreFPR(VD,fmt_mdmx,MX_Xor(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
diff --git a/sim/mips/mips.dc b/sim/mips/mips.dc
deleted file mode 100644
index 98da024..0000000
--- a/sim/mips/mips.dc
+++ /dev/null
@@ -1,16 +0,0 @@
-# most instructions
-# ------ options ------ : Fst : Lst : ff : fl : fe : word : --- fmt --- : model ...
-# { : mask : value : word }
-
-# Top level - create a very big switch statement.
-
-  padded-switch,combine :  31 :  26 :    :    :    :      :             :
-
-  switch,combine        :   5 :   0 :    :    :    :      :             :
-
-  switch,combine        :  20 :  16 :    :    :    :      :             :
-
-  switch,combine        :  25 :  21 :    :    :    :      :             :
-
-  switch,combine        :  10 :   6 :    :    :    :      :             :
-
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
deleted file mode 100644
index e179cf0..0000000
--- a/sim/mips/mips.igen
+++ /dev/null
@@ -1,5686 +0,0 @@
-// -*- C -*-
-//
-//    <insn> ::=
-//        <insn-word> { "+" <insn-word> }
-//        ":" <format-name>
-//        ":" <filter-flags>
-//        ":" <options>
-//        ":" <name>
-//        <nl>
-//        { <insn-model> }
-//        { <insn-mnemonic> }
-//        <code-block>
-//
-
-
-// IGEN config - mips16
-// :option:16::insn-bit-size:16
-// :option:16::hi-bit-nr:15
-:option:16::insn-specifying-widths:true
-:option:16::gen-delayed-branch:false
-
-// IGEN config - mips32/64..
-// :option:32::insn-bit-size:32
-// :option:32::hi-bit-nr:31
-:option:32::insn-specifying-widths:true
-:option:32::gen-delayed-branch:false
-
-
-// Generate separate simulators for each target
-// :option:::multi-sim:true
-
-
-// Models known by this simulator are defined below.
-//
-// When placing models in the instruction descriptions, please place
-// them one per line, in the order given here.
-
-//  MIPS ISAs:
-//
-//  Instructions and related functions for these models are included in
-//  this file.
-:model:::mipsI:mips3000:
-:model:::mipsII:mips6000:
-:model:::mipsIII:mips4000:
-:model:::mipsIV:mips8000:
-:model:::mipsV:mipsisaV:
-:model:::mips32:mipsisa32:
-:model:::mips32r2:mipsisa32r2:
-:model:::mips64:mipsisa64:
-:model:::mips64r2:mipsisa64r2:
-
-//  Vendor ISAs:
-//
-//  Standard MIPS ISA instructions used for these models are listed here,
-//  as are functions needed by those standard instructions.  Instructions
-//  which are model-dependent and which are not in the standard MIPS ISAs
-//  (or which pre-date or use different encodings than the standard
-//  instructions) are (for the most part) in separate .igen files.
-:model:::vr4100:mips4100:		// vr.igen
-:model:::vr4120:mips4120:
-:model:::vr5000:mips5000:
-:model:::vr5400:mips5400:
-:model:::vr5500:mips5500:
-:model:::r3900:mips3900:		// tx.igen
-
-//  MIPS Application Specific Extensions (ASEs)
-//
-//  Instructions for the ASEs are in separate .igen files.
-//  ASEs add instructions on to a base ISA.
-:model:::mips16:mips16:			// m16.igen (and m16.dc)
-:model:::mips16e:mips16e:		// m16e.igen
-:model:::mips3d:mips3d:			// mips3d.igen
-:model:::mdmx:mdmx:			// mdmx.igen
-:model:::dsp:dsp:			// dsp.igen
-
-//  Vendor Extensions
-//
-//  Instructions specific to these extensions are in separate .igen files.
-//  Extensions add instructions on to a base ISA.
-:model:::sb1:sb1:			// sb1.igen
-
-
-// Pseudo instructions known by IGEN
-:internal::::illegal:
-{
-  SignalException (ReservedInstruction, 0);
-}
-
-
-// Pseudo instructions known by interp.c
-// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
-000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
-"rsvd <OP>"
-{
-  SignalException (ReservedInstruction, instruction_0);
-}
-
-
-
-// Helper:
-//
-// Simulate a 32 bit delayslot instruction
-//
-
-:function:::address_word:delayslot32:address_word target
-{
-  instruction_word delay_insn;
-  sim_events_slip (SD, 1);
-  DSPC = CIA;
-  CIA = CIA + 4; /* NOTE not mips16 */
-  STATE |= simDELAYSLOT;
-  delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
-  ENGINE_ISSUE_PREFIX_HOOK();
-  idecode_issue (CPU_, delay_insn, (CIA));
-  STATE &= ~simDELAYSLOT;
-  return target;
-}
-
-:function:::address_word:nullify_next_insn32:
-{
-  sim_events_slip (SD, 1);
-  dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
-  return CIA + 8;
-}
-
-
-// Helper:
-//
-// Calculate an effective address given a base and an offset.
-//
-
-:function:::address_word:loadstore_ea:address_word base, address_word offset
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  return base + offset;
-}
-
-:function:::address_word:loadstore_ea:address_word base, address_word offset
-*mips64:
-*mips64r2:
-{
-#if 0 /* XXX FIXME: enable this only after some additional testing.  */
-  /* If in user mode and UX is not set, use 32-bit compatibility effective
-     address computations as defined in the MIPS64 Architecture for
-     Programmers Volume III, Revision 0.95, section 4.9.  */
-  if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
-      == (ksu_user << status_KSU_shift))
-    return (address_word)((signed32)base + (signed32)offset);
-#endif
-  return base + offset;
-}
-
-
-// Helper:
-//
-// Check that a 32-bit register value is properly sign-extended.
-// (See NotWordValue in ISA spec.)
-//
-
-:function:::int:not_word_value:unsigned_word value
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* For historical simulator compatibility (until documentation is
-     found that makes these operations unpredictable on some of these
-     architectures), this check never returns true.  */
-  return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
-*mips32:
-*mips32r2:
-{
-  /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
-  return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
-*mips64:
-*mips64r2:
-{
-  return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
-}
-
-
-// Helper:
-//
-// Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
-// theoretically portable code which invokes non-portable behaviour from
-// running with no indication of the portability issue.
-// (See definition of UNPREDICTABLE in ISA spec.)
-//
-
-:function:::void:unpredictable:
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-}
-
-:function:::void:unpredictable:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-{
-  unpredictable_action (CPU, CIA);
-}
-
-
-// Helpers:
-//
-// Check that an access to a HI/LO register meets timing requirements
-//
-// In all MIPS ISAs,
-//
-//	OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
-//	makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
-//
-// The following restrictions exist for MIPS I - MIPS III:
-//
-//	MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
-//	in between makes MF UNPREDICTABLE. (2)
-//
-//	MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
-//	in between makes MF UNPREDICTABLE. (3)
-//
-// On the r3900, restriction (2) is not present, and restriction (3) is not
-// present for multiplication.
-//
-// Unfortunately, there seems to be some confusion about whether the last
-// two restrictions should apply to "MIPS IV" as well.  One edition of
-// the MIPS IV ISA says they do, but references in later ISA documents
-// suggest they don't.
-//
-// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
-// these restrictions, while others, like the VR5500, don't.  To accomodate
-// such differences, the MIPS IV and MIPS V version of these helper functions
-// use auxillary routines to determine whether the restriction applies.
-
-// check_mf_cycles:
-//
-// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
-// to check for restrictions (2) and (3) above.
-//
-:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
-{
-  if (history->mf.timestamp + 3 > time)
-    {
-      sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
-			itable[MY_INDEX].name,
-			new, (long) CIA,
-			(long) history->mf.cia);
-      return 0;
-    }
-  return 1;
-}
-
-
-// check_mt_hilo:
-//
-// Check for restriction (2) above (for ISAs/processors that have it),
-// and record timestamps for restriction (1) above.
-//
-:function:::int:check_mt_hilo:hilo_history *history
-*mipsI:
-*mipsII:
-*mipsIII:
-*vr4100:
-*vr5000:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = check_mf_cycles (SD_, history, time, "MT");
-  history->mt.timestamp = time;
-  history->mt.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_mt_hilo:hilo_history *history
-*mipsIV:
-*mipsV:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
-	    || check_mf_cycles (SD_, history, time, "MT"));
-  history->mt.timestamp = time;
-  history->mt.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_mt_hilo:hilo_history *history
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*r3900:
-{
-  signed64 time = sim_events_time (SD);
-  history->mt.timestamp = time;
-  history->mt.cia = CIA;
-  return 1;
-}
-
-
-// check_mf_hilo:
-//
-// Check for restriction (1) above, and record timestamps for
-// restriction (2) and (3) above.
-//
-:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = 1;
-  if (peer != NULL
-      && peer->mt.timestamp > history->op.timestamp
-      && history->mt.timestamp < history->op.timestamp
-      && ! (history->mf.timestamp > history->op.timestamp
-	    && history->mf.timestamp < peer->mt.timestamp)
-      && ! (peer->mf.timestamp > history->op.timestamp
-	    && peer->mf.timestamp < peer->mt.timestamp))
-    {
-      /* The peer has been written to since the last OP yet we have
-         not */
-      sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
-			itable[MY_INDEX].name,
-			(long) CIA,
-			(long) history->op.cia,
-			(long) peer->mt.cia);
-      ok = 0;
-    }
-  history->mf.timestamp = time;
-  history->mf.cia = CIA;
-  return ok;
-}
-
-
-
-// check_mult_hilo:
-//
-// Check for restriction (3) above (for ISAs/processors that have it)
-// for MULT ops, and record timestamps for restriction (1) above.
-//
-:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
-*mipsI:
-*mipsII:
-*mipsIII:
-*vr4100:
-*vr5000:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = (check_mf_cycles (SD_, hi, time, "OP")
-	    && check_mf_cycles (SD_, lo, time, "OP"));
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
-*mipsIV:
-*mipsV:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
-	    || (check_mf_cycles (SD_, hi, time, "OP")
-	        && check_mf_cycles (SD_, lo, time, "OP")));
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*r3900:
-{
-  /* FIXME: could record the fact that a stall occured if we want */
-  signed64 time = sim_events_time (SD);
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return 1;
-}
-
-
-// check_div_hilo:
-//
-// Check for restriction (3) above (for ISAs/processors that have it)
-// for DIV ops, and record timestamps for restriction (1) above.
-//
-:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
-*mipsI:
-*mipsII:
-*mipsIII:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = (check_mf_cycles (SD_, hi, time, "OP")
-	    && check_mf_cycles (SD_, lo, time, "OP"));
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
-*mipsIV:
-*mipsV:
-{
-  signed64 time = sim_events_time (SD);
-  int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
-	    || (check_mf_cycles (SD_, hi, time, "OP")
-	        && check_mf_cycles (SD_, lo, time, "OP")));
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return ok;
-}
-
-:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-{
-  signed64 time = sim_events_time (SD);
-  hi->op.timestamp = time;
-  lo->op.timestamp = time;
-  hi->op.cia = CIA;
-  lo->op.cia = CIA;
-  return 1;
-}
-
-
-// Helper:
-//
-// Check that the 64-bit instruction can currently be used, and signal
-// a ReservedInstruction exception if not.
-//
-
-:function:::void:check_u64:instruction_word insn
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*vr5400:
-*vr5500:
-{
-  // The check should be similar to mips64 for any with PX/UX bit equivalents.
-}
-
-:function:::void:check_u64:instruction_word insn
-*mips16e:
-*mips64:
-*mips64r2:
-{
-#if 0 /* XXX FIXME: enable this only after some additional testing.  */
-  if (UserMode && (SR & (status_UX|status_PX)) == 0)
-    SignalException (ReservedInstruction, insn);
-#endif
-}
-
-
-
-//
-// MIPS Architecture:
-//
-//        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
-//
-
-
-
-000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
-"add r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  {
-    ALU32_BEGIN (GPR[RS]);
-    ALU32_ADD (GPR[RT]);
-    ALU32_END (GPR[RD]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
-"addi r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  if (NotWordValue (GPR[RS]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
-  {
-    ALU32_BEGIN (GPR[RS]);
-    ALU32_ADD (EXTEND16 (IMMEDIATE));
-    ALU32_END (GPR[RT]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-
-:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
-{
-  if (NotWordValue (GPR[rs]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
-  GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"addiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_addiu (SD_, RS, RT, IMMEDIATE);
-}
-
-
-
-:function:::void:do_addu:int rs, int rt, int rd
-{
-  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
-"addu r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_addu (SD_, RS, RT, RD);
-}
-
-
-
-:function:::void:do_and:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = GPR[rs] & GPR[rt];
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
-"and r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_and (SD_, RS, RT, RD);
-}
-
-
-
-001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
-  GPR[RT] = GPR[RS] & IMMEDIATE;
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-
-000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
-"beq r<RS>, r<RT>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
-"beql r<RS>, r<RT>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
-"bgez r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] >= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
-"bgezal r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if (RS == 31)
-    Unpredictable ();
-  RA = (CIA + 8);
-  if ((signed_word) GPR[RS] >= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
-"bgezall r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if (RS == 31)
-    Unpredictable ();
-  RA = (CIA + 8);
-  /* NOTE: The branch occurs AFTER the next instruction has been
-     executed */
-  if ((signed_word) GPR[RS] >= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
-"bgezl r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] >= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
-"bgtz r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] > 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
-"bgtzl r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  /* NOTE: The branch occurs AFTER the next instruction has been
-     executed */
-  if ((signed_word) GPR[RS] > 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
-"blez r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  /* NOTE: The branch occurs AFTER the next instruction has been
-     executed */
-  if ((signed_word) GPR[RS] <= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
-"bgezl r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] <= 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
-"bltz r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] < 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
-"bltzal r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if (RS == 31)
-    Unpredictable ();
-  RA = (CIA + 8);
-  /* NOTE: The branch occurs AFTER the next instruction has been
-     executed */
-  if ((signed_word) GPR[RS] < 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
-"bltzall r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if (RS == 31)
-    Unpredictable ();
-  RA = (CIA + 8);
-  if ((signed_word) GPR[RS] < 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
-"bltzl r<RS>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  /* NOTE: The branch occurs AFTER the next instruction has been
-     executed */
-  if ((signed_word) GPR[RS] < 0)
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
-"bne r<RS>, r<RT>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-
-010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
-"bnel r<RS>, r<RT>, <OFFSET>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word offset = EXTEND16 (OFFSET) << 2;
-  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    {
-      DELAY_SLOT (NIA + offset);
-    }
-  else
-    NULLIFY_NEXT_INSTRUCTION ();
-}
-
-
-
-000000,20.CODE,001101:SPECIAL:32::BREAK
-"break %#lx<CODE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* Check for some break instruction which are reserved for use by the simulator.  */
-  unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
-  if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
-      break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
-    {
-      sim_engine_halt (SD, CPU, NULL, cia,
-                       sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
-    }
-  else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
-           break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
-    {
-      if (STATE & simDELAYSLOT)
-        PC = cia - 4; /* reference the branch instruction */
-      else
-        PC = cia;
-      SignalException (BreakPoint, instruction_0);
-    }
-
-  else
-    {
-      /* If we get this far, we're not an instruction reserved by the sim.  Raise
-	 the exception. */
-      SignalException (BreakPoint, instruction_0);
-    }
-}
-
-
-
-011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
-"clo r<RD>, r<RS>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned32 temp = GPR[RS];
-  unsigned32 i, mask;
-  if (RT != RD)
-    Unpredictable ();
-  if (NotWordValue (GPR[RS]))
-    Unpredictable ();
-  TRACE_ALU_INPUT1 (GPR[RS]);
-  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
-    {
-      if ((temp & mask) == 0)
-	break;
-      mask >>= 1;
-    }
-  GPR[RD] = EXTEND32 (i);
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
-"clz r<RD>, r<RS>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned32 temp = GPR[RS];
-  unsigned32 i, mask;
-  if (RT != RD)
-    Unpredictable ();
-  if (NotWordValue (GPR[RS]))
-    Unpredictable ();
-  TRACE_ALU_INPUT1 (GPR[RS]);
-  for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
-    {
-      if ((temp & mask) != 0)
-	break;
-      mask >>= 1;
-    }
-  GPR[RD] = EXTEND32 (i);
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
-"dadd r<RD>, r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  {
-    ALU64_BEGIN (GPR[RS]);
-    ALU64_ADD (GPR[RT]);
-    ALU64_END (GPR[RD]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
-"daddi r<RT>, r<RS>, <IMMEDIATE>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
-  {
-    ALU64_BEGIN (GPR[RS]);
-    ALU64_ADD (EXTEND16 (IMMEDIATE));
-    ALU64_END (GPR[RT]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-
-:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
-{
-  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
-  GPR[rt] = GPR[rs] + EXTEND16 (immediate);
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
-"daddiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_daddiu (SD_, RS, RT, IMMEDIATE);
-}
-
-
-
-:function:::void:do_daddu:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = GPR[rs] + GPR[rt];
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
-"daddu r<RD>, r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_daddu (SD_, RS, RT, RD);
-}
-
-
-
-011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
-"dclo r<RD>, r<RS>"
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned64 temp = GPR[RS];
-  unsigned32 i;
-  unsigned64 mask;
-  check_u64 (SD_, instruction_0);
-  if (RT != RD)
-    Unpredictable ();
-  TRACE_ALU_INPUT1 (GPR[RS]);
-  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
-    {
-      if ((temp & mask) == 0)
-	break;
-      mask >>= 1;
-    }
-  GPR[RD] = EXTEND32 (i);
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
-"dclz r<RD>, r<RS>"
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned64 temp = GPR[RS];
-  unsigned32 i;
-  unsigned64 mask;
-  check_u64 (SD_, instruction_0);
-  if (RT != RD)
-    Unpredictable ();
-  TRACE_ALU_INPUT1 (GPR[RS]);
-  for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
-    {
-      if ((temp & mask) != 0)
-	break;
-      mask >>= 1;
-    }
-  GPR[RD] = EXTEND32 (i);
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-:function:::void:do_ddiv:int rs, int rt
-{
-  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  {
-    signed64 n = GPR[rs];
-    signed64 d = GPR[rt];
-    signed64 hi;
-    signed64 lo;
-    if (d == 0)
-      {
-	lo = SIGNED64 (0x8000000000000000);
-	hi = 0;
-      }
-    else if (d == -1 && n == SIGNED64 (0x8000000000000000))
-      {
-	lo = SIGNED64 (0x8000000000000000);
-	hi = 0;
-      }
-    else
-      {
-	lo = (n / d);
-	hi = (n % d);
-      }
-    HI = hi;
-    LO = lo;
-  }
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
-"ddiv r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_ddiv (SD_, RS, RT);
-}
-
-
-
-:function:::void:do_ddivu:int rs, int rt
-{
-  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  {
-    unsigned64 n = GPR[rs];
-    unsigned64 d = GPR[rt];
-    unsigned64 hi;
-    unsigned64 lo;
-    if (d == 0)
-      {
-	lo = SIGNED64 (0x8000000000000000);
-	hi = 0;
-      }
-    else
-      {
-	lo = (n / d);
-	hi = (n % d);
-      }
-    HI = hi;
-    LO = lo;
-  }
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
-"ddivu r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_ddivu (SD_, RS, RT);
-}
-
-:function:::void:do_div:int rs, int rt
-{
-  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  {
-    signed32 n = GPR[rs];
-    signed32 d = GPR[rt];
-    if (d == 0)
-      {
-	LO = EXTEND32 (0x80000000);
-	HI = EXTEND32 (0);
-      }
-    else if (n == SIGNED32 (0x80000000) && d == -1)
-      {
-	LO = EXTEND32 (0x80000000);
-	HI = EXTEND32 (0);
-      }
-    else
-      {
-	LO = EXTEND32 (n / d);
-	HI = EXTEND32 (n % d);
-      }
-  }
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
-"div r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_div (SD_, RS, RT);
-}
-
-
-
-:function:::void:do_divu:int rs, int rt
-{
-  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  {
-    unsigned32 n = GPR[rs];
-    unsigned32 d = GPR[rt];
-    if (d == 0)
-      {
-	LO = EXTEND32 (0x80000000);
-	HI = EXTEND32 (0);
-      }
-    else
-      {
-	LO = EXTEND32 (n / d);
-	HI = EXTEND32 (n % d);
-      }
-  }
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
-"divu r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_divu (SD_, RS, RT);
-}
-
-
-:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
-{
-  unsigned64 lo;
-  unsigned64 hi;
-  unsigned64 m00;
-  unsigned64 m01;
-  unsigned64 m10;
-  unsigned64 m11;
-  unsigned64 mid;
-  int sign;
-  unsigned64 op1 = GPR[rs];
-  unsigned64 op2 = GPR[rt];
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  /* make signed multiply unsigned */
-  sign = 0;
-  if (signed_p)
-    {
-      if ((signed64) op1 < 0)
-	{
-	  op1 = - op1;
-	  ++sign;
-	}
-      if ((signed64) op2 < 0)
-	{
-	  op2 = - op2;
-	  ++sign;
-	}
-    }
-  /* multiply out the 4 sub products */
-  m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
-  m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
-  m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
-  m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
-  /* add the products */
-  mid = ((unsigned64) VH4_8 (m00)
-	 + (unsigned64) VL4_8 (m10)
-	 + (unsigned64) VL4_8 (m01));
-  lo = U8_4 (mid, m00);
-  hi = (m11
-	+ (unsigned64) VH4_8 (mid)
-	+ (unsigned64) VH4_8 (m01)
-	+ (unsigned64) VH4_8 (m10));
-  /* fix the sign */
-  if (sign & 1)
-    {
-      lo = -lo;
-      if (lo == 0)
-	hi = -hi;
-      else
-	hi = -hi - 1;
-    }
-  /* save the result HI/LO (and a gpr) */
-  LO = lo;
-  HI = hi;
-  if (rd != 0)
-    GPR[rd] = lo;
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-:function:::void:do_dmult:int rs, int rt, int rd
-{
-  do_dmultx (SD_, rs, rt, rd, 1);
-}
-
-000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
-"dmult r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-{
-  check_u64 (SD_, instruction_0);
-  do_dmult (SD_, RS, RT, 0);
-}
-
-000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
-"dmult r<RS>, r<RT>":RD == 0
-"dmult r<RD>, r<RS>, r<RT>"
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dmult (SD_, RS, RT, RD);
-}
-
-
-
-:function:::void:do_dmultu:int rs, int rt, int rd
-{
-  do_dmultx (SD_, rs, rt, rd, 0);
-}
-
-000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
-"dmultu r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-{
-  check_u64 (SD_, instruction_0);
-  do_dmultu (SD_, RS, RT, 0);
-}
-
-000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
-"dmultu r<RD>, r<RS>, r<RT>":RD == 0
-"dmultu r<RS>, r<RT>"
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dmultu (SD_, RS, RT, RD);
-}
-
-
-:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
-{
-  unsigned64 result;
-
-  y &= 63;
-  TRACE_ALU_INPUT2 (x, y);
-  result = ROTR64 (x, y);
-  TRACE_ALU_RESULT (result);
-  return result;
-}
-
-000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
-"dror r<RD>, r<RT>, <SHIFT>"
-*mips64r2:
-*vr5400:
-*vr5500:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
-}
-
-000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
-"dror32 r<RD>, r<RT>, <SHIFT>"
-*mips64r2:
-*vr5400:
-*vr5500:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
-}
-
-000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
-"drorv r<RD>, r<RT>, r<RS>"
-*mips64r2:
-*vr5400:
-*vr5500:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
-}
-
-
-:function:::void:do_dsll:int rt, int rd, int shift
-{
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = GPR[rt] << shift;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
-"dsll r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsll (SD_, RT, RD, SHIFT);
-}
-
-
-000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
-"dsll32 r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  int s = 32 + SHIFT;
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RT], s);
-  GPR[RD] = GPR[RT] << s;
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-:function:::void:do_dsllv:int rs, int rt, int rd
-{
-  int s = MASKED64 (GPR[rs], 5, 0);
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = GPR[rt] << s;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
-"dsllv r<RD>, r<RT>, r<RS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsllv (SD_, RS, RT, RD);
-}
-
-:function:::void:do_dsra:int rt, int rd, int shift
-{
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = ((signed64) GPR[rt]) >> shift;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-
-000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
-"dsra r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsra (SD_, RT, RD, SHIFT);
-}
-
-
-000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  int s = 32 + SHIFT;
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RT], s);
-  GPR[RD] = ((signed64) GPR[RT]) >> s;
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-:function:::void:do_dsrav:int rs, int rt, int rd
-{
-  int s = MASKED64 (GPR[rs], 5, 0);
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = ((signed64) GPR[rt]) >> s;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
-"dsrav r<RD>, r<RT>, r<RS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsrav (SD_, RS, RT, RD);
-}
-
-:function:::void:do_dsrl:int rt, int rd, int shift
-{
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = (unsigned64) GPR[rt] >> shift;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-
-000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
-"dsrl r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsrl (SD_, RT, RD, SHIFT);
-}
-
-
-000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
-"dsrl32 r<RD>, r<RT>, <SHIFT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  int s = 32 + SHIFT;
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RT], s);
-  GPR[RD] = (unsigned64) GPR[RT] >> s;
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-:function:::void:do_dsrlv:int rs, int rt, int rd
-{
-  int s = MASKED64 (GPR[rs], 5, 0);
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = (unsigned64) GPR[rt] >> s;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-
-
-000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
-"dsrlv r<RD>, r<RT>, r<RS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsrlv (SD_, RS, RT, RD);
-}
-
-
-000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
-"dsub r<RD>, r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  {
-    ALU64_BEGIN (GPR[RS]);
-    ALU64_SUB (GPR[RT]);
-    ALU64_END (GPR[RD]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-:function:::void:do_dsubu:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = GPR[rs] - GPR[rt];
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
-"dsubu r<RD>, r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_dsubu (SD_, RS, RT, RD);
-}
-
-
-000010,26.INSTR_INDEX:NORMAL:32::J
-"j <INSTR_INDEX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* NOTE: The region used is that of the delay slot NIA and NOT the
-     current instruction */
-  address_word region = (NIA & MASK (63, 28));
-  DELAY_SLOT (region | (INSTR_INDEX << 2));
-}
-
-
-000011,26.INSTR_INDEX:NORMAL:32::JAL
-"jal <INSTR_INDEX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* NOTE: The region used is that of the delay slot and NOT the
-     current instruction */
-  address_word region = (NIA & MASK (63, 28));
-  GPR[31] = CIA + 8;
-  DELAY_SLOT (region | (INSTR_INDEX << 2));
-}
-
-000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
-"jalr r<RS>":RD == 31
-"jalr r<RD>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word temp = GPR[RS];
-  GPR[RD] = CIA + 8;
-  DELAY_SLOT (temp);
-}
-
-
-000000,5.RS,000000000000000,001000:SPECIAL:32::JR
-"jr r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  DELAY_SLOT (GPR[RS]);
-}
-
-
-:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
-  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  if ((vaddr & access) != 0)
-    {
-      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
-    }
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
-  byte = ((vaddr & mask) ^ bigendiancpu);
-  return (memval >> (8 * byte));
-}
-
-:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? -1 : 0);
-  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
-  unsigned int byte;
-  unsigned int word;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-  int nr_lhs_bits;
-  int nr_rhs_bits;
-  unsigned_word lhs_mask;
-  unsigned_word temp;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
-  paddr = (paddr ^ (reverseendian & mask));
-  if (BigEndianMem == 0)
-    paddr = paddr & ~access;
-
-  /* compute where within the word/mem we are */
-  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
-  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
-  nr_lhs_bits = 8 * byte + 8;
-  nr_rhs_bits = 8 * access - 8 * byte;
-  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
-
-  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
-	   (long) ((unsigned64) vaddr >> 32), (long) vaddr,
-	   (long) ((unsigned64) paddr >> 32), (long) paddr,
-	   word, byte, nr_lhs_bits, nr_rhs_bits); */
-
-  LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
-  if (word == 0)
-    {
-      /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
-      temp = (memval << nr_rhs_bits);
-    }
-  else
-    {
-      /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
-      temp = (memval >> nr_lhs_bits);
-    }
-  lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
-  rt = (rt & ~lhs_mask) | (temp & lhs_mask);
-
-  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
-	   (long) ((unsigned64) memval >> 32), (long) memval,
-	   (long) ((unsigned64) temp >> 32), (long) temp,
-	   (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
-	   (long) (rt >> 32), (long) rt); */
-  return rt;
-}
-
-:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? -1 : 0);
-  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
-  /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
-  paddr = (paddr ^ (reverseendian & mask));
-  if (BigEndianMem != 0)
-    paddr = paddr & ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
-  LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
-  /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
-     (long) paddr, byte, (long) paddr, (long) memval); */
-  {
-    unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
-    rt &= ~screen;
-    rt |= (memval >> (8 * byte)) & screen;
-  }
-  return rt;
-}
-
-
-100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
-"lb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
-"lbu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
-}
-
-
-110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
-"ld r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
-"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-
-
-011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
-"ldl r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
-"ldr r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
-"lh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
-"lhu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
-}
-
-
-110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
-"ll r<RT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      {
-        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
-      }
-    else
-      {
-	if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-	  {
-	    unsigned64 memval = 0;
-	    unsigned64 memval1 = 0;
-	    unsigned64 mask = 0x7;
-	    unsigned int shift = 2;
-	    unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-	    unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-	    unsigned int byte;
-	    paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-	    LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
-	    byte = ((vaddr & mask) ^ (bigend << shift));
-	    GPR[RT] = EXTEND32 (memval >> (8 * byte));
-	    LLBIT = 1;
-	  }
-      }
-  }
-}
-
-
-110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
-"lld r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  check_u64 (SD_, instruction_0);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      {
-	SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
-      }
-    else
-      {
-	if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-	  {
-	    unsigned64 memval = 0;
-	    unsigned64 memval1 = 0;
-	    LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
-	    GPR[RT] = memval;
-	    LLBIT = 1;
-	  }
-      }
-  }
-}
-
-
-001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
-"lui r<RT>, %#lx<IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  TRACE_ALU_INPUT1 (IMMEDIATE);
-  GPR[RT] = EXTEND32 (IMMEDIATE << 16);
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
-"lw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
-"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
-"lwl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
-}
-
-
-100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
-"lwr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
-}
-
-
-100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
-"lwu r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
-}
-
-
-
-011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
-"madd r<RS>, r<RT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  signed64 temp;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-          + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
-  LO = EXTEND32 (temp);
-  HI = EXTEND32 (VH4_8 (temp));
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-
-
-011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
-"maddu r<RS>, r<RT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned64 temp;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-          + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
-  LO = EXTEND32 (temp);
-  HI = EXTEND32 (VH4_8 (temp));
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-
-:function:::void:do_mfhi:int rd
-{
-  check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT1 (HI);
-  GPR[rd] = HI;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
-"mfhi r<RD>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_mfhi (SD_, RD);
-}
-
-
-
-:function:::void:do_mflo:int rd
-{
-  check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
-  TRACE_ALU_INPUT1 (LO);
-  GPR[rd] = LO;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
-"mflo r<RD>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_mflo (SD_, RD);
-}
-
-
-
-000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
-"movn r<RD>, r<RS>, r<RT>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  if (GPR[RT] != 0)
-    {
-      GPR[RD] = GPR[RS];
-      TRACE_ALU_RESULT (GPR[RD]);
-    }
-}
-
-
-
-000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
-"movz r<RD>, r<RS>, r<RT>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  if (GPR[RT] == 0)
-    {
-      GPR[RD] = GPR[RS];
-      TRACE_ALU_RESULT (GPR[RD]);
-    }
-}
-
-
-
-011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
-"msub r<RS>, r<RT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  signed64 temp;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-          - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
-  LO = EXTEND32 (temp);
-  HI = EXTEND32 (VH4_8 (temp));
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-
-
-011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
-"msubu r<RS>, r<RT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  unsigned64 temp;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-          - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
-  LO = EXTEND32 (temp);
-  HI = EXTEND32 (VH4_8 (temp));
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-
-
-000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
-"mthi r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_mt_hilo (SD_, HIHISTORY);
-  HI = GPR[RS];
-}
-
-
-
-000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
-"mtlo r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_mt_hilo (SD_, LOHISTORY);
-  LO = GPR[RS];
-}
-
-
-
-011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
-"mul r<RD>, r<RS>, r<RT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5500:
-{
-  signed64 prod;
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  prod = (((signed64)(signed32) GPR[RS])
-          * ((signed64)(signed32) GPR[RT]));
-  GPR[RD] = EXTEND32 (VL4_8 (prod));
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-
-:function:::void:do_mult:int rs, int rt, int rd
-{
-  signed64 prod;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  prod = (((signed64)(signed32) GPR[rs])
-	  * ((signed64)(signed32) GPR[rt]));
-  LO = EXTEND32 (VL4_8 (prod));
-  HI = EXTEND32 (VH4_8 (prod));
-  if (rd != 0)
-    GPR[rd] = LO;
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
-"mult r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-{
-  do_mult (SD_, RS, RT, 0);
-}
-
-
-000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
-"mult r<RS>, r<RT>":RD == 0
-"mult r<RD>, r<RS>, r<RT>"
-*vr5000:
-*r3900:
-{
-  do_mult (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_multu:int rs, int rt, int rd
-{
-  unsigned64 prod;
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  prod = (((unsigned64)(unsigned32) GPR[rs])
-	  * ((unsigned64)(unsigned32) GPR[rt]));
-  LO = EXTEND32 (VL4_8 (prod));
-  HI = EXTEND32 (VH4_8 (prod));
-  if (rd != 0)
-    GPR[rd] = LO;
-  TRACE_ALU_RESULT2 (HI, LO);
-}
-
-000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
-"multu r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-{
-  do_multu (SD_, RS, RT, 0);
-}
-
-000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
-"multu r<RS>, r<RT>":RD == 0
-"multu r<RD>, r<RS>, r<RT>"
-*vr5000:
-*r3900:
-{
-  do_multu (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_nor:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = ~ (GPR[rs] | GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
-"nor r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_nor (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_or:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = (GPR[rs] | GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
-"or r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_or (SD_, RS, RT, RD);
-}
-
-
-
-:function:::void:do_ori:int rs, int rt, unsigned immediate
-{
-  TRACE_ALU_INPUT2 (GPR[rs], immediate);
-  GPR[rt] = (GPR[rs] | immediate);
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
-"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_ori (SD_, RS, RT, IMMEDIATE);
-}
-
-
-110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
-"pref <HINT>, <OFFSET>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-	Prefetch(uncached,paddr,vaddr,isDATA,HINT);
-    }
-  }
-}
-
-
-:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
-{
-  unsigned64 result;
-
-  y &= 31;
-  TRACE_ALU_INPUT2 (x, y);
-  result = EXTEND32 (ROTR32 (x, y));
-  TRACE_ALU_RESULT (result);
-  return result;
-}
-
-000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
-"ror r<RD>, r<RT>, <SHIFT>"
-*mips32r2:
-*mips64r2:
-*vr5400:
-*vr5500:
-{
-  GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
-}
-
-000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
-"rorv r<RD>, r<RT>, r<RS>"
-*mips32r2:
-*mips64r2:
-*vr5400:
-*vr5500:
-{
-  GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
-}
-
-
-:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
-  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  if ((vaddr & access) != 0)
-    {
-      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
-    }
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  byte = ((vaddr & mask) ^ bigendiancpu);
-  memval = (word << (8 * byte));
-  StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
-}
-
-:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? -1 : 0);
-  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
-  unsigned int byte;
-  unsigned int word;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-  int nr_lhs_bits;
-  int nr_rhs_bits;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
-  paddr = (paddr ^ (reverseendian & mask));
-  if (BigEndianMem == 0)
-    paddr = paddr & ~access;
-
-  /* compute where within the word/mem we are */
-  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
-  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
-  nr_lhs_bits = 8 * byte + 8;
-  nr_rhs_bits = 8 * access - 8 * byte;
-  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
-  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
-	   (long) ((unsigned64) vaddr >> 32), (long) vaddr,
-	   (long) ((unsigned64) paddr >> 32), (long) paddr,
-	   word, byte, nr_lhs_bits, nr_rhs_bits); */
-
-  if (word == 0)
-    {
-      memval = (rt >> nr_rhs_bits);
-    }
-  else
-    {
-      memval = (rt << nr_lhs_bits);
-    }
-  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
-	   (long) ((unsigned64) rt >> 32), (long) rt,
-	   (long) ((unsigned64) memval >> 32), (long) memval); */
-  StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
-}
-
-:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
-{
-  address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-  address_word reverseendian = (ReverseEndian ? -1 : 0);
-  address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  address_word vaddr;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
-  paddr = (paddr ^ (reverseendian & mask));
-  if (BigEndianMem != 0)
-    paddr &= ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  memval = (rt << (byte * 8));
-  StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
-}
-
-
-101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
-"sb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
-"sc r<RT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  unsigned32 instruction = instruction_0;
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      {
-	SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
-      }
-    else
-      {
-	if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-	  {
-	    unsigned64 memval = 0;
-	    unsigned64 memval1 = 0;
-	    unsigned64 mask = 0x7;
-	    unsigned int byte;
-	    paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-	    byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
-	    memval = ((unsigned64) GPR[RT] << (8 * byte));
-	    if (LLBIT)
-	      {
-		StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-	      }
-	    GPR[RT] = LLBIT;
-	  }
-      }
-  }
-}
-
-
-111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
-"scd r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  check_u64 (SD_, instruction_0);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 7) != 0)
-      {
-	SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
-      }
-    else
-      {
-	if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-	  {
-	    unsigned64 memval = 0;
-	    unsigned64 memval1 = 0;
-	    memval = GPR[RT];
-	    if (LLBIT)
-	      {
-		StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
-	      }
-	    GPR[RT] = LLBIT;
-	  }
-      }
-  }
-}
-
-
-111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
-"sd r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
-"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
-}
-
-
-101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
-"sdl r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
-"sdr r<RT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  check_u64 (SD_, instruction_0);
-  do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-
-101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
-"sh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-:function:::void:do_sll:int rt, int rd, int shift
-{
-  unsigned32 temp = (GPR[rt] << shift);
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
-"nop":RD == 0 && RT == 0 && SHIFT == 0
-"sll r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* Skip shift for NOP, so that there won't be lots of extraneous
-     trace output.  */
-  if (RD != 0 || RT != 0 || SHIFT != 0)
-    do_sll (SD_, RT, RD, SHIFT);
-}
-
-000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
-"nop":RD == 0 && RT == 0 && SHIFT == 0
-"ssnop":RD == 0 && RT == 0 && SHIFT == 1
-"sll r<RD>, r<RT>, <SHIFT>"
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-{
-  /* Skip shift for NOP and SSNOP, so that there won't be lots of
-     extraneous trace output.  */
-  if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
-    do_sll (SD_, RT, RD, SHIFT);
-}
-
-
-:function:::void:do_sllv:int rs, int rt, int rd
-{
-  int s = MASKED (GPR[rs], 4, 0);
-  unsigned32 temp = (GPR[rt] << s);
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
-"sllv r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_sllv (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_slt:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
-"slt r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_slt (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_slti:int rs, int rt, unsigned16 immediate
-{
-  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
-  GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
-"slti r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_slti (SD_, RS, RT, IMMEDIATE);
-}
-
-
-:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
-{
-  TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
-  GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
-"sltiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_sltiu (SD_, RS, RT, IMMEDIATE);
-}
-
-
-
-:function:::void:do_sltu:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
-"sltu r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_sltu (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_sra:int rt, int rd, int shift
-{
-  signed32 temp = (signed32) GPR[rt] >> shift;
-  if (NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
-"sra r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_sra (SD_, RT, RD, SHIFT);
-}
-
-
-
-:function:::void:do_srav:int rs, int rt, int rd
-{
-  int s = MASKED (GPR[rs], 4, 0);
-  signed32 temp = (signed32) GPR[rt] >> s;
-  if (NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
-"srav r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_srav (SD_, RS, RT, RD);
-}
-
-
-
-:function:::void:do_srl:int rt, int rd, int shift
-{
-  unsigned32 temp = (unsigned32) GPR[rt] >> shift;
-  if (NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rt], shift);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
-"srl r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_srl (SD_, RT, RD, SHIFT);
-}
-
-
-:function:::void:do_srlv:int rs, int rt, int rd
-{
-  int s = MASKED (GPR[rs], 4, 0);
-  unsigned32 temp = (unsigned32) GPR[rt] >> s;
-  if (NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = EXTEND32 (temp);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
-"srlv r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_srlv (SD_, RS, RT, RD);
-}
-
-
-000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
-"sub r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  {
-    ALU32_BEGIN (GPR[RS]);
-    ALU32_SUB (GPR[RT]);
-    ALU32_END (GPR[RD]);   /* This checks for overflow.  */
-  }
-  TRACE_ALU_RESULT (GPR[RD]);
-}
-
-
-:function:::void:do_subu:int rs, int rt, int rd
-{
-  if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
-    Unpredictable ();
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
-"subu r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_subu (SD_, RS, RT, RD);
-}
-
-
-101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
-"sw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*r3900:
-*vr5000:
-{
-  do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
-"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
-}
-
-
-101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
-"swl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
-"swr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
-}
-
-
-000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
-"sync":STYPE == 0
-"sync <STYPE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  SyncOperation (STYPE);
-}
-
-
-000000,20.CODE,001100:SPECIAL:32::SYSCALL
-"syscall %#lx<CODE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  SignalException (SystemCall, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
-"teq r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
-"teqi r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
-"tge r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
-"tgei r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
-"tgeiu r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
-"tgeu r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
-"tlt r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
-"tlti r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
-"tltiu r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
-"tltu r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
-"tne r<RS>, r<RT>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    SignalException (Trap, instruction_0);
-}
-
-
-000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tnei r<RS>, <IMMEDIATE>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
-    SignalException (Trap, instruction_0);
-}
-
-
-:function:::void:do_xor:int rs, int rt, int rd
-{
-  TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  GPR[rd] = GPR[rs] ^ GPR[rt];
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
-"xor r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_xor (SD_, RS, RT, RD);
-}
-
-
-:function:::void:do_xori:int rs, int rt, unsigned16 immediate
-{
-  TRACE_ALU_INPUT2 (GPR[rs], immediate);
-  GPR[rt] = GPR[rs] ^ immediate;
-  TRACE_ALU_RESULT (GPR[rt]);
-}
-
-001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
-"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  do_xori (SD_, RS, RT, IMMEDIATE);
-}
-
-
-//
-// MIPS Architecture:
-//
-//        FPU Instruction Set (COP1 & COP1X)
-//
-
-
-:%s::::FMT:int fmt
-{
-  switch (fmt)
-    {
-    case fmt_single: return "s";
-    case fmt_double: return "d";
-    case fmt_word: return "w";
-    case fmt_long: return "l";
-    case fmt_ps: return "ps";
-    default: return "?";
-    }
-}
-
-:%s::::TF:int tf
-{
-  if (tf)
-    return "t";
-  else
-    return "f";
-}
-
-:%s::::ND:int nd
-{
-  if (nd)
-    return "l";
-  else
-    return "";
-}
-
-:%s::::COND:int cond
-{
-  switch (cond)
-    {
-    case 00: return "f";
-    case 01: return "un";
-    case 02: return "eq";
-    case 03: return "ueq";
-    case 04: return "olt";
-    case 05: return "ult";
-    case 06: return "ole";
-    case 07: return "ule";
-    case 010: return "sf";
-    case 011: return "ngle";
-    case 012: return "seq";
-    case 013: return "ngl";
-    case 014: return "lt";
-    case 015: return "nge";
-    case 016: return "le";
-    case 017: return "ngt";
-    default: return "?";
-    }
-}
-
-
-// Helpers:
-//
-// Check that the given FPU format is usable, and signal a
-// ReservedInstruction exception if not.
-//
-
-// check_fmt_p checks that the format is single, double, or paired single.
-:function:::void:check_fmt_p:int fmt, instruction_word insn
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mips32:
-*mips32r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  /* None of these ISAs support Paired Single, so just fall back to
-     the single/double check.  */
-  if ((fmt != fmt_single) && (fmt != fmt_double))
-    SignalException (ReservedInstruction, insn);
-}
-
-:function:::void:check_fmt_p:int fmt, instruction_word insn
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  if ((fmt != fmt_single) && (fmt != fmt_double)
-      && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
-    SignalException (ReservedInstruction, insn);
-}
-
-
-// Helper:
-//
-// Check that the FPU is currently usable, and signal a CoProcessorUnusable
-// exception if not.
-//
-
-:function:::void:check_fpu:
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  if (! COP_Usable (1))
-    SignalExceptionCoProcessorUnusable (1);
-}
-
-
-// Helper:
-//
-// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
-// or MIPS32.  do_load cannot be used instead because it returns an
-// unsigned_word, which is limited to the size of the machine's registers.
-//
-
-:function:::unsigned64:do_load_double:address_word base, address_word offset
-*mipsII:
-*mips32:
-*mips32r2:
-{
-  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
-  address_word vaddr;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-  unsigned64 v;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
-    {
-      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
-		       AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
-		       sim_core_unaligned_signal);
-    }
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
-		      isREAL);
-  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
-	      isDATA, isREAL);
-  v = (unsigned64)memval;
-  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
-	      isDATA, isREAL);
-  return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
-}
-
-
-// Helper:
-//
-// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
-// or MIPS32.  do_load cannot be used instead because it returns an
-// unsigned_word, which is limited to the size of the machine's registers.
-//
-
-:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
-*mipsII:
-*mips32:
-*mips32r2:
-{
-  int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
-  address_word vaddr;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-
-  vaddr = loadstore_ea (SD_, base, offset);
-  if ((vaddr & AccessLength_DOUBLEWORD) != 0)
-    {
-      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
-		       AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
-		       sim_core_unaligned_signal);
-    }
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
-		      isREAL);
-  memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
-  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
-	       isREAL);
-  memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
-  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
-	       isREAL);
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
-"abs.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
-}
-
-
-
-010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
-"add.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
-"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  unsigned64 fs;
-  unsigned64 ft;
-  unsigned64 fd;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  fs = ValueFPR (FS, fmt_ps);
-  if ((GPR[RS] & 0x3) != 0)
-    Unpredictable ();
-  if ((GPR[RS] & 0x4) == 0)
-    fd = fs;
-  else
-    {
-      ft = ValueFPR (FT, fmt_ps);
-      if (BigEndianCPU)
-	fd = PackPS (PSLower (fs), PSUpper (ft));
-      else
-	fd = PackPS (PSLower (ft), PSUpper (fs));
-    }
-  StoreFPR (FD, fmt_ps, fd);
-}
-
-
-// BC1F
-// BC1FL
-// BC1T
-// BC1TL
-
-010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
-"bc1%s<TF>%s<ND> <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{
-  check_fpu (SD_);
-  TRACE_BRANCH_INPUT (PREVCOC1());
-  if (PREVCOC1() == TF)
-    {
-      address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
-      TRACE_BRANCH_RESULT (dest);
-      DELAY_SLOT (dest);
-    }
-  else if (ND)
-    {
-      TRACE_BRANCH_RESULT (0);
-      NULLIFY_NEXT_INSTRUCTION ();
-    }
-  else
-    {
-      TRACE_BRANCH_RESULT (NIA);
-    }
-}
-
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
-"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
-"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-#*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  if (GETFCC(CC) == TF)
-    {
-      address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
-      DELAY_SLOT (dest);
-    }
-  else if (ND)
-    {
-      NULLIFY_NEXT_INSTRUCTION ();
-    }
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
-  TRACE_ALU_RESULT (ValueFCR (31));
-}
-
-010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
-"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
-  TRACE_ALU_RESULT (ValueFCR (31));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
-"ceil.l.%s<FMT> f<FD>, f<FS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
-	    fmt_long));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
-"ceil.w.%s<FMT> f<FD>, f<FS>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
-	    fmt_word));
-}
-
-
-010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
-"cfc1 r<RT>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{
-  check_fpu (SD_);
-  if (FS == 0)
-    PENDING_FILL (RT, EXTEND32 (FCR0));
-  else if (FS == 31)
-    PENDING_FILL (RT, EXTEND32 (FCR31));
-  /* else NOP */
-}
-
-010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
-"cfc1 r<RT>, f<FS>"
-*mipsIV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  if (FS == 0 || FS == 31)
-    {
-      unsigned_word  fcr = ValueFCR (FS);
-      TRACE_ALU_INPUT1 (fcr);
-      GPR[RT] = fcr;
-    }
-  /* else NOP */
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
-"cfc1 r<RT>, f<FS>"
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
-    {
-      unsigned_word  fcr = ValueFCR (FS);
-      TRACE_ALU_INPUT1 (fcr);
-      GPR[RT] = fcr;
-    }
-  /* else NOP */
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
-"ctc1 r<RT>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{
-  check_fpu (SD_);
-  if (FS == 31)
-    PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
-  /* else NOP */
-}
-
-010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
-"ctc1 r<RT>, f<FS>"
-*mipsIV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  if (FS == 31)
-    StoreFCR (FS, GPR[RT]);
-  /* else NOP */
-}
-
-010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
-"ctc1 r<RT>, f<FS>"
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
-      StoreFCR (FS, GPR[RT]);
-  /* else NOP */
-}
-
-
-//
-// FIXME: Does not correctly differentiate between mips*
-//
-010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
-"cvt.d.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  if ((fmt == fmt_double) | 0)
-    SignalException (ReservedInstruction, instruction_0);
-  StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
-	    fmt_double));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
-"cvt.l.%s<FMT> f<FD>, f<FS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
-    SignalException (ReservedInstruction, instruction_0);
-  StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
-	    fmt_long));
-}
-
-
-010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
-"cvt.ps.s f<FD>, f<FS>, f<FT>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
-				ValueFPR (FT, fmt_single)));
-}
-
-
-//
-// FIXME: Does not correctly differentiate between mips*
-//
-010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
-"cvt.s.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  if ((fmt == fmt_single) | 0)
-    SignalException (ReservedInstruction, instruction_0);
-  StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
-	    fmt_single));
-}
-
-
-010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
-"cvt.s.pl f<FD>, f<FS>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
-}
-
-
-010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
-"cvt.s.pu f<FD>, f<FS>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
-"cvt.w.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
-    SignalException (ReservedInstruction, instruction_0);
-  StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
-	    fmt_word));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
-"div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
-"dmfc1 r<RT>, f<FS>"
-*mipsIII:
-{
-  unsigned64 v;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if (SizeFGR () == 64)
-    v = FGR[FS];
-  else if ((FS & 0x1) == 0)
-    v = SET64HI (FGR[FS+1]) | FGR[FS];
-  else
-    v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
-  PENDING_FILL (RT, v);
-  TRACE_ALU_RESULT (v);
-}
-
-010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
-"dmfc1 r<RT>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if (SizeFGR () == 64)
-    GPR[RT] = FGR[FS];
-  else if ((FS & 0x1) == 0)
-    GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
-  else
-    GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
-"dmtc1 r<RT>, f<FS>"
-*mipsIII:
-{
-  unsigned64 v;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if (SizeFGR () == 64)
-    PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
-  else if ((FS & 0x1) == 0)
-    {
-      PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
-      PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
-    }
-  else
-    Unpredictable ();
-  TRACE_FP_RESULT (GPR[RT]);
-}
-
-010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
-"dmtc1 r<RT>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if (SizeFGR () == 64)
-    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
-  else if ((FS & 0x1) == 0)
-    StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
-  else
-    Unpredictable ();
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
-"floor.l.%s<FMT> f<FD>, f<FS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
-	    fmt_long));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
-"floor.w.%s<FMT> f<FD>, f<FS>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
-	    fmt_word));
-}
-
-
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
-"ldc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mips32:
-*mips32r2:
-{
-  check_fpu (SD_);
-  COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
-"ldc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
-"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
-}
-
-
-010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
-"luxc1 f<FD>, r<INDEX>(r<BASE>)"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  address_word base = GPR[BASE];
-  address_word index = GPR[INDEX];
-  address_word vaddr = base + index;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
-  if ((vaddr & 0x7) != 0)
-    index -= (vaddr & 0x7);
-  COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
-}
-
-
-110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
-"lwc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
-}
-
-
-010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
-"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
-}
-
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
-"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0); 
-  StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
-				  ValueFPR (FR, fmt), fmt));
-}
-
-
-010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
-"mfc1 r<RT>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{
-  unsigned64 v;
-  check_fpu (SD_);
-  v = EXTEND32 (FGR[FS]);
-  PENDING_FILL (RT, v);
-  TRACE_ALU_RESULT (v);
-}
-  
-010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
-"mfc1 r<RT>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{ 
-  check_fpu (SD_);
-  GPR[RT] = EXTEND32 (FGR[FS]);
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
-"mov.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, ValueFPR (FS, fmt));
-}
-
-
-// MOVF
-// MOVT
-000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
-"mov%s<TF> r<RD>, r<RS>, <CC>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  if (GETFCC(CC) == TF)
-    GPR[RD] = GPR[RS];
-}
-
-
-// MOVF.fmt
-// MOVT.fmt
-010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
-"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  if (fmt != fmt_ps)
-    {
-      if (GETFCC(CC) == TF)
-	StoreFPR (FD, fmt, ValueFPR (FS, fmt));
-      else
-	StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
-    }
-  else
-    {
-      unsigned64 fd;
-      fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
-				      fmt_ps)),
-		   PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
-				      fmt_ps)));
-      StoreFPR (FD, fmt_ps, fd);
-    }
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
-"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  if (GPR[RT] != 0)
-    StoreFPR (FD, FMT, ValueFPR (FS, FMT));
-  else
-    StoreFPR (FD, FMT, ValueFPR (FD, FMT));
-}
-
-
-// MOVT see MOVtf
-
-
-// MOVT.fmt see MOVtf.fmt
-
-
-
-010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
-"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  if (GPR[RT] == 0)
-    StoreFPR (FD, FMT, ValueFPR (FS, FMT));
-  else
-    StoreFPR (FD, FMT, ValueFPR (FD, FMT));
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
-"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
-				  ValueFPR (FR, fmt), fmt));
-}
-
-
-010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
-"mtc1 r<RT>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-{ 
-  check_fpu (SD_);
-  if (SizeFGR () == 64)
-    PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
-  else
-    PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
-  TRACE_FP_RESULT (GPR[RT]);
-} 
-
-010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
-"mtc1 r<RT>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_); 
-  StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
-"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
-"neg.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
-"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
-				     ValueFPR (FR, fmt), fmt));
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
-"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
-				     ValueFPR (FR, fmt), fmt));
-}
-
-
-010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
-"pll.ps f<FD>, f<FS>, f<FT>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
-				PSLower (ValueFPR (FT, fmt_ps))));
-}
-
-
-010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
-"plu.ps f<FD>, f<FS>, f<FT>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
-				PSUpper (ValueFPR (FT, fmt_ps))));
-}
-
-
-010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
-"prefx <HINT>, r<INDEX>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  address_word base = GPR[BASE];
-  address_word index = GPR[INDEX];
-  {
-    address_word vaddr = loadstore_ea (SD_, base, index);
-    address_word paddr;
-    int uncached;
-    if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-      Prefetch(uncached,paddr,vaddr,isDATA,HINT);
-  }
-}
-
-
-010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
-"pul.ps f<FD>, f<FS>, f<FT>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
-				PSLower (ValueFPR (FT, fmt_ps))));
-}
-
-
-010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
-"puu.ps f<FD>, f<FS>, f<FT>"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
-				PSUpper (ValueFPR (FT, fmt_ps))));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
-"recip.%s<FMT> f<FD>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
-"round.l.%s<FMT> f<FD>, f<FS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
-	    fmt_long));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
-"round.w.%s<FMT> f<FD>, f<FS>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
-	    fmt_word));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
-"rsqrt.%s<FMT> f<FD>, f<FS>"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
-}
-
-
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
-"sdc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsII:
-*mips32:
-*mips32r2:
-{
-  check_fpu (SD_);
-  do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
-}
-
-
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
-"sdc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  check_fpu (SD_);
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
-}
-
-
-010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
-"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
-}
-
-
-010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
-"suxc1 f<FS>, r<INDEX>(r<BASE>)"
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  unsigned64 v;
-  address_word base = GPR[BASE];
-  address_word index = GPR[INDEX];
-  address_word vaddr = base + index;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
-  if ((vaddr & 0x7) != 0)
-    index -= (vaddr & 0x7);
-  do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
-"sqrt.%s<FMT> f<FD>, f<FS>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
-}
-
-
-010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
-"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-
-111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
-"swc1 f<FT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  check_fpu (SD_);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if ((vaddr & 3) != 0)
-      {
-	SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
-      }
-    else
-      {
-	if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-	  {
-	    uword64 memval = 0;
-	    uword64 memval1 = 0;
-	    uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-	    address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
-	    address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
-	    unsigned int byte;
-	    paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-	    byte = ((vaddr & mask) ^ bigendiancpu);
-	    memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
-	    StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-	  }
-      }
-  }
-}
-
-
-010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
-"swxc1 f<FS>, r<INDEX>(r<BASE>)"
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr5000:
-{
-
-  address_word base = GPR[BASE];
-  address_word index = GPR[INDEX];
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  {
-   address_word vaddr = loadstore_ea (SD_, base, index);
-   address_word paddr;
-   int uncached;
-   if ((vaddr & 3) != 0)
-     {
-       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
-     }
-   else
-   {
-    if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-    {
-     unsigned64 memval = 0;
-     unsigned64 memval1 = 0;
-     unsigned64 mask = 0x7;
-     unsigned int byte;
-     paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-     byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
-     memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
-      {
-       StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-      }
-    }
-   }
-  }
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
-"trunc.l.%s<FMT> f<FD>, f<FS>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
-	    fmt_long));
-}
-
-
-010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
-"trunc.w.%s<FMT> f<FD>, f<FS>"
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
-	    fmt_word));
-}
-
-
-//
-// MIPS Architecture:
-//
-//        System Control Instruction Set (COP0)
-//
-
-
-010000,01000,00000,16.OFFSET:COP0:32::BC0F
-"bc0f <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-010000,01000,00000,16.OFFSET:COP0:32::BC0F
-"bc0f <OFFSET>"
-// stub needed for eCos as tx39 hardware bug workaround
-*r3900:
-{
-  /* do nothing */
-}
-
-
-010000,01000,00010,16.OFFSET:COP0:32::BC0FL
-"bc0fl <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-010000,01000,00001,16.OFFSET:COP0:32::BC0T
-"bc0t <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-
-
-010000,01000,00011,16.OFFSET:COP0:32::BC0TL
-"bc0tl <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
-"cache <OP>, <OFFSET>(r<BASE>)"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  address_word base = GPR[BASE];
-  address_word offset = EXTEND16 (OFFSET);
-  {
-    address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-      CacheOp(OP,vaddr,paddr,instruction_0);
-  }
-}
-
-
-010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
-"dmfc0 r<RT>, r<RD>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  DecodeCoproc (instruction_0);
-}
-
-
-010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
-"dmtc0 r<RT>, r<RD>"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  DecodeCoproc (instruction_0);
-}
-
-
-010000,1,0000000000000000000,011000:COP0:32::ERET
-"eret"
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-{
-  if (SR & status_ERL)
-    {
-      /* Oops, not yet available */
-      sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
-      NIA = EPC;
-      SR &= ~status_ERL;
-    }
-  else
-    {
-      NIA = EPC;
-      SR &= ~status_EXL;
-    }
-}
-
-
-010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
-"mfc0 r<RT>, r<RD> # <REGX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  TRACE_ALU_INPUT0 ();
-  DecodeCoproc (instruction_0);
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
-"mtc0 r<RT>, r<RD> # <REGX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  DecodeCoproc (instruction_0);
-}
-
-
-010000,1,0000000000000000000,010000:COP0:32::RFE
-"rfe"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-*r3900:
-{
-  DecodeCoproc (instruction_0);
-}
-
-
-0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*r3900:
-{
-  DecodeCoproc (instruction_0);
-}
-
-
-
-010000,1,0000000000000000000,001000:COP0:32::TLBP
-"tlbp"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-010000,1,0000000000000000000,000001:COP0:32::TLBR
-"tlbr"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-010000,1,0000000000000000000,000010:COP0:32::TLBWI
-"tlbwi"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-010000,1,0000000000000000000,000110:COP0:32::TLBWR
-"tlbwr"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips32r2:
-*mips64:
-*mips64r2:
-*vr4100:
-*vr5000:
-
-
-:include:::mips3264r2.igen
-:include:::m16.igen
-:include:::m16e.igen
-:include:::mdmx.igen
-:include:::mips3d.igen
-:include:::sb1.igen
-:include:::tx.igen
-:include:::vr.igen
-:include:::dsp.igen
-
diff --git a/sim/mips/mips3264r2.igen b/sim/mips/mips3264r2.igen
deleted file mode 100644
index e0d1326..0000000
--- a/sim/mips/mips3264r2.igen
+++ /dev/null
@@ -1,260 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the MIPS 32/64 revision 2 instructions.
-// Copyright (C) 2004 Free Software Foundation, Inc.
-// Contributed by David Ung, of MIPS Technologies.
-//
-// This file is part of GDB, the GNU debugger.
-// 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-
-011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
-"dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
-  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
-"dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
-  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
-"dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
-  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-010000,01011,5.RT,01100,00000,0,00,000::32::DI
-"di":RT == 0
-"di r<RT>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT0 ();
-  GPR[RT] = EXTEND32 (SR);
-  SR &= ~status_IE;
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
-"dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
-  if (LSB <= MSB)
-    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
-"dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
-  if (LSB <= MSB + 32)
-    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
-"dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
-*mips64r2:
-{
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
-  if (LSB <= MSB)
-    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32)))
-      & MASK64 (MSB + 32, LSB + 32);
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-011111,00000,5.RT,5.RD,00010,100100::64::DSBH
-"dsbh r<RD>, r<RT>"
-*mips64r2:
-{
-  union { unsigned64 d; unsigned16 h[4]; } u;
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  u.d = GPR[RT];
-  u.h[0] = SWAP_2 (u.h[0]);
-  u.h[1] = SWAP_2 (u.h[1]);
-  u.h[2] = SWAP_2 (u.h[2]);
-  u.h[3] = SWAP_2 (u.h[3]);
-  GPR[RD] = u.d;
-  TRACE_ALU_RESULT1 (GPR[RD]);
-}
-
-011111,00000,5.RT,5.RD,00101,100100::64::DSHD
-"dshd r<RD>, r<RT>"
-*mips64r2:
-{
-  unsigned64 d;
-  check_u64 (SD_, instruction_0);
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  d = GPR[RT];
-  GPR[RD] = ((d >> 48)
-	     | (d << 48)
-	     | ((d & 0x0000ffff00000000) >> 16)
-	     | ((d & 0x00000000ffff0000) << 16));
-  TRACE_ALU_RESULT1 (GPR[RD]);
-}
-
-
-010000,01011,5.RT,01100,00000,1,00,000::32::EI
-"ei":RT == 0
-"ei r<RT>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT0 ();
-  GPR[RT] = EXTEND32 (SR);
-  SR |= status_IE;
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
-"ext r<RT>, r<RS>, <LSB>, <SIZE+1>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
-  GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB));
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
-"mfhc1 r<RT>, f<FS>"
-*mips32r2:
-*mips64r2:
-{
-  check_fpu (SD_);
-  if (SizeFGR() == 64)
-    GPR[RT] = EXTEND32 (WORD64HI (FGR[FS]));
-  else if ((FS & 0x1) == 0)
-    GPR[RT] = EXTEND32 (FGR[FS + 1]);
-  else
-    {
-      if (STATE_VERBOSE_P(SD))
-	sim_io_eprintf (SD, 
-	         "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
-			(long) CIA);
-      GPR[RT] = EXTEND32 (0xBADF00D);
-    }
-  TRACE_ALU_RESULT (GPR[RT]);
-}
-
-010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
-"mthc1 r<RT>, f<FS>"
-*mips32r2:
-*mips64r2:
-{
-  check_fpu (SD_); 
-  if (SizeFGR() == 64)
-    StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS]));
-  else if ((FS & 0x1) == 0)
-    StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
-  else
-    {
-      if (STATE_VERBOSE_P(SD))
-	sim_io_eprintf (SD, 
-	         "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
-			(long) CIA);
-      StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE);
-    }
-  TRACE_FP_RESULT (GPR[RT]);
-}
-
-
-011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
-"ins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
-  if (LSB <= MSB)
-    GPR[RT] = EXTEND32 (GPR[RT] ^
-			((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB)));
-  TRACE_ALU_RESULT1 (GPR[RT]);
-}
-
-
-011111,00000,5.RT,5.RD,10000,100000::32::SEB
-"seb r<RD>, r<RT>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  GPR[RD] = EXTEND8 (GPR[RT]);
-  TRACE_ALU_RESULT1 (GPR[RD]);
-}
-
-011111,00000,5.RT,5.RD,11000,100000::32::SEH
-"seh r<RD>, r<RT>"
-*mips32r2:
-*mips64r2:
-{
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  GPR[RD] = EXTEND16 (GPR[RT]);
-  TRACE_ALU_RESULT1 (GPR[RD]);
-}
-
-
-000001,5.BASE,11111,16.OFFSET::32::SYNCI
-"synci <OFFSET>(r<BASE>)"
-*mips32r2:
-*mips64r2:
-{
-  // sync i-cache - nothing to do currently
-}
-
-
-011111,00000,5.RT,5.RD,00010,100000::32::WSBH
-"wsbh r<RD>, r<RT>"
-*mips32r2:
-*mips64r2:
-{
-  union { unsigned32 w; unsigned16 h[2]; } u;
-  TRACE_ALU_INPUT1 (GPR[RT]);
-  u.w = GPR[RT];
-  u.h[0] = SWAP_2 (u.h[0]);
-  u.h[1] = SWAP_2 (u.h[1]);
-  GPR[RD] = EXTEND32 (u.w);
-  TRACE_ALU_RESULT1 (GPR[RD]);
-}
-
-
-
diff --git a/sim/mips/mips3d.igen b/sim/mips/mips3d.igen
deleted file mode 100644
index d24a06c..0000000
--- a/sim/mips/mips3d.igen
+++ /dev/null
@@ -1,177 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the MIPS MIPS-3D ASE.
-// Copyright (C) 2002 Free Software Foundation, Inc.
-// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
-// Corporation (SiByte).
-//
-// This file is part of GDB, the GNU debugger.
-// 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-//  Reference: MIPS64 Architecture for Programmers Volume IV-c:
-//             The MIPS-3D Application-Specific Extension to the
-//             MIPS64 Architecture.  (MIPS Document MD00099)
-
-
-010001,10,110,5.FT,5.FS,5.FD,011000:COP1:64,f::ADDR.PS
-"addr.ps f<FD>, f<FS>, f<FT>"
-*mips3d:
-{
-  /* fd.PL = ft.PU + ft.PL;  fd.PU = fs.PU + fs.PL;  */
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, AddR (ValueFPR (FS, fmt_ps),
-			      ValueFPR (FT, fmt_ps), fmt_ps));
-}
-
-
-010001,01001,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY2tf
-"bc1any2%s<TF> <CC>, %#lx<OFFSET>"
-*mips3d:
-{
-  address_word offset;
-  int cc = CC;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if ((cc & 0x1) != 0)
-    Unpredictable ();
-  if ((GETFCC (cc) == TF) || (GETFCC (cc + 1) == TF))
-    {
-      offset = (EXTEND16 (OFFSET) << 2);
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-010001,01010,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY4tf
-"bc1any4%s<TF> <CC>, %#lx<OFFSET>"
-*mips3d:
-{
-  address_word offset;
-  int cc = CC;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  if ((cc & 0x3) != 0)
-    Unpredictable ();
-  if ((GETFCC (cc) == TF)
-      || (GETFCC (cc + 1) == TF)
-      || (GETFCC (cc + 2) == TF)
-      || (GETFCC (cc + 3) == TF))
-    {
-      offset = (EXTEND16 (OFFSET) << 2);
-      DELAY_SLOT (NIA + offset);
-    }
-}
-
-
-010001,10,3.FMT,5.FT,5.FS,3.CC,01,11,4.COND:COP1:64,f::CABS.cond.fmt
-"cabs.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
-*mips3d:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  CompareAbs (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
-  TRACE_ALU_RESULT (ValueFCR (31));
-}
-
-
-010001,10,110,00000,5.FS,5.FD,100100:COP1:64,f::CVT.PW.PS
-"cvt.pw.ps f<FD>, f<FS>"
-*mips3d:
-{
-  /* fd.pu = cvt_rnd (fs.pu); fd.pl = cvt_rnd (fs.pl);  */
-  /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_pw, ConvertPS (GETRM (), ValueFPR (FS, fmt_ps),
-				   fmt_ps, fmt_word));
-}
-
-
-010001,10,100,00000,5.FS,5.FD,100110:COP1:64,f::CVT.PS.PW
-"cvt.ps.pw f<FD>, f<FS>"
-*mips3d:
-{
-  /* fd.pl = cvt_rnd (fs.pl); fd.pu = cvt_rnd (fs.pu);  */
-  /* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word.  */
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, ConvertPS (GETRM (), ValueFPR (FS, fmt_pw),
-				   fmt_word, fmt_ps));
-}
-
-
-010001,10,110,5.FT,5.FS,5.FD,011010:COP1:64,f::MULR.PS
-"mulr.ps f<FD>, f<FS>, f<FT>"
-*mips3d:
-{
-  /* fd.PL = ft.PU * ft.PL;  fd.PU = fs.PU * fs.PL;  */
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  StoreFPR (FD, fmt_ps, MultiplyR (ValueFPR (FS, fmt_ps),
-				   ValueFPR (FT, fmt_ps), fmt_ps));
-}
-
-
-010001,10,3.FMT,00000,5.FS,5.FD,011101:COP1:64,f::RECIP1.fmt
-"recip1.%s<FMT> f<FD>, f<FS>"
-*mips3d:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Recip1 (ValueFPR (FS, fmt), fmt));
-}
-
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,011100:COP1:64,f::RECIP2.fmt
-"recip2.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mips3d:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, Recip2 (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-010001,10,3.FMT,00000,5.FS,5.FD,011110:COP1:64,f::RSQRT1.fmt
-"rsqrt1.%s<FMT> f<FD>, f<FS>"
-*mips3d:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, RSquareRoot1 (ValueFPR (FS, fmt), fmt));
-}
-
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,011111:COP1:64,f::RSQRT2.fmt
-"rsqrt2.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mips3d:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_u64 (SD_, instruction_0);
-  check_fmt_p (SD_, fmt, instruction_0);
-  StoreFPR (FD, fmt, RSquareRoot2 (ValueFPR (FS, fmt),
-				   ValueFPR (FT, fmt), fmt));
-}
diff --git a/sim/mips/sb1.igen b/sim/mips/sb1.igen
deleted file mode 100644
index b6534cb..0000000
--- a/sim/mips/sb1.igen
+++ /dev/null
@@ -1,244 +0,0 @@
-// -*- C -*-
-
-// Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
-// Copyright (C) 2002 Free Software Foundation, Inc.
-// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
-// Corporation (SiByte).
-//
-// This file is part of GDB, the GNU debugger.
-// 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation; either version 2, or (at your option)
-// any later version.
-// 
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License along
-// with this program; if not, write to the Free Software Foundation, Inc.,
-// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-
-// Helper:
-//
-// Check that the SB-1 extension instruction can currently be used, and
-// signal a ReservedInstruction exception if not.
-//
-
-:function:::void:check_sbx:instruction_word insn
-*sb1:
-{
-  if ((SR & status_SBX) == 0)
-    SignalException(ReservedInstruction, insn);
-}
-
-
-//  MDMX ASE Instructions
-//  ---------------------
-//
-//  The SB-1 implements the format OB subset of MDMX
-//  and has three additions (pavg, pabsdiff, pabsdifc).
-//  In addition, there are a couple of partial-decoding
-//  issues for the read/write accumulator instructions.
-//
-//  This code is structured so that mdmx.igen can be used by
-//  selecting the allowed instructions either via model, or by
-//  using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
-//  exception if the instruction is not allowed.
-
-
-:function:::void:check_mdmx:instruction_word insn
-*sb1:
-{
-  if (!COP_Usable(1))
-    SignalExceptionCoProcessorUnusable(1);
-  if ((SR & status_MX) == 0)
-    SignalExceptionMDMX();
-  check_u64 (SD_, insn);
-}
-
-:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
-*sb1:
-{
-  switch (fmtsel & 0x03)
-    {
-    case 0x00:     /* ob */
-    case 0x02:
-      return 1;
-    case 0x01:     /* qh */
-    case 0x03:     /* UNPREDICTABLE */
-      SignalException (ReservedInstruction, insn);
-      return 0;
-    }
-  return 0;
-}
-
-:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
-*sb1:
-{
-  switch (fmtop & 0x01)
-    {
-    case 0x00:     /* ob */
-      return 1;
-    case 0x01:     /* qh */
-      SignalException (ReservedInstruction, insn);
-      return 0;
-    }
-  return 0;
-}
-
-
-011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
-"rach.?<X>.%s<FMTOP> v<VD>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
-"racl.?<X>.%s<FMTOP> v<VD>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
-"racm.?<X>.%s<FMTOP> v<VD>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
-"rac?<X1>.?<X2> v<VD>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
-"wach.?<X>.%s<FMTOP> v<VS>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
-"wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
-"wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_mdmx_fmtop (SD_, instruction_0, FMTOP);
-  /* No op.  */
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
-"pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_sbx (SD_, instruction_0);
-  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-  StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
-"pabsdifc.%<FMTSEL> v<VS>,v<VT>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_sbx (SD_, instruction_0);
-  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-  MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
-}
-
-
-011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
-"pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
-*sb1:
-{
-  check_mdmx (SD_, instruction_0);
-  check_sbx (SD_, instruction_0);
-  check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
-  StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
-}
-
-
-//  Paired-Single Extension Instructions
-//  ------------------------------------
-//
-//  The SB-1 implements several .PS format instructions that are
-//  extensions to the MIPS64 architecture.
-
-010001,10,3.FMT=6,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.PS
-"div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*sb1:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_sbx (SD_, instruction_0);
-  StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
-}
-
-
-010001,10,3.FMT=6,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.PS
-"recip.%s<FMT> f<FD>, f<FS>"
-*sb1:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_sbx (SD_, instruction_0);
-  StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
-}
-
-
-010001,10,3.FMT=6,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.PS
-"rsqrt.%s<FMT> f<FD>, f<FS>"
-*sb1:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_sbx (SD_, instruction_0);
-  StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
-}
-
-
-010001,10,3.FMT=6,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.PS
-"sqrt.%s<FMT> f<FD>, f<FS>"
-*sb1:
-{
-  int fmt = FMT;
-  check_fpu (SD_);
-  check_sbx (SD_, instruction_0);
-  StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
-}
diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
deleted file mode 100644
index edee498..0000000
--- a/sim/mips/sim-main.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/*  Copyright (C) 1998, Cygnus Solutions
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-    */
-
-
-#ifndef SIM_MAIN_C
-#define SIM_MAIN_C
-
-#include "sim-main.h"
-#include "sim-assert.h"
-
-
-/*---------------------------------------------------------------------------*/
-/*-- simulator engine -------------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Translate a virtual address to a physical address and cache
-   coherence algorithm describing the mechanism used to resolve the
-   memory reference. Given the virtual address vAddr, and whether the
-   reference is to Instructions ot Data (IorD), find the corresponding
-   physical address (pAddr) and the cache coherence algorithm (CCA)
-   used to resolve the reference. If the virtual address is in one of
-   the unmapped address spaces the physical address and the CCA are
-   determined directly by the virtual address. If the virtual address
-   is in one of the mapped address spaces then the TLB is used to
-   determine the physical address and access type; if the required
-   translation is not present in the TLB or the desired access is not
-   permitted the function fails and an exception is taken.
-
-   NOTE: Normally (RAW == 0), when address translation fails, this
-   function raises an exception and does not return. */
-
-INLINE_SIM_MAIN
-(int)
-address_translation (SIM_DESC sd,
-		     sim_cpu * cpu,
-		     address_word cia,
-		     address_word vAddr,
-		     int IorD,
-		     int LorS,
-		     address_word * pAddr,
-		     int *CCA,
-		     int raw)
-{
-  int res = -1;			/* TRUE : Assume good return */
-
-#ifdef DEBUG
-  sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
-#endif
-
-  /* Check that the address is valid for this memory model */
-
-  /* For a simple (flat) memory model, we simply pass virtual
-     addressess through (mostly) unchanged. */
-  vAddr &= 0xFFFFFFFF;
-
-  *pAddr = vAddr;		/* default for isTARGET */
-  *CCA = Uncached;		/* not used for isHOST */
-
-  return (res);
-}
-
-
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Prefetch data from memory. Prefetch is an advisory instruction for
-   which an implementation specific action is taken. The action taken
-   may increase performance, but must not change the meaning of the
-   program, or alter architecturally-visible state. */
-
-INLINE_SIM_MAIN (void)
-prefetch (SIM_DESC sd,
-	  sim_cpu *cpu,
-	  address_word cia,
-	  int CCA,
-	  address_word pAddr,
-	  address_word vAddr,
-	  int DATA,
-	  int hint)
-{
-#ifdef DEBUG
-  sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
-#endif /* DEBUG */
-
-  /* For our simple memory model we do nothing */
-  return;
-}
-
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Load a value from memory. Use the cache and main memory as
-   specified in the Cache Coherence Algorithm (CCA) and the sort of
-   access (IorD) to find the contents of AccessLength memory bytes
-   starting at physical location pAddr. The data is returned in the
-   fixed width naturally-aligned memory element (MemElem). The
-   low-order two (or three) bits of the address and the AccessLength
-   indicate which of the bytes within MemElem needs to be given to the
-   processor. If the memory access type of the reference is uncached
-   then only the referenced bytes are read from memory and valid
-   within the memory element. If the access type is cached, and the
-   data is not present in cache, an implementation specific size and
-   alignment block of memory is read and loaded into the cache to
-   satisfy a load reference. At a minimum, the block is the entire
-   memory element. */
-INLINE_SIM_MAIN (void)
-load_memory (SIM_DESC SD,
-	     sim_cpu *CPU,
-	     address_word cia,
-	     uword64* memvalp,
-	     uword64* memval1p,
-	     int CCA,
-	     unsigned int AccessLength,
-	     address_word pAddr,
-	     address_word vAddr,
-	     int IorD)
-{
-  uword64 value = 0;
-  uword64 value1 = 0;
-
-#ifdef DEBUG
-  sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
-#endif /* DEBUG */
-
-#if defined(WARN_MEM)
-  if (CCA != uncached)
-    sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-#endif /* WARN_MEM */
-
-  if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
-    {
-      /* In reality this should be a Bus Error */
-      sim_io_error (SD, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
-		    AccessLength,
-		    (LOADDRMASK + 1) << 3,
-		    pr_addr (pAddr));
-    }
-
-#if defined(TRACE)
-  dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
-#endif /* TRACE */
-  
-  /* Read the specified number of bytes from memory.  Adjust for
-     host/target byte ordering/ Align the least significant byte
-     read. */
-
-  switch (AccessLength)
-    {
-    case AccessLength_QUADWORD:
-      {
-	unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
-	value1 = VH8_16 (val);
-	value = VL8_16 (val);
-	break;
-      }
-    case AccessLength_DOUBLEWORD:
-      value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_SEPTIBYTE:
-      value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_SEXTIBYTE:
-      value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_QUINTIBYTE:
-      value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_WORD:
-      value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_TRIPLEBYTE:
-      value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_HALFWORD:
-      value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
-      break;
-    case AccessLength_BYTE:
-      value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
-      break;
-    default:
-      abort ();
-    }
-  
-#ifdef DEBUG
-  printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
-	 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
-#endif /* DEBUG */
-  
-  /* See also store_memory. Position data in correct byte lanes. */
-  if (AccessLength <= LOADDRMASK)
-    {
-      if (BigEndianMem)
-	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
-	   shifted to the most significant byte position.  */
-	value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
-      else
-	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
-	   is already in the correct postition. */
-	value <<= ((pAddr & LOADDRMASK) * 8);
-    }
-  
-#ifdef DEBUG
-  printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
-	 pr_uword64(value1),pr_uword64(value));
-#endif /* DEBUG */
-  
-  *memvalp = value;
-  if (memval1p) *memval1p = value1;
-}
-
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Store a value to memory. The specified data is stored into the
-   physical location pAddr using the memory hierarchy (data caches and
-   main memory) as specified by the Cache Coherence Algorithm
-   (CCA). The MemElem contains the data for an aligned, fixed-width
-   memory element (word for 32-bit processors, doubleword for 64-bit
-   processors), though only the bytes that will actually be stored to
-   memory need to be valid. The low-order two (or three) bits of pAddr
-   and the AccessLength field indicates which of the bytes within the
-   MemElem data should actually be stored; only these bytes in memory
-   will be changed. */
-
-INLINE_SIM_MAIN (void)
-store_memory (SIM_DESC SD,
-	      sim_cpu *CPU,
-	      address_word cia,
-	      int CCA,
-	      unsigned int AccessLength,
-	      uword64 MemElem,
-	      uword64 MemElem1,   /* High order 64 bits */
-	      address_word pAddr,
-	      address_word vAddr)
-{
-#ifdef DEBUG
-  sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
-#endif /* DEBUG */
-  
-#if defined(WARN_MEM)
-  if (CCA != uncached)
-    sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-#endif /* WARN_MEM */
-  
-  if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
-    sim_io_error (SD, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
-		  AccessLength,
-		  (LOADDRMASK + 1) << 3,
-		  pr_addr(pAddr));
-  
-#if defined(TRACE)
-  dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
-#endif /* TRACE */
-  
-#ifdef DEBUG
-  printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
-#endif /* DEBUG */
-  
-  /* See also load_memory. Position data in correct byte lanes. */
-  if (AccessLength <= LOADDRMASK)
-    {
-      if (BigEndianMem)
-	/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
-	   shifted to the most significant byte position.  */
-	MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
-      else
-	/* For little endian target, byte (pAddr&LOADDRMASK == 0)
-	   is already in the correct postition. */
-	MemElem >>= ((pAddr & LOADDRMASK) * 8);
-    }
-  
-#ifdef DEBUG
-  printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
-#endif /* DEBUG */
-  
-  switch (AccessLength)
-    {
-    case AccessLength_QUADWORD:
-      {
-	unsigned_16 val = U16_8 (MemElem1, MemElem);
-	sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
-	break;
-      }
-    case AccessLength_DOUBLEWORD:
-      sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_SEPTIBYTE:
-      sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_SEXTIBYTE:
-      sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_QUINTIBYTE:
-      sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_WORD:
-      sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_TRIPLEBYTE:
-      sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_HALFWORD:
-      sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    case AccessLength_BYTE:
-      sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
-      break;
-    default:
-      abort ();
-    }	
-  
-  return;
-}
-
-
-INLINE_SIM_MAIN (unsigned32)
-ifetch32 (SIM_DESC SD,
-	  sim_cpu *CPU,
-	  address_word cia,
-	  address_word vaddr)
-{
-  /* Copy the action of the LW instruction */
-  address_word mask = LOADDRMASK;
-  address_word access = AccessLength_WORD;
-  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
-  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-
-  if ((vaddr & access) != 0)
-    SignalExceptionInstructionFetch ();
-  AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
-  byte = ((vaddr & mask) ^ bigendiancpu);
-  return (memval >> (8 * byte));
-}
-
-
-INLINE_SIM_MAIN (unsigned16)
-ifetch16 (SIM_DESC SD,
-	  sim_cpu *CPU,
-	  address_word cia,
-	  address_word vaddr)
-{
-  /* Copy the action of the LH instruction */
-  address_word mask = LOADDRMASK;
-  address_word access = AccessLength_HALFWORD;
-  address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
-  address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
-  unsigned int byte;
-  address_word paddr;
-  int uncached;
-  unsigned64 memval;
-
-  if ((vaddr & access) != 0)
-    SignalExceptionInstructionFetch ();
-  AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
-  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
-  byte = ((vaddr & mask) ^ bigendiancpu);
-  return (memval >> (8 * byte));
-}
-
-
-
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Order loads and stores to synchronise shared memory. Perform the
-   action necessary to make the effects of groups of synchronizable
-   loads and stores indicated by stype occur in the same order for all
-   processors. */
-INLINE_SIM_MAIN (void)
-sync_operation (SIM_DESC sd,
-		sim_cpu *cpu,
-		address_word cia,
-		int stype)
-{
-#ifdef DEBUG
-  sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
-#endif /* DEBUG */
-  return;
-}
-
-INLINE_SIM_MAIN (void)
-cache_op (SIM_DESC SD,
-	  sim_cpu *CPU,
-	  address_word cia,
-	  int op,
-	  address_word pAddr,
-	  address_word vAddr,
-	  unsigned int instruction)
-{
-#if 1 /* stop warning message being displayed (we should really just remove the code) */
-  static int icache_warning = 1;
-  static int dcache_warning = 1;
-#else
-  static int icache_warning = 0;
-  static int dcache_warning = 0;
-#endif
-
-  /* If CP0 is not useable (User or Supervisor mode) and the CP0
-     enable bit in the Status Register is clear - a coprocessor
-     unusable exception is taken. */
-#if 0
-  sim_io_printf(SD,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
-#endif
-
-  switch (op & 0x3) {
-    case 0: /* instruction cache */
-      switch (op >> 2) {
-        case 0: /* Index Invalidate */
-        case 1: /* Index Load Tag */
-        case 2: /* Index Store Tag */
-        case 4: /* Hit Invalidate */
-        case 5: /* Fill */
-        case 6: /* Hit Writeback */
-          if (!icache_warning)
-            {
-              sim_io_eprintf(SD,"Instruction CACHE operation %d to be coded\n",(op >> 2));
-              icache_warning = 1;
-            }
-          break;
-
-        default:
-          SignalException(ReservedInstruction,instruction);
-          break;
-      }
-      break;
-
-    case 1: /* data cache */
-    case 3: /* secondary data cache */
-      switch (op >> 2) {
-        case 0: /* Index Writeback Invalidate */
-        case 1: /* Index Load Tag */
-        case 2: /* Index Store Tag */
-        case 3: /* Create Dirty */
-        case 4: /* Hit Invalidate */
-        case 5: /* Hit Writeback Invalidate */
-        case 6: /* Hit Writeback */ 
-          if (!dcache_warning)
-            {
-              sim_io_eprintf(SD,"Data CACHE operation %d to be coded\n",(op >> 2));
-              dcache_warning = 1;
-            }
-          break;
-
-        default:
-          SignalException(ReservedInstruction,instruction);
-          break;
-      }
-      break;
-
-    default: /* unrecognised cache ID */
-      SignalException(ReservedInstruction,instruction);
-      break;
-  }
-
-  return;
-}
-
-
-INLINE_SIM_MAIN (void)
-pending_tick (SIM_DESC SD,
-	      sim_cpu *CPU,
-	      address_word cia)
-{
-  if (PENDING_TRACE)							
-    sim_io_eprintf (SD, "PENDING_DRAIN - 0x%lx - pending_in = %d, pending_out = %d, pending_total = %d\n", (unsigned long) cia, PENDING_IN, PENDING_OUT, PENDING_TOTAL); 
-  if (PENDING_OUT != PENDING_IN)					
-    {									
-      int loop;							
-      int index = PENDING_OUT;					
-      int total = PENDING_TOTAL;					
-      if (PENDING_TOTAL == 0)						
-	sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n"); 
-      for (loop = 0, index = PENDING_OUT;
-	   (loop < total);
-	   loop++, index = (index + 1) % PSLOTS)
-	{								
-	  if (PENDING_SLOT_DEST[index] != NULL)			
-	    {								
-	      PENDING_SLOT_DELAY[index] -= 1;				
-	      if (PENDING_SLOT_DELAY[index] == 0)			
-		{							
-		  if (PENDING_TRACE)
-		    sim_io_eprintf (SD, "PENDING_DRAIN - drained - index %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
-				    index,
-				    (unsigned long) PENDING_SLOT_DEST[index],
-				    PENDING_SLOT_BIT[index],
-				    (unsigned long) PENDING_SLOT_VALUE[index],
-				    PENDING_SLOT_SIZE[index]);
-		  if (PENDING_SLOT_BIT[index] >= 0)			
-		    switch (PENDING_SLOT_SIZE[index])                 
-		      {						
-		      case 4:
-			if (PENDING_SLOT_VALUE[index])		
-			  *(unsigned32*)PENDING_SLOT_DEST[index] |= 	
-			    BIT32 (PENDING_SLOT_BIT[index]);		
-			else						
-			  *(unsigned32*)PENDING_SLOT_DEST[index] &= 	
-			    BIT32 (PENDING_SLOT_BIT[index]);		
-			break;					
-		      case 8:					
-			if (PENDING_SLOT_VALUE[index])		
-			  *(unsigned64*)PENDING_SLOT_DEST[index] |= 	
-			    BIT64 (PENDING_SLOT_BIT[index]);		
-			else						
-			  *(unsigned64*)PENDING_SLOT_DEST[index] &= 	
-			    BIT64 (PENDING_SLOT_BIT[index]);		
-			break;					
-		      }
-		  else
-		    switch (PENDING_SLOT_SIZE[index])                 
-		      {						
-		      case 4:					
-			*(unsigned32*)PENDING_SLOT_DEST[index] = 	
-			  PENDING_SLOT_VALUE[index];			
-			break;					
-		      case 8:					
-			*(unsigned64*)PENDING_SLOT_DEST[index] = 	
-			  PENDING_SLOT_VALUE[index];			
-			break;					
-		      }							
-		  if (PENDING_OUT == index)
-		    {
-		      PENDING_SLOT_DEST[index] = NULL;
-		      PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
-		      PENDING_TOTAL--;
-		    }
-		}							
-	      else if (PENDING_TRACE && PENDING_SLOT_DELAY[index] > 0)
-		sim_io_eprintf (SD, "PENDING_DRAIN - queued - index %d, delay %d, dest 0x%lx, bit %d, val 0x%lx, size %d\n",
-				index, PENDING_SLOT_DELAY[index],
-				(unsigned long) PENDING_SLOT_DEST[index],
-				PENDING_SLOT_BIT[index],
-				(unsigned long) PENDING_SLOT_VALUE[index],
-				PENDING_SLOT_SIZE[index]);
-
-	    }								
-	}								
-    }									
-}
-
-
-#endif
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
deleted file mode 100644
index 76e6374..0000000
--- a/sim/mips/sim-main.h
+++ /dev/null
@@ -1,1020 +0,0 @@
-/* MIPS Simulator definition.
-   Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
-   Contributed by Cygnus Support.
-
-This file is part of GDB, the GNU debugger.
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef SIM_MAIN_H
-#define SIM_MAIN_H
-
-/* This simulator doesn't cache the Current Instruction Address */
-/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
-/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
-
-#define SIM_HAVE_BIENDIAN
-
-
-/* hobble some common features for moment */
-#define WITH_WATCHPOINTS 1
-#define WITH_MODULO_MEMORY 1
-
-
-#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
-mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
-
-#include "sim-basics.h"
-
-typedef address_word sim_cia;
-
-#include "sim-base.h"
-#include "bfd.h"
-
-/* Deprecated macros and types for manipulating 64bit values.  Use
-   ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
-
-typedef signed64 word64;
-typedef unsigned64 uword64;
-
-#define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
-#define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
-#define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
-#define SET64HI(t)	(((uword64)(t))<<32)
-#define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
-#define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
-
-/* Check if a value will fit within a halfword: */
-#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
-
-
-
-/* Floating-point operations: */
-
-#include "sim-fpu.h"
-#include "cp1.h"
-
-/* FPU registers must be one of the following types. All other values
-   are reserved (and undefined). */
-typedef enum {
- fmt_single  = 0,
- fmt_double  = 1,
- fmt_word    = 4,
- fmt_long    = 5,
- fmt_ps      = 6,
- /* The following are well outside the normal acceptable format
-    range, and are used in the register status vector. */
- fmt_unknown       = 0x10000000,
- fmt_uninterpreted = 0x20000000,
- fmt_uninterpreted_32 = 0x40000000,
- fmt_uninterpreted_64 = 0x80000000U,
-} FP_formats;
-
-/* For paired word (pw) operations, the opcode representation is fmt_word,
-   but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
-#define fmt_pw fmt_long
-
-/* This should be the COC1 value at the start of the preceding
-   instruction: */
-#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
-
-#ifdef TARGET_ENABLE_FR
-/* FIXME: this should be enabled for all targets, but needs testing first. */
-#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
-   ? ((SR & status_FR) ? 64 : 32) \
-   : (WITH_TARGET_FLOATING_POINT_BITSIZE))
-#else
-#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
-#endif
-
-
-
-
-
-/* HI/LO register accesses */
-
-/* For some MIPS targets, the HI/LO registers have certain timing
-   restrictions in that, for instance, a read of a HI register must be
-   separated by at least three instructions from a preceeding read.
-
-   The struct below is used to record the last access by each of A MT,
-   MF or other OP instruction to a HI/LO register.  See mips.igen for
-   more details. */
-
-typedef struct _hilo_access {
-  signed64 timestamp;
-  address_word cia;
-} hilo_access;
-
-typedef struct _hilo_history {
-  hilo_access mt;
-  hilo_access mf;
-  hilo_access op;
-} hilo_history;
-
-
-
-
-/* Integer ALU operations: */
-
-#include "sim-alu.h"
-
-#define ALU32_END(ANS) \
-  if (ALU32_HAD_OVERFLOW) \
-    SignalExceptionIntegerOverflow (); \
-  (ANS) = (signed32) ALU32_OVERFLOW_RESULT
-
-
-#define ALU64_END(ANS) \
-  if (ALU64_HAD_OVERFLOW) \
-    SignalExceptionIntegerOverflow (); \
-  (ANS) = ALU64_OVERFLOW_RESULT;
-
-
-
-
-
-/* The following is probably not used for MIPS IV onwards: */
-/* Slots for delayed register updates. For the moment we just have a
-   fixed number of slots (rather than a more generic, dynamic
-   system). This keeps the simulator fast. However, we only allow
-   for the register update to be delayed for a single instruction
-   cycle. */
-#define PSLOTS (8) /* Maximum number of instruction cycles */
-
-typedef struct _pending_write_queue {
-  int in;
-  int out;
-  int total;
-  int slot_delay[PSLOTS];
-  int slot_size[PSLOTS];
-  int slot_bit[PSLOTS];
-  void *slot_dest[PSLOTS];
-  unsigned64 slot_value[PSLOTS];
-} pending_write_queue;
-
-#ifndef PENDING_TRACE
-#define PENDING_TRACE 0
-#endif
-#define PENDING_IN ((CPU)->pending.in)
-#define PENDING_OUT ((CPU)->pending.out)
-#define PENDING_TOTAL ((CPU)->pending.total)
-#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
-#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
-#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
-#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
-#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
-
-/* Invalidate the pending write queue, all pending writes are
-   discarded. */
-
-#define PENDING_INVALIDATE() \
-memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
-
-/* Schedule a write to DEST for N cycles time.  For 64 bit
-   destinations, schedule two writes.  For floating point registers,
-   the caller should schedule a write to both the dest register and
-   the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
-   is updated. */
-
-#define PENDING_SCHED(DEST,VAL,DELAY,BIT)				\
-  do {									\
-    if (PENDING_SLOT_DEST[PENDING_IN] != NULL)				\
-      sim_engine_abort (SD, CPU, cia,					\
-		        "PENDING_SCHED - buffer overflow\n");		\
-    if (PENDING_TRACE)							\
-      sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",			\
-		      (unsigned long) cia, (unsigned long) &(DEST),	\
-		      (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
-		      PENDING_IN, PENDING_OUT, PENDING_TOTAL);		\
-    PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;			\
-    PENDING_SLOT_DEST[PENDING_IN] = &(DEST);				\
-    PENDING_SLOT_VALUE[PENDING_IN] = (VAL);				\
-    PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);			\
-    PENDING_SLOT_BIT[PENDING_IN] = (BIT);				\
-    PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
-    PENDING_TOTAL += 1;			                                \
-  } while (0)
-
-#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
-#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
-
-#define PENDING_TICK() pending_tick (SD, CPU, cia)
-
-#define PENDING_FLUSH() abort () /* think about this one */
-#define PENDING_FP() abort () /* think about this one */
-
-/* For backward compatibility */
-#define PENDING_FILL(R,VAL) 						\
-do {									\
-  if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)			\
-    {									\
-      PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);			\
-      PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
-    }									\
-  else									\
-    PENDING_SCHED(GPR[(R)], VAL, 1, -1);				\
-} while (0)
-
-
-enum float_operation
-  {
-    FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
-    FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
-    FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
-  };
-
-
-/* The internal representation of an MDMX accumulator. 
-   Note that 24 and 48 bit accumulator elements are represented in
-   32 or 64 bits.  Since the accumulators are 2's complement with
-   overflow suppressed, high-order bits can be ignored in most contexts.  */
-
-typedef signed32 signed24;
-typedef signed64 signed48;
-
-typedef union { 
-  signed24  ob[8];
-  signed48  qh[4]; 
-} MDMX_accumulator;
-
-
-/* Conventional system arguments.  */ 
-#define SIM_STATE  sim_cpu *cpu, address_word cia
-#define SIM_ARGS   CPU, cia
-
-struct _sim_cpu {
-
-
-  /* The following are internal simulator state variables: */
-#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
-#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
-  address_word dspc;  /* delay-slot PC */
-#define DSPC ((CPU)->dspc)
-
-#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
-#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
-
-
-  /* State of the simulator */
-  unsigned int state;
-  unsigned int dsstate;
-#define STATE ((CPU)->state)
-#define DSSTATE ((CPU)->dsstate)
-
-/* Flags in the "state" variable: */
-#define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
-#define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
-#define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
-#define simPCOC0        (1 << 17) /* COC[1] from current */
-#define simPCOC1        (1 << 18) /* COC[1] from previous */
-#define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
-#define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simSIGINT	(1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
-#define simJALDELAYSLOT	(1 << 29) /* 1 = in jal delay slot */
-
-#ifndef ENGINE_ISSUE_PREFIX_HOOK
-#define ENGINE_ISSUE_PREFIX_HOOK() \
-  { \
-    /* Perform any pending writes */ \
-    PENDING_TICK(); \
-    /* Set previous flag, depending on current: */ \
-    if (STATE & simPCOC0) \
-     STATE |= simPCOC1; \
-    else \
-     STATE &= ~simPCOC1; \
-    /* and update the current value: */ \
-    if (GETFCC(0)) \
-     STATE |= simPCOC0; \
-    else \
-     STATE &= ~simPCOC0; \
-  }
-#endif /* ENGINE_ISSUE_PREFIX_HOOK */
-
-
-/* This is nasty, since we have to rely on matching the register
-   numbers used by GDB. Unfortunately, depending on the MIPS target
-   GDB uses different register numbers. We cannot just include the
-   relevant "gdb/tm.h" link, since GDB may not be configured before
-   the sim world, and also the GDB header file requires too much other
-   state. */
-
-#ifndef TM_MIPS_H
-#define LAST_EMBED_REGNUM (96)
-#define NUM_REGS (LAST_EMBED_REGNUM + 1)
-
-#define FP0_REGNUM 38           /* Floating point register 0 (single float) */
-#define FCRCS_REGNUM 70         /* FP control/status */
-#define FCRIR_REGNUM 71         /* FP implementation/revision */
-#endif
-
-
-/* To keep this default simulator simple, and fast, we use a direct
-   vector of registers. The internal simulator engine then uses
-   manifests to access the correct slot. */
-
-  unsigned_word registers[LAST_EMBED_REGNUM + 1];
-
-  int register_widths[NUM_REGS];
-#define REGISTERS       ((CPU)->registers)
-
-#define GPR     (&REGISTERS[0])
-#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
-
-#define LO      (REGISTERS[33])
-#define HI      (REGISTERS[34])
-#define PCIDX	37
-#define PC      (REGISTERS[PCIDX])
-#define CAUSE   (REGISTERS[36])
-#define SRIDX   (32)
-#define SR      (REGISTERS[SRIDX])      /* CPU status register */
-#define FCR0IDX  (71)
-#define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
-#define FCR31IDX (70)
-#define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
-#define FCSR    (FCR31)
-#define Debug	(REGISTERS[86])
-#define DEPC	(REGISTERS[87])
-#define EPC	(REGISTERS[88])
-
-#define AC0LOIDX	(33)	/* Must be the same register as LO */
-#define AC0HIIDX	(34)	/* Must be the same register as HI */
-#define AC1LOIDX	(90)
-#define AC1HIIDX	(91)
-#define AC2LOIDX	(92)
-#define AC2HIIDX	(93)
-#define AC3LOIDX	(94)
-#define AC3HIIDX	(95)
-
-#define DSPLO(N)	(REGISTERS[DSPLO_REGNUM[N]])
-#define DSPHI(N)	(REGISTERS[DSPHI_REGNUM[N]])
-
-#define DSPCRIDX	(96)	/* DSP control register */
-#define DSPCR		(REGISTERS[DSPCRIDX])
-
-#define DSPCR_POS_SHIFT		(0)
-#define DSPCR_POS_MASK		(0x3f)
-#define DSPCR_POS_SMASK		(DSPCR_POS_MASK << DSPCR_POS_SHIFT)
-
-#define DSPCR_SCOUNT_SHIFT	(7)
-#define DSPCR_SCOUNT_MASK	(0x3f)
-#define DSPCR_SCOUNT_SMASK	(DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
-
-#define DSPCR_CARRY_SHIFT	(13)
-#define DSPCR_CARRY_MASK	(1)
-#define DSPCR_CARRY_SMASK	(DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
-#define DSPCR_CARRY		(1 << DSPCR_CARRY_SHIFT)
-
-#define DSPCR_EFI_SHIFT		(14)
-#define DSPCR_EFI_MASK		(1)
-#define DSPCR_EFI_SMASK		(DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
-#define DSPCR_EFI		(1 << DSPCR_EFI_MASK)
-
-#define DSPCR_OUFLAG_SHIFT	(16)
-#define DSPCR_OUFLAG_MASK	(0xff)
-#define DSPCR_OUFLAG_SMASK	(DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
-#define DSPCR_OUFLAG4		(1 << (DSPCR_OUFLAG_SHIFT + 4))
-#define DSPCR_OUFLAG5		(1 << (DSPCR_OUFLAG_SHIFT + 5))
-#define DSPCR_OUFLAG6		(1 << (DSPCR_OUFLAG_SHIFT + 6))
-#define DSPCR_OUFLAG7		(1 << (DSPCR_OUFLAG_SHIFT + 7))
-
-#define DSPCR_CCOND_SHIFT	(24)
-#define DSPCR_CCOND_MASK	(0xf)
-#define DSPCR_CCOND_SMASK	(DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
-
-  /* All internal state modified by signal_exception() that may need to be
-     rolled back for passing moment-of-exception image back to gdb. */
-  unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
-  unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
-  int exc_suspended;
-
-#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
-#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
-#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
-
-  unsigned_word c0_config_reg;
-#define C0_CONFIG ((CPU)->c0_config_reg)
-
-/* The following are pseudonyms for standard registers */
-#define ZERO    (REGISTERS[0])
-#define V0      (REGISTERS[2])
-#define A0      (REGISTERS[4])
-#define A1      (REGISTERS[5])
-#define A2      (REGISTERS[6])
-#define A3      (REGISTERS[7])
-#define T8IDX   24
-#define T8	(REGISTERS[T8IDX])
-#define SPIDX   29
-#define SP      (REGISTERS[SPIDX])
-#define RAIDX   31
-#define RA      (REGISTERS[RAIDX])
-
-  /* While space is allocated in the main registers arrray for some of
-     the COP0 registers, that space isn't sufficient.  Unknown COP0
-     registers overflow into the array below */
-
-#define NR_COP0_GPR	32
-  unsigned_word cop0_gpr[NR_COP0_GPR];
-#define COP0_GPR	((CPU)->cop0_gpr)
-#define COP0_BADVADDR	(COP0_GPR[8])
-
-  /* While space is allocated for the floating point registers in the
-     main registers array, they are stored separatly.  This is because
-     their size may not necessarily match the size of either the
-     general-purpose or system specific registers.  */
-#define NR_FGR    (32)
-#define FGR_BASE  FP0_REGNUM
-  fp_word fgr[NR_FGR];
-#define FGR       ((CPU)->fgr)
-
-  /* Keep the current format state for each register: */
-  FP_formats fpr_state[32];
-#define FPR_STATE ((CPU)->fpr_state)
-
-  pending_write_queue pending;
-
-  /* The MDMX accumulator (used only for MDMX ASE).  */
-  MDMX_accumulator acc; 
-#define ACC             ((CPU)->acc)
-
-  /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
-     read-write instructions. It is set when a linked load occurs. It
-     is tested and cleared by the conditional store. It is cleared
-     (during other CPU operations) when a store to the location would
-     no longer be atomic. In particular, it is cleared by exception
-     return instructions. */
-  int llbit;
-#define LLBIT ((CPU)->llbit)
-
-
-/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
-   corruptions caused by using the HI or LO register too close to a
-   following operation is spotted. See mips.igen for more details. */
-
-  hilo_history hi_history;
-#define HIHISTORY (&(CPU)->hi_history)
-  hilo_history lo_history;
-#define LOHISTORY (&(CPU)->lo_history)
-
-
-  sim_cpu_base base;
-};
-
-
-/* MIPS specific simulator watch config */
-
-void watch_options_install PARAMS ((SIM_DESC sd));
-
-struct swatch {
-  sim_event *pc;
-  sim_event *clock;
-  sim_event *cycles;
-};
-
-
-/* FIXME: At present much of the simulator is still static */
-struct sim_state {
-
-  struct swatch watch;
-
-  sim_cpu cpu[MAX_NR_PROCESSORS];
-#if (WITH_SMP)
-#define STATE_CPU(sd,n) (&(sd)->cpu[n])
-#else
-#define STATE_CPU(sd,n) (&(sd)->cpu[0])
-#endif
-
-
-  sim_state_base base;
-};
-
-
-
-/* Status information: */
-
-/* TODO : these should be the bitmasks for these bits within the
-   status register. At the moment the following are VR4300
-   bit-positions: */
-#define status_KSU_mask  (0x18)         /* mask for KSU bits */
-#define status_KSU_shift (3)            /* shift for field */
-#define ksu_kernel       (0x0)
-#define ksu_supervisor   (0x1)
-#define ksu_user         (0x2)
-#define ksu_unknown      (0x3)
-
-#define SR_KSU		 ((SR & status_KSU_mask) >> status_KSU_shift)
-
-#define status_IE	 (1 <<  0)      /* Interrupt enable */
-#define status_EIE	 (1 << 16)      /* Enable Interrupt Enable */
-#define status_EXL	 (1 <<  1)	/* Exception level */
-#define status_RE        (1 << 25)      /* Reverse Endian in user mode */
-#define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
-#define status_SR        (1 << 20)      /* soft reset or NMI */
-#define status_BEV       (1 << 22)      /* Location of general exception vectors */
-#define status_TS        (1 << 21)      /* TLB shutdown has occurred */
-#define status_ERL       (1 <<  2)      /* Error level */
-#define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
-#define status_RP        (1 << 27)      /* Reduced Power mode */
-
-/* Specializations for TX39 family */
-#define status_IEc       (1 << 0)       /* Interrupt enable (current) */
-#define status_KUc       (1 << 1)       /* Kernel/User mode */
-#define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
-#define status_KUp       (1 << 3)       /* Kernel/User mode */
-#define status_IEo       (1 << 4)       /* Interrupt enable (old) */
-#define status_KUo       (1 << 5)       /* Kernel/User mode */
-#define status_IM_mask   (0xff)         /* Interrupt mask */
-#define status_IM_shift  (8)
-#define status_NMI       (1 << 20)      /* NMI */
-#define status_NMI       (1 << 20)      /* NMI */
-
-/* Status bits used by MIPS32/MIPS64.  */
-#define status_UX        (1 <<  5)      /* 64-bit user addrs */
-#define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
-#define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
-#define status_TS        (1 << 21)      /* TLB shutdown has occurred */
-#define status_PX        (1 << 23)      /* Enable 64 bit operations */
-#define status_MX        (1 << 24)      /* Enable MDMX resources */
-#define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
-#define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
-#define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
-#define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
-/* Bits reserved for implementations:  */
-#define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
-
-#define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
-#define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
-#define cause_CE_mask     0x30000000	/* Coprocessor exception */
-#define cause_CE_shift    28
-#define cause_EXC2_mask   0x00070000
-#define cause_EXC2_shift  16
-#define cause_IP7 	  (1 << 15)	/* Interrupt pending */
-#define cause_SIOP        (1 << 12)     /* SIO pending */
-#define cause_IP3 	  (1 << 11)	/* Int 0 pending */
-#define cause_IP2 	  (1 << 10)	/* Int 1 pending */
-
-#define cause_EXC_mask  (0x1c)          /* Exception code */
-#define cause_EXC_shift (2)
-
-#define cause_SW0       (1 << 8)        /* Software interrupt 0 */
-#define cause_SW1       (1 << 9)        /* Software interrupt 1 */
-#define cause_IP_mask   (0x3f)          /* Interrupt pending field */
-#define cause_IP_shift  (10)
-
-#define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
-#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
-
-
-/* NOTE: We keep the following status flags as bit values (1 for true,
-   0 for false). This allows them to be used in binary boolean
-   operations without worrying about what exactly the non-zero true
-   value is. */
-
-/* UserMode */
-#ifdef SUBTARGET_R3900
-#define UserMode        ((SR & status_KUc) ? 1 : 0)
-#else
-#define UserMode	((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
-#endif /* SUBTARGET_R3900 */
-
-/* BigEndianMem */
-/* Hardware configuration. Affects endianness of LoadMemory and
-   StoreMemory and the endianness of Kernel and Supervisor mode
-   execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
-/*(state & simBE) ? 1 : 0)*/
-
-/* ReverseEndian */
-/* This mode is selected if in User mode with the RE bit being set in
-   SR (Status Register). It reverses the endianness of load and store
-   instructions. */
-#define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
-
-/* BigEndianCPU */
-/* The endianness for load and store instructions (0=little;1=big). In
-   User mode this endianness may be switched by setting the state_RE
-   bit in the SR register. Thus, BigEndianCPU may be computed as
-   (BigEndianMem EOR ReverseEndian). */
-#define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
-
-
-
-/* Exceptions: */
-
-/* NOTE: These numbers depend on the processor architecture being
-   simulated: */
-enum ExceptionCause {
-  Interrupt               = 0,
-  TLBModification         = 1,
-  TLBLoad                 = 2,
-  TLBStore                = 3,
-  AddressLoad             = 4,
-  AddressStore            = 5,
-  InstructionFetch        = 6,
-  DataReference           = 7,
-  SystemCall              = 8,
-  BreakPoint              = 9,
-  ReservedInstruction     = 10,
-  CoProcessorUnusable     = 11,
-  IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
-  Trap                    = 13,
-  FPE                     = 15,
-  DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
-  MDMX                    = 22,
-  Watch                   = 23,
-  MCheck                  = 24,
-  CacheErr                = 30,
-  NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
-
-
-/* The following exception code is actually private to the simulator
-   world. It is *NOT* a processor feature, and is used to signal
-   run-time errors in the simulator. */
-  SimulatorFault      	  = 0xFFFFFFFF
-};
-
-#define TLB_REFILL  (0)
-#define TLB_INVALID (1)
-
-
-/* The following break instructions are reserved for use by the
-   simulator.  The first is used to halt the simulation.  The second
-   is used by gdb for break-points.  NOTE: Care must be taken, since 
-   this value may be used in later revisions of the MIPS ISA. */
-#define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
-
-#define HALT_INSTRUCTION        (0x03ff000d)
-#define HALT_INSTRUCTION2       (0x0000ffcd)
-
-
-#define BREAKPOINT_INSTRUCTION  (0x0005000d)
-#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
-
-
-
-void interrupt_event (SIM_DESC sd, void *data);
-
-void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
-#define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
-#define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
-#define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
-#define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
-#define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
-#define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
-#define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
-#define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
-#define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
-#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
-#define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
-#define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
-#define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
-#define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
-#define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
-#define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
-#define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
-#define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
-#define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
-#define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
-
-/* Co-processor accesses */
-
-/* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
-#define COP_Usable(coproc_num)		(coproc_num == 1)
-
-void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
-void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
-unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
-uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
-
-#define COP_LW(coproc_num,coproc_reg,memword) \
-cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
-#define COP_LD(coproc_num,coproc_reg,memword) \
-cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
-#define COP_SW(coproc_num,coproc_reg) \
-cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
-#define COP_SD(coproc_num,coproc_reg) \
-cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
-
-
-void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
-#define DecodeCoproc(instruction) \
-decode_coproc (SD, CPU, cia, (instruction))
-
-int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
-  
-
-/* FPR access.  */
-unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
-#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
-void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
-#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
-unsigned64 ps_lower (SIM_STATE, unsigned64 op);
-#define PSLower(op) ps_lower (SIM_ARGS, op)
-unsigned64 ps_upper (SIM_STATE, unsigned64 op);
-#define PSUpper(op) ps_upper (SIM_ARGS, op)
-unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
-#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
-
-
-/* FCR access.  */
-unsigned_word value_fcr (SIM_STATE, int fcr);
-#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
-void store_fcr (SIM_STATE, int fcr, unsigned_word value);
-#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
-void test_fcsr (SIM_STATE);
-#define TestFCSR() test_fcsr (SIM_ARGS)
-
-
-/* FPU operations.  */
-void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
-#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
-unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
-unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
-unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
-unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
-unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
-unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
-		    unsigned64 op3, FP_formats fmt);
-#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
-		    unsigned64 op3, FP_formats fmt);
-#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
-		     unsigned64 op3, FP_formats fmt);
-#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
-		     unsigned64 op3, FP_formats fmt);
-#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
-unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
-#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
-unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
-		       FP_formats to);
-#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
-
-
-/* MIPS-3D ASE operations.  */
-#define CompareAbs(op1,op2,fmt,cond,cc) \
-fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
-unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
-unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
-unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
-#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
-unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
-#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
-
-
-/* MDMX access.  */
-
-typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
-#define ob_fmtsel(sel) (((sel)<<1)|0x0)
-#define qh_fmtsel(sel) (((sel)<<2)|0x1)
-
-#define fmt_mdmx fmt_uninterpreted
-
-#define MX_VECT_AND  (0)
-#define MX_VECT_NOR  (1)
-#define MX_VECT_OR   (2)
-#define MX_VECT_XOR  (3)
-#define MX_VECT_SLL  (4)
-#define MX_VECT_SRL  (5)
-#define MX_VECT_ADD  (6)
-#define MX_VECT_SUB  (7)
-#define MX_VECT_MIN  (8)
-#define MX_VECT_MAX  (9)
-#define MX_VECT_MUL  (10)
-#define MX_VECT_MSGN (11)
-#define MX_VECT_SRA  (12)
-#define MX_VECT_ABSD (13)		/* SB-1 only.  */
-#define MX_VECT_AVG  (14)		/* SB-1 only.  */
-
-unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
-#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
-#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
-#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
-#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
-#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
-#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
-#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
-#define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
-#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
-#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
-#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
-#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
-#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
-#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
-#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
-
-#define MX_C_EQ  0x1
-#define MX_C_LT  0x4
-
-void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
-#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
-
-unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
-#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
-
-#define MX_VECT_ADDA  (0)
-#define MX_VECT_ADDL  (1)
-#define MX_VECT_MULA  (2)
-#define MX_VECT_MULL  (3)
-#define MX_VECT_MULS  (4)
-#define MX_VECT_MULSL (5)
-#define MX_VECT_SUBA  (6)
-#define MX_VECT_SUBL  (7)
-#define MX_VECT_ABSDA (8)		/* SB-1 only.  */
-
-void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
-#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
-#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
-#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
-#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
-#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
-#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
-#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
-#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
-#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
-
-#define MX_FMT_OB   (0)
-#define MX_FMT_QH   (1)
-
-/* The following codes chosen to indicate the units of shift.  */
-#define MX_RAC_L    (0)
-#define MX_RAC_M    (1)
-#define MX_RAC_H    (2)
-
-unsigned64 mdmx_rac_op (SIM_STATE, int, int);
-#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
-
-void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
-#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
-void mdmx_wach (SIM_STATE, int, unsigned64);
-#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
-
-#define MX_RND_AS   (0)
-#define MX_RND_AU   (1)
-#define MX_RND_ES   (2)
-#define MX_RND_EU   (3)
-#define MX_RND_ZS   (4)
-#define MX_RND_ZU   (5)
-
-unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
-#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
-#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
-#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
-#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
-#define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
-#define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
-
-unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
-#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
-
-
-
-/* Memory accesses */
-
-/* The following are generic to all versions of the MIPS architecture
-   to date: */
-
-/* Memory Access Types (for CCA): */
-#define Uncached                (0)
-#define CachedNoncoherent       (1)
-#define CachedCoherent          (2)
-#define Cached                  (3)
-
-#define isINSTRUCTION   (1 == 0) /* FALSE */
-#define isDATA          (1 == 1) /* TRUE */
-#define isLOAD          (1 == 0) /* FALSE */
-#define isSTORE         (1 == 1) /* TRUE */
-#define isREAL          (1 == 0) /* FALSE */
-#define isRAW           (1 == 1) /* TRUE */
-/* The parameter HOST (isTARGET / isHOST) is ignored */
-#define isTARGET        (1 == 0) /* FALSE */
-/* #define isHOST          (1 == 1) TRUE */
-
-/* The "AccessLength" specifications for Loads and Stores. NOTE: This
-   is the number of bytes minus 1. */
-#define AccessLength_BYTE       (0)
-#define AccessLength_HALFWORD   (1)
-#define AccessLength_TRIPLEBYTE (2)
-#define AccessLength_WORD       (3)
-#define AccessLength_QUINTIBYTE (4)
-#define AccessLength_SEXTIBYTE  (5)
-#define AccessLength_SEPTIBYTE  (6)
-#define AccessLength_DOUBLEWORD (7)
-#define AccessLength_QUADWORD   (15)
-
-#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
-		    ? AccessLength_DOUBLEWORD /*7*/ \
-		    : AccessLength_WORD /*3*/)
-#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
-
-
-INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
-#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
-address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
-
-INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
-#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
-load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
-
-INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
-#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
-store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
-
-INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
-#define CacheOp(op,pAddr,vAddr,instruction) \
-cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
-
-INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
-#define SyncOperation(stype) \
-sync_operation (SD, CPU, cia, (stype))
-
-INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
-#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
-prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
-
-void unpredictable_action (sim_cpu *cpu, address_word cia);
-#define NotWordValue(val)	not_word_value (SD_, (val))
-#define Unpredictable()		unpredictable (SD_)
-#define UnpredictableResult()	/* For now, do nothing.  */
-
-INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
-#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
-INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
-#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
-#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
-
-void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
-extern FILE *tracefh;
-
-extern int DSPLO_REGNUM[4];
-extern int DSPHI_REGNUM[4];
-
-INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
-extern SIM_CORE_SIGNAL_FN mips_core_signal;
-
-char* pr_addr PARAMS ((SIM_ADDR addr));
-char* pr_uword64 PARAMS ((uword64 addr));
-
-
-#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
-
-void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
-void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
-void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
-
-#ifdef MIPS_MACH_MULTI
-extern int mips_mach_multi(SIM_DESC sd);
-#define MIPS_MACH(SD)	mips_mach_multi(SD)
-#else
-#define	MIPS_MACH(SD)	MIPS_MACH_DEFAULT
-#endif
-
-/* Macros for determining whether a MIPS IV or MIPS V part is subject
-   to the hi/lo restrictions described in mips.igen.  */
-
-#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
-  (MIPS_MACH (SD) != bfd_mach_mips5500)
-
-#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
-  (MIPS_MACH (SD) != bfd_mach_mips5500)
-
-#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
-  (MIPS_MACH (SD) != bfd_mach_mips5500)
-
-#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
-#include "sim-main.c"
-#endif
-
-#endif
diff --git a/sim/mips/tconfig.in b/sim/mips/tconfig.in
deleted file mode 100644
index 2f14ce1..0000000
--- a/sim/mips/tconfig.in
+++ /dev/null
@@ -1,36 +0,0 @@
-/* mips target configuration file.  */
-
-/* See sim-hload.c.  We properly handle LMA.  */
-#ifdef TARGET_TX3904
-#define SIM_HANDLES_LMA 1
-
-/* FIXME: This is unnecessarily necessary: */
-#include "ansidecl.h"
-#include "gdb/callback.h"
-#include "gdb/remote-sim.h"
-#include "sim-module.h"
-
-MODULE_INSTALL_FN dv_sockser_install;
-#define MODULE_LIST dv_sockser_install,
-#else
-#define SIM_HANDLES_LMA 0
-#endif
-
-/* Define this if the simulator supports profiling.
-   See the mips simulator for an example.
-   This enables the `-p foo' and `-s bar' options.
-   The target is required to provide sim_set_profile{,_size}.  */
-#define SIM_HAVE_PROFILE
-
-/* Define this if the simulator uses an instruction cache.
-   See the h8/300 simulator for an example.
-   This enables the `-c size' option to set the size of the cache.
-   The target is required to provide sim_set_simcache_size.  */
-/* #define SIM_HAVE_SIMCACHE */
-
-/* Define this if the target cpu is bi-endian
-   and the simulator supports it.  */
-#define SIM_HAVE_BIENDIAN
-
-/* MIPS uses an unusual format for floating point quiet NaNs.  */
-#define SIM_QUIET_NAN_NEGATED
diff --git a/sim/mips/tx.igen b/sim/mips/tx.igen
deleted file mode 100644
index cd8d76a..0000000
--- a/sim/mips/tx.igen
+++ /dev/null
@@ -1,46 +0,0 @@
-// -*- C -*-
-//
-// toshiba specific instructions.
-//
-
-011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD
-"madd r<RS>, r<RT>":RD == 0
-"madd r<RD>, r<RS>, r<RT>"
-*r3900
-{
-  signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-		   + ((signed64) EXTEND32 (GPR[RT])
-		      * (signed64) EXTEND32 (GPR[RS])));
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  LO = EXTEND32 (prod);
-  HI = EXTEND32 (VH4_8 (prod));
-  TRACE_ALU_RESULT2 (HI, LO);
-  if(RD != 0 )
-    GPR[RD] = LO;
-}
-
-
-011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU
-"maddu r<RS>, r<RT>":RD == 0
-"maddu r<RD>, r<RS>, r<RT>"
-*r3900
-{
-  unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
-		     + ((unsigned64) VL4_8 (GPR[RS])
-			* (unsigned64) VL4_8 (GPR[RT])));
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
-  LO = EXTEND32 (prod);
-  HI = EXTEND32 (VH4_8 (prod));
-  TRACE_ALU_RESULT2 (HI, LO);
-  if(RD != 0)
-    GPR[RD] = LO;
-}
-
-000000,CODE.20,001110::CO1:::SDBBP
-"sdbbp"
-*r3900:
-{
-  SignalException (DebugBreakPoint, instruction);
-}
diff --git a/sim/mips/vr.igen b/sim/mips/vr.igen
deleted file mode 100644
index 9266ae6..0000000
--- a/sim/mips/vr.igen
+++ /dev/null
@@ -1,257 +0,0 @@
-// -*- C -*-
-//
-// NEC specific instructions
-//
-
-:%s::::MFHI:int hi
-{
-  return hi ? "hi" : "";
-}
-
-:%s::::SAT:int s
-{
-  return s ? "s" : "";
-}
-
-:%s::::UNS:int u
-{
-  return u ? "u" : "";
-}
-
-// Simulate the various kinds of multiply and multiply-accumulate instructions.
-// Perform an operation of the form:
-//
-//	LHS (+/-) GPR[RS] * GPR[RT]
-//
-// and store it in the 64-bit accumulator.  Optionally copy either LO or
-// HI into a general purpose register.
-//
-// - RD is the destination register of the LO or HI move
-// - RS are RT are the multiplication source registers
-// - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
-//     false if it should be 0.
-// - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
-// - UNSIGNED_P is true if the operation should be unsigned.
-// - SATURATE_P is true if the result should be saturated to a 32-bit value.
-// - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
-//     false if it should be added.
-// - SHORT_P is true if RS and RT must be 16-bit numbers.
-// - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
-//     concatenation of the low 32 bits of HI and LO.
-:function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
-{
-  unsigned64 lhs, x, y, xcut, ycut, product, result;
-
-  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
-
-  lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
-  x = GPR[rs];
-  y = GPR[rt];
-
-  /* Work out the canonical form of X and Y from their significant bits.  */
-  if (!short_p)
-    {
-      /* Normal sign-extension rule for 32-bit operands.  */
-      xcut = EXTEND32 (x);
-      ycut = EXTEND32 (y);
-    }
-  else if (unsigned_p)
-    {
-      /* Operands must be zero-extended 16-bit numbers.  */
-      xcut = x & 0xffff;
-      ycut = y & 0xffff;
-    }
-  else
-    {
-      /* Likewise but sign-extended.  */
-      xcut = EXTEND16 (x);
-      ycut = EXTEND16 (y);
-    }
-  if (x != xcut || y != ycut)
-    sim_engine_abort (SD, CPU, CIA,
-		      "invalid multiplication operand at 0x%08lx\n",
-		      (long) CIA);
-
-  TRACE_ALU_INPUT2 (x, y);
-  product = (unsigned_p
-	     ? V8_4 (x, 1) * V8_4 (y, 1)
-	     : EXTEND32 (x) * EXTEND32 (y));
-  result = (subtract_p ? lhs - product : lhs + product);
-  if (saturate_p)
-    {
-      /* Saturate the result to 32 bits.  An unsigned, unsaturated
-	 result is zero-extended to 64 bits, but unsigned overflow
-	 causes all 64 bits to be set.  */
-      if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
-	result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
-      else if (unsigned_p && (result >> 32) != 0)
-	result = (unsigned64) 0 - 1;
-    }
-  TRACE_ALU_RESULT (result);
-
-  if (double_p)
-    LO = result;
-  else
-    {
-      LO = EXTEND32 (result);
-      HI = EXTEND32 (VH4_8 (result));
-    }
-  if (rd != 0)
-    GPR[rd] = store_hi_p ? HI : LO;
-}
-
-// VR4100 instructions.
-
-000000,5.RS,5.RT,00000,00000,101000::32::MADD16
-"madd16 r<RS>, r<RT>"
-*vr4100:
-{
-  do_vr_mul_op (SD_, 0, RS, RT,
-		1 /* accumulate */,
-		0 /* store in LO */,
-		0 /* signed arithmetic */,
-		0 /* don't saturate */,
-		0 /* don't subtract */,
-		1 /* short */,
-		0 /* single */);
-}
-
-000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
-"dmadd16 r<RS>, r<RT>"
-*vr4100:
-{
-  do_vr_mul_op (SD_, 0, RS, RT,
-		1 /* accumulate */,
-		0 /* store in LO */,
-		0 /* signed arithmetic */,
-		0 /* don't saturate */,
-		0 /* don't subtract */,
-		1 /* short */,
-		1 /* double */);
-}
-
-
-
-// VR4120 and VR4130 instructions.
-
-000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
-"dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
-*vr4120:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		1 /* accumulate */,
-		MFHI, UNS, SAT,
-		0 /* don't subtract */,
-		SAT /* short */,
-		1 /* double */);
-}
-
-000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
-"macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
-*vr4120:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		1 /* accumulate */,
-		MFHI, UNS, SAT,
-		0 /* don't subtract */,
-		SAT /* short */,
-		0 /* single */);
-}
-
-
-// VR5400 and VR5500 instructions.
-
-000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
-"mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
-*vr5400:
-*vr5500:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		0 /* don't accumulate */,
-		MFHI, UNS,
-		0 /* don't saturate */,
-		0 /* don't subtract */,
-		0 /* not short */,
-		0 /* single */);
-}
-
-000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
-"muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
-*vr5400:
-*vr5500:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		0 /* don't accumulate */,
-		MFHI, UNS,
-		0 /* don't saturate */,
-		1 /* subtract */,
-		0 /* not short */,
-		0 /* single */);
-}
-
-000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
-"macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
-*vr5400:
-*vr5500:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		1 /* accumulate */,
-		MFHI, UNS,
-		0 /* don't saturate */,
-		0 /* don't subtract */,
-		0 /* not short */,
-		0 /* single */);
-}
-
-000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
-"msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
-*vr5400:
-*vr5500:
-{
-  do_vr_mul_op (SD_, RD, RS, RT,
-		1 /* accumulate */,
-		MFHI, UNS,
-		0 /* don't saturate */,
-		1 /* subtract */,
-		0 /* not short */,
-		0 /* single */);
-}
-
-
-010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
-"luxc1 f<FD>, r<INDEX>(r<BASE>)"
-*vr5500:
-{
-  check_fpu (SD_);
-  COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
-			  (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
-}
-
-010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
-"suxc1 f<FS>, r<INDEX>(r<BASE>)"
-*vr5500:
-{
-  check_fpu (SD_);
-  do_store (SD_, AccessLength_DOUBLEWORD,
-	    (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
-	    COP_SD (1, FS));
-}
-
-010000,1,19.*,100000:COP0:32::WAIT
-"wait"
-*vr5500:
-
-011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
-"mfdr r<RT>, r<DR>"
-*vr5400:
-*vr5500:
-
-011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
-"mtdr r<RT>, r<DR>"
-*vr5400:
-*vr5500:
-
-011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
-"dret"
-*vr5400:
-*vr5500: