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author | Mike Frysinger <vapier@gentoo.org> | 2011-03-06 00:20:21 +0000 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-06 00:20:21 +0000 |
commit | ef016f835f292f01f065412fcfd84c50bfff1fea (patch) | |
tree | fe72facf7bcdc58af74f3a37d30f0f25d501f6a0 /sim/bfin/TODO | |
parent | 7dcf22fd41de725f3280c80a1274bcef309d6891 (diff) | |
download | gdb-ef016f835f292f01f065412fcfd84c50bfff1fea.zip gdb-ef016f835f292f01f065412fcfd84c50bfff1fea.tar.gz gdb-ef016f835f292f01f065412fcfd84c50bfff1fea.tar.bz2 |
sim: bfin: new port
This can boot Das U-Boot and a Linux kernel. It also supports Linux
userspace FLAT and FDPIC (dynamic and static) ELFs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/TODO')
-rw-r--r-- | sim/bfin/TODO | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/sim/bfin/TODO b/sim/bfin/TODO new file mode 100644 index 0000000..d180ab2 --- /dev/null +++ b/sim/bfin/TODO @@ -0,0 +1,28 @@ +need to review ASTAT write behavior + +how to model RETE and IVG0 bit in IPEND ... + +model the loop buffer ? this means no ifetches because they're cached. +see page 4-26 in Blackfin PRM under hardware loops. + +handle DSPID at 0xffe05000 + +CEC should handle multiple exceptions at same address. would need +exception processing to be delayed ? at least needs a stack for +the CEC to pop things off. + +R0 = [SP++]; gets traced as R0 = [P6++]; + +merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC + +fix single stepping over debug assert instructions in hardware + +exception in IVG5 causes double fault ? + +add a "file" option to the async banks to back it + +tests: + - check AN bits with Dreg subtraction + R0 = R1 - R2; + - check astat bits with vector add/sub +|+ + - check acc with VIT_MAX and similiar insns |