From ef016f835f292f01f065412fcfd84c50bfff1fea Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 6 Mar 2011 00:20:21 +0000 Subject: sim: bfin: new port This can boot Das U-Boot and a Linux kernel. It also supports Linux userspace FLAT and FDPIC (dynamic and static) ELFs. Signed-off-by: Mike Frysinger --- sim/bfin/TODO | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 sim/bfin/TODO (limited to 'sim/bfin/TODO') diff --git a/sim/bfin/TODO b/sim/bfin/TODO new file mode 100644 index 0000000..d180ab2 --- /dev/null +++ b/sim/bfin/TODO @@ -0,0 +1,28 @@ +need to review ASTAT write behavior + +how to model RETE and IVG0 bit in IPEND ... + +model the loop buffer ? this means no ifetches because they're cached. +see page 4-26 in Blackfin PRM under hardware loops. + +handle DSPID at 0xffe05000 + +CEC should handle multiple exceptions at same address. would need +exception processing to be delayed ? at least needs a stack for +the CEC to pop things off. + +R0 = [SP++]; gets traced as R0 = [P6++]; + +merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC + +fix single stepping over debug assert instructions in hardware + +exception in IVG5 causes double fault ? + +add a "file" option to the async banks to back it + +tests: + - check AN bits with Dreg subtraction + R0 = R1 - R2; + - check astat bits with vector add/sub +|+ + - check acc with VIT_MAX and similiar insns -- cgit v1.1