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| author | Mike Frysinger <vapier@gentoo.org> | 2021-05-01 15:54:33 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-05-01 16:25:02 -0400 |
| commit | f1ca32150cbc83e15a2002d3543f5dd7256ad248 (patch) | |
| tree | 5da2c4fd8ab89efcbe54a34d85c6eaf25a15a752 /sim/aarch64 | |
| parent | ce2248135a651d313f87d838e965477b5e4d6131 (diff) | |
| download | gdb-f1ca32150cbc83e15a2002d3543f5dd7256ad248.zip gdb-f1ca32150cbc83e15a2002d3543f5dd7256ad248.tar.gz gdb-f1ca32150cbc83e15a2002d3543f5dd7256ad248.tar.bz2 | |
sim: aarch64: use PRIx64 for formatting 64-bit types
We can't assume that %lx is big enough for 64-bit types as it isn't on
most 32-bit builds. Use the standard format define for this instead.
Diffstat (limited to 'sim/aarch64')
| -rw-r--r-- | sim/aarch64/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/aarch64/cpustate.c | 11 |
2 files changed, 12 insertions, 5 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index 2d13cf1..81b878f 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,5 +1,11 @@ 2021-05-01 Mike Frysinger <vapier@gentoo.org> + * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64. + (aarch64_set_FP_double, aarch64_set_FP_long_double, + aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise. + +2021-05-01 Mike Frysinger <vapier@gentoo.org> + * simulator.c (do_fcvtzu): Change UL to ULL. 2021-04-26 Mike Frysinger <vapier@gentoo.org> diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c index e901a07..f6b93fb 100644 --- a/sim/aarch64/cpustate.c +++ b/sim/aarch64/cpustate.c @@ -379,7 +379,7 @@ aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val) v.s = val; TRACE_REGISTER (cpu, - "FR[%d].s changes from %f to %f [hex: %0lx]", + "FR[%d].s changes from %f to %f [hex: %0" PRIx64 "]", reg, cpu->fr[reg].s, val, v.v[0]); } @@ -397,7 +397,7 @@ aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val) v.d = val; TRACE_REGISTER (cpu, - "FR[%d].d changes from %f to %f [hex: %0lx]", + "FR[%d].d changes from %f to %f [hex: %0" PRIx64 "]", reg, cpu->fr[reg].d, val, v.v[0]); } cpu->fr[reg].d = val; @@ -409,7 +409,8 @@ aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) if (cpu->fr[reg].v[0] != a.v[0] || cpu->fr[reg].v[1] != a.v[1]) TRACE_REGISTER (cpu, - "FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ", + "FR[%d].q changes from [%0" PRIx64 " %0" PRIx64 "] to [%0" + PRIx64 " %0" PRIx64 "] ", reg, cpu->fr[reg].v[0], cpu->fr[reg].v[1], a.v[0], a.v[1]); @@ -518,7 +519,7 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element) void aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val) { - SET_VEC_ELEMENT (reg, element, val, v, "%16lx"); + SET_VEC_ELEMENT (reg, element, val, v, "%16" PRIx64); } void @@ -542,7 +543,7 @@ aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val) void aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val) { - SET_VEC_ELEMENT (reg, element, val, V, "%16lx"); + SET_VEC_ELEMENT (reg, element, val, V, "%16" PRIx64); } void |